1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/mcp_public.h 337517 2018-08-09 01:17:35Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs/**************************************************************************** 32316485Sdavidcs * 33316485Sdavidcs * Name: mcp_public.h 34316485Sdavidcs * 35316485Sdavidcs * Description: MCP public data 36316485Sdavidcs * 37316485Sdavidcs * Created: 13/01/2013 yanivr 38316485Sdavidcs * 39316485Sdavidcs ****************************************************************************/ 40316485Sdavidcs 41316485Sdavidcs#ifndef MCP_PUBLIC_H 42316485Sdavidcs#define MCP_PUBLIC_H 43316485Sdavidcs 44316485Sdavidcs#define VF_MAX_STATIC 192 /* In case of AH */ 45316485Sdavidcs 46316485Sdavidcs#define MCP_GLOB_PATH_MAX 2 47316485Sdavidcs#define MCP_PORT_MAX 2 /* Global */ 48316485Sdavidcs#define MCP_GLOB_PORT_MAX 4 /* Global */ 49316485Sdavidcs#define MCP_GLOB_FUNC_MAX 16 /* Global */ 50316485Sdavidcs 51316485Sdavidcstypedef u32 offsize_t; /* In DWORDS !!! */ 52316485Sdavidcs/* Offset from the beginning of the MCP scratchpad */ 53320164Sdavidcs#define OFFSIZE_OFFSET_OFFSET 0 54316485Sdavidcs#define OFFSIZE_OFFSET_MASK 0x0000ffff 55316485Sdavidcs/* Size of specific element (not the whole array if any) */ 56320164Sdavidcs#define OFFSIZE_SIZE_OFFSET 16 57316485Sdavidcs#define OFFSIZE_SIZE_MASK 0xffff0000 58316485Sdavidcs 59316485Sdavidcs/* SECTION_OFFSET is calculating the offset in bytes out of offsize */ 60320164Sdavidcs#define SECTION_OFFSET(_offsize) ((((_offsize & OFFSIZE_OFFSET_MASK) >> OFFSIZE_OFFSET_OFFSET) << 2)) 61316485Sdavidcs 62316485Sdavidcs/* SECTION_SIZE is calculating the size in bytes out of offsize */ 63320164Sdavidcs#define SECTION_SIZE(_offsize) (((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_OFFSET) << 2) 64316485Sdavidcs 65316485Sdavidcs/* SECTION_ADDR returns the GRC addr of a section, given offsize and index within section */ 66316485Sdavidcs#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx)) 67316485Sdavidcs 68316485Sdavidcs/* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use offsetof, since the OFFSETUP collide with the firmware definition */ 69316485Sdavidcs#define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 70316485Sdavidcs/* PHY configuration */ 71316485Sdavidcsstruct eth_phy_cfg { 72316485Sdavidcs u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */ 73316485Sdavidcs#define ETH_SPEED_AUTONEG 0 74316485Sdavidcs#define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */ 75316485Sdavidcs 76316485Sdavidcs u32 pause; /* bitmask */ 77316485Sdavidcs#define ETH_PAUSE_NONE 0x0 78316485Sdavidcs#define ETH_PAUSE_AUTONEG 0x1 79316485Sdavidcs#define ETH_PAUSE_RX 0x2 80316485Sdavidcs#define ETH_PAUSE_TX 0x4 81316485Sdavidcs 82316485Sdavidcs u32 adv_speed; /* Default should be the speed_cap_mask */ 83316485Sdavidcs u32 loopback_mode; 84316485Sdavidcs#define ETH_LOOPBACK_NONE (0) 85316485Sdavidcs#define ETH_LOOPBACK_INT_PHY (1) /* Serdes loopback. In AH, it refers to Near End */ 86316485Sdavidcs#define ETH_LOOPBACK_EXT_PHY (2) /* External PHY Loopback */ 87316485Sdavidcs#define ETH_LOOPBACK_EXT (3) /* External Loopback (Require loopback plug) */ 88316485Sdavidcs#define ETH_LOOPBACK_MAC (4) /* MAC Loopback - not supported */ 89316485Sdavidcs#define ETH_LOOPBACK_CNIG_AH_ONLY_0123 (5) /* Port to itself */ 90316485Sdavidcs#define ETH_LOOPBACK_CNIG_AH_ONLY_2301 (6) /* Port to Port */ 91316485Sdavidcs#define ETH_LOOPBACK_PCS_AH_ONLY (7) /* PCS loopback (TX to RX) */ 92316485Sdavidcs#define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY (8) /* Loop RX packet from PCS to TX */ 93316485Sdavidcs#define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY (9) /* Remote Serdes Loopback (RX to TX) */ 94316485Sdavidcs 95316485Sdavidcs u32 eee_cfg; 96316485Sdavidcs#define EEE_CFG_EEE_ENABLED (1<<0) /* EEE is enabled (configuration). Refer to eee_status->active for negotiated status */ 97316485Sdavidcs#define EEE_CFG_TX_LPI (1<<1) 98316485Sdavidcs#define EEE_CFG_ADV_SPEED_1G (1<<2) 99316485Sdavidcs#define EEE_CFG_ADV_SPEED_10G (1<<3) 100316485Sdavidcs#define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 101320164Sdavidcs#define EEE_TX_TIMER_USEC_OFFSET 4 102316485Sdavidcs#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 103316485Sdavidcs#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 104316485Sdavidcs#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 105316485Sdavidcs 106316485Sdavidcs u32 link_modes; /* Additional link modes */ 107320164Sdavidcs#define LINK_MODE_SMARTLINQ_ENABLE 0x1 /* XXX Deprecate */ 108316485Sdavidcs}; 109316485Sdavidcs 110316485Sdavidcsstruct port_mf_cfg { 111316485Sdavidcs 112316485Sdavidcs u32 dynamic_cfg; /* device control channel */ 113316485Sdavidcs#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 114320164Sdavidcs#define PORT_MF_CFG_OV_TAG_OFFSET 0 115316485Sdavidcs#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 116316485Sdavidcs 117316485Sdavidcs u32 reserved[1]; 118316485Sdavidcs}; 119316485Sdavidcs 120316485Sdavidcs/* DO NOT add new fields in the middle 121316485Sdavidcs * MUST be synced with struct pmm_stats_map 122316485Sdavidcs */ 123316485Sdavidcsstruct eth_stats { 124316485Sdavidcs u64 r64; /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/ 125316485Sdavidcs u64 r127; /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/ 126316485Sdavidcs u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/ 127316485Sdavidcs u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/ 128316485Sdavidcs u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/ 129316485Sdavidcs u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */ 130316485Sdavidcs union { 131316485Sdavidcs struct { /* bb */ 132316485Sdavidcs u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */ 133316485Sdavidcs u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/ 134316485Sdavidcs u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/ 135316485Sdavidcs u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/ 136316485Sdavidcs u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */ 137316485Sdavidcs 138316485Sdavidcs } bb0; 139316485Sdavidcs struct { /* ah */ 140316485Sdavidcs u64 unused1; 141316485Sdavidcs u64 r1519_to_max; /* 0x07 (Offset 0x38 ) RX 1519 to max byte frame counter*/ 142316485Sdavidcs u64 unused2; 143316485Sdavidcs u64 unused3; 144316485Sdavidcs u64 unused4; 145316485Sdavidcs } ah0; 146316485Sdavidcs } u0; 147316485Sdavidcs u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/ 148316485Sdavidcs u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/ 149316485Sdavidcs u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/ 150316485Sdavidcs u64 rxpp; /* 0x12 (Offset 0x70 ) RX PFC frame counter*/ 151316485Sdavidcs u64 raln; /* 0x16 (Offset 0x78 ) RX alignment error counter*/ 152316485Sdavidcs u64 rfcr; /* 0x19 (Offset 0x80 ) RX false carrier counter */ 153316485Sdavidcs u64 rovr; /* 0x1A (Offset 0x88 ) RX oversized frame counter*/ 154316485Sdavidcs u64 rjbr; /* 0x1B (Offset 0x90 ) RX jabber frame counter */ 155316485Sdavidcs u64 rund; /* 0x34 (Offset 0x98 ) RX undersized frame counter */ 156316485Sdavidcs u64 rfrg; /* 0x35 (Offset 0xa0 ) RX fragment counter */ 157316485Sdavidcs u64 t64; /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */ 158316485Sdavidcs u64 t127; /* 0x41 (Offset 0xb0 ) TX 65 to 127 byte frame counter */ 159316485Sdavidcs u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/ 160316485Sdavidcs u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/ 161316485Sdavidcs u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/ 162316485Sdavidcs u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */ 163316485Sdavidcs union { 164316485Sdavidcs struct { /* bb */ 165316485Sdavidcs u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */ 166316485Sdavidcs u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */ 167316485Sdavidcs u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */ 168316485Sdavidcs u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */ 169316485Sdavidcs } bb1; 170316485Sdavidcs struct { /* ah */ 171316485Sdavidcs u64 t1519_to_max; /* 0x47 (Offset 0xd8 ) TX 1519 to max byte frame counter */ 172316485Sdavidcs u64 unused6; 173316485Sdavidcs u64 unused7; 174316485Sdavidcs u64 unused8; 175316485Sdavidcs } ah1; 176316485Sdavidcs } u1; 177316485Sdavidcs u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */ 178316485Sdavidcs u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */ 179316485Sdavidcs union { 180316485Sdavidcs struct { /* bb */ 181316485Sdavidcs u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */ 182316485Sdavidcs u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */ 183316485Sdavidcs } bb2; 184316485Sdavidcs struct { /* ah */ 185316485Sdavidcs u64 unused9; 186316485Sdavidcs u64 unused10; 187316485Sdavidcs } ah2; 188316485Sdavidcs } u2; 189316485Sdavidcs u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */ 190316485Sdavidcs u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */ 191316485Sdavidcs u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */ 192316485Sdavidcs u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */ 193316485Sdavidcs u64 rxpok; /* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */ 194316485Sdavidcs u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */ 195316485Sdavidcs u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */ 196316485Sdavidcs u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */ 197316485Sdavidcs u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */ 198316485Sdavidcs u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */ 199316485Sdavidcs /* HSI - Cannot add more stats to this struct. If needed, then need to open new struct */ 200316485Sdavidcs}; 201316485Sdavidcs 202316485Sdavidcsstruct brb_stats { 203316485Sdavidcs u64 brb_truncate[8]; 204316485Sdavidcs u64 brb_discard[8]; 205316485Sdavidcs}; 206316485Sdavidcs 207316485Sdavidcsstruct port_stats { 208316485Sdavidcs struct brb_stats brb; 209316485Sdavidcs struct eth_stats eth; 210316485Sdavidcs}; 211316485Sdavidcs 212316485Sdavidcs/*-----+----------------------------------------------------------------------------- 213316485Sdavidcs * Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines 214316485Sdavidcs * | rate of physical | team #1 | team #2 |are used|per path | (paths) enabled 215316485Sdavidcs * | ports | | | | | 216316485Sdavidcs *======+==================+=========+=========+========+==========+================= 217316485Sdavidcs * BB | 1x100G | This is special mode, where there are actually 2 HW func 218316485Sdavidcs * BB | 2x10/20Gbps | 0,1 | NA | No | 1 | 1 219316485Sdavidcs * BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1 220316485Sdavidcs * BB | 2x50Gbps | 0,1 | NA | No | 1 | 1 221316485Sdavidcs * BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional) 222316485Sdavidcs * BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional) 223316485Sdavidcs * BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional) 224316485Sdavidcs * BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1 225316485Sdavidcs * AH | 2x10/20Gbps | 0,1 | NA | NA | 1 | NA 226316485Sdavidcs * AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA 227316485Sdavidcs * AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA 228316485Sdavidcs * AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA 229316485Sdavidcs * AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA 230316485Sdavidcs *======+==================+=========+=========+========+==========+=================== 231316485Sdavidcs */ 232316485Sdavidcs 233316485Sdavidcs#define CMT_TEAM0 0 234316485Sdavidcs#define CMT_TEAM1 1 235316485Sdavidcs#define CMT_TEAM_MAX 2 236316485Sdavidcs 237316485Sdavidcsstruct couple_mode_teaming { 238316485Sdavidcs u8 port_cmt[MCP_GLOB_PORT_MAX]; 239316485Sdavidcs#define PORT_CMT_IN_TEAM (1<<0) 240316485Sdavidcs 241316485Sdavidcs#define PORT_CMT_PORT_ROLE (1<<1) 242316485Sdavidcs#define PORT_CMT_PORT_INACTIVE (0<<1) 243316485Sdavidcs#define PORT_CMT_PORT_ACTIVE (1<<1) 244316485Sdavidcs 245316485Sdavidcs#define PORT_CMT_TEAM_MASK (1<<2) 246316485Sdavidcs#define PORT_CMT_TEAM0 (0<<2) 247316485Sdavidcs#define PORT_CMT_TEAM1 (1<<2) 248316485Sdavidcs}; 249316485Sdavidcs 250316485Sdavidcs/************************************** 251316485Sdavidcs * LLDP and DCBX HSI structures 252316485Sdavidcs **************************************/ 253337517Sdavidcs#define LLDP_CHASSIS_ID_STAT_LEN 4 254337517Sdavidcs#define LLDP_PORT_ID_STAT_LEN 4 255316485Sdavidcs#define DCBX_MAX_APP_PROTOCOL 32 256337517Sdavidcs#define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ 257337517Sdavidcs#define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ 258316485Sdavidcstypedef enum _lldp_agent_e { 259316485Sdavidcs LLDP_NEAREST_BRIDGE = 0, 260316485Sdavidcs LLDP_NEAREST_NON_TPMR_BRIDGE, 261316485Sdavidcs LLDP_NEAREST_CUSTOMER_BRIDGE, 262316485Sdavidcs LLDP_MAX_LLDP_AGENTS 263316485Sdavidcs} lldp_agent_e; 264316485Sdavidcs 265316485Sdavidcsstruct lldp_config_params_s { 266316485Sdavidcs u32 config; 267316485Sdavidcs#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 268320164Sdavidcs#define LLDP_CONFIG_TX_INTERVAL_OFFSET 0 269316485Sdavidcs#define LLDP_CONFIG_HOLD_MASK 0x00000f00 270320164Sdavidcs#define LLDP_CONFIG_HOLD_OFFSET 8 271316485Sdavidcs#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 272320164Sdavidcs#define LLDP_CONFIG_MAX_CREDIT_OFFSET 12 273316485Sdavidcs#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 274320164Sdavidcs#define LLDP_CONFIG_ENABLE_RX_OFFSET 30 275316485Sdavidcs#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 276320164Sdavidcs#define LLDP_CONFIG_ENABLE_TX_OFFSET 31 277316485Sdavidcs /* Holds local Chassis ID TLV header, subtype and 9B of payload. 278316485Sdavidcs If firtst byte is 0, then we will use default chassis ID */ 279316485Sdavidcs u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 280316485Sdavidcs /* Holds local Port ID TLV header, subtype and 9B of payload. 281316485Sdavidcs If firtst byte is 0, then we will use default port ID */ 282316485Sdavidcs u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 283316485Sdavidcs}; 284316485Sdavidcs 285316485Sdavidcsstruct lldp_status_params_s { 286316485Sdavidcs u32 prefix_seq_num; 287316485Sdavidcs u32 status; /* TBD */ 288316485Sdavidcs /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 289316485Sdavidcs u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 290316485Sdavidcs /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 291316485Sdavidcs u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 292316485Sdavidcs u32 suffix_seq_num; 293316485Sdavidcs}; 294316485Sdavidcs 295316485Sdavidcsstruct dcbx_ets_feature { 296316485Sdavidcs u32 flags; 297316485Sdavidcs#define DCBX_ETS_ENABLED_MASK 0x00000001 298320164Sdavidcs#define DCBX_ETS_ENABLED_OFFSET 0 299316485Sdavidcs#define DCBX_ETS_WILLING_MASK 0x00000002 300320164Sdavidcs#define DCBX_ETS_WILLING_OFFSET 1 301316485Sdavidcs#define DCBX_ETS_ERROR_MASK 0x00000004 302320164Sdavidcs#define DCBX_ETS_ERROR_OFFSET 2 303316485Sdavidcs#define DCBX_ETS_CBS_MASK 0x00000008 304320164Sdavidcs#define DCBX_ETS_CBS_OFFSET 3 305316485Sdavidcs#define DCBX_ETS_MAX_TCS_MASK 0x000000f0 306320164Sdavidcs#define DCBX_ETS_MAX_TCS_OFFSET 4 307316485Sdavidcs#define DCBX_OOO_TC_MASK 0x00000f00 308320164Sdavidcs#define DCBX_OOO_TC_OFFSET 8 309316485Sdavidcs /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 310316485Sdavidcs u32 pri_tc_tbl[1]; 311316485Sdavidcs/* Fixed TCP OOO TC usage is deprecated and used only for driver backward compatibility */ 312316485Sdavidcs#define DCBX_TCP_OOO_TC (4) 313316485Sdavidcs#define DCBX_TCP_OOO_K2_4PORT_TC (3) 314316485Sdavidcs 315316485Sdavidcs#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 316316485Sdavidcs#define DCBX_CEE_STRICT_PRIORITY 0xf 317316485Sdavidcs /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 318316485Sdavidcs u32 tc_bw_tbl[2]; 319316485Sdavidcs /* Entries in tc table are orginized that the left most is pri 0, right most is prio 7 */ 320316485Sdavidcs u32 tc_tsa_tbl[2]; 321316485Sdavidcs#define DCBX_ETS_TSA_STRICT 0 322316485Sdavidcs#define DCBX_ETS_TSA_CBS 1 323316485Sdavidcs#define DCBX_ETS_TSA_ETS 2 324316485Sdavidcs}; 325316485Sdavidcs 326316485Sdavidcsstruct dcbx_app_priority_entry { 327316485Sdavidcs u32 entry; 328316485Sdavidcs#define DCBX_APP_PRI_MAP_MASK 0x000000ff 329320164Sdavidcs#define DCBX_APP_PRI_MAP_OFFSET 0 330316485Sdavidcs#define DCBX_APP_PRI_0 0x01 331316485Sdavidcs#define DCBX_APP_PRI_1 0x02 332316485Sdavidcs#define DCBX_APP_PRI_2 0x04 333316485Sdavidcs#define DCBX_APP_PRI_3 0x08 334316485Sdavidcs#define DCBX_APP_PRI_4 0x10 335316485Sdavidcs#define DCBX_APP_PRI_5 0x20 336316485Sdavidcs#define DCBX_APP_PRI_6 0x40 337316485Sdavidcs#define DCBX_APP_PRI_7 0x80 338316485Sdavidcs#define DCBX_APP_SF_MASK 0x00000300 339320164Sdavidcs#define DCBX_APP_SF_OFFSET 8 340316485Sdavidcs#define DCBX_APP_SF_ETHTYPE 0 341316485Sdavidcs#define DCBX_APP_SF_PORT 1 342316485Sdavidcs#define DCBX_APP_SF_IEEE_MASK 0x0000f000 343320164Sdavidcs#define DCBX_APP_SF_IEEE_OFFSET 12 344316485Sdavidcs#define DCBX_APP_SF_IEEE_RESERVED 0 345316485Sdavidcs#define DCBX_APP_SF_IEEE_ETHTYPE 1 346316485Sdavidcs#define DCBX_APP_SF_IEEE_TCP_PORT 2 347316485Sdavidcs#define DCBX_APP_SF_IEEE_UDP_PORT 3 348316485Sdavidcs#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 349316485Sdavidcs 350316485Sdavidcs#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 351320164Sdavidcs#define DCBX_APP_PROTOCOL_ID_OFFSET 16 352316485Sdavidcs}; 353316485Sdavidcs 354316485Sdavidcs 355316485Sdavidcs/* FW structure in BE */ 356316485Sdavidcsstruct dcbx_app_priority_feature { 357316485Sdavidcs u32 flags; 358316485Sdavidcs#define DCBX_APP_ENABLED_MASK 0x00000001 359320164Sdavidcs#define DCBX_APP_ENABLED_OFFSET 0 360316485Sdavidcs#define DCBX_APP_WILLING_MASK 0x00000002 361320164Sdavidcs#define DCBX_APP_WILLING_OFFSET 1 362316485Sdavidcs#define DCBX_APP_ERROR_MASK 0x00000004 363320164Sdavidcs#define DCBX_APP_ERROR_OFFSET 2 364316485Sdavidcs /* Not in use 365316485Sdavidcs #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00 366320164Sdavidcs #define DCBX_APP_DEFAULT_PRI_OFFSET 8 367316485Sdavidcs */ 368316485Sdavidcs#define DCBX_APP_MAX_TCS_MASK 0x0000f000 369320164Sdavidcs#define DCBX_APP_MAX_TCS_OFFSET 12 370316485Sdavidcs#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 371320164Sdavidcs#define DCBX_APP_NUM_ENTRIES_OFFSET 16 372316485Sdavidcs struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 373316485Sdavidcs}; 374316485Sdavidcs 375316485Sdavidcs/* FW structure in BE */ 376316485Sdavidcsstruct dcbx_features { 377316485Sdavidcs /* PG feature */ 378316485Sdavidcs struct dcbx_ets_feature ets; 379316485Sdavidcs /* PFC feature */ 380316485Sdavidcs u32 pfc; 381316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 382320164Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_OFFSET 0 383316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 384316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 385316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 386316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 387316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 388316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 389316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 390316485Sdavidcs#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 391316485Sdavidcs 392316485Sdavidcs#define DCBX_PFC_FLAGS_MASK 0x0000ff00 393320164Sdavidcs#define DCBX_PFC_FLAGS_OFFSET 8 394316485Sdavidcs#define DCBX_PFC_CAPS_MASK 0x00000f00 395320164Sdavidcs#define DCBX_PFC_CAPS_OFFSET 8 396316485Sdavidcs#define DCBX_PFC_MBC_MASK 0x00004000 397320164Sdavidcs#define DCBX_PFC_MBC_OFFSET 14 398316485Sdavidcs#define DCBX_PFC_WILLING_MASK 0x00008000 399320164Sdavidcs#define DCBX_PFC_WILLING_OFFSET 15 400316485Sdavidcs#define DCBX_PFC_ENABLED_MASK 0x00010000 401320164Sdavidcs#define DCBX_PFC_ENABLED_OFFSET 16 402316485Sdavidcs#define DCBX_PFC_ERROR_MASK 0x00020000 403320164Sdavidcs#define DCBX_PFC_ERROR_OFFSET 17 404316485Sdavidcs 405316485Sdavidcs /* APP feature */ 406316485Sdavidcs struct dcbx_app_priority_feature app; 407316485Sdavidcs}; 408316485Sdavidcs 409316485Sdavidcsstruct dcbx_local_params { 410316485Sdavidcs u32 config; 411316485Sdavidcs#define DCBX_CONFIG_VERSION_MASK 0x00000007 412320164Sdavidcs#define DCBX_CONFIG_VERSION_OFFSET 0 413316485Sdavidcs#define DCBX_CONFIG_VERSION_DISABLED 0 414316485Sdavidcs#define DCBX_CONFIG_VERSION_IEEE 1 415316485Sdavidcs#define DCBX_CONFIG_VERSION_CEE 2 416337517Sdavidcs#define DCBX_CONFIG_VERSION_DYNAMIC (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) 417316485Sdavidcs#define DCBX_CONFIG_VERSION_STATIC 4 418316485Sdavidcs 419316485Sdavidcs u32 flags; 420316485Sdavidcs struct dcbx_features features; 421316485Sdavidcs}; 422316485Sdavidcs 423316485Sdavidcsstruct dcbx_mib { 424316485Sdavidcs u32 prefix_seq_num; 425316485Sdavidcs u32 flags; 426316485Sdavidcs /* 427316485Sdavidcs #define DCBX_CONFIG_VERSION_MASK 0x00000007 428320164Sdavidcs #define DCBX_CONFIG_VERSION_OFFSET 0 429316485Sdavidcs #define DCBX_CONFIG_VERSION_DISABLED 0 430316485Sdavidcs #define DCBX_CONFIG_VERSION_IEEE 1 431316485Sdavidcs #define DCBX_CONFIG_VERSION_CEE 2 432316485Sdavidcs #define DCBX_CONFIG_VERSION_STATIC 4 433316485Sdavidcs */ 434316485Sdavidcs struct dcbx_features features; 435316485Sdavidcs u32 suffix_seq_num; 436316485Sdavidcs}; 437316485Sdavidcs 438316485Sdavidcsstruct lldp_system_tlvs_buffer_s { 439337517Sdavidcs u32 flags; 440337517Sdavidcs#define LLDP_SYSTEM_TLV_VALID_MASK 0x1 441337517Sdavidcs#define LLDP_SYSTEM_TLV_VALID_OFFSET 0 442337517Sdavidcs/* This bit defines if system TLVs are instead of mandatory TLVS or in 443337517Sdavidcs * addition to them. Set 1 for replacing mandatory TLVs 444337517Sdavidcs */ 445337517Sdavidcs#define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 446337517Sdavidcs#define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 447337517Sdavidcs#define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 448337517Sdavidcs#define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 449316485Sdavidcs u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 450316485Sdavidcs}; 451316485Sdavidcs 452337517Sdavidcs/* Since this struct is written by MFW and read by driver need to add 453337517Sdavidcs * sequence guards (as in case of DCBX MIB) 454337517Sdavidcs */ 455337517Sdavidcsstruct lldp_received_tlvs_s { 456337517Sdavidcs u32 prefix_seq_num; 457337517Sdavidcs u32 length; 458337517Sdavidcs u32 tlvs_buffer[MAX_TLV_BUFFER]; 459337517Sdavidcs u32 suffix_seq_num; 460337517Sdavidcs}; 461337517Sdavidcs 462316485Sdavidcsstruct dcb_dscp_map { 463316485Sdavidcs u32 flags; 464316485Sdavidcs#define DCB_DSCP_ENABLE_MASK 0x1 465320164Sdavidcs#define DCB_DSCP_ENABLE_OFFSET 0 466316485Sdavidcs#define DCB_DSCP_ENABLE 1 467316485Sdavidcs u32 dscp_pri_map[8]; 468316485Sdavidcs /* the map structure is the following: 469316485Sdavidcs each u32 is split into 4 bits chunks, each chunk holds priority for respective dscp 470316485Sdavidcs Lowest dscp is at lsb 471316485Sdavidcs 31 28 24 20 16 12 8 4 0 472316485Sdavidcs dscp_pri_map[0]: | dscp7 pri | dscp6 pri | dscp5 pri | dscp4 pri | dscp3 pri | dscp2 pri | dscp1 pri | dscp0 pri | 473316485Sdavidcs dscp_pri_map[1]: | dscp15 pri| dscp14 pri| dscp13 pri| dscp12 pri| dscp11 pri| dscp10 pri| dscp9 pri | dscp8 pri | 474316485Sdavidcs etc.*/ 475316485Sdavidcs}; 476316485Sdavidcs 477337517Sdavidcsstruct mcp_val64 { 478337517Sdavidcs u32 lo; 479337517Sdavidcs u32 hi; 480337517Sdavidcs}; 481337517Sdavidcs 482337517Sdavidcs/* generic_idc_msg_t to be used for inter driver communication. 483337517Sdavidcs * source_pf specifies the originating PF that sent messages to all target PFs 484337517Sdavidcs * msg contains 64 bit value of the message - opaque to the MFW 485337517Sdavidcs */ 486337517Sdavidcsstruct generic_idc_msg_s { 487337517Sdavidcs u32 source_pf; 488337517Sdavidcs struct mcp_val64 msg; 489337517Sdavidcs}; 490337517Sdavidcs 491337517Sdavidcs/************************************** 492337517Sdavidcs * Attributes commands 493337517Sdavidcs **************************************/ 494337517Sdavidcs 495337517Sdavidcsenum _attribute_commands_e { 496337517Sdavidcs ATTRIBUTE_CMD_READ = 0, 497337517Sdavidcs ATTRIBUTE_CMD_WRITE, 498337517Sdavidcs ATTRIBUTE_CMD_READ_CLEAR, 499337517Sdavidcs ATTRIBUTE_CMD_CLEAR, 500337517Sdavidcs ATTRIBUTE_NUM_OF_COMMANDS 501337517Sdavidcs}; 502337517Sdavidcs 503316485Sdavidcs/**************************************/ 504316485Sdavidcs/* */ 505316485Sdavidcs/* P U B L I C G L O B A L */ 506316485Sdavidcs/* */ 507316485Sdavidcs/**************************************/ 508316485Sdavidcsstruct public_global { 509316485Sdavidcs u32 max_path; /* 32bit is wasty, but this will be used often */ 510316485Sdavidcs u32 max_ports; /* (Global) 32bit is wasty, but this will be used often */ 511316485Sdavidcs#define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */ 512316485Sdavidcs#define MODE_2P 2 513316485Sdavidcs#define MODE_3P 3 514316485Sdavidcs#define MODE_4P 4 515316485Sdavidcs u32 debug_mb_offset; 516316485Sdavidcs u32 phymod_dbg_mb_offset; 517316485Sdavidcs struct couple_mode_teaming cmt; 518316485Sdavidcs s32 internal_temperature; /* Temperature in Celcius (-255C / +255C), measured every second. */ 519316485Sdavidcs u32 mfw_ver; 520316485Sdavidcs u32 running_bundle_id; 521316485Sdavidcs s32 external_temperature; 522316485Sdavidcs u32 mdump_reason; 523316485Sdavidcs#define MDUMP_REASON_INTERNAL_ERROR (1 << 0) 524316485Sdavidcs#define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1) 525316485Sdavidcs#define MDUMP_REASON_DUMP_AGED (1 << 2) 526316485Sdavidcs u32 ext_phy_upgrade_fw; 527316485Sdavidcs#define EXT_PHY_FW_UPGRADE_STATUS_MASK (0x0000ffff) 528320164Sdavidcs#define EXT_PHY_FW_UPGRADE_STATUS_OFFSET (0) 529316485Sdavidcs#define EXT_PHY_FW_UPGRADE_STATUS_IN_PROGRESS (1) 530316485Sdavidcs#define EXT_PHY_FW_UPGRADE_STATUS_FAILED (2) 531316485Sdavidcs#define EXT_PHY_FW_UPGRADE_STATUS_SUCCESS (3) 532316485Sdavidcs#define EXT_PHY_FW_UPGRADE_TYPE_MASK (0xffff0000) 533320164Sdavidcs#define EXT_PHY_FW_UPGRADE_TYPE_OFFSET (16) 534316485Sdavidcs 535316485Sdavidcs u8 runtime_port_swap_map[MODE_4P]; 536316485Sdavidcs u32 data_ptr; 537316485Sdavidcs u32 data_size; 538316485Sdavidcs}; 539316485Sdavidcs 540316485Sdavidcs/**************************************/ 541316485Sdavidcs/* */ 542316485Sdavidcs/* P U B L I C P A T H */ 543316485Sdavidcs/* */ 544316485Sdavidcs/**************************************/ 545316485Sdavidcs 546316485Sdavidcs/**************************************************************************** 547316485Sdavidcs * Shared Memory 2 Region * 548316485Sdavidcs ****************************************************************************/ 549316485Sdavidcs/* The fw_flr_ack is actually built in the following way: */ 550316485Sdavidcs/* 8 bit: PF ack */ 551316485Sdavidcs/* 128 bit: VF ack */ 552316485Sdavidcs/* 8 bit: ios_dis_ack */ 553316485Sdavidcs/* In order to maintain endianity in the mailbox hsi, we want to keep using */ 554316485Sdavidcs/* u32. The fw must have the VF right after the PF since this is how it */ 555316485Sdavidcs/* access arrays(it expects always the VF to reside after the PF, and that */ 556316485Sdavidcs/* makes the calculation much easier for it. ) */ 557316485Sdavidcs/* In order to answer both limitations, and keep the struct small, the code */ 558316485Sdavidcs/* will abuse the structure defined here to achieve the actual partition */ 559316485Sdavidcs/* above */ 560316485Sdavidcs/****************************************************************************/ 561316485Sdavidcsstruct fw_flr_mb { 562316485Sdavidcs u32 aggint; 563316485Sdavidcs u32 opgen_addr; 564316485Sdavidcs u32 accum_ack; /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */ 565316485Sdavidcs#define ACCUM_ACK_PF_BASE 0 566316485Sdavidcs#define ACCUM_ACK_PF_SHIFT 0 567316485Sdavidcs 568316485Sdavidcs#define ACCUM_ACK_VF_BASE 8 569316485Sdavidcs#define ACCUM_ACK_VF_SHIFT 3 570316485Sdavidcs 571316485Sdavidcs#define ACCUM_ACK_IOV_DIS_BASE 256 572316485Sdavidcs#define ACCUM_ACK_IOV_DIS_SHIFT 8 573316485Sdavidcs 574316485Sdavidcs}; 575316485Sdavidcs 576316485Sdavidcsstruct public_path { 577316485Sdavidcs struct fw_flr_mb flr_mb; 578316485Sdavidcs /* 579316485Sdavidcs * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 580316485Sdavidcs * which were disabled/flred 581316485Sdavidcs */ 582316485Sdavidcs u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */ 583316485Sdavidcs 584316485Sdavidcs u32 process_kill; /* Reset on mcp reset, and incremented for eveny process kill event. */ 585316485Sdavidcs#define PROCESS_KILL_COUNTER_MASK 0x0000ffff 586320164Sdavidcs#define PROCESS_KILL_COUNTER_OFFSET 0 587316485Sdavidcs#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 588320164Sdavidcs#define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 589316485Sdavidcs#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id*32 + aeu_bit) 590316485Sdavidcs}; 591316485Sdavidcs 592316485Sdavidcs/**************************************/ 593316485Sdavidcs/* */ 594316485Sdavidcs/* P U B L I C P O R T */ 595316485Sdavidcs/* */ 596316485Sdavidcs/**************************************/ 597316485Sdavidcs#define FC_NPIV_WWPN_SIZE 8 598316485Sdavidcs#define FC_NPIV_WWNN_SIZE 8 599316485Sdavidcsstruct dci_npiv_settings { 600316485Sdavidcs u8 npiv_wwpn[FC_NPIV_WWPN_SIZE]; 601316485Sdavidcs u8 npiv_wwnn[FC_NPIV_WWNN_SIZE]; 602316485Sdavidcs}; 603316485Sdavidcs 604316485Sdavidcsstruct dci_fc_npiv_cfg { 605316485Sdavidcs /* hdr used internally by the MFW */ 606316485Sdavidcs u32 hdr; 607316485Sdavidcs u32 num_of_npiv; 608316485Sdavidcs}; 609316485Sdavidcs 610316485Sdavidcs#define MAX_NUMBER_NPIV 64 611316485Sdavidcsstruct dci_fc_npiv_tbl { 612316485Sdavidcs struct dci_fc_npiv_cfg fc_npiv_cfg; 613316485Sdavidcs struct dci_npiv_settings settings[MAX_NUMBER_NPIV]; 614316485Sdavidcs}; 615316485Sdavidcs 616316485Sdavidcs/**************************************************************************** 617316485Sdavidcs * Driver <-> FW Mailbox * 618316485Sdavidcs ****************************************************************************/ 619316485Sdavidcs 620316485Sdavidcsstruct public_port { 621316485Sdavidcs u32 validity_map; /* 0x0 (4*2 = 0x8) */ 622316485Sdavidcs 623316485Sdavidcs /* validity bits */ 624316485Sdavidcs#define MCP_VALIDITY_PCI_CFG 0x00100000 625316485Sdavidcs#define MCP_VALIDITY_MB 0x00200000 626316485Sdavidcs#define MCP_VALIDITY_DEV_INFO 0x00400000 627316485Sdavidcs#define MCP_VALIDITY_RESERVED 0x00000007 628316485Sdavidcs 629316485Sdavidcs /* One licensing bit should be set */ 630316485Sdavidcs#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd ? license */ 631316485Sdavidcs#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 632316485Sdavidcs#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 633316485Sdavidcs#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 634316485Sdavidcs 635316485Sdavidcs /* Active MFW */ 636316485Sdavidcs#define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 637316485Sdavidcs#define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 638316485Sdavidcs#define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040 639316485Sdavidcs#define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 640316485Sdavidcs 641316485Sdavidcs u32 link_status; 642316485Sdavidcs#define LINK_STATUS_LINK_UP 0x00000001 643316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 644316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1<<1) 645316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2<<1) 646316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3<<1) 647316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4<<1) 648316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5<<1) 649316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6<<1) 650316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7<<1) 651316485Sdavidcs#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8<<1) 652316485Sdavidcs#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 653316485Sdavidcs#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 654316485Sdavidcs#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 655316485Sdavidcs#define LINK_STATUS_PFC_ENABLED 0x00000100 656316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 657316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 658316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 659316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 660316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 661316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 662316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 663316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 664316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 665316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 666316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 667316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 668316485Sdavidcs#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 669316485Sdavidcs#define LINK_STATUS_SFP_TX_FAULT 0x00100000 670316485Sdavidcs#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 671316485Sdavidcs#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 672316485Sdavidcs#define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 673316485Sdavidcs#define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 674316485Sdavidcs#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 675316485Sdavidcs#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 676316485Sdavidcs#define LINK_STATUS_FEC_MODE_MASK 0x38000000 677316485Sdavidcs#define LINK_STATUS_FEC_MODE_NONE (0<<27) 678316485Sdavidcs#define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1<<27) 679316485Sdavidcs#define LINK_STATUS_FEC_MODE_RS_CL91 (2<<27) 680316485Sdavidcs#define LINK_STATUS_EXT_PHY_LINK_UP 0x40000000 681316485Sdavidcs 682316485Sdavidcs u32 link_status1; 683337517Sdavidcs#define LP_PRESENCE_STATUS_OFFSET 0 684337517Sdavidcs#define LP_PRESENCE_STATUS_MASK 0x3 685337517Sdavidcs#define LP_PRESENCE_UNKNOWN 0x0 686337517Sdavidcs#define LP_PRESENCE_PROBING 0x1 687337517Sdavidcs#define LP_PRESENT 0x2 688337517Sdavidcs#define LP_NOT_PRESENT 0x3 689337517Sdavidcs 690316485Sdavidcs u32 ext_phy_fw_version; 691316485Sdavidcs u32 drv_phy_cfg_addr; /* Points to struct eth_phy_cfg (For READ-ONLY) */ 692316485Sdavidcs 693316485Sdavidcs u32 port_stx; 694316485Sdavidcs 695316485Sdavidcs u32 stat_nig_timer; 696316485Sdavidcs 697316485Sdavidcs struct port_mf_cfg port_mf_config; 698316485Sdavidcs struct port_stats stats; 699316485Sdavidcs 700316485Sdavidcs u32 media_type; 701316485Sdavidcs#define MEDIA_UNSPECIFIED 0x0 702316485Sdavidcs#define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */ 703316485Sdavidcs#define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */ 704316485Sdavidcs#define MEDIA_DA_TWINAX 0x3 705316485Sdavidcs#define MEDIA_BASE_T 0x4 706316485Sdavidcs#define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */ 707316485Sdavidcs#define MEDIA_MODULE_FIBER 0x6 708316485Sdavidcs#define MEDIA_KR 0xf0 709316485Sdavidcs#define MEDIA_NOT_PRESENT 0xff 710316485Sdavidcs 711316485Sdavidcs u32 lfa_status; 712316485Sdavidcs#define LFA_LINK_FLAP_REASON_OFFSET 0 713316485Sdavidcs#define LFA_LINK_FLAP_REASON_MASK 0x000000ff 714316485Sdavidcs#define LFA_NO_REASON (0<<0) 715316485Sdavidcs#define LFA_LINK_DOWN (1<<0) 716316485Sdavidcs#define LFA_FORCE_INIT (1<<1) 717316485Sdavidcs#define LFA_LOOPBACK_MISMATCH (1<<2) 718316485Sdavidcs#define LFA_SPEED_MISMATCH (1<<3) 719316485Sdavidcs#define LFA_FLOW_CTRL_MISMATCH (1<<4) 720316485Sdavidcs#define LFA_ADV_SPEED_MISMATCH (1<<5) 721316485Sdavidcs#define LFA_EEE_MISMATCH (1<<6) 722316485Sdavidcs#define LFA_LINK_MODES_MISMATCH (1<<7) 723316485Sdavidcs#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 724316485Sdavidcs#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 725316485Sdavidcs#define LINK_FLAP_COUNT_OFFSET 16 726316485Sdavidcs#define LINK_FLAP_COUNT_MASK 0x00ff0000 727316485Sdavidcs 728316485Sdavidcs u32 link_change_count; 729316485Sdavidcs 730316485Sdavidcs /* LLDP params */ 731316485Sdavidcs struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; // offset: 536 bytes? 732316485Sdavidcs struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 733316485Sdavidcs struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 734316485Sdavidcs 735316485Sdavidcs /* DCBX related MIB */ 736316485Sdavidcs struct dcbx_local_params local_admin_dcbx_mib; 737316485Sdavidcs struct dcbx_mib remote_dcbx_mib; 738316485Sdavidcs struct dcbx_mib operational_dcbx_mib; 739316485Sdavidcs 740316485Sdavidcs /* FC_NPIV table offset & size in NVRAM value of 0 means not present */ 741316485Sdavidcs u32 fc_npiv_nvram_tbl_addr; 742316485Sdavidcs#define NPIV_TBL_INVALID_ADDR 0xFFFFFFFF 743316485Sdavidcs 744316485Sdavidcs u32 fc_npiv_nvram_tbl_size; 745316485Sdavidcs u32 transceiver_data; 746316485Sdavidcs#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 747320164Sdavidcs#define ETH_TRANSCEIVER_STATE_OFFSET 0x0 748316485Sdavidcs#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00 749316485Sdavidcs#define ETH_TRANSCEIVER_STATE_PRESENT 0x01 750316485Sdavidcs#define ETH_TRANSCEIVER_STATE_VALID 0x03 751316485Sdavidcs#define ETH_TRANSCEIVER_STATE_UPDATING 0x08 752316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 753320164Sdavidcs#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8 754316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_NONE 0x00 755316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF 756316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 /* 1G Passive copper cable */ 757316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 /* 1G Active copper cable */ 758316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 759316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 760316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 761316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 762316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 763316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 764316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 /* 10G Passive copper cable */ 765316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a /* 10G Active copper cable */ 766316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 767316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 768316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 769316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 770316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f /* Active optical cable */ 771316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 772316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 773316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 774316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 /* Active copper cable */ 775316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 776316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 777316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 /* 25G Passive copper cable - short */ 778316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 /* 25G Active copper cable - short */ 779316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 /* 25G Passive copper cable - medium */ 780316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 /* 25G Active copper cable - medium */ 781316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a /* 25G Passive copper cable - long */ 782316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b /* 25G Active copper cable - long */ 783316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 784316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 785316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 786316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 787316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 788337517Sdavidcs#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 789337517Sdavidcs#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 790316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 791316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 792316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 793316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 794316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 795316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 796316485Sdavidcs#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 797316485Sdavidcs u32 wol_info; 798316485Sdavidcs u32 wol_pkt_len; 799316485Sdavidcs u32 wol_pkt_details; 800316485Sdavidcs struct dcb_dscp_map dcb_dscp_map; 801316485Sdavidcs 802316485Sdavidcs u32 eee_status; 803316485Sdavidcs#define EEE_ACTIVE_BIT (1<<0) /* Set when EEE negotiation is complete. */ 804316485Sdavidcs 805316485Sdavidcs#define EEE_LD_ADV_STATUS_MASK 0x000000f0 /* Shows the Local Device EEE capabilities */ 806320164Sdavidcs#define EEE_LD_ADV_STATUS_OFFSET 4 807316485Sdavidcs #define EEE_1G_ADV (1<<1) 808316485Sdavidcs #define EEE_10G_ADV (1<<2) 809316485Sdavidcs#define EEE_LP_ADV_STATUS_MASK 0x00000f00 /* Same values as in EEE_LD_ADV, but for Link Parter */ 810320164Sdavidcs#define EEE_LP_ADV_STATUS_OFFSET 8 811316485Sdavidcs 812337517Sdavidcs#define EEE_SUPPORTED_SPEED_MASK 0x0000f000 /* Supported speeds for EEE */ 813337517Sdavidcs#define EEE_SUPPORTED_SPEED_OFFSET 12 814337517Sdavidcs #define EEE_1G_SUPPORTED (1 << 1) 815337517Sdavidcs #define EEE_10G_SUPPORTED (1 << 2) 816337517Sdavidcs 817316485Sdavidcs u32 eee_remote; /* Used for EEE in LLDP */ 818316485Sdavidcs#define EEE_REMOTE_TW_TX_MASK 0x0000ffff 819320164Sdavidcs#define EEE_REMOTE_TW_TX_OFFSET 0 820316485Sdavidcs#define EEE_REMOTE_TW_RX_MASK 0xffff0000 821320164Sdavidcs#define EEE_REMOTE_TW_RX_OFFSET 16 822316485Sdavidcs 823316485Sdavidcs u32 module_info; 824316485Sdavidcs#define ETH_TRANSCEIVER_MONITORING_TYPE_MASK 0x000000FF 825316485Sdavidcs#define ETH_TRANSCEIVER_MONITORING_TYPE_OFFSET 0 826316485Sdavidcs#define ETH_TRANSCEIVER_ADDR_CHNG_REQUIRED (1 << 2) 827316485Sdavidcs#define ETH_TRANSCEIVER_RCV_PWR_MEASURE_TYPE (1 << 3) 828316485Sdavidcs#define ETH_TRANSCEIVER_EXTERNALLY_CALIBRATED (1 << 4) 829316485Sdavidcs#define ETH_TRANSCEIVER_INTERNALLY_CALIBRATED (1 << 5) 830316485Sdavidcs#define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) 831316485Sdavidcs#define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 832316485Sdavidcs#define ETH_TRANSCEIVER_IDENT_OFFSET 8 833337517Sdavidcs 834337517Sdavidcs u32 oem_cfg_port; 835337517Sdavidcs#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 836337517Sdavidcs#define OEM_CFG_CHANNEL_TYPE_OFFSET 0 837337517Sdavidcs#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 838337517Sdavidcs#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 839337517Sdavidcs 840337517Sdavidcs#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 841337517Sdavidcs#define OEM_CFG_SCHED_TYPE_OFFSET 2 842337517Sdavidcs#define OEM_CFG_SCHED_TYPE_ETS 0x1 843337517Sdavidcs#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 844337517Sdavidcs 845337517Sdavidcs struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; 846337517Sdavidcs u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; 847316485Sdavidcs}; 848316485Sdavidcs 849316485Sdavidcs/**************************************/ 850316485Sdavidcs/* */ 851316485Sdavidcs/* P U B L I C F U N C */ 852316485Sdavidcs/* */ 853316485Sdavidcs/**************************************/ 854316485Sdavidcs 855316485Sdavidcsstruct public_func { 856316485Sdavidcs 857316485Sdavidcs u32 iscsi_boot_signature; 858316485Sdavidcs u32 iscsi_boot_block_offset; 859316485Sdavidcs 860316485Sdavidcs /* MTU size per funciton is needed for the OV feature */ 861316485Sdavidcs u32 mtu_size; 862316485Sdavidcs /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */ 863316485Sdavidcs /* For PCP values 0-3 use the map lower */ 864316485Sdavidcs /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1, 865316485Sdavidcs * 0x0000FF00 - PCP 2, 0x000000FF PCP 3 866316485Sdavidcs */ 867316485Sdavidcs u32 c2s_pcp_map_lower; 868316485Sdavidcs /* For PCP values 4-7 use the map upper */ 869316485Sdavidcs /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5, 870316485Sdavidcs * 0x0000FF00 - PCP 6, 0x000000FF PCP 7 871316485Sdavidcs */ 872316485Sdavidcs u32 c2s_pcp_map_upper; 873316485Sdavidcs 874316485Sdavidcs /* For PCP default value get the MSB byte of the map default */ 875316485Sdavidcs u32 c2s_pcp_map_default; 876316485Sdavidcs 877337517Sdavidcs /* For generic inter driver communication channel messages between PFs via MFW*/ 878337517Sdavidcs struct generic_idc_msg_s generic_idc_msg; 879316485Sdavidcs 880337517Sdavidcs u32 num_of_msix; 881337517Sdavidcs 882316485Sdavidcs // replace old mf_cfg 883316485Sdavidcs u32 config; 884316485Sdavidcs /* E/R/I/D */ 885316485Sdavidcs /* function 0 of each port cannot be hidden */ 886316485Sdavidcs#define FUNC_MF_CFG_FUNC_HIDE 0x00000001 887316485Sdavidcs#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 888320164Sdavidcs#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_OFFSET 0x00000001 889316485Sdavidcs 890316485Sdavidcs 891316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 892320164Sdavidcs#define FUNC_MF_CFG_PROTOCOL_OFFSET 4 893316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 894316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 895316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 896316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 897316485Sdavidcs#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 898316485Sdavidcs 899316485Sdavidcs /* MINBW, MAXBW */ 900316485Sdavidcs /* value range - 0..100, increments in 1 % */ 901316485Sdavidcs#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 902320164Sdavidcs#define FUNC_MF_CFG_MIN_BW_OFFSET 8 903316485Sdavidcs#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 904316485Sdavidcs#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 905320164Sdavidcs#define FUNC_MF_CFG_MAX_BW_OFFSET 16 906316485Sdavidcs#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 907316485Sdavidcs 908316485Sdavidcs /*RDMA PROTOCL*/ 909316485Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_MASK 0x03000000 910320164Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_OFFSET 24 911316485Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_NONE 0x00000000 912316485Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_ROCE 0x01000000 913316485Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_IWARP 0x02000000 914316485Sdavidcs /*for future support*/ 915316485Sdavidcs#define FUNC_MF_CFG_RDMA_PROTOCOL_BOTH 0x03000000 916316485Sdavidcs 917316485Sdavidcs#define FUNC_MF_CFG_BOOT_MODE_MASK 0x0C000000 918320164Sdavidcs#define FUNC_MF_CFG_BOOT_MODE_OFFSET 26 919316485Sdavidcs#define FUNC_MF_CFG_BOOT_MODE_BIOS_CTRL 0x00000000 920316485Sdavidcs#define FUNC_MF_CFG_BOOT_MODE_DISABLED 0x04000000 921316485Sdavidcs#define FUNC_MF_CFG_BOOT_MODE_ENABLED 0x08000000 922316485Sdavidcs 923316485Sdavidcs u32 status; 924337517Sdavidcs#define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 925337517Sdavidcs#define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 926337517Sdavidcs#define FUNC_STATUS_FORCED_LINK 0x00000004 927316485Sdavidcs 928316485Sdavidcs u32 mac_upper; /* MAC */ 929316485Sdavidcs#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 930320164Sdavidcs#define FUNC_MF_CFG_UPPERMAC_OFFSET 0 931316485Sdavidcs#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 932316485Sdavidcs u32 mac_lower; 933316485Sdavidcs#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 934316485Sdavidcs 935316485Sdavidcs u32 fcoe_wwn_port_name_upper; 936316485Sdavidcs u32 fcoe_wwn_port_name_lower; 937316485Sdavidcs 938316485Sdavidcs u32 fcoe_wwn_node_name_upper; 939316485Sdavidcs u32 fcoe_wwn_node_name_lower; 940316485Sdavidcs 941316485Sdavidcs u32 ovlan_stag; /* tags */ 942316485Sdavidcs#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 943320164Sdavidcs#define FUNC_MF_CFG_OV_STAG_OFFSET 0 944316485Sdavidcs#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 945316485Sdavidcs 946316485Sdavidcs u32 pf_allocation; /* vf per pf */ 947316485Sdavidcs 948316485Sdavidcs u32 preserve_data; /* Will be used bt CCM */ 949316485Sdavidcs 950316485Sdavidcs u32 driver_last_activity_ts; 951316485Sdavidcs 952316485Sdavidcs /* 953316485Sdavidcs * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 954316485Sdavidcs * VFs 955316485Sdavidcs */ 956316485Sdavidcs u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */ 957316485Sdavidcs 958316485Sdavidcs u32 drv_id; 959316485Sdavidcs#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 960320164Sdavidcs#define DRV_ID_PDA_COMP_VER_OFFSET 0 961316485Sdavidcs 962316485Sdavidcs#define LOAD_REQ_HSI_VERSION 2 963316485Sdavidcs#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 964320164Sdavidcs#define DRV_ID_MCP_HSI_VER_OFFSET 16 965320164Sdavidcs#define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << DRV_ID_MCP_HSI_VER_OFFSET) 966316485Sdavidcs 967316485Sdavidcs#define DRV_ID_DRV_TYPE_MASK 0x7f000000 968320164Sdavidcs#define DRV_ID_DRV_TYPE_OFFSET 24 969320164Sdavidcs#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_OFFSET) 970320164Sdavidcs#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_OFFSET) 971320164Sdavidcs#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_OFFSET) 972320164Sdavidcs#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_OFFSET) 973320164Sdavidcs#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_OFFSET) 974320164Sdavidcs#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_OFFSET) 975320164Sdavidcs#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_OFFSET) 976320164Sdavidcs#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_OFFSET) 977320164Sdavidcs#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_OFFSET) 978316485Sdavidcs 979316485Sdavidcs#define DRV_ID_DRV_TYPE_OS (DRV_ID_DRV_TYPE_LINUX | DRV_ID_DRV_TYPE_WINDOWS | \ 980316485Sdavidcs DRV_ID_DRV_TYPE_SOLARIS | DRV_ID_DRV_TYPE_VMWARE | \ 981316485Sdavidcs DRV_ID_DRV_TYPE_FREEBSD | DRV_ID_DRV_TYPE_AIX) 982316485Sdavidcs 983316485Sdavidcs#define DRV_ID_DRV_INIT_HW_MASK 0x80000000 984320164Sdavidcs#define DRV_ID_DRV_INIT_HW_OFFSET 31 985320164Sdavidcs#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) 986337517Sdavidcs 987337517Sdavidcs u32 oem_cfg_func; 988337517Sdavidcs#define OEM_CFG_FUNC_TC_MASK 0x0000000F 989337517Sdavidcs#define OEM_CFG_FUNC_TC_OFFSET 0 990337517Sdavidcs#define OEM_CFG_FUNC_TC_0 0x0 991337517Sdavidcs#define OEM_CFG_FUNC_TC_1 0x1 992337517Sdavidcs#define OEM_CFG_FUNC_TC_2 0x2 993337517Sdavidcs#define OEM_CFG_FUNC_TC_3 0x3 994337517Sdavidcs#define OEM_CFG_FUNC_TC_4 0x4 995337517Sdavidcs#define OEM_CFG_FUNC_TC_5 0x5 996337517Sdavidcs#define OEM_CFG_FUNC_TC_6 0x6 997337517Sdavidcs#define OEM_CFG_FUNC_TC_7 0x7 998337517Sdavidcs 999337517Sdavidcs#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 1000337517Sdavidcs#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 1001337517Sdavidcs#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 1002337517Sdavidcs#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 1003316485Sdavidcs}; 1004316485Sdavidcs 1005316485Sdavidcs/**************************************/ 1006316485Sdavidcs/* */ 1007316485Sdavidcs/* P U B L I C M B */ 1008316485Sdavidcs/* */ 1009316485Sdavidcs/**************************************/ 1010316485Sdavidcs/* This is the only section that the driver can write to, and each */ 1011316485Sdavidcs/* Basically each driver request to set feature parameters, 1012316485Sdavidcs * will be done using a different command, which will be linked 1013316485Sdavidcs * to a specific data structure from the union below. 1014316485Sdavidcs * For huge strucuture, the common blank structure should be used. 1015316485Sdavidcs */ 1016316485Sdavidcs 1017316485Sdavidcsstruct mcp_mac { 1018316485Sdavidcs u32 mac_upper; /* Upper 16 bits are always zeroes */ 1019316485Sdavidcs u32 mac_lower; 1020316485Sdavidcs}; 1021316485Sdavidcs 1022316485Sdavidcsstruct mcp_file_att { 1023316485Sdavidcs u32 nvm_start_addr; 1024316485Sdavidcs u32 len; 1025316485Sdavidcs}; 1026316485Sdavidcs 1027316485Sdavidcsstruct bist_nvm_image_att { 1028316485Sdavidcs u32 return_code; 1029316485Sdavidcs u32 image_type; /* Image type */ 1030316485Sdavidcs u32 nvm_start_addr; /* NVM address of the image */ 1031316485Sdavidcs u32 len; /* Include CRC */ 1032316485Sdavidcs}; 1033316485Sdavidcs 1034316485Sdavidcs#define MCP_DRV_VER_STR_SIZE 16 1035316485Sdavidcs#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 1036316485Sdavidcs#define MCP_DRV_NVM_BUF_LEN 32 1037316485Sdavidcsstruct drv_version_stc { 1038316485Sdavidcs u32 version; 1039316485Sdavidcs u8 name[MCP_DRV_VER_STR_SIZE - 4]; 1040316485Sdavidcs}; 1041316485Sdavidcs 1042316485Sdavidcs/* statistics for ncsi */ 1043316485Sdavidcsstruct lan_stats_stc { 1044316485Sdavidcs u64 ucast_rx_pkts; 1045316485Sdavidcs u64 ucast_tx_pkts; 1046316485Sdavidcs u32 fcs_err; 1047316485Sdavidcs u32 rserved; 1048316485Sdavidcs}; 1049316485Sdavidcs 1050316485Sdavidcsstruct fcoe_stats_stc { 1051316485Sdavidcs u64 rx_pkts; 1052316485Sdavidcs u64 tx_pkts; 1053316485Sdavidcs u32 fcs_err; 1054316485Sdavidcs u32 login_failure; 1055316485Sdavidcs}; 1056316485Sdavidcs 1057316485Sdavidcsstruct iscsi_stats_stc { 1058316485Sdavidcs u64 rx_pdus; 1059316485Sdavidcs u64 tx_pdus; 1060316485Sdavidcs u64 rx_bytes; 1061316485Sdavidcs u64 tx_bytes; 1062316485Sdavidcs}; 1063316485Sdavidcs 1064316485Sdavidcsstruct rdma_stats_stc { 1065316485Sdavidcs u64 rx_pkts; 1066316485Sdavidcs u64 tx_pkts; 1067316485Sdavidcs u64 rx_bytes; 1068316485Sdavidcs u64 tx_bytes; 1069316485Sdavidcs}; 1070316485Sdavidcs 1071316485Sdavidcsstruct ocbb_data_stc { 1072316485Sdavidcs u32 ocbb_host_addr; 1073316485Sdavidcs u32 ocsd_host_addr; 1074316485Sdavidcs u32 ocsd_req_update_interval; 1075316485Sdavidcs}; 1076316485Sdavidcs 1077316485Sdavidcs#define MAX_NUM_OF_SENSORS 7 1078316485Sdavidcs#define MFW_SENSOR_LOCATION_INTERNAL 1 1079316485Sdavidcs#define MFW_SENSOR_LOCATION_EXTERNAL 2 1080316485Sdavidcs#define MFW_SENSOR_LOCATION_SFP 3 1081316485Sdavidcs 1082320164Sdavidcs#define SENSOR_LOCATION_OFFSET 0 1083316485Sdavidcs#define SENSOR_LOCATION_MASK 0x000000ff 1084320164Sdavidcs#define THRESHOLD_HIGH_OFFSET 8 1085316485Sdavidcs#define THRESHOLD_HIGH_MASK 0x0000ff00 1086320164Sdavidcs#define CRITICAL_TEMPERATURE_OFFSET 16 1087316485Sdavidcs#define CRITICAL_TEMPERATURE_MASK 0x00ff0000 1088320164Sdavidcs#define CURRENT_TEMP_OFFSET 24 1089316485Sdavidcs#define CURRENT_TEMP_MASK 0xff000000 1090316485Sdavidcsstruct temperature_status_stc { 1091316485Sdavidcs u32 num_of_sensors; 1092316485Sdavidcs u32 sensor[MAX_NUM_OF_SENSORS]; 1093316485Sdavidcs}; 1094316485Sdavidcs 1095316485Sdavidcs/* crash dump configuration header */ 1096316485Sdavidcsstruct mdump_config_stc { 1097316485Sdavidcs u32 version; 1098316485Sdavidcs u32 config; 1099316485Sdavidcs u32 epoc; 1100316485Sdavidcs u32 num_of_logs; 1101316485Sdavidcs u32 valid_logs; 1102316485Sdavidcs}; 1103316485Sdavidcs 1104316485Sdavidcsenum resource_id_enum { 1105337517Sdavidcs RESOURCE_NUM_SB_E = 0, 1106316485Sdavidcs RESOURCE_NUM_L2_QUEUE_E = 1, 1107316485Sdavidcs RESOURCE_NUM_VPORT_E = 2, 1108337517Sdavidcs RESOURCE_NUM_VMQ_E = 3, 1109316485Sdavidcs RESOURCE_FACTOR_NUM_RSS_PF_E = 4, /* Not a real resource!! it's a factor used to calculate others */ 1110316485Sdavidcs RESOURCE_FACTOR_RSS_PER_VF_E = 5, /* Not a real resource!! it's a factor used to calculate others */ 1111337517Sdavidcs RESOURCE_NUM_RL_E = 6, 1112337517Sdavidcs RESOURCE_NUM_PQ_E = 7, 1113337517Sdavidcs RESOURCE_NUM_VF_E = 8, 1114316485Sdavidcs RESOURCE_VFC_FILTER_E = 9, 1115337517Sdavidcs RESOURCE_ILT_E = 10, 1116337517Sdavidcs RESOURCE_CQS_E = 11, 1117316485Sdavidcs RESOURCE_GFT_PROFILES_E = 12, 1118337517Sdavidcs RESOURCE_NUM_TC_E = 13, 1119316485Sdavidcs RESOURCE_NUM_RSS_ENGINES_E = 14, 1120316485Sdavidcs RESOURCE_LL2_QUEUE_E = 15, 1121316485Sdavidcs RESOURCE_RDMA_STATS_QUEUE_E = 16, 1122337517Sdavidcs RESOURCE_BDQ_E = 17, 1123316485Sdavidcs RESOURCE_MAX_NUM, 1124316485Sdavidcs RESOURCE_NUM_INVALID = 0xFFFFFFFF 1125316485Sdavidcs}; 1126316485Sdavidcs 1127316485Sdavidcs/* Resource ID is to be filled by the driver in the MB request 1128316485Sdavidcs * Size, offset & flags to be filled by the MFW in the MB response 1129316485Sdavidcs */ 1130316485Sdavidcsstruct resource_info { 1131316485Sdavidcs enum resource_id_enum res_id; 1132316485Sdavidcs u32 size; /* number of allocated resources */ 1133316485Sdavidcs u32 offset; /* Offset of the 1st resource */ 1134316485Sdavidcs u32 vf_size; 1135316485Sdavidcs u32 vf_offset; 1136316485Sdavidcs u32 flags; 1137316485Sdavidcs#define RESOURCE_ELEMENT_STRICT (1 << 0) 1138316485Sdavidcs}; 1139316485Sdavidcs 1140316485Sdavidcsstruct mcp_wwn { 1141316485Sdavidcs u32 wwn_upper; 1142316485Sdavidcs u32 wwn_lower; 1143316485Sdavidcs}; 1144316485Sdavidcs 1145316485Sdavidcs#define DRV_ROLE_NONE 0 1146316485Sdavidcs#define DRV_ROLE_PREBOOT 1 1147316485Sdavidcs#define DRV_ROLE_OS 2 1148316485Sdavidcs#define DRV_ROLE_KDUMP 3 1149316485Sdavidcs 1150316485Sdavidcsstruct load_req_stc { 1151316485Sdavidcs u32 drv_ver_0; 1152316485Sdavidcs u32 drv_ver_1; 1153316485Sdavidcs u32 fw_ver; 1154316485Sdavidcs u32 misc0; 1155316485Sdavidcs#define LOAD_REQ_ROLE_MASK 0x000000FF 1156320164Sdavidcs#define LOAD_REQ_ROLE_OFFSET 0 1157316485Sdavidcs#define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 1158320164Sdavidcs#define LOAD_REQ_LOCK_TO_OFFSET 8 1159316485Sdavidcs#define LOAD_REQ_LOCK_TO_DEFAULT 0 1160316485Sdavidcs#define LOAD_REQ_LOCK_TO_NONE 255 1161316485Sdavidcs#define LOAD_REQ_FORCE_MASK 0x000F0000 1162320164Sdavidcs#define LOAD_REQ_FORCE_OFFSET 16 1163316485Sdavidcs#define LOAD_REQ_FORCE_NONE 0 1164316485Sdavidcs#define LOAD_REQ_FORCE_PF 1 1165316485Sdavidcs#define LOAD_REQ_FORCE_ALL 2 1166316485Sdavidcs#define LOAD_REQ_FLAGS0_MASK 0x00F00000 1167320164Sdavidcs#define LOAD_REQ_FLAGS0_OFFSET 20 1168316485Sdavidcs#define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 1169316485Sdavidcs}; 1170316485Sdavidcs 1171316485Sdavidcsstruct load_rsp_stc { 1172316485Sdavidcs u32 drv_ver_0; 1173316485Sdavidcs u32 drv_ver_1; 1174316485Sdavidcs u32 fw_ver; 1175316485Sdavidcs u32 misc0; 1176316485Sdavidcs#define LOAD_RSP_ROLE_MASK 0x000000FF 1177320164Sdavidcs#define LOAD_RSP_ROLE_OFFSET 0 1178316485Sdavidcs#define LOAD_RSP_HSI_MASK 0x0000FF00 1179320164Sdavidcs#define LOAD_RSP_HSI_OFFSET 8 1180316485Sdavidcs#define LOAD_RSP_FLAGS0_MASK 0x000F0000 1181320164Sdavidcs#define LOAD_RSP_FLAGS0_OFFSET 16 1182316485Sdavidcs#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 1183316485Sdavidcs}; 1184316485Sdavidcs 1185316485Sdavidcsstruct mdump_retain_data_stc { 1186316485Sdavidcs u32 valid; 1187316485Sdavidcs u32 epoch; 1188316485Sdavidcs u32 pf; 1189316485Sdavidcs u32 status; 1190316485Sdavidcs}; 1191316485Sdavidcs 1192337517Sdavidcsstruct attribute_cmd_write_stc { 1193337517Sdavidcs u32 val; 1194337517Sdavidcs u32 mask; 1195337517Sdavidcs u32 offset; 1196337517Sdavidcs}; 1197337517Sdavidcs 1198337517Sdavidcsstruct lldp_stats_stc { 1199337517Sdavidcs u32 tx_frames_total; 1200337517Sdavidcs u32 rx_frames_total; 1201337517Sdavidcs u32 rx_frames_discarded; 1202337517Sdavidcs u32 rx_age_outs; 1203337517Sdavidcs}; 1204337517Sdavidcs 1205316485Sdavidcsunion drv_union_data { 1206316485Sdavidcs struct mcp_mac wol_mac; /* UNLOAD_DONE */ 1207316485Sdavidcs 1208316485Sdavidcs /* This configuration should be set by the driver for the LINK_SET command. */ 1209316485Sdavidcs struct eth_phy_cfg drv_phy_cfg; 1210316485Sdavidcs 1211316485Sdavidcs struct mcp_val64 val64; /* For PHY / AVS commands */ 1212316485Sdavidcs 1213316485Sdavidcs u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 1214316485Sdavidcs 1215316485Sdavidcs struct mcp_file_att file_att; 1216316485Sdavidcs 1217316485Sdavidcs u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 1218316485Sdavidcs 1219316485Sdavidcs struct drv_version_stc drv_version; 1220316485Sdavidcs 1221316485Sdavidcs struct lan_stats_stc lan_stats; 1222316485Sdavidcs struct fcoe_stats_stc fcoe_stats; 1223316485Sdavidcs struct iscsi_stats_stc iscsi_stats; 1224316485Sdavidcs struct rdma_stats_stc rdma_stats; 1225316485Sdavidcs struct ocbb_data_stc ocbb_info; 1226316485Sdavidcs struct temperature_status_stc temp_info; 1227316485Sdavidcs struct resource_info resource; 1228316485Sdavidcs struct bist_nvm_image_att nvm_image_att; 1229316485Sdavidcs struct mdump_config_stc mdump_config; 1230316485Sdavidcs struct mcp_mac lldp_mac; 1231316485Sdavidcs struct mcp_wwn fcoe_fabric_name; 1232316485Sdavidcs u32 dword; 1233316485Sdavidcs 1234316485Sdavidcs struct load_req_stc load_req; 1235316485Sdavidcs struct load_rsp_stc load_rsp; 1236316485Sdavidcs struct mdump_retain_data_stc mdump_retain; 1237337517Sdavidcs struct attribute_cmd_write_stc attribute_cmd_write; 1238337517Sdavidcs struct lldp_stats_stc lldp_stats; 1239316485Sdavidcs /* ... */ 1240316485Sdavidcs}; 1241316485Sdavidcs 1242316485Sdavidcsstruct public_drv_mb { 1243316485Sdavidcs 1244316485Sdavidcs u32 drv_mb_header; 1245316485Sdavidcs#define DRV_MSG_CODE_MASK 0xffff0000 1246316485Sdavidcs#define DRV_MSG_CODE_LOAD_REQ 0x10000000 1247316485Sdavidcs#define DRV_MSG_CODE_LOAD_DONE 0x11000000 1248316485Sdavidcs#define DRV_MSG_CODE_INIT_HW 0x12000000 1249316485Sdavidcs#define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 1250316485Sdavidcs#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 1251316485Sdavidcs#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1252316485Sdavidcs#define DRV_MSG_CODE_INIT_PHY 0x22000000 1253316485Sdavidcs /* Params - FORCE - Reinitialize the link regardless of LFA */ 1254316485Sdavidcs /* - DONT_CARE - Don't flap the link if up */ 1255316485Sdavidcs#define DRV_MSG_CODE_LINK_RESET 0x23000000 1256316485Sdavidcs 1257316485Sdavidcs#define DRV_MSG_CODE_SET_LLDP 0x24000000 1258337517Sdavidcs#define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 1259316485Sdavidcs#define DRV_MSG_CODE_SET_DCBX 0x25000000 1260316485Sdavidcs /* OneView feature driver HSI*/ 1261316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 1262316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 1263316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 1264316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 1265316485Sdavidcs#define DRV_MSG_CODE_NIG_DRAIN 0x30000000 1266316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 1267316485Sdavidcs#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 1268316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 1269316485Sdavidcs#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 /* DRV_MB Param: driver version supp, FW_MB param: MFW version supp, data: struct resource_info */ 1270316485Sdavidcs#define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 1271316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 1272316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 1273316485Sdavidcs#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 1274316485Sdavidcs#define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 1275316485Sdavidcs#define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 1276316485Sdavidcs#define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 1277316485Sdavidcs#define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 1278316485Sdavidcs#define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 1279337517Sdavidcs#define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 1280337517Sdavidcs#define DRV_MSG_CODE_GET_LLDP_STATS 0x42000000 1281337517Sdavidcs#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 /* params [31:8] - reserved, [7:0] - bitmap */ 1282316485Sdavidcs 1283316485Sdavidcs#define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 /*deprecated don't use*/ 1284316485Sdavidcs#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 1285316485Sdavidcs#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1286316485Sdavidcs#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 1287320164Sdavidcs#define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 1288316485Sdavidcs#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 /* Param is either DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW/IMAGE */ 1289316485Sdavidcs#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* Param should be set to the transaction size (up to 64 bytes) */ 1290316485Sdavidcs#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 /* MFW will place the file offset and len in file_att struct */ 1291316485Sdavidcs#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 /* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes*/ 1292316485Sdavidcs#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 /* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] ??? Len in Bytes. In case this address is in the range of secured file in secured mode, the operation will fail */ 1293316485Sdavidcs#define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000 /* Delete a file from nvram. Param is image_type. */ 1294316485Sdavidcs#define DRV_MSG_CODE_MCP_RESET 0x00090000 /* Reset MCP when no NVM operation is going on, and no drivers are loaded. In case operation succeed, MCP will not ack back. */ 1295316485Sdavidcs#define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000 /* Temporary command to set secure mode, where the param is 0 (None secure) / 1 (Secure) / 2 (Full-Secure) */ 1296316485Sdavidcs#define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port*/ 1297316485Sdavidcs#define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000 /* Param: [0:15] - Address, [16:18] - lane# (0/1/2/3 - for single lane, 4/5 - for dual lanes, 6 - for all lanes, [28] - PMD reg, [29] - select port, [30:31] - port */ 1298316485Sdavidcs#define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000 /* Param: [0:15] - Address, [30:31] - port */ 1299316485Sdavidcs#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:15] - Address, [30:31] - port */ 1300316485Sdavidcs#define DRV_MSG_CODE_SET_VERSION 0x000f0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */ 1301316485Sdavidcs#define DRV_MSG_CODE_MCP_HALT 0x00100000 /* Halts the MCP. To resume MCP, user will need to use MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */ 1302316485Sdavidcs#define DRV_MSG_CODE_SET_VMAC 0x00110000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1303316485Sdavidcs#define DRV_MSG_CODE_GET_VMAC 0x00120000 /* Set virtual mac address, params [31:6] - reserved, [5:4] - type, [3:0] - func, drv_data[7:0] - MAC/WWNN/WWPN */ 1304320164Sdavidcs#define DRV_MSG_CODE_VMAC_TYPE_OFFSET 4 1305316485Sdavidcs#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 1306316485Sdavidcs#define DRV_MSG_CODE_VMAC_TYPE_MAC 1 1307316485Sdavidcs#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 1308316485Sdavidcs#define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 1309316485Sdavidcs 1310316485Sdavidcs#define DRV_MSG_CODE_GET_STATS 0x00130000 /* Get statistics from pf, params [31:4] - reserved, [3:0] - stats type */ 1311316485Sdavidcs#define DRV_MSG_CODE_STATS_TYPE_LAN 1 1312316485Sdavidcs#define DRV_MSG_CODE_STATS_TYPE_FCOE 2 1313316485Sdavidcs#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 1314316485Sdavidcs#define DRV_MSG_CODE_STATS_TYPE_RDMA 4 1315316485Sdavidcs#define DRV_MSG_CODE_PMD_DIAG_DUMP 0x00140000 /* Host shall provide buffer and size for MFW */ 1316316485Sdavidcs#define DRV_MSG_CODE_PMD_DIAG_EYE 0x00150000 /* Host shall provide buffer and size for MFW */ 1317316485Sdavidcs#define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 /* Param: [0:1] - Port, [2:7] - read size, [8:15] - I2C address, [16:31] - offset */ 1318316485Sdavidcs#define DRV_MSG_CODE_TRANSCEIVER_WRITE 0x00170000 /* Param: [0:1] - Port, [2:7] - write size, [8:15] - I2C address, [16:31] - offset */ 1319316485Sdavidcs#define DRV_MSG_CODE_OCBB_DATA 0x00180000 /* indicate OCBB related information */ 1320316485Sdavidcs#define DRV_MSG_CODE_SET_BW 0x00190000 /* Set function BW, params[15:8] - min, params[7:0] - max */ 1321316485Sdavidcs#define BW_MAX_MASK 0x000000ff 1322320164Sdavidcs#define BW_MAX_OFFSET 0 1323316485Sdavidcs#define BW_MIN_MASK 0x0000ff00 1324320164Sdavidcs#define BW_MIN_OFFSET 8 1325316485Sdavidcs 1326316485Sdavidcs#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 /* When param is set to 1, all parities will be masked(disabled). When params are set to 0, parities will be unmasked again. */ 1327316485Sdavidcs#define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000 /* param[0] - Simulate fan failure, param[1] - simulate over temp. */ 1328316485Sdavidcs#define DRV_MSG_FAN_FAILURE_TYPE (1 << 0) 1329316485Sdavidcs#define DRV_MSG_TEMPERATURE_FAILURE_TYPE (1 << 1) 1330316485Sdavidcs#define DRV_MSG_CODE_GPIO_READ 0x001c0000 /* Param: [0:15] - gpio number */ 1331316485Sdavidcs#define DRV_MSG_CODE_GPIO_WRITE 0x001d0000 /* Param: [0:15] - gpio number, [16:31] - gpio value */ 1332316485Sdavidcs#define DRV_MSG_CODE_BIST_TEST 0x001e0000 /* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */ 1333316485Sdavidcs#define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000 1334316485Sdavidcs#define DRV_MSG_CODE_SET_LED_MODE 0x00200000 /* Set LED mode params :0 operational, 1 LED turn ON, 2 LED turn OFF */ 1335316485Sdavidcs#define DRV_MSG_CODE_TIMESTAMP 0x00210000 /* drv_data[7:0] - EPOC in seconds, drv_data[15:8] - driver version (MAJ MIN BUILD SUB) */ 1336316485Sdavidcs#define DRV_MSG_CODE_EMPTY_MB 0x00220000 /* This is an empty mailbox just return OK*/ 1337316485Sdavidcs 1338316485Sdavidcs#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 /* Param[0:4] - resource number (0-31), Param[5:7] - opcode, param[15:8] - age */ 1339316485Sdavidcs 1340316485Sdavidcs#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 1341320164Sdavidcs#define RESOURCE_CMD_REQ_RESC_OFFSET 0 1342316485Sdavidcs#define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 1343320164Sdavidcs#define RESOURCE_CMD_REQ_OPCODE_OFFSET 5 1344316485Sdavidcs#define RESOURCE_OPCODE_REQ 1 /* request resource ownership with default aging */ 1345316485Sdavidcs#define RESOURCE_OPCODE_REQ_WO_AGING 2 /* request resource ownership without aging */ 1346316485Sdavidcs#define RESOURCE_OPCODE_REQ_W_AGING 3 /* request resource ownership with specific aging timer (in seconds) */ 1347316485Sdavidcs#define RESOURCE_OPCODE_RELEASE 4 /* release resource */ 1348316485Sdavidcs#define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */ 1349316485Sdavidcs#define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 1350320164Sdavidcs#define RESOURCE_CMD_REQ_AGE_OFFSET 8 1351316485Sdavidcs 1352316485Sdavidcs#define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 1353320164Sdavidcs#define RESOURCE_CMD_RSP_OWNER_OFFSET 0 1354316485Sdavidcs#define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 1355320164Sdavidcs#define RESOURCE_CMD_RSP_OPCODE_OFFSET 8 1356316485Sdavidcs#define RESOURCE_OPCODE_GNT 1 /* resource is free and granted to requester */ 1357316485Sdavidcs#define RESOURCE_OPCODE_BUSY 2 /* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15, 16 = MFW, 17 = diag over serial */ 1358316485Sdavidcs#define RESOURCE_OPCODE_RELEASED 3 /* indicate release request was acknowledged */ 1359316485Sdavidcs#define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 /* indicate release request was previously received by other owner */ 1360316485Sdavidcs#define RESOURCE_OPCODE_WRONG_OWNER 5 /* indicate wrong owner during release */ 1361316485Sdavidcs#define RESOURCE_OPCODE_UNKNOWN_CMD 255 1362316485Sdavidcs 1363316485Sdavidcs#define RESOURCE_DUMP 0 /* dedicate resource 0 for dump */ 1364316485Sdavidcs 1365316485Sdavidcs#define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */ 1366316485Sdavidcs#define DRV_MSG_CODE_MDUMP_CMD 0x00250000 /* Send crash dump commands with param[3:0] - opcode */ 1367316485Sdavidcs#define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 1368316485Sdavidcs#define DRV_MSG_CODE_MDUMP_ACK 0x01 /* acknowledge reception of error indication */ 1369316485Sdavidcs#define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 /* set epoc and personality as follow: drv_data[3:0] - epoch, drv_data[7:4] - personality */ 1370316485Sdavidcs#define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 /* trigger crash dump procedure */ 1371316485Sdavidcs#define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 /* Request valid logs and config words */ 1372316485Sdavidcs#define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 /* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger enabled */ 1373316485Sdavidcs#define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */ 1374316485Sdavidcs#define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 /* Get retained data */ 1375316485Sdavidcs#define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 /* Clear retain data */ 1376316485Sdavidcs#define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */ 1377316485Sdavidcs#define DRV_MSG_CODE_GPIO_INFO 0x00270000 /* Param: [0:15] - gpio number */ 1378316485Sdavidcs#define DRV_MSG_CODE_EXT_PHY_READ 0x00280000 /* Value will be placed in union */ 1379316485Sdavidcs#define DRV_MSG_CODE_EXT_PHY_WRITE 0x00290000 /* Value shoud be placed in union */ 1380320164Sdavidcs#define DRV_MB_PARAM_ADDR_OFFSET 0 1381316485Sdavidcs#define DRV_MB_PARAM_ADDR_MASK 0x0000FFFF 1382320164Sdavidcs#define DRV_MB_PARAM_DEVAD_OFFSET 16 1383316485Sdavidcs#define DRV_MB_PARAM_DEVAD_MASK 0x001F0000 1384320164Sdavidcs#define DRV_MB_PARAM_PORT_OFFSET 21 1385316485Sdavidcs#define DRV_MB_PARAM_PORT_MASK 0x00600000 1386316485Sdavidcs#define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 1387316485Sdavidcs#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 1388316485Sdavidcs#define DRV_MSG_CODE_SET_LLDP_MAC 0x002c0000 1389316485Sdavidcs#define DRV_MSG_CODE_GET_LLDP_MAC 0x002d0000 1390316485Sdavidcs#define DRV_MSG_CODE_OS_WOL 0x002e0000 1391316485Sdavidcs 1392316485Sdavidcs#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ 1393316485Sdavidcs#define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ 1394316485Sdavidcs#define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ 1395316485Sdavidcs 1396316485Sdavidcs#define DRV_MSG_CODE_READ_WOL_REG 0X00320000 1397316485Sdavidcs#define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 1398316485Sdavidcs#define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 1399337517Sdavidcs#define DRV_MSG_CODE_ATTRIBUTE 0x00350000 /* Param: [0:23] Attribute key, [24:31] Attribute sub command */ 1400316485Sdavidcs 1401337517Sdavidcs#define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 /* Param: Password len. Union: Plain Password */ 1402337517Sdavidcs#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */ 1403337517Sdavidcs 1404337517Sdavidcs /* Pmbus commands */ 1405337517Sdavidcs#define DRV_MSG_CODE_PMBUS_READ 0x00380000 /* Param: [0:7] - Cmd, [8:9] - len */ 1406337517Sdavidcs#define DRV_MSG_CODE_PMBUS_WRITE 0x00390000 /* Param: [0:7] - Cmd, [8:9] - len, [16:31] -data*/ 1407337517Sdavidcs 1408337517Sdavidcs#define DRV_MB_PARAM_PMBUS_CMD_OFFSET 0 1409337517Sdavidcs#define DRV_MB_PARAM_PMBUS_CMD_MASK 0xFF 1410337517Sdavidcs#define DRV_MB_PARAM_PMBUS_LEN_OFFSET 8 1411337517Sdavidcs#define DRV_MB_PARAM_PMBUS_LEN_MASK 0x300 1412337517Sdavidcs#define DRV_MB_PARAM_PMBUS_DATA_OFFSET 16 1413337517Sdavidcs#define DRV_MB_PARAM_PMBUS_DATA_MASK 0xFFFF0000 1414337517Sdavidcs 1415337517Sdavidcs#define DRV_MSG_CODE_GENERIC_IDC 0x003a0000 1416337517Sdavidcs 1417316485Sdavidcs#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1418316485Sdavidcs 1419316485Sdavidcs u32 drv_mb_param; 1420316485Sdavidcs /* UNLOAD_REQ params */ 1421316485Sdavidcs#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 1422316485Sdavidcs#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 1423316485Sdavidcs#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 1424316485Sdavidcs#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 1425316485Sdavidcs 1426316485Sdavidcs /* UNLOAD_DONE_params */ 1427316485Sdavidcs#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001 1428316485Sdavidcs 1429316485Sdavidcs /* INIT_PHY params */ 1430316485Sdavidcs#define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001 1431316485Sdavidcs#define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 1432316485Sdavidcs 1433316485Sdavidcs /* LLDP / DCBX params*/ 1434337517Sdavidcs /* To be used with SET_LLDP command */ 1435316485Sdavidcs#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 1436320164Sdavidcs#define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 1437337517Sdavidcs /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ 1438316485Sdavidcs#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 1439320164Sdavidcs#define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 1440337517Sdavidcs /* To be used with REGISTER_LLDP_TLVS_RX command */ 1441337517Sdavidcs#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 1442337517Sdavidcs#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 1443337517Sdavidcs#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 1444337517Sdavidcs#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 1445337517Sdavidcs /* To be used with SET_DCBX command */ 1446316485Sdavidcs#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 1447320164Sdavidcs#define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 1448316485Sdavidcs 1449316485Sdavidcs#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF 1450320164Sdavidcs#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_OFFSET 0 1451316485Sdavidcs 1452316485Sdavidcs#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1 1453316485Sdavidcs#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2 1454316485Sdavidcs 1455320164Sdavidcs#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 1456316485Sdavidcs#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 1457320164Sdavidcs#define DRV_MB_PARAM_NVM_LEN_OFFSET 24 1458316485Sdavidcs#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 1459316485Sdavidcs 1460320164Sdavidcs#define DRV_MB_PARAM_PHY_ADDR_OFFSET 0 1461316485Sdavidcs#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF 1462320164Sdavidcs#define DRV_MB_PARAM_PHY_LANE_OFFSET 16 1463316485Sdavidcs#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000 1464320164Sdavidcs#define DRV_MB_PARAM_PHY_SELECT_PORT_OFFSET 29 1465316485Sdavidcs#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000 1466320164Sdavidcs#define DRV_MB_PARAM_PHY_PORT_OFFSET 30 1467316485Sdavidcs#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000 1468316485Sdavidcs 1469320164Sdavidcs#define DRV_MB_PARAM_PHYMOD_LANE_OFFSET 0 1470316485Sdavidcs#define DRV_MB_PARAM_PHYMOD_LANE_MASK 0x000000FF 1471320164Sdavidcs#define DRV_MB_PARAM_PHYMOD_SIZE_OFFSET 8 1472316485Sdavidcs#define DRV_MB_PARAM_PHYMOD_SIZE_MASK 0x000FFF00 1473320164Sdavidcs /* configure vf MSIX params BB */ 1474320164Sdavidcs#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET 0 1475320164Sdavidcs#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 1476320164Sdavidcs#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET 8 1477316485Sdavidcs#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 1478320164Sdavidcs /* configure vf MSIX for PF params AH*/ 1479320164Sdavidcs#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_OFFSET 0 1480320164Sdavidcs#define DRV_MB_PARAM_CFG_PF_VFS_MSIX_SB_NUM_MASK 0x000000FF 1481316485Sdavidcs 1482316485Sdavidcs /* OneView configuration parametres */ 1483320164Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_OFFSET 0 1484316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 1485316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 1486316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_OS 1 1487316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 1488316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 1489316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_VC_CLP 4 1490316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_CNU 5 1491316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_DCI 6 1492316485Sdavidcs#define DRV_MB_PARAM_OV_CURR_CFG_HII 7 1493316485Sdavidcs 1494320164Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OFFSET 0 1495316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF 1496316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0) 1497316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1) 1498316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1) 1499316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2) 1500316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3) 1501316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3) 1502316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4) 1503316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5) 1504316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6) 1505316485Sdavidcs#define DRV_MB_PARAM_OV_UPDATE_BOOT_COMPLETED 0 1506316485Sdavidcs 1507320164Sdavidcs#define DRV_MB_PARAM_OV_PCI_BUS_NUM_OFFSET 0 1508316485Sdavidcs#define DRV_MB_PARAM_OV_PCI_BUS_NUM_MASK 0x000000FF 1509316485Sdavidcs 1510320164Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_OFFSET 0 1511316485Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 1512316485Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 1513316485Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 1514316485Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 1515316485Sdavidcs#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 1516316485Sdavidcs 1517320164Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_OFFSET 0 1518316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 1519316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 1520316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 /* Not Installed*/ 1521316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 1522316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 /* installed but disabled by user/admin/OS */ 1523316485Sdavidcs#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 /* installed and active */ 1524316485Sdavidcs 1525320164Sdavidcs#define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 1526316485Sdavidcs#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 1527316485Sdavidcs 1528316485Sdavidcs#define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 1529316485Sdavidcs DRV_MB_PARAM_WOL_DISABLED | \ 1530316485Sdavidcs DRV_MB_PARAM_WOL_ENABLED) 1531316485Sdavidcs#define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 1532316485Sdavidcs#define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 1533316485Sdavidcs#define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 1534316485Sdavidcs 1535316485Sdavidcs#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 1536316485Sdavidcs DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 1537316485Sdavidcs DRV_MB_PARAM_ESWITCH_MODE_VEPA) 1538316485Sdavidcs#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 1539316485Sdavidcs#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 1540316485Sdavidcs#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 1541316485Sdavidcs 1542316485Sdavidcs#define DRV_MB_PARAM_FCOE_CVID_MASK 0xFFF 1543320164Sdavidcs#define DRV_MB_PARAM_FCOE_CVID_OFFSET 0 1544316485Sdavidcs 1545337517Sdavidcs#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 1546337517Sdavidcs#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 1547337517Sdavidcs 1548337517Sdavidcs#define DRV_MB_PARAM_LLDP_STATS_AGENT_MASK 0xFF 1549337517Sdavidcs#define DRV_MB_PARAM_LLDP_STATS_AGENT_OFFSET 0 1550337517Sdavidcs 1551316485Sdavidcs#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 1552316485Sdavidcs#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 1553316485Sdavidcs#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 1554316485Sdavidcs 1555320164Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 1556316485Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 1557320164Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 1558316485Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 1559320164Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 1560316485Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 1561320164Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 1562316485Sdavidcs#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 1563316485Sdavidcs 1564320164Sdavidcs#define DRV_MB_PARAM_GPIO_NUMBER_OFFSET 0 1565316485Sdavidcs#define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF 1566320164Sdavidcs#define DRV_MB_PARAM_GPIO_VALUE_OFFSET 16 1567316485Sdavidcs#define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000 1568320164Sdavidcs#define DRV_MB_PARAM_GPIO_DIRECTION_OFFSET 16 1569316485Sdavidcs#define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000 1570320164Sdavidcs#define DRV_MB_PARAM_GPIO_CTRL_OFFSET 24 1571316485Sdavidcs#define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000 1572316485Sdavidcs 1573316485Sdavidcs /* Resource Allocation params - Driver version support*/ 1574316485Sdavidcs#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1575320164Sdavidcs#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1576316485Sdavidcs#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1577320164Sdavidcs#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1578316485Sdavidcs 1579316485Sdavidcs#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0 1580316485Sdavidcs#define DRV_MB_PARAM_BIST_REGISTER_TEST 1 1581316485Sdavidcs#define DRV_MB_PARAM_BIST_CLOCK_TEST 2 1582316485Sdavidcs#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 1583316485Sdavidcs#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 1584316485Sdavidcs 1585316485Sdavidcs#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 1586316485Sdavidcs#define DRV_MB_PARAM_BIST_RC_PASSED 1 1587316485Sdavidcs#define DRV_MB_PARAM_BIST_RC_FAILED 2 1588316485Sdavidcs#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 1589316485Sdavidcs 1590320164Sdavidcs#define DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET 0 1591316485Sdavidcs#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 1592320164Sdavidcs#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET 8 1593316485Sdavidcs#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 1594316485Sdavidcs 1595316485Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 1596337517Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 1597316485Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ 0x00000001 /* driver supports SmartLinQ parameter */ 1598316485Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 /* driver supports EEE parameter */ 1599316485Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 1600320164Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 1601337517Sdavidcs#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 /* driver supports virtual link parameter */ 1602337517Sdavidcs /* Driver attributes params */ 1603337517Sdavidcs#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 1604337517Sdavidcs#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF 1605337517Sdavidcs#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 1606337517Sdavidcs#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 1607316485Sdavidcs 1608316485Sdavidcs u32 fw_mb_header; 1609316485Sdavidcs#define FW_MSG_CODE_MASK 0xffff0000 1610316485Sdavidcs#define FW_MSG_CODE_UNSUPPORTED 0x00000000 1611316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 1612316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1613316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1614316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 1615316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 1616316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 1617316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 1618316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 1619316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 1620316485Sdavidcs#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1621316485Sdavidcs#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 1622316485Sdavidcs#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 1623316485Sdavidcs#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 1624316485Sdavidcs#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1625316485Sdavidcs#define FW_MSG_CODE_INIT_PHY_DONE 0x21200000 1626316485Sdavidcs#define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000 1627316485Sdavidcs#define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 1628316485Sdavidcs#define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 1629316485Sdavidcs#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 1630337517Sdavidcs#define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 1631316485Sdavidcs#define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 1632316485Sdavidcs#define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 1633316485Sdavidcs#define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 1634316485Sdavidcs#define FW_MSG_CODE_UPDATE_BOOT_PROGRESS_DONE 0x28000000 1635316485Sdavidcs#define FW_MSG_CODE_UPDATE_STORM_FW_VER_DONE 0x29000000 1636316485Sdavidcs#define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000 1637316485Sdavidcs#define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000 1638316485Sdavidcs#define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000 1639316485Sdavidcs#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 1640316485Sdavidcs#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 1641316485Sdavidcs#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 1642316485Sdavidcs#define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 1643316485Sdavidcs#define FW_MSG_CODE_UPDATE_WOL_DONE 0x38000000 1644316485Sdavidcs#define FW_MSG_CODE_UPDATE_ESWITCH_MODE_DONE 0x39000000 1645316485Sdavidcs#define FW_MSG_CODE_UPDATE_ERR 0x3a010000 1646316485Sdavidcs#define FW_MSG_CODE_UPDATE_PARAM_ERR 0x3a020000 1647316485Sdavidcs#define FW_MSG_CODE_UPDATE_NOT_ALLOWED 0x3a030000 1648316485Sdavidcs#define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 1649316485Sdavidcs#define FW_MSG_CODE_UPDATE_FCOE_CVID_DONE 0x3c000000 1650316485Sdavidcs#define FW_MSG_CODE_UPDATE_FCOE_FABRIC_NAME_DONE 0x3d000000 1651316485Sdavidcs#define FW_MSG_CODE_UPDATE_BOOT_CFG_DONE 0x3e000000 1652316485Sdavidcs#define FW_MSG_CODE_RESET_TO_DEFAULT_ACK 0x3f000000 1653316485Sdavidcs#define FW_MSG_CODE_OV_GET_CURR_CFG_DONE 0x40000000 1654337517Sdavidcs#define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 1655337517Sdavidcs#define FW_MSG_CODE_GET_LLDP_STATS_DONE 0x42000000 1656337517Sdavidcs#define FW_MSG_CODE_GET_LLDP_STATS_ERROR 0x42010000 1657316485Sdavidcs 1658316485Sdavidcs#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 1659316485Sdavidcs#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1660316485Sdavidcs#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 1661316485Sdavidcs#define FW_MSG_CODE_FLR_ACK 0x02000000 1662316485Sdavidcs#define FW_MSG_CODE_FLR_NACK 0x02100000 1663316485Sdavidcs#define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 1664316485Sdavidcs#define FW_MSG_CODE_SET_VMAC_SUCCESS 0x02300000 1665316485Sdavidcs#define FW_MSG_CODE_SET_VMAC_FAIL 0x02400000 1666316485Sdavidcs 1667316485Sdavidcs#define FW_MSG_CODE_NVM_OK 0x00010000 1668316485Sdavidcs#define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000 1669316485Sdavidcs#define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000 1670316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000 1671316485Sdavidcs#define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000 1672316485Sdavidcs#define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000 1673316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000 1674316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000 1675316485Sdavidcs#define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000 1676316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000 1677316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000 1678316485Sdavidcs#define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000 1679316485Sdavidcs#define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000 1680316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000 1681316485Sdavidcs#define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000 1682316485Sdavidcs#define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000 1683316485Sdavidcs#define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000 1684316485Sdavidcs#define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000 1685316485Sdavidcs#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 1686316485Sdavidcs#define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000 /* MFW reject "mcp reset" command if one of the drivers is up */ 1687316485Sdavidcs#define FW_MSG_CODE_NVM_FAILED_CALC_HASH 0x00310000 1688316485Sdavidcs#define FW_MSG_CODE_NVM_PUBLIC_KEY_MISSING 0x00320000 1689316485Sdavidcs#define FW_MSG_CODE_NVM_INVALID_PUBLIC_KEY 0x00330000 1690316485Sdavidcs 1691316485Sdavidcs#define FW_MSG_CODE_PHY_OK 0x00110000 1692316485Sdavidcs#define FW_MSG_CODE_PHY_ERROR 0x00120000 1693316485Sdavidcs#define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000 1694316485Sdavidcs#define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000 1695316485Sdavidcs#define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000 1696316485Sdavidcs#define FW_MSG_CODE_OK 0x00160000 1697337517Sdavidcs#define FW_MSG_CODE_ERROR 0x00170000 1698316485Sdavidcs#define FW_MSG_CODE_LED_MODE_INVALID 0x00170000 1699316485Sdavidcs#define FW_MSG_CODE_PHY_DIAG_OK 0x00160000 1700316485Sdavidcs#define FW_MSG_CODE_PHY_DIAG_ERROR 0x00170000 1701316485Sdavidcs#define FW_MSG_CODE_INIT_HW_FAILED_TO_ALLOCATE_PAGE 0x00040000 1702316485Sdavidcs#define FW_MSG_CODE_INIT_HW_FAILED_BAD_STATE 0x00170000 1703316485Sdavidcs#define FW_MSG_CODE_INIT_HW_FAILED_TO_SET_WINDOW 0x000d0000 1704316485Sdavidcs#define FW_MSG_CODE_INIT_HW_FAILED_NO_IMAGE 0x000c0000 1705316485Sdavidcs#define FW_MSG_CODE_INIT_HW_FAILED_VERSION_MISMATCH 0x00100000 1706316485Sdavidcs#define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 1707316485Sdavidcs#define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 1708316485Sdavidcs#define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 1709316485Sdavidcs#define FW_MSG_CODE_TRANSCEIVER_BAD_BUFFER_SIZE 0x000f0000 1710316485Sdavidcs#define FW_MSG_CODE_GPIO_OK 0x00160000 1711316485Sdavidcs#define FW_MSG_CODE_GPIO_DIRECTION_ERR 0x00170000 1712316485Sdavidcs#define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000 1713316485Sdavidcs#define FW_MSG_CODE_GPIO_INVALID 0x000f0000 1714316485Sdavidcs#define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000 1715316485Sdavidcs#define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000 1716316485Sdavidcs#define FW_MSG_CODE_EXTPHY_INVALID_IMAGE_HEADER 0x00700000 1717316485Sdavidcs#define FW_MSG_CODE_EXTPHY_INVALID_PHY_TYPE 0x00710000 1718316485Sdavidcs#define FW_MSG_CODE_EXTPHY_OPERATION_FAILED 0x00720000 1719316485Sdavidcs#define FW_MSG_CODE_EXTPHY_NO_PHY_DETECTED 0x00730000 1720316485Sdavidcs#define FW_MSG_CODE_RECOVERY_MODE 0x00740000 1721316485Sdavidcs 1722316485Sdavidcs /* mdump related response codes */ 1723316485Sdavidcs#define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000 1724316485Sdavidcs#define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000 1725316485Sdavidcs#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 1726316485Sdavidcs#define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000 1727316485Sdavidcs#define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000 1728316485Sdavidcs 1729316485Sdavidcs#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 1730316485Sdavidcs#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 1731316485Sdavidcs 1732316485Sdavidcs#define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 1733316485Sdavidcs#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 1734316485Sdavidcs#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 1735316485Sdavidcs#define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 1736316485Sdavidcs#define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 1737316485Sdavidcs 1738320164Sdavidcs 1739320164Sdavidcs#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 1740320164Sdavidcs#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 1741320164Sdavidcs 1742316485Sdavidcs#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1743316485Sdavidcs 1744337517Sdavidcs#define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 1745337517Sdavidcs#define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 1746316485Sdavidcs 1747337517Sdavidcs#define FW_MSG_CODE_IDC_BUSY 0x00010000 1748337517Sdavidcs 1749316485Sdavidcs u32 fw_mb_param; 1750316485Sdavidcs/* Resource Allocation params - MFW version support */ 1751316485Sdavidcs#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 1752320164Sdavidcs#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET 16 1753316485Sdavidcs#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 1754320164Sdavidcs#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET 0 1755316485Sdavidcs 1756316485Sdavidcs/* get pf rdma protocol command response */ 1757316485Sdavidcs#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 1758316485Sdavidcs#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 1759316485Sdavidcs#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 1760316485Sdavidcs#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 1761316485Sdavidcs 1762316485Sdavidcs/* get MFW feature support response */ 1763337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports SmartLinQ */ 1764337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 /* MFW supports EEE */ 1765337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 /* MFW supports DRV_LOAD Timeout */ 1766337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_LP_PRES_DET 0x00000008 /* MFW supports early detection of LP Presence */ 1767337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_RELAXED_ORD 0x00000010 /* MFW supports relaxed ordering setting */ 1768337517Sdavidcs#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 /* MFW supports virtual link */ 1769316485Sdavidcs 1770316485Sdavidcs#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1<<0) 1771316485Sdavidcs 1772337517Sdavidcs#define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF 1773337517Sdavidcs#define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 1774337517Sdavidcs#define FW_MB_PARAM_OEM_UPDATE_BW 0x01 1775337517Sdavidcs#define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 1776337517Sdavidcs#define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 1777337517Sdavidcs 1778337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 1779337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0 1780337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 1781337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1 1782337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 1783337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2 1784337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 1785337517Sdavidcs#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3 1786337517Sdavidcs 1787337517Sdavidcs#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF 1788337517Sdavidcs#define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0 1789337517Sdavidcs 1790316485Sdavidcs u32 drv_pulse_mb; 1791316485Sdavidcs#define DRV_PULSE_SEQ_MASK 0x00007fff 1792316485Sdavidcs#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1793316485Sdavidcs /* 1794316485Sdavidcs * The system time is in the format of 1795316485Sdavidcs * (year-2001)*12*32 + month*32 + day. 1796316485Sdavidcs */ 1797316485Sdavidcs#define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1798316485Sdavidcs /* 1799316485Sdavidcs * Indicate to the firmware not to go into the 1800316485Sdavidcs * OS-absent when it is not getting driver pulse. 1801316485Sdavidcs * This is used for debugging as well for PXE(MBA). 1802316485Sdavidcs */ 1803316485Sdavidcs 1804316485Sdavidcs u32 mcp_pulse_mb; 1805316485Sdavidcs#define MCP_PULSE_SEQ_MASK 0x00007fff 1806316485Sdavidcs#define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1807316485Sdavidcs /* Indicates to the driver not to assert due to lack 1808316485Sdavidcs * of MCP response */ 1809316485Sdavidcs#define MCP_EVENT_MASK 0xffff0000 1810316485Sdavidcs#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1811316485Sdavidcs 1812316485Sdavidcs /* The union data is used by the driver to pass parameters to the scratchpad. */ 1813316485Sdavidcs union drv_union_data union_data; 1814316485Sdavidcs 1815316485Sdavidcs}; 1816316485Sdavidcs 1817316485Sdavidcs/* MFW - DRV MB */ 1818316485Sdavidcs/********************************************************************** 1819316485Sdavidcs * Description 1820316485Sdavidcs * Incremental Aggregative 1821316485Sdavidcs * 8-bit MFW counter per message 1822316485Sdavidcs * 8-bit ack-counter per message 1823316485Sdavidcs * Capabilities 1824316485Sdavidcs * Provides up to 256 aggregative message per type 1825316485Sdavidcs * Provides 4 message types in dword 1826316485Sdavidcs * Message type pointers to byte offset 1827316485Sdavidcs * Backward Compatibility by using sizeof for the counters. 1828316485Sdavidcs * No lock requires for 32bit messages 1829316485Sdavidcs * Limitations: 1830316485Sdavidcs * In case of messages greater than 32bit, a dedicated mechanism(e.g lock) 1831316485Sdavidcs * is required to prevent data corruption. 1832316485Sdavidcs **********************************************************************/ 1833316485Sdavidcsenum MFW_DRV_MSG_TYPE { 1834316485Sdavidcs MFW_DRV_MSG_LINK_CHANGE, 1835316485Sdavidcs MFW_DRV_MSG_FLR_FW_ACK_FAILED, 1836316485Sdavidcs MFW_DRV_MSG_VF_DISABLED, 1837316485Sdavidcs MFW_DRV_MSG_LLDP_DATA_UPDATED, 1838316485Sdavidcs MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 1839316485Sdavidcs MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 1840316485Sdavidcs MFW_DRV_MSG_ERROR_RECOVERY, 1841316485Sdavidcs MFW_DRV_MSG_BW_UPDATE, 1842316485Sdavidcs MFW_DRV_MSG_S_TAG_UPDATE, 1843316485Sdavidcs MFW_DRV_MSG_GET_LAN_STATS, 1844316485Sdavidcs MFW_DRV_MSG_GET_FCOE_STATS, 1845316485Sdavidcs MFW_DRV_MSG_GET_ISCSI_STATS, 1846316485Sdavidcs MFW_DRV_MSG_GET_RDMA_STATS, 1847316485Sdavidcs MFW_DRV_MSG_FAILURE_DETECTED, 1848316485Sdavidcs MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 1849316485Sdavidcs MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 1850316485Sdavidcs MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, 1851316485Sdavidcs MFW_DRV_MSG_GET_TLV_REQ, 1852337517Sdavidcs MFW_DRV_MSG_OEM_CFG_UPDATE, 1853337517Sdavidcs MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, 1854337517Sdavidcs MFW_DRV_MSG_GENERIC_IDC, /* Generic Inter Driver Communication message */ 1855316485Sdavidcs MFW_DRV_MSG_MAX 1856316485Sdavidcs}; 1857316485Sdavidcs 1858316485Sdavidcs#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 1859316485Sdavidcs#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 1860316485Sdavidcs#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 1861316485Sdavidcs#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 1862316485Sdavidcs 1863316485Sdavidcs#ifdef BIG_ENDIAN /* Like MFW */ 1864316485Sdavidcs#define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[msg_id]++; 1865316485Sdavidcs#else 1866316485Sdavidcs#define DRV_ACK_MSG(msg_p, msg_id) (u8)((u8*)msg_p)[((msg_id & ~3) | ((~msg_id) & 3))]++; 1867316485Sdavidcs#endif 1868316485Sdavidcs 1869316485Sdavidcs#define MFW_DRV_UPDATE(shmem_func, msg_id) (u8)((u8*)(MFW_MB_P(shmem_func)->msg))[msg_id]++; 1870316485Sdavidcs 1871316485Sdavidcsstruct public_mfw_mb { 1872316485Sdavidcs u32 sup_msgs; /* Assigend with MFW_DRV_MSG_MAX */ 1873316485Sdavidcs u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the MFW */ 1874316485Sdavidcs u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; /* Incremented by the driver */ 1875316485Sdavidcs}; 1876316485Sdavidcs 1877316485Sdavidcs/**************************************/ 1878316485Sdavidcs/* */ 1879316485Sdavidcs/* P U B L I C D A T A */ 1880316485Sdavidcs/* */ 1881316485Sdavidcs/**************************************/ 1882316485Sdavidcsenum public_sections { 1883316485Sdavidcs PUBLIC_DRV_MB, /* Points to the first drv_mb of path0 */ 1884316485Sdavidcs PUBLIC_MFW_MB, /* Points to the first mfw_mb of path0 */ 1885316485Sdavidcs PUBLIC_GLOBAL, 1886316485Sdavidcs PUBLIC_PATH, 1887316485Sdavidcs PUBLIC_PORT, 1888316485Sdavidcs PUBLIC_FUNC, 1889316485Sdavidcs PUBLIC_MAX_SECTIONS 1890316485Sdavidcs}; 1891316485Sdavidcs 1892316485Sdavidcsstruct drv_ver_info_stc { 1893316485Sdavidcs u32 ver; 1894316485Sdavidcs u8 name[32]; 1895316485Sdavidcs}; 1896316485Sdavidcs 1897316485Sdavidcs/* Runtime data needs about 1/2K. We use 2K to be on the safe side. 1898316485Sdavidcs * Please make sure data does not exceed this size. 1899316485Sdavidcs */ 1900316485Sdavidcs#define NUM_RUNTIME_DWORDS 16 1901316485Sdavidcsstruct drv_init_hw_stc { 1902316485Sdavidcs u32 init_hw_bitmask[NUM_RUNTIME_DWORDS]; 1903316485Sdavidcs u32 init_hw_data[NUM_RUNTIME_DWORDS * 32]; 1904316485Sdavidcs}; 1905316485Sdavidcs 1906316485Sdavidcsstruct mcp_public_data { 1907316485Sdavidcs /* The sections fields is an array */ 1908316485Sdavidcs u32 num_sections; 1909316485Sdavidcs offsize_t sections[PUBLIC_MAX_SECTIONS]; 1910316485Sdavidcs struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 1911316485Sdavidcs struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 1912316485Sdavidcs struct public_global global; 1913316485Sdavidcs struct public_path path[MCP_GLOB_PATH_MAX]; 1914316485Sdavidcs struct public_port port[MCP_GLOB_PORT_MAX]; 1915316485Sdavidcs struct public_func func[MCP_GLOB_FUNC_MAX]; 1916316485Sdavidcs}; 1917316485Sdavidcs 1918316485Sdavidcs#define I2C_TRANSCEIVER_ADDR 0xa0 1919316485Sdavidcs#define MAX_I2C_TRANSACTION_SIZE 16 1920316485Sdavidcs#define MAX_I2C_TRANSCEIVER_PAGE_SIZE 256 1921316485Sdavidcs 1922316485Sdavidcs/* OCBB definitions */ 1923316485Sdavidcsenum tlvs { 1924316485Sdavidcs /* Category 1: Device Properties */ 1925316485Sdavidcs DRV_TLV_CLP_STR, 1926316485Sdavidcs DRV_TLV_CLP_STR_CTD, 1927316485Sdavidcs /* Category 6: Device Configuration */ 1928316485Sdavidcs DRV_TLV_SCSI_TO, 1929316485Sdavidcs DRV_TLV_R_T_TOV, 1930316485Sdavidcs DRV_TLV_R_A_TOV, 1931316485Sdavidcs DRV_TLV_E_D_TOV, 1932316485Sdavidcs DRV_TLV_CR_TOV, 1933316485Sdavidcs DRV_TLV_BOOT_TYPE, 1934316485Sdavidcs /* Category 8: Port Configuration */ 1935316485Sdavidcs DRV_TLV_NPIV_ENABLED, 1936316485Sdavidcs /* Category 10: Function Configuration */ 1937316485Sdavidcs DRV_TLV_FEATURE_FLAGS, 1938316485Sdavidcs DRV_TLV_LOCAL_ADMIN_ADDR, 1939316485Sdavidcs DRV_TLV_ADDITIONAL_MAC_ADDR_1, 1940316485Sdavidcs DRV_TLV_ADDITIONAL_MAC_ADDR_2, 1941316485Sdavidcs DRV_TLV_LSO_MAX_OFFLOAD_SIZE, 1942316485Sdavidcs DRV_TLV_LSO_MIN_SEGMENT_COUNT, 1943316485Sdavidcs DRV_TLV_PROMISCUOUS_MODE, 1944316485Sdavidcs DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, 1945316485Sdavidcs DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, 1946316485Sdavidcs DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, 1947316485Sdavidcs DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, 1948316485Sdavidcs DRV_TLV_OS_DRIVER_STATES, 1949316485Sdavidcs DRV_TLV_PXE_BOOT_PROGRESS, 1950316485Sdavidcs /* Category 12: FC/FCoE Configuration */ 1951316485Sdavidcs DRV_TLV_NPIV_STATE, 1952316485Sdavidcs DRV_TLV_NUM_OF_NPIV_IDS, 1953316485Sdavidcs DRV_TLV_SWITCH_NAME, 1954316485Sdavidcs DRV_TLV_SWITCH_PORT_NUM, 1955316485Sdavidcs DRV_TLV_SWITCH_PORT_ID, 1956316485Sdavidcs DRV_TLV_VENDOR_NAME, 1957316485Sdavidcs DRV_TLV_SWITCH_MODEL, 1958316485Sdavidcs DRV_TLV_SWITCH_FW_VER, 1959316485Sdavidcs DRV_TLV_QOS_PRIORITY_PER_802_1P, 1960316485Sdavidcs DRV_TLV_PORT_ALIAS, 1961316485Sdavidcs DRV_TLV_PORT_STATE, 1962316485Sdavidcs DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, 1963316485Sdavidcs DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, 1964316485Sdavidcs DRV_TLV_LINK_FAILURE_COUNT, 1965316485Sdavidcs DRV_TLV_FCOE_BOOT_PROGRESS, 1966316485Sdavidcs /* Category 13: iSCSI Configuration */ 1967316485Sdavidcs DRV_TLV_TARGET_LLMNR_ENABLED, 1968316485Sdavidcs DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, 1969316485Sdavidcs DRV_TLV_DATA_DIGEST_FLAG_ENABLED, 1970316485Sdavidcs DRV_TLV_AUTHENTICATION_METHOD, 1971316485Sdavidcs DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, 1972316485Sdavidcs DRV_TLV_MAX_FRAME_SIZE, 1973316485Sdavidcs DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, 1974316485Sdavidcs DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, 1975316485Sdavidcs DRV_TLV_ISCSI_BOOT_PROGRESS, 1976316485Sdavidcs /* Category 20: Device Data */ 1977316485Sdavidcs DRV_TLV_PCIE_BUS_RX_UTILIZATION, 1978316485Sdavidcs DRV_TLV_PCIE_BUS_TX_UTILIZATION, 1979316485Sdavidcs DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, 1980316485Sdavidcs DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, 1981316485Sdavidcs DRV_TLV_NCSI_RX_BYTES_RECEIVED, 1982316485Sdavidcs DRV_TLV_NCSI_TX_BYTES_SENT, 1983316485Sdavidcs /* Category 22: Base Port Data */ 1984316485Sdavidcs DRV_TLV_RX_DISCARDS, 1985316485Sdavidcs DRV_TLV_RX_ERRORS, 1986316485Sdavidcs DRV_TLV_TX_ERRORS, 1987316485Sdavidcs DRV_TLV_TX_DISCARDS, 1988316485Sdavidcs DRV_TLV_RX_FRAMES_RECEIVED, 1989316485Sdavidcs DRV_TLV_TX_FRAMES_SENT, 1990316485Sdavidcs /* Category 23: FC/FCoE Port Data */ 1991316485Sdavidcs DRV_TLV_RX_BROADCAST_PACKETS, 1992316485Sdavidcs DRV_TLV_TX_BROADCAST_PACKETS, 1993316485Sdavidcs /* Category 28: Base Function Data */ 1994316485Sdavidcs DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, 1995316485Sdavidcs DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, 1996316485Sdavidcs DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 1997316485Sdavidcs DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 1998316485Sdavidcs DRV_TLV_PF_RX_FRAMES_RECEIVED, 1999316485Sdavidcs DRV_TLV_RX_BYTES_RECEIVED, 2000316485Sdavidcs DRV_TLV_PF_TX_FRAMES_SENT, 2001316485Sdavidcs DRV_TLV_TX_BYTES_SENT, 2002316485Sdavidcs DRV_TLV_IOV_OFFLOAD, 2003316485Sdavidcs DRV_TLV_PCI_ERRORS_CAP_ID, 2004316485Sdavidcs DRV_TLV_UNCORRECTABLE_ERROR_STATUS, 2005316485Sdavidcs DRV_TLV_UNCORRECTABLE_ERROR_MASK, 2006316485Sdavidcs DRV_TLV_CORRECTABLE_ERROR_STATUS, 2007316485Sdavidcs DRV_TLV_CORRECTABLE_ERROR_MASK, 2008316485Sdavidcs DRV_TLV_PCI_ERRORS_AECC_REGISTER, 2009316485Sdavidcs DRV_TLV_TX_QUEUES_EMPTY, 2010316485Sdavidcs DRV_TLV_RX_QUEUES_EMPTY, 2011316485Sdavidcs DRV_TLV_TX_QUEUES_FULL, 2012316485Sdavidcs DRV_TLV_RX_QUEUES_FULL, 2013316485Sdavidcs /* Category 29: FC/FCoE Function Data */ 2014316485Sdavidcs DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 2015316485Sdavidcs DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 2016316485Sdavidcs DRV_TLV_FCOE_RX_FRAMES_RECEIVED, 2017316485Sdavidcs DRV_TLV_FCOE_RX_BYTES_RECEIVED, 2018316485Sdavidcs DRV_TLV_FCOE_TX_FRAMES_SENT, 2019316485Sdavidcs DRV_TLV_FCOE_TX_BYTES_SENT, 2020316485Sdavidcs DRV_TLV_CRC_ERROR_COUNT, 2021316485Sdavidcs DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, 2022316485Sdavidcs DRV_TLV_CRC_ERROR_1_TIMESTAMP, 2023316485Sdavidcs DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, 2024316485Sdavidcs DRV_TLV_CRC_ERROR_2_TIMESTAMP, 2025316485Sdavidcs DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, 2026316485Sdavidcs DRV_TLV_CRC_ERROR_3_TIMESTAMP, 2027316485Sdavidcs DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, 2028316485Sdavidcs DRV_TLV_CRC_ERROR_4_TIMESTAMP, 2029316485Sdavidcs DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, 2030316485Sdavidcs DRV_TLV_CRC_ERROR_5_TIMESTAMP, 2031316485Sdavidcs DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, 2032316485Sdavidcs DRV_TLV_LOSS_OF_SIGNAL_ERRORS, 2033316485Sdavidcs DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, 2034316485Sdavidcs DRV_TLV_DISPARITY_ERROR_COUNT, 2035316485Sdavidcs DRV_TLV_CODE_VIOLATION_ERROR_COUNT, 2036316485Sdavidcs DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, 2037316485Sdavidcs DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, 2038316485Sdavidcs DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, 2039316485Sdavidcs DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, 2040316485Sdavidcs DRV_TLV_LAST_FLOGI_TIMESTAMP, 2041316485Sdavidcs DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, 2042316485Sdavidcs DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, 2043316485Sdavidcs DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, 2044316485Sdavidcs DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, 2045316485Sdavidcs DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, 2046316485Sdavidcs DRV_TLV_LAST_FLOGI_RJT, 2047316485Sdavidcs DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, 2048316485Sdavidcs DRV_TLV_FDISCS_SENT_COUNT, 2049316485Sdavidcs DRV_TLV_FDISC_ACCS_RECEIVED, 2050316485Sdavidcs DRV_TLV_FDISC_RJTS_RECEIVED, 2051316485Sdavidcs DRV_TLV_PLOGI_SENT_COUNT, 2052316485Sdavidcs DRV_TLV_PLOGI_ACCS_RECEIVED, 2053316485Sdavidcs DRV_TLV_PLOGI_RJTS_RECEIVED, 2054316485Sdavidcs DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, 2055316485Sdavidcs DRV_TLV_PLOGI_1_TIMESTAMP, 2056316485Sdavidcs DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, 2057316485Sdavidcs DRV_TLV_PLOGI_2_TIMESTAMP, 2058316485Sdavidcs DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, 2059316485Sdavidcs DRV_TLV_PLOGI_3_TIMESTAMP, 2060316485Sdavidcs DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, 2061316485Sdavidcs DRV_TLV_PLOGI_4_TIMESTAMP, 2062316485Sdavidcs DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, 2063316485Sdavidcs DRV_TLV_PLOGI_5_TIMESTAMP, 2064316485Sdavidcs DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, 2065316485Sdavidcs DRV_TLV_PLOGI_1_ACC_TIMESTAMP, 2066316485Sdavidcs DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, 2067316485Sdavidcs DRV_TLV_PLOGI_2_ACC_TIMESTAMP, 2068316485Sdavidcs DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, 2069316485Sdavidcs DRV_TLV_PLOGI_3_ACC_TIMESTAMP, 2070316485Sdavidcs DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, 2071316485Sdavidcs DRV_TLV_PLOGI_4_ACC_TIMESTAMP, 2072316485Sdavidcs DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, 2073316485Sdavidcs DRV_TLV_PLOGI_5_ACC_TIMESTAMP, 2074316485Sdavidcs DRV_TLV_LOGOS_ISSUED, 2075316485Sdavidcs DRV_TLV_LOGO_ACCS_RECEIVED, 2076316485Sdavidcs DRV_TLV_LOGO_RJTS_RECEIVED, 2077316485Sdavidcs DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, 2078316485Sdavidcs DRV_TLV_LOGO_1_TIMESTAMP, 2079316485Sdavidcs DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, 2080316485Sdavidcs DRV_TLV_LOGO_2_TIMESTAMP, 2081316485Sdavidcs DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, 2082316485Sdavidcs DRV_TLV_LOGO_3_TIMESTAMP, 2083316485Sdavidcs DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, 2084316485Sdavidcs DRV_TLV_LOGO_4_TIMESTAMP, 2085316485Sdavidcs DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, 2086316485Sdavidcs DRV_TLV_LOGO_5_TIMESTAMP, 2087316485Sdavidcs DRV_TLV_LOGOS_RECEIVED, 2088316485Sdavidcs DRV_TLV_ACCS_ISSUED, 2089316485Sdavidcs DRV_TLV_PRLIS_ISSUED, 2090316485Sdavidcs DRV_TLV_ACCS_RECEIVED, 2091316485Sdavidcs DRV_TLV_ABTS_SENT_COUNT, 2092316485Sdavidcs DRV_TLV_ABTS_ACCS_RECEIVED, 2093316485Sdavidcs DRV_TLV_ABTS_RJTS_RECEIVED, 2094316485Sdavidcs DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, 2095316485Sdavidcs DRV_TLV_ABTS_1_TIMESTAMP, 2096316485Sdavidcs DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, 2097316485Sdavidcs DRV_TLV_ABTS_2_TIMESTAMP, 2098316485Sdavidcs DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, 2099316485Sdavidcs DRV_TLV_ABTS_3_TIMESTAMP, 2100316485Sdavidcs DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, 2101316485Sdavidcs DRV_TLV_ABTS_4_TIMESTAMP, 2102316485Sdavidcs DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, 2103316485Sdavidcs DRV_TLV_ABTS_5_TIMESTAMP, 2104316485Sdavidcs DRV_TLV_RSCNS_RECEIVED, 2105316485Sdavidcs DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, 2106316485Sdavidcs DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, 2107316485Sdavidcs DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, 2108316485Sdavidcs DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, 2109316485Sdavidcs DRV_TLV_LUN_RESETS_ISSUED, 2110316485Sdavidcs DRV_TLV_ABORT_TASK_SETS_ISSUED, 2111316485Sdavidcs DRV_TLV_TPRLOS_SENT, 2112316485Sdavidcs DRV_TLV_NOS_SENT_COUNT, 2113316485Sdavidcs DRV_TLV_NOS_RECEIVED_COUNT, 2114316485Sdavidcs DRV_TLV_OLS_COUNT, 2115316485Sdavidcs DRV_TLV_LR_COUNT, 2116316485Sdavidcs DRV_TLV_LRR_COUNT, 2117316485Sdavidcs DRV_TLV_LIP_SENT_COUNT, 2118316485Sdavidcs DRV_TLV_LIP_RECEIVED_COUNT, 2119316485Sdavidcs DRV_TLV_EOFA_COUNT, 2120316485Sdavidcs DRV_TLV_EOFNI_COUNT, 2121316485Sdavidcs DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, 2122316485Sdavidcs DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, 2123316485Sdavidcs DRV_TLV_SCSI_STATUS_BUSY_COUNT, 2124316485Sdavidcs DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, 2125316485Sdavidcs DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, 2126316485Sdavidcs DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, 2127316485Sdavidcs DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, 2128316485Sdavidcs DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, 2129316485Sdavidcs DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, 2130316485Sdavidcs DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, 2131316485Sdavidcs DRV_TLV_SCSI_CHECK_1_TIMESTAMP, 2132316485Sdavidcs DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, 2133316485Sdavidcs DRV_TLV_SCSI_CHECK_2_TIMESTAMP, 2134316485Sdavidcs DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, 2135316485Sdavidcs DRV_TLV_SCSI_CHECK_3_TIMESTAMP, 2136316485Sdavidcs DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, 2137316485Sdavidcs DRV_TLV_SCSI_CHECK_4_TIMESTAMP, 2138316485Sdavidcs DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, 2139316485Sdavidcs DRV_TLV_SCSI_CHECK_5_TIMESTAMP, 2140316485Sdavidcs /* Category 30: iSCSI Function Data */ 2141316485Sdavidcs DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 2142316485Sdavidcs DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 2143316485Sdavidcs DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, 2144316485Sdavidcs DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, 2145316485Sdavidcs DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, 2146316485Sdavidcs DRV_TLV_ISCSI_PDU_TX_BYTES_SENT 2147316485Sdavidcs}; 2148316485Sdavidcs 2149337517Sdavidcs#define I2C_DEV_ADDR_A2 0xa2 2150337517Sdavidcs#define SFP_EEPROM_A2_TEMPERATURE_ADDR 0x60 2151337517Sdavidcs#define SFP_EEPROM_A2_TEMPERATURE_SIZE 2 2152337517Sdavidcs#define SFP_EEPROM_A2_VCC_ADDR 0x62 2153337517Sdavidcs#define SFP_EEPROM_A2_VCC_SIZE 2 2154337517Sdavidcs#define SFP_EEPROM_A2_TX_BIAS_ADDR 0x64 2155337517Sdavidcs#define SFP_EEPROM_A2_TX_BIAS_SIZE 2 2156337517Sdavidcs#define SFP_EEPROM_A2_TX_POWER_ADDR 0x66 2157337517Sdavidcs#define SFP_EEPROM_A2_TX_POWER_SIZE 2 2158337517Sdavidcs#define SFP_EEPROM_A2_RX_POWER_ADDR 0x68 2159337517Sdavidcs#define SFP_EEPROM_A2_RX_POWER_SIZE 2 2160337517Sdavidcs 2161337517Sdavidcs#define I2C_DEV_ADDR_A0 0xa0 2162337517Sdavidcs#define QSFP_EEPROM_A0_TEMPERATURE_ADDR 0x16 2163337517Sdavidcs#define QSFP_EEPROM_A0_TEMPERATURE_SIZE 2 2164337517Sdavidcs#define QSFP_EEPROM_A0_VCC_ADDR 0x1a 2165337517Sdavidcs#define QSFP_EEPROM_A0_VCC_SIZE 2 2166337517Sdavidcs#define QSFP_EEPROM_A0_TX1_BIAS_ADDR 0x2a 2167337517Sdavidcs#define QSFP_EEPROM_A0_TX1_BIAS_SIZE 2 2168337517Sdavidcs#define QSFP_EEPROM_A0_TX1_POWER_ADDR 0x32 2169337517Sdavidcs#define QSFP_EEPROM_A0_TX1_POWER_SIZE 2 2170337517Sdavidcs#define QSFP_EEPROM_A0_RX1_POWER_ADDR 0x22 2171337517Sdavidcs#define QSFP_EEPROM_A0_RX1_POWER_SIZE 2 2172337517Sdavidcs 2173337517Sdavidcs/************************************** 2174337517Sdavidcs * eDiag NETWORK Mode (DON) 2175337517Sdavidcs **************************************/ 2176337517Sdavidcs 2177337517Sdavidcs#define ETH_DON_TYPE 0x0911 /* NETWORK Mode for QeDiag */ 2178337517Sdavidcs#define ETH_DON_TRACE_TYPE 0x0912 /* NETWORK Mode Continous Trace */ 2179337517Sdavidcs 2180337517Sdavidcs#define DON_RESP_UNKNOWN_CMD_ID 0x10 /* Response Error */ 2181337517Sdavidcs 2182337517Sdavidcs/* Op Codes, Response is Op Code+1 */ 2183337517Sdavidcs 2184337517Sdavidcs#define DON_REG_READ_REQ_CMD_ID 0x11 2185337517Sdavidcs#define DON_REG_WRITE_REQ_CMD_ID 0x22 2186337517Sdavidcs#define DON_CHALLENGE_REQ_CMD_ID 0x33 2187337517Sdavidcs#define DON_NVM_READ_REQ_CMD_ID 0x44 2188337517Sdavidcs#define DON_BLOCK_READ_REQ_CMD_ID 0x55 2189337517Sdavidcs 2190337517Sdavidcs#define DON_MFW_MODE_TRACE_CONTINUOUS_ID 0x70 2191337517Sdavidcs 2192337517Sdavidcs#if defined(MFW) || defined(DIAG) || defined(WINEDIAG) 2193337517Sdavidcs 2194337517Sdavidcs#ifndef UEFI 2195337517Sdavidcs#if defined(_MSC_VER) 2196337517Sdavidcs#pragma pack(push,1) 2197337517Sdavidcs#else 2198337517Sdavidcs#pragma pack(1) 2199337517Sdavidcs#endif 2200337517Sdavidcs#endif 2201337517Sdavidcs 2202337517Sdavidcstypedef struct { 2203337517Sdavidcs u8 dst_addr[6]; 2204337517Sdavidcs u8 src_addr[6]; 2205337517Sdavidcs u16 ether_type; 2206337517Sdavidcs 2207337517Sdavidcs /* DON Message data starts here, after L2 header */ 2208337517Sdavidcs /* Do not change alignment to keep backward compatability */ 2209337517Sdavidcs u16 cmd_id; /* Op code and response code */ 2210337517Sdavidcs 2211337517Sdavidcs union { 2212337517Sdavidcs struct { /* DON Commands */ 2213337517Sdavidcs u32 address; 2214337517Sdavidcs u32 val; 2215337517Sdavidcs u32 resp_status; 2216337517Sdavidcs }; 2217337517Sdavidcs struct { /* DON Traces */ 2218337517Sdavidcs u16 mcp_clock; /* MCP Clock in MHz */ 2219337517Sdavidcs u16 trace_size; /* Trace size in bytes */ 2220337517Sdavidcs 2221337517Sdavidcs u32 seconds; /* Seconds since last reset */ 2222337517Sdavidcs u32 ticks; /* Timestamp (NOW) */ 2223337517Sdavidcs }; 2224337517Sdavidcs }; 2225337517Sdavidcs union { 2226337517Sdavidcs u8 digest[32]; /* SHA256 */ 2227337517Sdavidcs u8 data[32]; 2228337517Sdavidcs /* u32 dword[8]; */ 2229337517Sdavidcs }; 2230337517Sdavidcs} don_packet_t; 2231337517Sdavidcs 2232337517Sdavidcs#ifndef UEFI 2233337517Sdavidcs#if defined(_MSC_VER) 2234337517Sdavidcs#pragma pack(pop) 2235337517Sdavidcs#else 2236337517Sdavidcs#pragma pack(0) 2237337517Sdavidcs#endif 2238337517Sdavidcs#endif /* #ifndef UEFI */ 2239337517Sdavidcs 2240337517Sdavidcs#endif /* #if defined(MFW) || defined(DIAG) || defined(WINEDIAG) */ 2241337517Sdavidcs 2242316485Sdavidcs#endif /* MCP_PUBLIC_H */ 2243