ecore_hsi_eth.h revision 337517
1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_hsi_eth.h 337517 2018-08-09 01:17:35Z davidcs $ 28 * 29 */ 30 31#ifndef __ECORE_HSI_ETH__ 32#define __ECORE_HSI_ETH__ 33/************************************************************************/ 34/* Add include to common eth target for both eCore and protocol driver */ 35/************************************************************************/ 36#include "eth_common.h" 37 38/* 39 * The eth storm context for the Tstorm 40 */ 41struct tstorm_eth_conn_st_ctx 42{ 43 __le32 reserved[4]; 44}; 45 46/* 47 * The eth storm context for the Pstorm 48 */ 49struct pstorm_eth_conn_st_ctx 50{ 51 __le32 reserved[8]; 52}; 53 54/* 55 * The eth storm context for the Xstorm 56 */ 57struct xstorm_eth_conn_st_ctx 58{ 59 __le32 reserved[60]; 60}; 61 62struct e4_xstorm_eth_conn_ag_ctx 63{ 64 u8 reserved0 /* cdu_validation */; 65 u8 state /* state */; 66 u8 flags0; 67#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 68#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 69#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 70#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 71#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 72#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 73#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 74#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 75#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 76#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 77#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 78#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 79#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 80#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 81#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 82#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 83 u8 flags1; 84#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 85#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 86#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 87#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 88#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 89#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 90#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 91#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 92#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 93#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 94#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 95#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 96#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 97#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 98#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 99#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 100 u8 flags2; 101#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 102#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 103#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 104#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 105#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 106#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 107#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 108#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 109 u8 flags3; 110#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 111#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 112#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 113#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 114#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 115#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 116#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 117#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 118 u8 flags4; 119#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 120#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 121#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 122#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 123#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 124#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 125#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 126#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 127 u8 flags5; 128#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 129#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 130#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 131#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 132#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 133#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 134#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 135#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 136 u8 flags6; 137#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 138#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 139#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 140#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 141#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 142#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 143#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 144#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 145 u8 flags7; 146#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 147#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 148#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 149#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 150#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 151#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 152#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 153#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 154#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 155#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 156 u8 flags8; 157#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 158#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 159#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 160#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 161#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 162#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 163#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 164#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 165#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 166#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 167#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 168#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 169#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 170#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 171#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 172#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 173 u8 flags9; 174#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 175#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 176#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 177#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 178#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 179#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 180#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 181#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 182#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 183#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 184#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 185#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 186#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 187#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 188#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 189#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 190 u8 flags10; 191#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 192#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 193#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 194#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 195#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 196#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 197#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 198#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 199#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 200#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 201#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 202#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 203#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 204#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 205#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 206#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 207 u8 flags11; 208#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 209#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 210#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 211#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 212#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 213#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 214#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 215#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 216#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 217#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 218#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 219#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 220#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 221#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 222#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 223#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 224 u8 flags12; 225#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 226#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 227#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 228#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 229#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 230#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 231#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 232#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 233#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 234#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 235#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 236#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 237#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 238#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 239#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 240#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 241 u8 flags13; 242#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 243#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 244#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 245#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 246#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 247#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 248#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 249#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 250#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 251#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 252#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 253#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 254#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 255#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 256#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 257#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 258 u8 flags14; 259#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 260#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 261#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 262#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 263#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 264#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 265#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 266#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 267#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 268#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 269#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 270#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 271#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 272#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 273 u8 edpm_event_id /* byte2 */; 274 __le16 physical_q0 /* physical_q0 */; 275 __le16 e5_reserved1 /* physical_q1 */; 276 __le16 edpm_num_bds /* physical_q2 */; 277 __le16 tx_bd_cons /* word3 */; 278 __le16 tx_bd_prod /* word4 */; 279 __le16 tx_class /* word5 */; 280 __le16 conn_dpi /* conn_dpi */; 281 u8 byte3 /* byte3 */; 282 u8 byte4 /* byte4 */; 283 u8 byte5 /* byte5 */; 284 u8 byte6 /* byte6 */; 285 __le32 reg0 /* reg0 */; 286 __le32 reg1 /* reg1 */; 287 __le32 reg2 /* reg2 */; 288 __le32 reg3 /* reg3 */; 289 __le32 reg4 /* reg4 */; 290 __le32 reg5 /* cf_array0 */; 291 __le32 reg6 /* cf_array1 */; 292 __le16 word7 /* word7 */; 293 __le16 word8 /* word8 */; 294 __le16 word9 /* word9 */; 295 __le16 word10 /* word10 */; 296 __le32 reg7 /* reg7 */; 297 __le32 reg8 /* reg8 */; 298 __le32 reg9 /* reg9 */; 299 u8 byte7 /* byte7 */; 300 u8 byte8 /* byte8 */; 301 u8 byte9 /* byte9 */; 302 u8 byte10 /* byte10 */; 303 u8 byte11 /* byte11 */; 304 u8 byte12 /* byte12 */; 305 u8 byte13 /* byte13 */; 306 u8 byte14 /* byte14 */; 307 u8 byte15 /* byte15 */; 308 u8 e5_reserved /* e5_reserved */; 309 __le16 word11 /* word11 */; 310 __le32 reg10 /* reg10 */; 311 __le32 reg11 /* reg11 */; 312 __le32 reg12 /* reg12 */; 313 __le32 reg13 /* reg13 */; 314 __le32 reg14 /* reg14 */; 315 __le32 reg15 /* reg15 */; 316 __le32 reg16 /* reg16 */; 317 __le32 reg17 /* reg17 */; 318 __le32 reg18 /* reg18 */; 319 __le32 reg19 /* reg19 */; 320 __le16 word12 /* word12 */; 321 __le16 word13 /* word13 */; 322 __le16 word14 /* word14 */; 323 __le16 word15 /* word15 */; 324}; 325 326/* 327 * The eth storm context for the Ystorm 328 */ 329struct ystorm_eth_conn_st_ctx 330{ 331 __le32 reserved[8]; 332}; 333 334struct e4_ystorm_eth_conn_ag_ctx 335{ 336 u8 byte0 /* cdu_validation */; 337 u8 state /* state */; 338 u8 flags0; 339#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 340#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 341#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 342#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 343#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 344#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 345#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 346#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 347#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 348#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 349 u8 flags1; 350#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 351#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 352#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 353#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 354#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 355#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 356#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 357#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 358#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 359#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 360#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 361#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 362#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 363#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 364#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 365#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 366 u8 tx_q0_int_coallecing_timeset /* byte2 */; 367 u8 byte3 /* byte3 */; 368 __le16 word0 /* word0 */; 369 __le32 terminate_spqe /* reg0 */; 370 __le32 reg1 /* reg1 */; 371 __le16 tx_bd_cons_upd /* word1 */; 372 __le16 word2 /* word2 */; 373 __le16 word3 /* word3 */; 374 __le16 word4 /* word4 */; 375 __le32 reg2 /* reg2 */; 376 __le32 reg3 /* reg3 */; 377}; 378 379struct e4_tstorm_eth_conn_ag_ctx 380{ 381 u8 byte0 /* cdu_validation */; 382 u8 byte1 /* state */; 383 u8 flags0; 384#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 385#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 386#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 387#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 388#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 389#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 390#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 391#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 392#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 393#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 394#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 395#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 396#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 397#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 398 u8 flags1; 399#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 400#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 401#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 402#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 403#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 404#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 405#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 406#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 407 u8 flags2; 408#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 409#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 410#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 411#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 412#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 413#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 414#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 415#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 416 u8 flags3; 417#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 418#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 419#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 420#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 421#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 422#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 423#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 424#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 425#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 426#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 427#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 428#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 429 u8 flags4; 430#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 431#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 432#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 433#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 434#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 435#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 436#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 437#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 438#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 439#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 440#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 441#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 442#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 443#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 444#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 445#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 446 u8 flags5; 447#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 448#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 449#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 450#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 451#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 452#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 453#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 454#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 455#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 456#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 457#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 458#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 459#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 460#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 461#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 462#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 463 __le32 reg0 /* reg0 */; 464 __le32 reg1 /* reg1 */; 465 __le32 reg2 /* reg2 */; 466 __le32 reg3 /* reg3 */; 467 __le32 reg4 /* reg4 */; 468 __le32 reg5 /* reg5 */; 469 __le32 reg6 /* reg6 */; 470 __le32 reg7 /* reg7 */; 471 __le32 reg8 /* reg8 */; 472 u8 byte2 /* byte2 */; 473 u8 byte3 /* byte3 */; 474 __le16 rx_bd_cons /* word0 */; 475 u8 byte4 /* byte4 */; 476 u8 byte5 /* byte5 */; 477 __le16 rx_bd_prod /* word1 */; 478 __le16 word2 /* conn_dpi */; 479 __le16 word3 /* word3 */; 480 __le32 reg9 /* reg9 */; 481 __le32 reg10 /* reg10 */; 482}; 483 484struct e4_ustorm_eth_conn_ag_ctx 485{ 486 u8 byte0 /* cdu_validation */; 487 u8 byte1 /* state */; 488 u8 flags0; 489#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 490#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 491#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 492#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 493#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 494#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 495#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 496#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 497#define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 498#define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 499 u8 flags1; 500#define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 501#define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 502#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 503#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 504#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 505#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 506#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 507#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 508 u8 flags2; 509#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 510#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 511#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 512#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 513#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 514#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 515#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 516#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 517#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 518#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 519#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 520#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 521#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 522#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 523#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 524#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 525 u8 flags3; 526#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 527#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 528#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 529#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 530#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 531#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 532#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 533#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 534#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 535#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 536#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 537#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 538#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 539#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 540#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 541#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 542 u8 byte2 /* byte2 */; 543 u8 byte3 /* byte3 */; 544 __le16 word0 /* conn_dpi */; 545 __le16 tx_bd_cons /* word1 */; 546 __le32 reg0 /* reg0 */; 547 __le32 reg1 /* reg1 */; 548 __le32 reg2 /* reg2 */; 549 __le32 tx_int_coallecing_timeset /* reg3 */; 550 __le16 tx_drv_bd_cons /* word2 */; 551 __le16 rx_drv_cqe_cons /* word3 */; 552}; 553 554/* 555 * The eth storm context for the Ustorm 556 */ 557struct ustorm_eth_conn_st_ctx 558{ 559 __le32 reserved[40]; 560}; 561 562/* 563 * The eth storm context for the Mstorm 564 */ 565struct mstorm_eth_conn_st_ctx 566{ 567 __le32 reserved[8]; 568}; 569 570/* 571 * eth connection context 572 */ 573struct e4_eth_conn_context 574{ 575 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 576 struct regpair tstorm_st_padding[2] /* padding */; 577 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 578 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 579 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 580 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 581 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 582 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 583 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 584 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 585 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 586}; 587 588 589struct e5_xstorm_eth_conn_ag_ctx 590{ 591 u8 reserved0 /* cdu_validation */; 592 u8 state_and_core_id /* state_and_core_id */; 593 u8 flags0; 594#define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 595#define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 596#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 597#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 598#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 599#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 600#define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 601#define E5_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 602#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 603#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 604#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 605#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 606#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 607#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 608#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 609#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 610 u8 flags1; 611#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 612#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 613#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 614#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 615#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 616#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 617#define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 618#define E5_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 619#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 620#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 621#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 622#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 623#define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 624#define E5_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 625#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 626#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 627 u8 flags2; 628#define E5_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 629#define E5_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 630#define E5_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 631#define E5_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 632#define E5_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 633#define E5_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 634#define E5_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 635#define E5_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 636 u8 flags3; 637#define E5_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 638#define E5_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 639#define E5_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 640#define E5_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 641#define E5_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 642#define E5_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 643#define E5_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 644#define E5_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 645 u8 flags4; 646#define E5_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 647#define E5_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 648#define E5_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 649#define E5_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 650#define E5_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 651#define E5_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 652#define E5_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 653#define E5_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 654 u8 flags5; 655#define E5_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 656#define E5_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 657#define E5_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 658#define E5_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 659#define E5_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 660#define E5_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 661#define E5_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 662#define E5_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 663 u8 flags6; 664#define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 665#define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 666#define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 667#define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 668#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 669#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 670#define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 671#define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 672 u8 flags7; 673#define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 674#define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 675#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 676#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 677#define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 678#define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 679#define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 680#define E5_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 681#define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 682#define E5_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 683 u8 flags8; 684#define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 685#define E5_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 686#define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 687#define E5_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 688#define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 689#define E5_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 690#define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 691#define E5_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 692#define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 693#define E5_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 694#define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 695#define E5_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 696#define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 697#define E5_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 698#define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 699#define E5_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 700 u8 flags9; 701#define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 702#define E5_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 703#define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 704#define E5_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 705#define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 706#define E5_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 707#define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 708#define E5_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 709#define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 710#define E5_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 711#define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 712#define E5_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 713#define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 714#define E5_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 715#define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 716#define E5_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 717 u8 flags10; 718#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 719#define E5_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 720#define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 721#define E5_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 722#define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 723#define E5_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 724#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 725#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 726#define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 727#define E5_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 728#define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 729#define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 730#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 731#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 732#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 733#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 734 u8 flags11; 735#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 736#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 737#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 738#define E5_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 739#define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 740#define E5_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 741#define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 742#define E5_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 743#define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 744#define E5_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 745#define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 746#define E5_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 747#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 748#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 749#define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 750#define E5_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 751 u8 flags12; 752#define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 753#define E5_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 754#define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 755#define E5_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 756#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 757#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 758#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 759#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 760#define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 761#define E5_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 762#define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 763#define E5_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 764#define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 765#define E5_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 766#define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 767#define E5_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 768 u8 flags13; 769#define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 770#define E5_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 771#define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 772#define E5_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 773#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 774#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 775#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 776#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 777#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 778#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 779#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 780#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 781#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 782#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 783#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 784#define E5_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 785 u8 flags14; 786#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 787#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 788#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 789#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 790#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 791#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 792#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 793#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 794#define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 795#define E5_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 796#define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 797#define E5_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 798#define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 799#define E5_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 800 u8 edpm_vport /* byte2 */; 801 __le16 physical_q0 /* physical_q0 */; 802 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 803 __le16 edpm_num_bds /* physical_q2 */; 804 __le16 tx_bd_cons /* word3 */; 805 __le16 tx_bd_prod /* word4 */; 806 __le16 tx_class /* word5 */; 807 __le16 conn_dpi /* conn_dpi */; 808 u8 byte3 /* byte3 */; 809 u8 byte4 /* byte4 */; 810 u8 byte5 /* byte5 */; 811 u8 byte6 /* byte6 */; 812 __le32 reg0 /* reg0 */; 813 __le32 reg1 /* reg1 */; 814 __le32 reg2 /* reg2 */; 815 __le32 reg3 /* reg3 */; 816 __le32 reg4 /* reg4 */; 817 __le32 reg5 /* cf_array0 */; 818 __le32 reg6 /* cf_array1 */; 819 u8 flags15; 820#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_MASK 0x1 /* bit22 */ 821#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_LO_SHIFT 0 822#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_MASK 0x1 /* bit23 */ 823#define E5_XSTORM_ETH_CONN_AG_CTX_EDPM_REDIRECTION_CONDITION_HI_SHIFT 1 824#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 825#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 826#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 827#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 828#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 829#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 830#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 831#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 832#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 833#define E5_XSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 834 u8 byte7 /* byte7 */; 835 __le16 word7 /* word7 */; 836 __le16 word8 /* word8 */; 837 __le16 word9 /* word9 */; 838 __le16 word10 /* word10 */; 839 __le16 word11 /* word11 */; 840 __le32 reg7 /* reg7 */; 841 __le32 reg8 /* reg8 */; 842 __le32 reg9 /* reg9 */; 843 u8 byte8 /* byte8 */; 844 u8 byte9 /* byte9 */; 845 u8 byte10 /* byte10 */; 846 u8 byte11 /* byte11 */; 847 u8 byte12 /* byte12 */; 848 u8 byte13 /* byte13 */; 849 u8 byte14 /* byte14 */; 850 u8 byte15 /* byte15 */; 851 __le32 reg10 /* reg10 */; 852 __le32 reg11 /* reg11 */; 853 __le32 reg12 /* reg12 */; 854 __le32 reg13 /* reg13 */; 855 __le32 reg14 /* reg14 */; 856 __le32 reg15 /* reg15 */; 857 __le32 reg16 /* reg16 */; 858 __le32 reg17 /* reg17 */; 859 __le32 reg18 /* reg18 */; 860 __le32 reg19 /* reg19 */; 861 __le16 word12 /* word12 */; 862 __le16 word13 /* word13 */; 863 __le16 word14 /* word14 */; 864 __le16 word15 /* word15 */; 865}; 866 867struct e5_tstorm_eth_conn_ag_ctx 868{ 869 u8 byte0 /* cdu_validation */; 870 u8 byte1 /* state_and_core_id */; 871 u8 flags0; 872#define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 873#define E5_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 874#define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 875#define E5_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 876#define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 877#define E5_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 878#define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 879#define E5_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 880#define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 881#define E5_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 882#define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 883#define E5_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 884#define E5_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 885#define E5_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 886 u8 flags1; 887#define E5_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 888#define E5_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 889#define E5_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 890#define E5_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 891#define E5_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 892#define E5_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 893#define E5_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 894#define E5_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 895 u8 flags2; 896#define E5_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 897#define E5_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 898#define E5_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 899#define E5_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 900#define E5_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 901#define E5_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 902#define E5_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 903#define E5_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 904 u8 flags3; 905#define E5_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 906#define E5_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 907#define E5_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 908#define E5_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 909#define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 910#define E5_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 911#define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 912#define E5_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 913#define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 914#define E5_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 915#define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 916#define E5_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 917 u8 flags4; 918#define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 919#define E5_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 920#define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 921#define E5_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 922#define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 923#define E5_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 924#define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 925#define E5_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 926#define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 927#define E5_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 928#define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 929#define E5_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 930#define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 931#define E5_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 932#define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 933#define E5_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 934 u8 flags5; 935#define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 936#define E5_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 937#define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 938#define E5_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 939#define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 940#define E5_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 941#define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 942#define E5_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 943#define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 944#define E5_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 945#define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 /* rule6en */ 946#define E5_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 947#define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 948#define E5_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 949#define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 950#define E5_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 951 u8 flags6; 952#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 953#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 954#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 955#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 956#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 957#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 958#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 959#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 960#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 961#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 962#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 963#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 964#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 965#define E5_TSTORM_ETH_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 966 u8 byte2 /* byte2 */; 967 __le16 rx_bd_cons /* word0 */; 968 __le32 reg0 /* reg0 */; 969 __le32 reg1 /* reg1 */; 970 __le32 reg2 /* reg2 */; 971 __le32 reg3 /* reg3 */; 972 __le32 reg4 /* reg4 */; 973 __le32 reg5 /* reg5 */; 974 __le32 reg6 /* reg6 */; 975 __le32 reg7 /* reg7 */; 976 __le32 reg8 /* reg8 */; 977 u8 byte3 /* byte3 */; 978 u8 byte4 /* byte4 */; 979 u8 byte5 /* byte5 */; 980 u8 e4_reserved8 /* byte6 */; 981 __le16 rx_bd_prod /* word1 */; 982 __le16 word2 /* conn_dpi */; 983 __le32 reg9 /* reg9 */; 984 __le16 word3 /* word3 */; 985 __le16 e4_reserved9 /* word4 */; 986}; 987 988struct e5_ystorm_eth_conn_ag_ctx 989{ 990 u8 byte0 /* cdu_validation */; 991 u8 state_and_core_id /* state_and_core_id */; 992 u8 flags0; 993#define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 994#define E5_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 995#define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 996#define E5_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 997#define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf0 */ 998#define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 999#define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 /* cf1 */ 1000#define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 1001#define E5_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1002#define E5_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1003 u8 flags1; 1004#define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf0en */ 1005#define E5_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 1006#define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1007#define E5_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 1008#define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1009#define E5_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1010#define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1011#define E5_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 1012#define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1013#define E5_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 1014#define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1015#define E5_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 1016#define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1017#define E5_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 1018#define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1019#define E5_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 1020 u8 tx_q0_int_coallecing_timeset /* byte2 */; 1021 u8 byte3 /* byte3 */; 1022 __le16 word0 /* word0 */; 1023 __le32 terminate_spqe /* reg0 */; 1024 __le32 reg1 /* reg1 */; 1025 __le16 tx_bd_cons_upd /* word1 */; 1026 __le16 word2 /* word2 */; 1027 __le16 word3 /* word3 */; 1028 __le16 word4 /* word4 */; 1029 __le32 reg2 /* reg2 */; 1030 __le32 reg3 /* reg3 */; 1031}; 1032 1033struct e5_ustorm_eth_conn_ag_ctx 1034{ 1035 u8 byte0 /* cdu_validation */; 1036 u8 byte1 /* state_and_core_id */; 1037 u8 flags0; 1038#define E5_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1039#define E5_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 1040#define E5_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1041#define E5_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 1042#define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 /* timer0cf */ 1043#define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 1044#define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 /* timer1cf */ 1045#define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 1046#define E5_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1047#define E5_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 1048 u8 flags1; 1049#define E5_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1050#define E5_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 1051#define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 /* cf4 */ 1052#define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 1053#define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 /* cf5 */ 1054#define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 1055#define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 /* cf6 */ 1056#define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 1057 u8 flags2; 1058#define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf0en */ 1059#define E5_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 1060#define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 /* cf1en */ 1061#define E5_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 1062#define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1063#define E5_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 1064#define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1065#define E5_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 1066#define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 /* cf4en */ 1067#define E5_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 1068#define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 /* cf5en */ 1069#define E5_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 1070#define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 /* cf6en */ 1071#define E5_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 1072#define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1073#define E5_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 1074 u8 flags3; 1075#define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1076#define E5_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 1077#define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1078#define E5_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 1079#define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1080#define E5_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 1081#define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1082#define E5_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 1083#define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1084#define E5_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 1085#define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1086#define E5_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 1087#define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1088#define E5_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 1089#define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1090#define E5_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 1091 u8 flags4; 1092#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1093#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1094#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1095#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1096#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1097#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1098#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1099#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1100#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1101#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1102#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1103#define E5_USTORM_ETH_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1104 u8 byte2 /* byte2 */; 1105 __le16 word0 /* conn_dpi */; 1106 __le16 tx_bd_cons /* word1 */; 1107 __le32 reg0 /* reg0 */; 1108 __le32 reg1 /* reg1 */; 1109 __le32 reg2 /* reg2 */; 1110 __le32 tx_int_coallecing_timeset /* reg3 */; 1111 __le16 tx_drv_bd_cons /* word2 */; 1112 __le16 rx_drv_cqe_cons /* word3 */; 1113}; 1114 1115/* 1116 * eth connection context 1117 */ 1118struct e5_eth_conn_context 1119{ 1120 struct tstorm_eth_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1121 struct regpair tstorm_st_padding[2] /* padding */; 1122 struct pstorm_eth_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1123 struct xstorm_eth_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1124 struct regpair xstorm_st_padding[2] /* padding */; 1125 struct e5_xstorm_eth_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1126 struct e5_tstorm_eth_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1127 struct ystorm_eth_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1128 struct e5_ystorm_eth_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 1129 struct e5_ustorm_eth_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1130 struct ustorm_eth_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1131 struct mstorm_eth_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1132}; 1133 1134 1135/* 1136 * Ethernet filter types: mac/vlan/pair 1137 */ 1138enum eth_error_code 1139{ 1140 ETH_OK=0x00 /* command succeeded */, 1141 ETH_FILTERS_MAC_ADD_FAIL_FULL /* mac add filters command failed due to cam full state */, 1142 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2 /* mac add filters command failed due to mtt2 full state */, 1143 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2 /* mac add filters command failed due to duplicate mac address */, 1144 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2 /* mac add filters command failed due to duplicate mac address */, 1145 ETH_FILTERS_MAC_DEL_FAIL_NOF /* mac delete filters command failed due to not found state */, 1146 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2 /* mac delete filters command failed due to not found state */, 1147 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2 /* mac delete filters command failed due to not found state */, 1148 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC /* mac add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1149 ETH_FILTERS_VLAN_ADD_FAIL_FULL /* vlan add filters command failed due to cam full state */, 1150 ETH_FILTERS_VLAN_ADD_FAIL_DUP /* vlan add filters command failed due to duplicate VLAN filter */, 1151 ETH_FILTERS_VLAN_DEL_FAIL_NOF /* vlan delete filters command failed due to not found state */, 1152 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1 /* vlan delete filters command failed due to not found state */, 1153 ETH_FILTERS_PAIR_ADD_FAIL_DUP /* pair add filters command failed due to duplicate request */, 1154 ETH_FILTERS_PAIR_ADD_FAIL_FULL /* pair add filters command failed due to full state */, 1155 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC /* pair add filters command failed due to full state */, 1156 ETH_FILTERS_PAIR_DEL_FAIL_NOF /* pair add filters command failed due not found state */, 1157 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1 /* pair add filters command failed due not found state */, 1158 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC /* pair add filters command failed due to MAC Address of 00:00:00:00:00:00 */, 1159 ETH_FILTERS_VNI_ADD_FAIL_FULL /* vni add filters command failed due to cam full state */, 1160 ETH_FILTERS_VNI_ADD_FAIL_DUP /* vni add filters command failed due to duplicate VNI filter */, 1161 ETH_FILTERS_GFT_UPDATE_FAIL /* Fail update GFT filter. */, 1162 MAX_ETH_ERROR_CODE 1163}; 1164 1165 1166/* 1167 * opcodes for the event ring 1168 */ 1169enum eth_event_opcode 1170{ 1171 ETH_EVENT_UNUSED, 1172 ETH_EVENT_VPORT_START, 1173 ETH_EVENT_VPORT_UPDATE, 1174 ETH_EVENT_VPORT_STOP, 1175 ETH_EVENT_TX_QUEUE_START, 1176 ETH_EVENT_TX_QUEUE_STOP, 1177 ETH_EVENT_RX_QUEUE_START, 1178 ETH_EVENT_RX_QUEUE_UPDATE, 1179 ETH_EVENT_RX_QUEUE_STOP, 1180 ETH_EVENT_FILTERS_UPDATE, 1181 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 1182 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 1183 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 1184 ETH_EVENT_RX_ADD_UDP_FILTER, 1185 ETH_EVENT_RX_DELETE_UDP_FILTER, 1186 ETH_EVENT_RX_CREATE_GFT_ACTION, 1187 ETH_EVENT_RX_GFT_UPDATE_FILTER, 1188 ETH_EVENT_TX_QUEUE_UPDATE, 1189 MAX_ETH_EVENT_OPCODE 1190}; 1191 1192 1193/* 1194 * Classify rule types in E2/E3 1195 */ 1196enum eth_filter_action 1197{ 1198 ETH_FILTER_ACTION_UNUSED, 1199 ETH_FILTER_ACTION_REMOVE, 1200 ETH_FILTER_ACTION_ADD, 1201 ETH_FILTER_ACTION_REMOVE_ALL /* Remove all filters of given type and vport ID. */, 1202 MAX_ETH_FILTER_ACTION 1203}; 1204 1205 1206/* 1207 * Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ 1208 */ 1209struct eth_filter_cmd 1210{ 1211 u8 type /* Filter Type (MAC/VLAN/Pair/VNI) (use enum eth_filter_type) */; 1212 u8 vport_id /* the vport id */; 1213 u8 action /* filter command action: add/remove/replace (use enum eth_filter_action) */; 1214 u8 reserved0; 1215 __le32 vni; 1216 __le16 mac_lsb; 1217 __le16 mac_mid; 1218 __le16 mac_msb; 1219 __le16 vlan_id; 1220}; 1221 1222 1223/* 1224 * $$KEEP_ENDIANNESS$$ 1225 */ 1226struct eth_filter_cmd_header 1227{ 1228 u8 rx /* If set, apply these commands to the RX path */; 1229 u8 tx /* If set, apply these commands to the TX path */; 1230 u8 cmd_cnt /* Number of filter commands */; 1231 u8 assert_on_error /* 0 - dont assert in case of filter configuration error. Just return an error code. 1 - assert in case of filter configuration error. */; 1232 u8 reserved1[4]; 1233}; 1234 1235 1236/* 1237 * Ethernet filter types: mac/vlan/pair 1238 */ 1239enum eth_filter_type 1240{ 1241 ETH_FILTER_TYPE_UNUSED, 1242 ETH_FILTER_TYPE_MAC /* Add/remove a MAC address */, 1243 ETH_FILTER_TYPE_VLAN /* Add/remove a VLAN */, 1244 ETH_FILTER_TYPE_PAIR /* Add/remove a MAC-VLAN pair */, 1245 ETH_FILTER_TYPE_INNER_MAC /* Add/remove a inner MAC address */, 1246 ETH_FILTER_TYPE_INNER_VLAN /* Add/remove a inner VLAN */, 1247 ETH_FILTER_TYPE_INNER_PAIR /* Add/remove a inner MAC-VLAN pair */, 1248 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR /* Add/remove a inner MAC-VNI pair */, 1249 ETH_FILTER_TYPE_MAC_VNI_PAIR /* Add/remove a MAC-VNI pair */, 1250 ETH_FILTER_TYPE_VNI /* Add/remove a VNI */, 1251 MAX_ETH_FILTER_TYPE 1252}; 1253 1254 1255/* 1256 * eth IPv4 Fragment Type 1257 */ 1258enum eth_ipv4_frag_type 1259{ 1260 ETH_IPV4_NOT_FRAG /* IPV4 Packet Not Fragmented */, 1261 ETH_IPV4_FIRST_FRAG /* First Fragment of IPv4 Packet (contains headers) */, 1262 ETH_IPV4_NON_FIRST_FRAG /* Non-First Fragment of IPv4 Packet (does not contain headers) */, 1263 MAX_ETH_IPV4_FRAG_TYPE 1264}; 1265 1266 1267/* 1268 * eth IPv4 Fragment Type 1269 */ 1270enum eth_ip_type 1271{ 1272 ETH_IPV4 /* IPv4 */, 1273 ETH_IPV6 /* IPv6 */, 1274 MAX_ETH_IP_TYPE 1275}; 1276 1277 1278/* 1279 * Ethernet Ramrod Command IDs 1280 */ 1281enum eth_ramrod_cmd_id 1282{ 1283 ETH_RAMROD_UNUSED, 1284 ETH_RAMROD_VPORT_START /* VPort Start Ramrod */, 1285 ETH_RAMROD_VPORT_UPDATE /* VPort Update Ramrod */, 1286 ETH_RAMROD_VPORT_STOP /* VPort Stop Ramrod */, 1287 ETH_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 1288 ETH_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 1289 ETH_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 1290 ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 1291 ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */, 1292 ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */, 1293 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION /* RX - Create an Openflow Action */, 1294 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER /* RX - Add an Openflow Filter to the Searcher */, 1295 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER /* RX - Delete an Openflow Filter to the Searcher */, 1296 ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */, 1297 ETH_RAMROD_RX_DELETE_UDP_FILTER /* RX - Delete a UDP Filter to the Searcher */, 1298 ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */, 1299 ETH_RAMROD_GFT_UPDATE_FILTER /* RX - Add/Delete a GFT Filter to the Searcher */, 1300 ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 1301 MAX_ETH_RAMROD_CMD_ID 1302}; 1303 1304 1305/* 1306 * return code from eth sp ramrods 1307 */ 1308struct eth_return_code 1309{ 1310 u8 value; 1311#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F /* error code (use enum eth_error_code) */ 1312#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 1313#define ETH_RETURN_CODE_RESERVED_MASK 0x3 1314#define ETH_RETURN_CODE_RESERVED_SHIFT 5 1315#define ETH_RETURN_CODE_RX_TX_MASK 0x1 /* rx path - 0, tx path - 1 */ 1316#define ETH_RETURN_CODE_RX_TX_SHIFT 7 1317}; 1318 1319 1320/* 1321 * What to do in case an error occurs 1322 */ 1323enum eth_tx_err 1324{ 1325 ETH_TX_ERR_DROP /* Drop erroneous packet. */, 1326 ETH_TX_ERR_ASSERT_MALICIOUS /* Assert an interrupt for PF, declare as malicious for VF */, 1327 MAX_ETH_TX_ERR 1328}; 1329 1330 1331/* 1332 * Array of the different error type behaviors 1333 */ 1334struct eth_tx_err_vals 1335{ 1336 __le16 values; 1337#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 /* Wrong VLAN insertion mode (use enum eth_tx_err) */ 1338#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 1339#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 /* Packet is below minimal size (use enum eth_tx_err) */ 1340#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 1341#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 /* Vport has sent spoofed packet (use enum eth_tx_err) */ 1342#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 1343#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 /* Packet with illegal type of inband tag (use enum eth_tx_err) */ 1344#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 1345#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 /* Packet marked for VLAN insertion when inband tag is present (use enum eth_tx_err) */ 1346#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 1347#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 /* Non LSO packet larger than MTU (use enum eth_tx_err) */ 1348#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 1349#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 /* VF/PF has sent LLDP/PFC or any other type of control packet which is not allowed to (use enum eth_tx_err) */ 1350#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 1351#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 1352#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 1353}; 1354 1355 1356/* 1357 * vport rss configuration data 1358 */ 1359struct eth_vport_rss_config 1360{ 1361 __le16 capabilities; 1362#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 /* configuration of the IpV4 2-tuple capability */ 1363#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 1364#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 /* configuration of the IpV6 2-tuple capability */ 1365#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 1366#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for TCP */ 1367#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 1368#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for TCP */ 1369#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 1370#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV4 4-tuple capability for UDP */ 1371#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 1372#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 /* configuration of the IpV6 4-tuple capability for UDP */ 1373#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 1374#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 /* configuration of the 5-tuple capability */ 1375#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 1376#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF /* if set update the rss keys */ 1377#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 1378 u8 rss_id /* The RSS engine ID. Must be allocated to each vport with RSS enabled. Total number of RSS engines is ETH_RSS_ENGINE_NUM_ , according to chip type. */; 1379 u8 rss_mode /* The RSS mode for this function (use enum eth_vport_rss_mode) */; 1380 u8 update_rss_key /* if set update the rss key */; 1381 u8 update_rss_ind_table /* if set update the indirection table values */; 1382 u8 update_rss_capabilities /* if set update the capabilities and indirection table size. */; 1383 u8 tbl_size /* rss mask (Tbl size) */; 1384 __le32 reserved2[2]; 1385 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM] /* RSS indirection table */; 1386 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS] /* RSS key supplied to us by OS */; 1387 __le32 reserved3[2]; 1388}; 1389 1390 1391/* 1392 * eth vport RSS mode 1393 */ 1394enum eth_vport_rss_mode 1395{ 1396 ETH_VPORT_RSS_MODE_DISABLED /* RSS Disabled */, 1397 ETH_VPORT_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 1398 MAX_ETH_VPORT_RSS_MODE 1399}; 1400 1401 1402/* 1403 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1404 */ 1405struct eth_vport_rx_mode 1406{ 1407 __le16 state; 1408#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1409#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 1410#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1411#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1412#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 /* accept all unmatched unicast packets */ 1413#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 1414#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1415#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 1416#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1417#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 1418#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1419#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 1420#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF 1421#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 1422}; 1423 1424 1425/* 1426 * Command for setting tpa parameters 1427 */ 1428struct eth_vport_tpa_param 1429{ 1430 u8 tpa_ipv4_en_flg /* Enable TPA for IPv4 packets */; 1431 u8 tpa_ipv6_en_flg /* Enable TPA for IPv6 packets */; 1432 u8 tpa_ipv4_tunn_en_flg /* Enable TPA for IPv4 over tunnel */; 1433 u8 tpa_ipv6_tunn_en_flg /* Enable TPA for IPv6 over tunnel */; 1434 u8 tpa_pkt_split_flg /* If set, start each TPA segment on new BD (GRO mode). One BD per segment allowed. */; 1435 u8 tpa_hdr_data_split_flg /* If set, put header of first TPA segment on first BD and data on second BD. */; 1436 u8 tpa_gro_consistent_flg /* If set, GRO data consistent will checked for TPA continue */; 1437 u8 tpa_max_aggs_num /* maximum number of opened aggregations per v-port */; 1438 __le16 tpa_max_size /* maximal size for the aggregated TPA packets */; 1439 __le16 tpa_min_size_to_start /* minimum TCP payload size for a packet to start aggregation */; 1440 __le16 tpa_min_size_to_cont /* minimum TCP payload size for a packet to continue aggregation */; 1441 u8 max_buff_num /* maximal number of buffers that can be used for one aggregation */; 1442 u8 reserved; 1443}; 1444 1445 1446/* 1447 * Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ 1448 */ 1449struct eth_vport_tx_mode 1450{ 1451 __le16 state; 1452#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 /* drop all unicast packets */ 1453#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 1454#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 /* accept all unicast packets (subject to vlan) */ 1455#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 1456#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 /* drop all multicast packets */ 1457#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 1458#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 /* accept all multicast packets (subject to vlan) */ 1459#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 1460#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 /* accept all broadcast packets (subject to vlan) */ 1461#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 1462#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 1463#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 1464}; 1465 1466 1467/* 1468 * GFT filter update action type. 1469 */ 1470enum gft_filter_update_action 1471{ 1472 GFT_ADD_FILTER, 1473 GFT_DELETE_FILTER, 1474 MAX_GFT_FILTER_UPDATE_ACTION 1475}; 1476 1477 1478 1479 1480/* 1481 * Ramrod data for rx add openflow filter 1482 */ 1483struct rx_add_openflow_filter_data 1484{ 1485 __le16 action_icid /* CID of Action to run for this filter */; 1486 u8 priority /* Searcher String - Packet priority */; 1487 u8 reserved0; 1488 __le32 tenant_id /* Searcher String - Tenant ID */; 1489 __le16 dst_mac_hi /* Searcher String - Destination Mac Bytes 0 to 1 */; 1490 __le16 dst_mac_mid /* Searcher String - Destination Mac Bytes 2 to 3 */; 1491 __le16 dst_mac_lo /* Searcher String - Destination Mac Bytes 4 to 5 */; 1492 __le16 src_mac_hi /* Searcher String - Source Mac 0 to 1 */; 1493 __le16 src_mac_mid /* Searcher String - Source Mac 2 to 3 */; 1494 __le16 src_mac_lo /* Searcher String - Source Mac 4 to 5 */; 1495 __le16 vlan_id /* Searcher String - Vlan ID */; 1496 __le16 l2_eth_type /* Searcher String - Last L2 Ethertype */; 1497 u8 ipv4_dscp /* Searcher String - IPv4 6 MSBs of the TOS Field */; 1498 u8 ipv4_frag_type /* Searcher String - IPv4 Fragmentation Type (use enum eth_ipv4_frag_type) */; 1499 u8 ipv4_over_ip /* Searcher String - IPv4 Over IP Type */; 1500 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1501 __le32 ipv4_dst_addr /* Searcher String - IPv4 Destination Address */; 1502 __le32 ipv4_src_addr /* Searcher String - IPv4 Source Address */; 1503 __le16 l4_dst_port /* Searcher String - TCP/UDP Destination Port */; 1504 __le16 l4_src_port /* Searcher String - TCP/UDP Source Port */; 1505}; 1506 1507 1508/* 1509 * Ramrod data for rx create gft action 1510 */ 1511struct rx_create_gft_action_data 1512{ 1513 u8 vport_id /* Vport Id of GFT Action */; 1514 u8 reserved[7]; 1515}; 1516 1517 1518/* 1519 * Ramrod data for rx create openflow action 1520 */ 1521struct rx_create_openflow_action_data 1522{ 1523 u8 vport_id /* ID of RX queue */; 1524 u8 reserved[7]; 1525}; 1526 1527 1528/* 1529 * Ramrod data for rx queue start ramrod 1530 */ 1531struct rx_queue_start_ramrod_data 1532{ 1533 __le16 rx_queue_id /* ID of RX queue */; 1534 __le16 num_of_pbl_pages /* Number of pages in CQE PBL */; 1535 __le16 bd_max_bytes /* maximal bytes that can be places on the bd */; 1536 __le16 sb_id /* Status block ID */; 1537 u8 sb_index /* index of the protocol index */; 1538 u8 vport_id /* ID of virtual port */; 1539 u8 default_rss_queue_flg /* set queue as default rss queue if set */; 1540 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1541 u8 complete_event_flg /* post completion to the event ring if set */; 1542 u8 stats_counter_id /* Statistics counter ID */; 1543 u8 pin_context /* Pin context in CCFC to improve performance */; 1544 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD/SGE fetch */; 1545 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet placement */; 1546 u8 pxp_st_hint /* PXP command Steering tag hint. Use enum pxp_tph_st_hint */; 1547 __le16 pxp_st_index /* PXP command Steering tag index */; 1548 u8 pmd_mode /* Indicates that current queue belongs to poll-mode driver */; 1549 u8 notify_en /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */; 1550 u8 toggle_val /* Initial value for the toggle valid bit - used in PMD mode */; 1551 u8 vf_rx_prod_index /* Index of RX producers in VF zone. Used for VF only. */; 1552 u8 vf_rx_prod_use_zone_a /* Backward compatibility mode. If set, unprotected mStorm queue zone will used for VF RX producers instead of VF zone. */; 1553 u8 reserved[5]; 1554 __le16 reserved1 /* FW reserved. */; 1555 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 1556 struct regpair bd_base /* bd address of the first bd page */; 1557 struct regpair reserved2 /* FW reserved. */; 1558}; 1559 1560 1561/* 1562 * Ramrod data for rx queue stop ramrod 1563 */ 1564struct rx_queue_stop_ramrod_data 1565{ 1566 __le16 rx_queue_id /* ID of RX queue */; 1567 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1568 u8 complete_event_flg /* post completion to the event ring if set */; 1569 u8 vport_id /* ID of virtual port */; 1570 u8 reserved[3]; 1571}; 1572 1573 1574/* 1575 * Ramrod data for rx queue update ramrod 1576 */ 1577struct rx_queue_update_ramrod_data 1578{ 1579 __le16 rx_queue_id /* ID of RX queue */; 1580 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 1581 u8 complete_event_flg /* post completion to the event ring if set */; 1582 u8 vport_id /* ID of virtual port */; 1583 u8 set_default_rss_queue /* If set, update default rss queue to this RX queue. */; 1584 u8 reserved[3]; 1585 u8 reserved1 /* FW reserved. */; 1586 u8 reserved2 /* FW reserved. */; 1587 u8 reserved3 /* FW reserved. */; 1588 __le16 reserved4 /* FW reserved. */; 1589 __le16 reserved5 /* FW reserved. */; 1590 struct regpair reserved6 /* FW reserved. */; 1591}; 1592 1593 1594/* 1595 * Ramrod data for rx Add UDP Filter 1596 */ 1597struct rx_udp_filter_data 1598{ 1599 __le16 action_icid /* CID of Action to run for this filter */; 1600 __le16 vlan_id /* Searcher String - Vlan ID */; 1601 u8 ip_type /* Searcher String - IP Type (use enum eth_ip_type) */; 1602 u8 tenant_id_exists /* Searcher String - Tenant ID Exists */; 1603 __le16 reserved1; 1604 __le32 ip_dst_addr[4] /* Searcher String - IP Destination Address, for IPv4 use ip_dst_addr[0] only */; 1605 __le32 ip_src_addr[4] /* Searcher String - IP Source Address, for IPv4 use ip_dst_addr[0] only */; 1606 __le16 udp_dst_port /* Searcher String - UDP Destination Port */; 1607 __le16 udp_src_port /* Searcher String - UDP Source Port */; 1608 __le32 tenant_id /* Searcher String - Tenant ID */; 1609}; 1610 1611 1612/* 1613 * add or delete GFT filter - filter is packet header of type of packet wished to pass certain FW flow 1614 */ 1615struct rx_update_gft_filter_data 1616{ 1617 struct regpair pkt_hdr_addr /* Pointer to Packet Header That Defines GFT Filter */; 1618 __le16 pkt_hdr_length /* Packet Header Length */; 1619 __le16 action_icid /* Action icid. Valid if action_icid_valid flag set. */; 1620 __le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */; 1621 __le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */; 1622 __le16 vport_id /* RX vport Id. For drop flow, set to ETH_GFT_TRASHCAN_VPORT. */; 1623 u8 action_icid_valid /* If set, action_icid will used for GFT filter update. */; 1624 u8 rx_qid_valid /* If set, rx_qid will used for traffic steering, in additional to vport_id. flow_id_valid must be cleared. If cleared, queue ID will selected by RSS. */; 1625 u8 flow_id_valid /* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If cleared, flow_id 0 will reported by CQE. */; 1626 u8 filter_action /* Use to set type of action on filter (use enum gft_filter_update_action) */; 1627 u8 assert_on_error /* 0 - dont assert in case of error. Just return an error code. 1 - assert in case of error. */; 1628 u8 reserved; 1629}; 1630 1631 1632 1633/* 1634 * Ramrod data for tx queue start ramrod 1635 */ 1636struct tx_queue_start_ramrod_data 1637{ 1638 __le16 sb_id /* Status block ID */; 1639 u8 sb_index /* Status block protocol index */; 1640 u8 vport_id /* VPort ID */; 1641 u8 reserved0 /* FW reserved. (qcn_rl_en) */; 1642 u8 stats_counter_id /* Statistics counter ID to use */; 1643 __le16 qm_pq_id /* QM PQ ID */; 1644 u8 flags; 1645#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 /* 0: Enable QM opportunistic flow. 1: Disable QM opportunistic flow */ 1646#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 1647#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 /* If set, Test Mode - packets will be duplicated by Xstorm handler */ 1648#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 1649#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 /* If set, Test Mode - packets destination will be determined by dest_port_mode field from Tx BD */ 1650#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 1651#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 /* Indicates that current queue belongs to poll-mode driver */ 1652#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 1653#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 /* Indicates that the current queue is using the TX notification queue mechanism - should be set only for PMD queue */ 1654#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 1655#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 /* Pin context in CCFC to improve performance */ 1656#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 1657#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 1658#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 1659 u8 pxp_st_hint /* PXP command Steering tag hint (use enum pxp_tph_st_hint) */; 1660 u8 pxp_tph_valid_bd /* PXP command TPH Valid - for BD fetch */; 1661 u8 pxp_tph_valid_pkt /* PXP command TPH Valid - for packet fetch */; 1662 __le16 pxp_st_index /* PXP command Steering tag index */; 1663 __le16 comp_agg_size /* TX completion min agg size - for PMD queues */; 1664 __le16 queue_zone_id /* queue zone ID to use */; 1665 __le16 reserved2 /* FW reserved. (test_dup_count) */; 1666 __le16 pbl_size /* Number of BD pages pointed by PBL */; 1667 __le16 tx_queue_id /* unique Queue ID - currently used only by PMD flow */; 1668 __le16 same_as_last_id /* Unique Same-As-Last Resource ID - improves performance for same-as-last packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs available) */; 1669 __le16 reserved[3]; 1670 struct regpair pbl_base_addr /* address of the pbl page */; 1671 struct regpair bd_cons_address /* BD consumer address in host - for PMD queues */; 1672}; 1673 1674 1675/* 1676 * Ramrod data for tx queue stop ramrod 1677 */ 1678struct tx_queue_stop_ramrod_data 1679{ 1680 __le16 reserved[4]; 1681}; 1682 1683 1684/* 1685 * Ramrod data for tx queue update ramrod 1686 */ 1687struct tx_queue_update_ramrod_data 1688{ 1689 __le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 1690 __le16 qm_pq_id /* Updated QM PQ ID */; 1691 __le32 reserved0; 1692 struct regpair reserved1[5]; 1693}; 1694 1695 1696 1697/* 1698 * Ramrod data for vport update ramrod 1699 */ 1700struct vport_filter_update_ramrod_data 1701{ 1702 struct eth_filter_cmd_header filter_cmd_hdr /* Header for Filter Commands (RX/TX, Add/Remove/Replace, etc) */; 1703 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT] /* Filter Commands */; 1704}; 1705 1706 1707/* 1708 * Ramrod data for vport start ramrod 1709 */ 1710struct vport_start_ramrod_data 1711{ 1712 u8 vport_id; 1713 u8 sw_fid; 1714 __le16 mtu; 1715 u8 drop_ttl0_en /* if set, drop packet with ttl=0 */; 1716 u8 inner_vlan_removal_en; 1717 struct eth_vport_rx_mode rx_mode /* Rx filter data */; 1718 struct eth_vport_tx_mode tx_mode /* Tx filter data */; 1719 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1720 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1721 u8 tx_switching_en /* Tx switching is enabled for current Vport */; 1722 u8 anti_spoofing_en /* Anti-spoofing verification is set for current Vport */; 1723 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1724 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1725 u8 silent_vlan_removal_en /* If enable then innerVlan will be striped and not written to cqe */; 1726 u8 untagged /* If set untagged filter (vlan0) is added to current Vport, otherwise port is marked as any-vlan */; 1727 struct eth_tx_err_vals tx_err_behav /* Desired behavior per TX error type */; 1728 u8 zero_placement_offset /* If set, ETH header padding will not inserted. placement_offset will be zero. */; 1729 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1730 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1731 u8 reserved[1]; 1732}; 1733 1734 1735/* 1736 * Ramrod data for vport stop ramrod 1737 */ 1738struct vport_stop_ramrod_data 1739{ 1740 u8 vport_id; 1741 u8 reserved[7]; 1742}; 1743 1744 1745/* 1746 * Ramrod data for vport update ramrod 1747 */ 1748struct vport_update_ramrod_data_cmn 1749{ 1750 u8 vport_id; 1751 u8 update_rx_active_flg /* set if rx active flag should be handled */; 1752 u8 rx_active_flg /* rx active flag value */; 1753 u8 update_tx_active_flg /* set if tx active flag should be handled */; 1754 u8 tx_active_flg /* tx active flag value */; 1755 u8 update_rx_mode_flg /* set if rx state data should be handled */; 1756 u8 update_tx_mode_flg /* set if tx state data should be handled */; 1757 u8 update_approx_mcast_flg /* set if approx. mcast data should be handled */; 1758 u8 update_rss_flg /* set if rss data should be handled */; 1759 u8 update_inner_vlan_removal_en_flg /* set if inner_vlan_removal_en should be handled */; 1760 u8 inner_vlan_removal_en; 1761 u8 update_tpa_param_flg /* set if tpa parameters should be handled, TPA must be disable before */; 1762 u8 update_tpa_en_flg /* set if tpa enable changes */; 1763 u8 update_tx_switching_en_flg /* set if tx switching en flag should be handled */; 1764 u8 tx_switching_en /* tx switching en value */; 1765 u8 update_anti_spoofing_en_flg /* set if anti spoofing flag should be handled */; 1766 u8 anti_spoofing_en /* Anti-spoofing verification en value */; 1767 u8 update_handle_ptp_pkts /* set if handle_ptp_pkts should be handled. */; 1768 u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */; 1769 u8 update_default_vlan_en_flg /* If set, the default Vlan enable flag is updated */; 1770 u8 default_vlan_en /* If set, the default Vlan value is forced by the FW */; 1771 u8 update_default_vlan_flg /* If set, the default Vlan value is updated */; 1772 __le16 default_vlan /* Default Vlan value to be forced by FW */; 1773 u8 update_accept_any_vlan_flg /* set if accept_any_vlan should be handled */; 1774 u8 accept_any_vlan /* accept_any_vlan updated value */; 1775 u8 silent_vlan_removal_en /* Set to remove vlan silently, update_inner_vlan_removal_en_flg must be enabled as well. If Rx is in noSgl mode send rx_queue_update_ramrod_data */; 1776 u8 update_mtu_flg /* If set, MTU will be updated. Vport must be not active. */; 1777 __le16 mtu /* New MTU value. Used if update_mtu_flg are set */; 1778 u8 update_ctl_frame_checks_en_flg /* If set, ctl_frame_mac_check_en and ctl_frame_ethtype_check_en will be updated */; 1779 u8 ctl_frame_mac_check_en /* If set, control frames will be filtered according to MAC check. */; 1780 u8 ctl_frame_ethtype_check_en /* If set, control frames will be filtered according to ethtype check. */; 1781 u8 reserved[15]; 1782}; 1783 1784struct vport_update_ramrod_mcast 1785{ 1786 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS] /* multicast bins */; 1787}; 1788 1789/* 1790 * Ramrod data for vport update ramrod 1791 */ 1792struct vport_update_ramrod_data 1793{ 1794 struct vport_update_ramrod_data_cmn common /* Common data for all vport update ramrods */; 1795 struct eth_vport_rx_mode rx_mode /* vport rx mode bitmap */; 1796 struct eth_vport_tx_mode tx_mode /* vport tx mode bitmap */; 1797 __le32 reserved[3]; 1798 struct eth_vport_tpa_param tpa_param /* TPA configuration parameters */; 1799 struct vport_update_ramrod_mcast approx_mcast; 1800 struct eth_vport_rss_config rss_config /* rss config data */; 1801}; 1802 1803 1804 1805 1806 1807 1808struct E4XstormEthConnAgCtxDqExtLdPart 1809{ 1810 u8 reserved0 /* cdu_validation */; 1811 u8 state /* state */; 1812 u8 flags0; 1813#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1814#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1815#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1816#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1817#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1818#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1819#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1820#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1821#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1822#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1823#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1824#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1825#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1826#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1827#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1828#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1829 u8 flags1; 1830#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1831#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1832#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1833#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1834#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 1835#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 1836#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1837#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1838#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 /* bit12 */ 1839#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 1840#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 /* bit13 */ 1841#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 1842#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1843#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 1844#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1845#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 1846 u8 flags2; 1847#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1848#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1849#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1850#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1851#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1852#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1853#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1854#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1855 u8 flags3; 1856#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 1857#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 1858#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 1859#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 1860#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 1861#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 1862#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 1863#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 1864 u8 flags4; 1865#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1866#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1867#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1868#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1869#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1870#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1871#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1872#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1873 u8 flags5; 1874#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1875#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1876#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1877#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1878#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 1879#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 1880#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1881#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1882 u8 flags6; 1883#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 1884#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 1885#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 1886#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 1887#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 1888#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 1889#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 1890#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 1891 u8 flags7; 1892#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 1893#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 1894#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 1895#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 1896#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1897#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1898#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1899#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1900#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1901#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1902 u8 flags8; 1903#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1904#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1905#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1906#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1907#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 1908#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 1909#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 1910#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 1911#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 1912#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 1913#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 1914#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 1915#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1916#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1917#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1918#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1919 u8 flags9; 1920#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1921#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1922#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1923#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1924#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1925#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1926#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1927#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1928#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 1929#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 1930#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1931#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1932#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 1933#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 1934#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 1935#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 1936 u8 flags10; 1937#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 1938#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 1939#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1940#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 1941#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1942#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 1943#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 1944#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 1945#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1946#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1947#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 1948#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 1949#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 1950#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 1951#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 1952#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 1953 u8 flags11; 1954#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 1955#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 1956#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 1957#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 1958#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1959#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 1960#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1961#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1962#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1963#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1964#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 1965#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 1966#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1967#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1968#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1969#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1970 u8 flags12; 1971#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 1972#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 1973#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1974#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1975#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1976#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1977#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1978#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1979#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 1980#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 1981#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1982#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1983#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 1984#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 1985#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 1986#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 1987 u8 flags13; 1988#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1989#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1990#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1991#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1992#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1993#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1994#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1995#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1996#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1997#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1998#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1999#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 2000#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 2001#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 2002#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 2003#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 2004 u8 flags14; 2005#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2006#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 2007#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2008#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 2009#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2010#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 2011#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2012#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2013#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2014#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 2015#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2016#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 2017#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 2018#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 2019 u8 edpm_event_id /* byte2 */; 2020 __le16 physical_q0 /* physical_q0 */; 2021 __le16 e5_reserved1 /* physical_q1 */; 2022 __le16 edpm_num_bds /* physical_q2 */; 2023 __le16 tx_bd_cons /* word3 */; 2024 __le16 tx_bd_prod /* word4 */; 2025 __le16 tx_class /* word5 */; 2026 __le16 conn_dpi /* conn_dpi */; 2027 u8 byte3 /* byte3 */; 2028 u8 byte4 /* byte4 */; 2029 u8 byte5 /* byte5 */; 2030 u8 byte6 /* byte6 */; 2031 __le32 reg0 /* reg0 */; 2032 __le32 reg1 /* reg1 */; 2033 __le32 reg2 /* reg2 */; 2034 __le32 reg3 /* reg3 */; 2035 __le32 reg4 /* reg4 */; 2036}; 2037 2038 2039struct e4_mstorm_eth_conn_ag_ctx 2040{ 2041 u8 byte0 /* cdu_validation */; 2042 u8 byte1 /* state */; 2043 u8 flags0; 2044#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2045#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2046#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2047#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2048#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2049#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2050#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2051#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2052#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2053#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2054 u8 flags1; 2055#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2056#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2057#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2058#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2059#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2060#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2061#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2062#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2063#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2064#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2065#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2066#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2067#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2068#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2069#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2070#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2071 __le16 word0 /* word0 */; 2072 __le16 word1 /* word1 */; 2073 __le32 reg0 /* reg0 */; 2074 __le32 reg1 /* reg1 */; 2075}; 2076 2077 2078 2079 2080 2081struct e4_xstorm_eth_hw_conn_ag_ctx 2082{ 2083 u8 reserved0 /* cdu_validation */; 2084 u8 state /* state */; 2085 u8 flags0; 2086#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2087#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2088#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2089#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2090#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2091#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2092#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2093#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2094#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2095#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2096#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2097#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2098#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2099#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2100#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2101#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2102 u8 flags1; 2103#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2104#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2105#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2106#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2107#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2108#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2109#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2110#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2111#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 /* bit12 */ 2112#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 2113#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 /* bit13 */ 2114#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 2115#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2116#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2117#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2118#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2119 u8 flags2; 2120#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2121#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2122#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2123#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2124#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2125#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2126#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2127#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2128 u8 flags3; 2129#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2130#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2131#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2132#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2133#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2134#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2135#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2136#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2137 u8 flags4; 2138#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2139#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2140#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2141#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2142#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2143#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2144#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2145#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2146 u8 flags5; 2147#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2148#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2149#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2150#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2151#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2152#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2153#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2154#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2155 u8 flags6; 2156#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2157#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2158#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2159#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2160#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2161#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2162#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2163#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2164 u8 flags7; 2165#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2166#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2167#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2168#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2169#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2170#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2171#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2172#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2173#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2174#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2175 u8 flags8; 2176#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2177#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2178#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2179#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2180#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2181#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2182#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2183#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2184#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2185#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2186#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2187#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2188#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2189#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2190#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2191#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2192 u8 flags9; 2193#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2194#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2195#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2196#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2197#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2198#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2199#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2200#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2201#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2202#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2203#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2204#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2205#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2206#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2207#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2208#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2209 u8 flags10; 2210#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2211#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2212#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2213#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2214#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2215#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2216#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2217#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2218#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2219#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2220#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2221#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2222#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2223#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2224#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2225#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2226 u8 flags11; 2227#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2228#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2229#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2230#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2231#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2232#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2233#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2234#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2235#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2236#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2237#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2238#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2239#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2240#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2241#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2242#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2243 u8 flags12; 2244#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2245#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2246#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2247#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2248#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2249#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2250#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2251#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2252#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2253#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2254#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2255#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2256#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2257#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2258#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2259#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2260 u8 flags13; 2261#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2262#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2263#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2264#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2265#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2266#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2267#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2268#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2269#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2270#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2271#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2272#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2273#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2274#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2275#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2276#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2277 u8 flags14; 2278#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2279#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2280#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2281#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2282#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2283#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2284#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2285#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2286#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2287#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2288#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2289#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2290#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2291#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2292 u8 edpm_event_id /* byte2 */; 2293 __le16 physical_q0 /* physical_q0 */; 2294 __le16 e5_reserved1 /* physical_q1 */; 2295 __le16 edpm_num_bds /* physical_q2 */; 2296 __le16 tx_bd_cons /* word3 */; 2297 __le16 tx_bd_prod /* word4 */; 2298 __le16 tx_class /* word5 */; 2299 __le16 conn_dpi /* conn_dpi */; 2300}; 2301 2302 2303 2304struct E5XstormEthConnAgCtxDqExtLdPart 2305{ 2306 u8 reserved0 /* cdu_validation */; 2307 u8 state_and_core_id /* state_and_core_id */; 2308 u8 flags0; 2309#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2310#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 2311#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2312#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 2313#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2314#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 2315#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2316#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 2317#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 2318#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 2319#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 2320#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 2321#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 2322#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 2323#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 2324#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 2325 u8 flags1; 2326#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 2327#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 2328#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 2329#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 2330#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 /* bit10 */ 2331#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 2332#define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 2333#define E5XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 2334#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2335#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_LO_SHIFT 4 2336#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2337#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_COPY_CONDITION_HI_SHIFT 5 2338#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2339#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 2340#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2341#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 2342 u8 flags2; 2343#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 2344#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 2345#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 2346#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 2347#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 2348#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 2349#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 2350#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 2351 u8 flags3; 2352#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 2353#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 2354#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 2355#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 2356#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 2357#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 2358#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 /* cf7 */ 2359#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 2360 u8 flags4; 2361#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 2362#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 2363#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 2364#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 2365#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 2366#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 2367#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 2368#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 2369 u8 flags5; 2370#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 2371#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 2372#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 2373#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 2374#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 2375#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 2376#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 2377#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 2378 u8 flags6; 2379#define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2380#define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 2381#define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2382#define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 2383#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 /* cf18 */ 2384#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 2385#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 /* cf19 */ 2386#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 2387 u8 flags7; 2388#define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 /* cf20 */ 2389#define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 2390#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 /* cf21 */ 2391#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 2392#define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 2393#define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 2394#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 2395#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 2396#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 2397#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 2398 u8 flags8; 2399#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 2400#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 2401#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 2402#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 2403#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 2404#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 2405#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 2406#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 2407#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 2408#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 2409#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 /* cf7en */ 2410#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 2411#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 2412#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 2413#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 2414#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 2415 u8 flags9; 2416#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 2417#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 2418#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 2419#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 2420#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 2421#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 2422#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 2423#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 2424#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 2425#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 2426#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 2427#define E5XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 2428#define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2429#define E5XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 2430#define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2431#define E5XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 2432 u8 flags10; 2433#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 /* cf18en */ 2434#define E5XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 2435#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2436#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 2437#define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2438#define E5XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 2439#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 /* cf21en */ 2440#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 2441#define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2442#define E5XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 2443#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2444#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 2445#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 /* rule0en */ 2446#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 2447#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 /* rule1en */ 2448#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 2449 u8 flags11; 2450#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 /* rule2en */ 2451#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 2452#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 /* rule3en */ 2453#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 2454#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2455#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 2456#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 2457#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 2458#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 2459#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 2460#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 2461#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 2462#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 2463#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 2464#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 2465#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 2466 u8 flags12; 2467#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 2468#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 2469#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 2470#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 2471#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 2472#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 2473#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 2474#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 2475#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 2476#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 2477#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 2478#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 2479#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 2480#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 2481#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 2482#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 2483 u8 flags13; 2484#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 2485#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 2486#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 2487#define E5XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 2488#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 2489#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 2490#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 2491#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 2492#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 2493#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 2494#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 2495#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 2496#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 2497#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 2498#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 2499#define E5XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 2500 u8 flags14; 2501#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2502#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 2503#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2504#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 2505#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2506#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 2507#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2508#define E5XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2509#define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2510#define E5XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 2511#define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2512#define E5XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 2513#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 /* cf23 */ 2514#define E5XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 2515 u8 edpm_vport /* byte2 */; 2516 __le16 physical_q0 /* physical_q0 */; 2517 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2518 __le16 edpm_num_bds /* physical_q2 */; 2519 __le16 tx_bd_cons /* word3 */; 2520 __le16 tx_bd_prod /* word4 */; 2521 __le16 tx_class /* word5 */; 2522 __le16 conn_dpi /* conn_dpi */; 2523 u8 byte3 /* byte3 */; 2524 u8 byte4 /* byte4 */; 2525 u8 byte5 /* byte5 */; 2526 u8 byte6 /* byte6 */; 2527 __le32 reg0 /* reg0 */; 2528 __le32 reg1 /* reg1 */; 2529 __le32 reg2 /* reg2 */; 2530 __le32 reg3 /* reg3 */; 2531 __le32 reg4 /* reg4 */; 2532}; 2533 2534 2535struct e5_mstorm_eth_conn_ag_ctx 2536{ 2537 u8 byte0 /* cdu_validation */; 2538 u8 byte1 /* state_and_core_id */; 2539 u8 flags0; 2540#define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2541#define E5_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2542#define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2543#define E5_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 2544#define E5_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2545#define E5_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 2546#define E5_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2547#define E5_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 2548#define E5_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2549#define E5_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 2550 u8 flags1; 2551#define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2552#define E5_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 2553#define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2554#define E5_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 2555#define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2556#define E5_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 2557#define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2558#define E5_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 2559#define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2560#define E5_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 2561#define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2562#define E5_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 2563#define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2564#define E5_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 2565#define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2566#define E5_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 2567 __le16 word0 /* word0 */; 2568 __le16 word1 /* word1 */; 2569 __le32 reg0 /* reg0 */; 2570 __le32 reg1 /* reg1 */; 2571}; 2572 2573 2574 2575 2576 2577struct e5_xstorm_eth_hw_conn_ag_ctx 2578{ 2579 u8 reserved0 /* cdu_validation */; 2580 u8 state_and_core_id /* state_and_core_id */; 2581 u8 flags0; 2582#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2583#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2584#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2585#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 2586#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2587#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 2588#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2589#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2590#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2591#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 2592#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2593#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 2594#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2595#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 2596#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2597#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 2598 u8 flags1; 2599#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2600#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 2601#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2602#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 2603#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2604#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 2605#define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2606#define E5_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 2607#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_MASK 0x1 /* bit12 */ 2608#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_LO_SHIFT 4 2609#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_MASK 0x1 /* bit13 */ 2610#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_COPY_CONDITION_HI_SHIFT 5 2611#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2612#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2613#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2614#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2615 u8 flags2; 2616#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2617#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 2618#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2619#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 2620#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2621#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 2622#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2623#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 2624 u8 flags3; 2625#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2626#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 2627#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2628#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 2629#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2630#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 2631#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2632#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 2633 u8 flags4; 2634#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2635#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 2636#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2637#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 2638#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2639#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 2640#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2641#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 2642 u8 flags5; 2643#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2644#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 2645#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2646#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 2647#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2648#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 2649#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2650#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 2651 u8 flags6; 2652#define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 /* cf16 */ 2653#define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 2654#define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 /* cf_array_cf */ 2655#define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 2656#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2657#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 2658#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2659#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2660 u8 flags7; 2661#define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2662#define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2663#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2664#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 2665#define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2666#define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2667#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2668#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 2669#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2670#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 2671 u8 flags8; 2672#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2673#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 2674#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2675#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 2676#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2677#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 2678#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2679#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 2680#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2681#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 2682#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2683#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 2684#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2685#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 2686#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2687#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 2688 u8 flags9; 2689#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2690#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 2691#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2692#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 2693#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2694#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 2695#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2696#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 2697#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2698#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 2699#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2700#define E5_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 2701#define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 /* cf16en */ 2702#define E5_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 2703#define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 /* cf_array_cf_en */ 2704#define E5_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 2705 u8 flags10; 2706#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2707#define E5_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2708#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2709#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2710#define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2711#define E5_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2712#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2713#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 2714#define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2715#define E5_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2716#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 /* cf23en */ 2717#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 2718#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2719#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 2720#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2721#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 2722 u8 flags11; 2723#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2724#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 2725#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2726#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 2727#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2728#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2729#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2730#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 2731#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2732#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 2733#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2734#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 2735#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2736#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2737#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2738#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 2739 u8 flags12; 2740#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2741#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 2742#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2743#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 2744#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2745#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2746#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2747#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2748#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2749#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 2750#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2751#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 2752#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2753#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 2754#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2755#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 2756 u8 flags13; 2757#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2758#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 2759#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2760#define E5_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 2761#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2762#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2763#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2764#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2765#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2766#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2767#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2768#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2769#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2770#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2771#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2772#define E5_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2773 u8 flags14; 2774#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 /* bit16 */ 2775#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 2776#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 /* bit17 */ 2777#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 2778#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 /* bit18 */ 2779#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 2780#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 /* bit19 */ 2781#define E5_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 2782#define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 /* bit20 */ 2783#define E5_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 2784#define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2785#define E5_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2786#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 /* cf23 */ 2787#define E5_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 2788 u8 edpm_vport /* byte2 */; 2789 __le16 physical_q0 /* physical_q0 */; 2790 __le16 tx_l2_edpm_usg_cnt /* physical_q1 */; 2791 __le16 edpm_num_bds /* physical_q2 */; 2792 __le16 tx_bd_cons /* word3 */; 2793 __le16 tx_bd_prod /* word4 */; 2794 __le16 tx_class /* word5 */; 2795 __le16 conn_dpi /* conn_dpi */; 2796}; 2797 2798 2799 2800/* 2801 * GFT CAM line struct 2802 */ 2803struct gft_cam_line 2804{ 2805 __le32 camline; 2806#define GFT_CAM_LINE_VALID_MASK 0x1 /* Indication if the line is valid. */ 2807#define GFT_CAM_LINE_VALID_SHIFT 0 2808#define GFT_CAM_LINE_DATA_MASK 0x3FFF /* Data bits, the word that compared with the profile key */ 2809#define GFT_CAM_LINE_DATA_SHIFT 1 2810#define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF /* Mask bits, indicate the bits in the data that are Dont-Care */ 2811#define GFT_CAM_LINE_MASK_BITS_SHIFT 15 2812#define GFT_CAM_LINE_RESERVED1_MASK 0x7 2813#define GFT_CAM_LINE_RESERVED1_SHIFT 29 2814}; 2815 2816 2817/* 2818 * GFT CAM line struct with fields breakout 2819 */ 2820struct gft_cam_line_mapped 2821{ 2822 __le32 camline; 2823#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 /* Indication if the line is valid. */ 2824#define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 2825#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2826#define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 2827#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 /* (use enum gft_profile_ip_version) */ 2828#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 2829#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF /* (use enum gft_profile_upper_protocol_type) */ 2830#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 2831#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF /* (use enum gft_profile_tunnel_type) */ 2832#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 2833#define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 2834#define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 2835#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 2836#define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 2837#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 2838#define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 2839#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 2840#define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 2841#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 2842#define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 2843#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 2844#define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 2845#define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 2846#define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 2847}; 2848 2849 2850union gft_cam_line_union 2851{ 2852 struct gft_cam_line cam_line; 2853 struct gft_cam_line_mapped cam_line_mapped; 2854}; 2855 2856 2857/* 2858 * Used in gft_profile_key: Indication for ip version 2859 */ 2860enum gft_profile_ip_version 2861{ 2862 GFT_PROFILE_IPV4=0, 2863 GFT_PROFILE_IPV6=1, 2864 MAX_GFT_PROFILE_IP_VERSION 2865}; 2866 2867 2868/* 2869 * Profile key stucr fot GFT logic in Prs 2870 */ 2871struct gft_profile_key 2872{ 2873 __le16 profile_key; 2874#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2875#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 2876#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 /* use enum gft_profile_ip_version (use enum gft_profile_ip_version) */ 2877#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 2878#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF /* use enum gft_profile_upper_protocol_type (use enum gft_profile_upper_protocol_type) */ 2879#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 2880#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF /* use enum gft_profile_tunnel_type (use enum gft_profile_tunnel_type) */ 2881#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 2882#define GFT_PROFILE_KEY_PF_ID_MASK 0xF 2883#define GFT_PROFILE_KEY_PF_ID_SHIFT 10 2884#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 2885#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 2886}; 2887 2888 2889/* 2890 * Used in gft_profile_key: Indication for tunnel type 2891 */ 2892enum gft_profile_tunnel_type 2893{ 2894 GFT_PROFILE_NO_TUNNEL=0, 2895 GFT_PROFILE_VXLAN_TUNNEL=1, 2896 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL=2, 2897 GFT_PROFILE_GRE_IP_TUNNEL=3, 2898 GFT_PROFILE_GENEVE_MAC_TUNNEL=4, 2899 GFT_PROFILE_GENEVE_IP_TUNNEL=5, 2900 MAX_GFT_PROFILE_TUNNEL_TYPE 2901}; 2902 2903 2904/* 2905 * Used in gft_profile_key: Indication for protocol type 2906 */ 2907enum gft_profile_upper_protocol_type 2908{ 2909 GFT_PROFILE_ROCE_PROTOCOL=0, 2910 GFT_PROFILE_RROCE_PROTOCOL=1, 2911 GFT_PROFILE_FCOE_PROTOCOL=2, 2912 GFT_PROFILE_ICMP_PROTOCOL=3, 2913 GFT_PROFILE_ARP_PROTOCOL=4, 2914 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER=5, 2915 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER=6, 2916 GFT_PROFILE_TCP_PROTOCOL=7, 2917 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER=8, 2918 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER=9, 2919 GFT_PROFILE_UDP_PROTOCOL=10, 2920 GFT_PROFILE_USER_IP_1_INNER=11, 2921 GFT_PROFILE_USER_IP_2_OUTER=12, 2922 GFT_PROFILE_USER_ETH_1_INNER=13, 2923 GFT_PROFILE_USER_ETH_2_OUTER=14, 2924 GFT_PROFILE_RAW=15, 2925 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 2926}; 2927 2928 2929/* 2930 * GFT RAM line struct 2931 */ 2932struct gft_ram_line 2933{ 2934 __le32 lo; 2935#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 /* (use enum gft_vlan_select) */ 2936#define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 2937#define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 2938#define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 2939#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 2940#define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 2941#define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 2942#define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 2943#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 2944#define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 2945#define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 2946#define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 2947#define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 2948#define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 2949#define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 2950#define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 2951#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 2952#define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 2953#define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 2954#define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 2955#define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 2956#define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 2957#define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 2958#define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 2959#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 2960#define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 2961#define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 2962#define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 2963#define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 2964#define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 2965#define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 2966#define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 2967#define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 2968#define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 2969#define GFT_RAM_LINE_TTL_MASK 0x1 2970#define GFT_RAM_LINE_TTL_SHIFT 18 2971#define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 2972#define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 2973#define GFT_RAM_LINE_RESERVED0_MASK 0x1 2974#define GFT_RAM_LINE_RESERVED0_SHIFT 20 2975#define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 2976#define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 2977#define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 2978#define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 2979#define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 2980#define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 2981#define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 2982#define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 2983#define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 2984#define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 2985#define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 2986#define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 2987#define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 2988#define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 2989#define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 2990#define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 2991#define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 2992#define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 2993#define GFT_RAM_LINE_DST_PORT_MASK 0x1 2994#define GFT_RAM_LINE_DST_PORT_SHIFT 30 2995#define GFT_RAM_LINE_SRC_PORT_MASK 0x1 2996#define GFT_RAM_LINE_SRC_PORT_SHIFT 31 2997 __le32 hi; 2998#define GFT_RAM_LINE_DSCP_MASK 0x1 2999#define GFT_RAM_LINE_DSCP_SHIFT 0 3000#define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 3001#define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 3002#define GFT_RAM_LINE_DST_IP_MASK 0x1 3003#define GFT_RAM_LINE_DST_IP_SHIFT 2 3004#define GFT_RAM_LINE_SRC_IP_MASK 0x1 3005#define GFT_RAM_LINE_SRC_IP_SHIFT 3 3006#define GFT_RAM_LINE_PRIORITY_MASK 0x1 3007#define GFT_RAM_LINE_PRIORITY_SHIFT 4 3008#define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 3009#define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 3010#define GFT_RAM_LINE_VLAN_MASK 0x1 3011#define GFT_RAM_LINE_VLAN_SHIFT 6 3012#define GFT_RAM_LINE_DST_MAC_MASK 0x1 3013#define GFT_RAM_LINE_DST_MAC_SHIFT 7 3014#define GFT_RAM_LINE_SRC_MAC_MASK 0x1 3015#define GFT_RAM_LINE_SRC_MAC_SHIFT 8 3016#define GFT_RAM_LINE_TENANT_ID_MASK 0x1 3017#define GFT_RAM_LINE_TENANT_ID_SHIFT 9 3018#define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 3019#define GFT_RAM_LINE_RESERVED1_SHIFT 10 3020}; 3021 3022 3023/* 3024 * Used in the first 2 bits for gft_ram_line: Indication for vlan mask 3025 */ 3026enum gft_vlan_select 3027{ 3028 INNER_PROVIDER_VLAN=0, 3029 INNER_VLAN=1, 3030 OUTER_PROVIDER_VLAN=2, 3031 OUTER_VLAN=3, 3032 MAX_GFT_VLAN_SELECT 3033}; 3034 3035#endif /* __ECORE_HSI_ETH__ */ 3036