1285242Sachim/******************************************************************************* 2285242Sachim*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285242Sachim* 4285242Sachim*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285242Sachim*that the following conditions are met: 6285242Sachim*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285242Sachim*following disclaimer. 8285242Sachim*2. Redistributions in binary form must reproduce the above copyright notice, 9285242Sachim*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285242Sachim*with the distribution. 11285242Sachim* 12285242Sachim*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285242Sachim*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285242Sachim*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285242Sachim*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285242Sachim*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285242Sachim*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285242Sachim*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285242Sachim*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285242Sachim 21285242Sachim********************************************************************************/ 22285242Sachim/*******************************************************************************/ 23285242Sachim/*! \file saint.c 24285242Sachim * \brief The file implements the functions to handle/enable/disable interrupt 25285242Sachim * 26285242Sachim */ 27285242Sachim/*******************************************************************************/ 28285242Sachim#include <sys/cdefs.h> 29285242Sachim__FBSDID("$FreeBSD$"); 30285242Sachim#include <dev/pms/config.h> 31285242Sachim 32285242Sachim#include <dev/pms/RefTisa/sallsdk/spc/saglobal.h> 33285242Sachim#define SA_CLEAR_ODCR_IN_INTERRUPT 34285242Sachim 35285242Sachim//#define SA_TEST_FW_SPURIOUS_INT 36285242Sachim 37285242Sachim#ifdef SA_TEST_FW_SPURIOUS_INT 38285242Sachimbit32 gOurIntCount = 0; 39285242Sachimbit32 gSpuriousIntCount = 0; 40285242Sachimbit32 gSpuriousInt[64]= 41285242Sachim{ 42285242Sachim0,0,0,0,0,0,0,0, 43285242Sachim0,0,0,0,0,0,0,0, 44285242Sachim0,0,0,0,0,0,0,0, 45285242Sachim0,0,0,0,0,0,0,0, 46285242Sachim0,0,0,0,0,0,0,0, 47285242Sachim0,0,0,0,0,0,0,0, 48285242Sachim0,0,0,0,0,0,0,0, 49285242Sachim0,0,0,0,0,0,0,0 50285242Sachim}; 51285242Sachimbit32 gSpuriousInt1[64]= 52285242Sachim{ 53285242Sachim0,0,0,0,0,0,0,0, 54285242Sachim0,0,0,0,0,0,0,0, 55285242Sachim0,0,0,0,0,0,0,0, 56285242Sachim0,0,0,0,0,0,0,0, 57285242Sachim0,0,0,0,0,0,0,0, 58285242Sachim0,0,0,0,0,0,0,0, 59285242Sachim0,0,0,0,0,0,0,0, 60285242Sachim0,0,0,0,0,0,0,0 61285242Sachim}; 62285242Sachim#endif /* SA_TEST_FW_SPURIOUS_INT */ 63285242Sachim 64285242Sachim#ifdef SA_ENABLE_TRACE_FUNCTIONS 65285242Sachim#ifdef siTraceFileID 66285242Sachim#undef siTraceFileID 67285242Sachim#endif /* siTraceFileID */ 68285242Sachim#define siTraceFileID 'G' 69285242Sachim#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 70285242Sachim 71285242SachimLOCAL FORCEINLINE bit32 siProcessOBMsg( 72285242Sachim agsaRoot_t *agRoot, 73285242Sachim bit32 count, 74285242Sachim bit32 queueNum 75285242Sachim ); 76285242Sachim 77285242SachimLOCAL bit32 siFatalInterruptHandler( 78285242Sachim agsaRoot_t *agRoot, 79285242Sachim bit32 interruptVectorIndex 80285242Sachim ) 81285242Sachim{ 82285242Sachim agsaLLRoot_t *saRoot = agNULL; 83285242Sachim agsaFatalErrorInfo_t fatal_error; 84285242Sachim bit32 value; 85285242Sachim bit32 ret = AGSA_RC_FAILURE; 86285242Sachim bit32 Sendfatal = agTRUE; 87285242Sachim 88285242Sachim SA_ASSERT((agNULL != agRoot), ""); 89285242Sachim if (agRoot == agNULL) 90285242Sachim { 91285242Sachim SA_DBG1(("siFatalInterruptHandler: agRoot == agNULL\n")); 92285242Sachim return AGSA_RC_FAILURE; 93285242Sachim } 94285242Sachim saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 95285242Sachim SA_ASSERT((agNULL != saRoot), ""); 96285242Sachim if (saRoot == agNULL) 97285242Sachim { 98285242Sachim SA_DBG1(("siFatalInterruptHandler: saRoot == agNULL\n")); 99285242Sachim return AGSA_RC_FAILURE; 100285242Sachim } 101285242Sachim 102285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 103285242Sachim if (saRoot->ResetFailed) 104285242Sachim { 105285242Sachim SA_DBG1(("siFatalInterruptHandler: ResetFailed\n")); 106285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 107285242Sachim return AGSA_RC_FAILURE; 108285242Sachim } 109285242Sachim 110285242Sachim if(SCRATCH_PAD1_V_ERROR_STATE( value ) ) 111285242Sachim { 112285242Sachim si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 113285242Sachim /* read detail fatal errors */ 114285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 115285242Sachim fatal_error.errorInfo0 = value; 116285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad0 AAP error 0x%x code 0x%x\n",SCRATCH_PAD1_V_ERROR_STATE( value ), value)); 117285242Sachim 118285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 119285242Sachim fatal_error.errorInfo1 = value; 120285242Sachim /* AAP error state */ 121285242Sachim SA_DBG1(("siFatalInterruptHandler: AAP error state and error code 0x%x\n", value)); 122285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 123285242Sachim fatal_error.errorInfo2 = value; 124285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2 0x%08x\n", fatal_error.errorInfo2 )); 125285242Sachim 126285242Sachim#if defined(SALLSDK_DEBUG) 127285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) 128285242Sachim { 129285242Sachim SA_DBG1(("siFatalInterruptHandler:SCRATCH_PAD1_V_ERROR_STATE SCRATCH_PAD2_FW_ILA_ERR 0x%08x\n", SCRATCH_PAD2_FW_ILA_ERR)); 130285242Sachim } 131285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) 132285242Sachim { 133285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FLM_ERR 0x%08x\n", SCRATCH_PAD2_FW_FLM_ERR)); 134285242Sachim } 135285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) 136285242Sachim { 137285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_FW_ASRT_ERR 0x%08x\n", SCRATCH_PAD2_FW_FW_ASRT_ERR)); 138285242Sachim } 139285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) 140285242Sachim { 141285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_WDG_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_WDG_ERR)); 142285242Sachim } 143285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) 144285242Sachim { 145285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x%08x\n", SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR)); 146285242Sachim } 147285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) 148285242Sachim { 149285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_UNDTMN_ERR 0x%08x\n",SCRATCH_PAD2_FW_UNDTMN_ERR )); 150285242Sachim } 151285242Sachim if(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) 152285242Sachim { 153285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_FATAL_ERR 0x%08x\n", SCRATCH_PAD2_FW_HW_FATAL_ERR)); 154285242Sachim } 155285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR ) 156285242Sachim { 157285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x%08x\n", value)); 158285242Sachim } 159285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR ) 160285242Sachim { 161285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x%08x\n", value)); 162285242Sachim } 163285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR ) 164285242Sachim { 165285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x%08x\n", value)); 166285242Sachim } 167285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) ==SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR ) 168285242Sachim { 169285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x%08x\n", value)); 170285242Sachim } 171285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR ) 172285242Sachim { 173285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x%08x\n", value)); 174285242Sachim } 175285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR ) 176285242Sachim { 177285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x%08x\n", value)); 178285242Sachim } 179285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR ) 180285242Sachim { 181285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x%08x\n", value)); 182285242Sachim } 183285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR ) 184285242Sachim { 185285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x%08x\n", value)); 186285242Sachim } 187285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR ) 188285242Sachim { 189285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x%08x\n", value)); 190285242Sachim } 191285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR ) 192285242Sachim { 193285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x%08x\n", value)); 194285242Sachim } 195285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR ) 196285242Sachim { 197285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x%08x\n", value)); 198285242Sachim } 199285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR ) 200285242Sachim { 201285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x%08x\n", value)); 202285242Sachim } 203285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) 204285242Sachim { 205285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x%08x\n", value)); 206285242Sachim } 207285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR ) 208285242Sachim { 209285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x%08x\n", value)); 210285242Sachim } 211285242Sachim if((fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_MASK) == SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED ) 212285242Sachim { 213285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0x%08x\n", value)); 214285242Sachim } 215285242Sachim#endif /* SALLSDK_DEBUG */ 216285242Sachim 217285242Sachim if( fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_NON_FATAL_ERR && 218285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_ILA_ERR) && 219285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FLM_ERR) && 220285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_FW_ASRT_ERR) && 221285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_WDG_ERR) && 222285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR) && 223285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_UNDTMN_ERR) && 224285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR) && 225285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR) && 226285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR) && 227285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR) && 228285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR) && 229285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR) && 230285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR) && 231285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR) && 232285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR) && 233285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR) && 234285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR) && 235285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR) && 236285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR) && 237285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED) && 238285242Sachim !(fatal_error.errorInfo2 & SCRATCH_PAD2_FW_HW_FATAL_ERR) ) 239285242Sachim { 240285242Sachim SA_DBG1(("siFatalInterruptHandler: SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x%08x\n", value)); 241285242Sachim Sendfatal = agFALSE; 242285242Sachim } 243285242Sachim 244285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 245285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad3 IOP error code 0x%08x\n", value)); 246285242Sachim fatal_error.errorInfo3 = value; 247285242Sachim 248285242Sachim if (agNULL != saRoot) 249285242Sachim { 250285242Sachim fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 251285242Sachim fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 252285242Sachim fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 253285242Sachim fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 254285242Sachim fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 255285242Sachim fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 256285242Sachim } 257285242Sachim else 258285242Sachim { 259285242Sachim fatal_error.regDumpBusBaseNum0 = 0; 260285242Sachim fatal_error.regDumpOffset0 = 0; 261285242Sachim fatal_error.regDumpLen0 = 0; 262285242Sachim fatal_error.regDumpBusBaseNum1 = 0; 263285242Sachim fatal_error.regDumpOffset1 = 0; 264285242Sachim fatal_error.regDumpLen1 = 0; 265285242Sachim } 266285242Sachim /* Call Back with error */ 267285242Sachim SA_DBG1(("siFatalInterruptHandler: Sendfatal %x HostR0 0x%x\n",Sendfatal ,ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ) )); 268285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 269285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_2_Register), 270285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Host_Scratchpad_3_Register) )); 271285242Sachim 272285242Sachim ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 273285242Sachim ret = AGSA_RC_SUCCESS; 274285242Sachim } 275285242Sachim else 276285242Sachim { 277285242Sachim bit32 host_reg0; 278285242Sachim host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 279285242Sachim if( host_reg0 == 0x2) 280285242Sachim { 281285242Sachim Sendfatal = agFALSE; 282285242Sachim 283285242Sachim SA_DBG1(("siFatalInterruptHandler: Non fatal ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 284285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 285285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 286285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 287285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 288285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 289285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 290285242Sachim 291285242Sachim ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, Sendfatal, (void *)&fatal_error, agNULL); 292285242Sachim ret = AGSA_RC_SUCCESS; 293285242Sachim } 294285242Sachim else if( host_reg0 == HDA_AES_DIF_FUNC) 295285242Sachim { 296285242Sachim SA_DBG1(("siFatalInterruptHandler: HDA_AES_DIF_FUNC 0x%x\n", 297285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register))); 298285242Sachim Sendfatal = agFALSE; 299285242Sachim ret = AGSA_RC_SUCCESS; 300285242Sachim } 301285242Sachim else 302285242Sachim { 303285242Sachim SA_DBG1(("siFatalInterruptHandler: No error detected ScratchPad1 0x%x HostR0 0x%x\n", value,host_reg0)); 304285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 305285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 306285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 307285242Sachim SA_DBG1(("siFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 308285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 309285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 310285242Sachim 311285242Sachim SA_DBG1(("siFatalInterruptHandler: Doorbell_Set %08X U %08X\n", 312285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 313285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 314285242Sachim SA_DBG1(("siFatalInterruptHandler: Doorbell_Mask %08X U %08X\n", 315285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 316285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 317285242Sachim 318285242Sachim ret = AGSA_RC_FAILURE; 319285242Sachim } 320285242Sachim } 321285242Sachim return ret; 322285242Sachim 323285242Sachim} 324285242Sachim 325285242SachimGLOBAL bit32 saFatalInterruptHandler( 326285242Sachim agsaRoot_t *agRoot, 327285242Sachim bit32 interruptVectorIndex 328285242Sachim ) 329285242Sachim{ 330285242Sachim agsaLLRoot_t *saRoot = agNULL; 331285242Sachim bit32 ret = AGSA_RC_FAILURE; 332285242Sachim 333285242Sachim /* sanity check */ 334285242Sachim SA_ASSERT((agNULL != agRoot), ""); 335285242Sachim saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 336285242Sachim SA_ASSERT((agNULL != saRoot), ""); 337285242Sachim 338285242Sachim if (saRoot->ResetFailed) 339285242Sachim { 340285242Sachim SA_DBG1(("saFatalInterruptHandler: ResetFailed\n")); 341285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 342285242Sachim return AGSA_RC_FAILURE; 343285242Sachim } 344285242Sachim if (saRoot->swConfig.fatalErrorInterruptEnable != 1) 345285242Sachim { 346285242Sachim SA_DBG1(("saFatalInterruptHandler: fatalErrorInterrtupt is NOT enabled\n")); 347285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 348285242Sachim return AGSA_RC_FAILURE; 349285242Sachim } 350285242Sachim 351285242Sachim if (saRoot->swConfig.fatalErrorInterruptVector != interruptVectorIndex) 352285242Sachim { 353285242Sachim SA_DBG1(("saFatalInterruptHandler: interruptVectorIndex does not match 0x%x 0x%x\n", 354285242Sachim saRoot->swConfig.fatalErrorInterruptVector, interruptVectorIndex)); 355285242Sachim SA_DBG1(("saFatalInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 356285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 357285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 358285242Sachim SA_DBG1(("saFatalInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 359285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 360285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 361285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 362285242Sachim return AGSA_RC_FAILURE; 363285242Sachim } 364285242Sachim 365285242Sachim ret = siFatalInterruptHandler(agRoot,interruptVectorIndex); 366285242Sachim 367285242Sachim 368285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 369285242Sachim 370285242Sachim return ret; 371285242Sachim} 372285242Sachim/******************************************************************************/ 373285242Sachim/*! \brief Function to process the interrupts 374285242Sachim * 375285242Sachim * The saInterruptHandler() function is called after an interrupts has 376285242Sachim * been received 377285242Sachim * This function disables interrupts 378285242Sachim * 379285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 380285242Sachim * instance of SAS/SATA hardware 381285242Sachim * \param interruptVectorIndex message that caused MSI message 382285242Sachim * 383285242Sachim * \return TRUE if we caused interrupt 384285242Sachim * 385285242Sachim */ 386285242Sachim/*******************************************************************************/ 387285242SachimFORCEINLINE bit32 388285242SachimsaInterruptHandler( 389285242Sachim agsaRoot_t *agRoot, 390285242Sachim bit32 interruptVectorIndex 391285242Sachim ) 392285242Sachim{ 393285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 394285242Sachim bit32 ToBeProcessedCount = 0; 395285242Sachim bit32 our_int = 0; 396285242Sachim#ifdef SA_TEST_FW_SPURIOUS_INT 397285242Sachim bit8 i; 398285242Sachim#endif/* SA_TEST_FW_SPURIOUS_INT */ 399285242Sachim 400285242Sachim if( agNULL == saRoot ) 401285242Sachim { 402285242Sachim /* Can be called before initialize is completed in a shared 403285242Sachim interrupt environment like windows 2003 404285242Sachim */ 405285242Sachim return(ToBeProcessedCount); 406285242Sachim } 407285242Sachim 408285242Sachim if( (our_int = saRoot->OurInterrupt(agRoot,interruptVectorIndex)) == FALSE ) 409285242Sachim { 410285242Sachim#ifdef SA_TEST_FW_SPURIOUS_INT 411285242Sachim gSpuriousIntCount++; 412285242Sachim smTrace(hpDBG_REGISTERS,"S1",gSpuriousIntCount); 413285242Sachim /* TP:S1 gSpuriousIntCount */ 414285242Sachim#endif /* SA_TEST_FW_SPURIOUS_INT */ 415285242Sachim return(ToBeProcessedCount); 416285242Sachim } 417285242Sachim 418285242Sachim smTraceFuncEnter(hpDBG_TICK_INT, "5q"); 419285242Sachim 420285242Sachim smTrace(hpDBG_TICK_INT,"VI",interruptVectorIndex); 421285242Sachim /* TP:Vi interrupt VectorIndex */ 422285242Sachim 423285242Sachim if ( agFALSE == saRoot->sysIntsActive ) 424285242Sachim { 425285242Sachim // SA_ASSERT(0, "saInterruptHandler sysIntsActive not set"); 426285242Sachim 427285242Sachim#ifdef SA_PRINTOUT_IN_WINDBG 428285242Sachim#ifndef DBG 429285242Sachim DbgPrint("saInterruptHandler: sysIntsActive not set Doorbell_Mask_Set %08X U %08X\n", 430285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 431285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU) ); 432285242Sachim#endif /* DBG */ 433285242Sachim#endif /* SA_PRINTOUT_IN_WINDBG */ 434285242Sachim 435285242Sachim 436285242Sachim SA_DBG1(("saInterruptHandler: Doorbell_Mask_Set %08X U %08X\n", 437285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 438285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 439285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 440285242Sachim return(ToBeProcessedCount); 441285242Sachim 442285242Sachim } 443285242Sachim 444285242Sachim /* Allow replacement of disable interrupt */ 445285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 446285242Sachim 447285242Sachim 448285242Sachim#ifdef SA_TEST_FW_SPURIOUS_INT 449285242Sachim 450285242Sachim /* count for my interrupt */ 451285242Sachim gOurIntCount++; 452285242Sachim 453285242Sachim smTrace(hpDBG_REGISTERS,"S4",gOurIntCount); 454285242Sachim /* TP:S4 gOurIntCount */ 455285242Sachim#endif /* SA_TEST_FW_SPURIOUS_INT */ 456285242Sachim 457285242Sachim smTraceFuncExit(hpDBG_TICK_INT, 'a', "5q"); 458285242Sachim return(TRUE); 459285242Sachim 460285242Sachim} 461285242Sachim 462285242Sachim/******************************************************************************/ 463285242Sachim/*! \brief Function to disable MSIX interrupts 464285242Sachim * 465285242Sachim * siDisableMSIXInterrupts disables interrupts 466285242Sachim * called thru macro ossaDisableInterrupts 467285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 468285242Sachim * instance of SAS/SATA hardware 469285242Sachim * \param interruptVectorIndex - vector index for message 470285242Sachim * 471285242Sachim */ 472285242Sachim/*******************************************************************************/ 473285242SachimGLOBAL void siDisableMSIXInterrupts( 474285242Sachim agsaRoot_t *agRoot, 475285242Sachim bit32 interruptVectorIndex 476285242Sachim ) 477285242Sachim{ 478285242Sachim bit32 msi_index; 479285242Sachim#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 480285242Sachim bit32 value; 481285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 482285242Sachim msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 483285242Sachim msi_index += MSIX_TABLE_BASE; 484285242Sachim ossaHwRegWrite(agRoot,msi_index , MSIX_INTERRUPT_DISABLE); 485285242Sachim ossaHwRegRead(agRoot, msi_index); /* Dummy read */ 486285242Sachim#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 487285242Sachim value = (1 << interruptVectorIndex); 488285242Sachim ossaHwRegWrite(agRoot, MSGU_ODCR, value); 489285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 490285242Sachim} 491285242Sachim 492285242Sachim/******************************************************************************/ 493285242Sachim/*! \brief Function to disable MSIX V interrupts 494285242Sachim * 495285242Sachim * siDisableMSIXInterrupts disables interrupts 496285242Sachim * called thru macro ossaDisableInterrupts 497285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 498285242Sachim * instance of SAS/SATA hardware 499285242Sachim * \param interruptVectorIndex - vector index for message 500285242Sachim * 501285242Sachim */ 502285242Sachim/*******************************************************************************/ 503285242Sachimvoid siDisableMSIX_V_Interrupts( 504285242Sachim agsaRoot_t *agRoot, 505285242Sachim bit32 interruptVectorIndex 506285242Sachim ) 507285242Sachim{ 508285242Sachim bit64 mask; 509285242Sachim agsabit32bit64 u64; 510285242Sachim mask =( (bit64)1 << interruptVectorIndex); 511285242Sachim u64.B64 = mask; 512285242Sachim if(smIS64bInt(agRoot)) 513285242Sachim { 514285242Sachim SA_DBG4(("siDisableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 515285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[1]); 516285242Sachim } 517285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, u64.S32[0]); 518285242Sachim 519285242Sachim} 520285242Sachim/******************************************************************************/ 521285242Sachim/*! \brief Function to disable MSI interrupts 522285242Sachim * 523285242Sachim * siDisableMSIInterrupts disables interrupts 524285242Sachim * called thru macro ossaDisableInterrupts 525285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 526285242Sachim * instance of SAS/SATA hardware 527285242Sachim * \param interruptVectorIndex - vector index for message 528285242Sachim * 529285242Sachim */ 530285242Sachim/*******************************************************************************/ 531285242SachimGLOBAL void siDisableMSIInterrupts( 532285242Sachim agsaRoot_t *agRoot, 533285242Sachim bit32 interruptVectorIndex 534285242Sachim ) 535285242Sachim{ 536285242Sachim bit32 ODMRValue; 537285242Sachim bit32 mask; 538285242Sachim mask = 1 << interruptVectorIndex; 539285242Sachim 540285242Sachim /*Must be protected for interuption */ 541285242Sachim ODMRValue = ossaHwRegRead(agRoot, MSGU_ODMR); 542285242Sachim ODMRValue |= mask; 543285242Sachim 544285242Sachim ossaHwRegWrite(agRoot, MSGU_ODMR, ODMRValue); 545285242Sachim ossaHwRegWrite(agRoot, MSGU_ODCR, mask); 546285242Sachim} 547285242Sachim 548285242Sachim/******************************************************************************/ 549285242Sachim/*! \brief Function to disable MSI V interrupts 550285242Sachim * 551285242Sachim * siDisableMSIInterrupts disables interrupts 552285242Sachim * called thru macro ossaDisableInterrupts 553285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 554285242Sachim * instance of SAS/SATA hardware 555285242Sachim * \param interruptVectorIndex - vector index for message 556285242Sachim * 557285242Sachim */ 558285242Sachim/*******************************************************************************/ 559285242SachimGLOBAL void siDisableMSI_V_Interrupts( 560285242Sachim agsaRoot_t *agRoot, 561285242Sachim bit32 interruptVectorIndex 562285242Sachim ) 563285242Sachim{ 564285242Sachim SA_ASSERT(0, "Should not be called"); 565285242Sachim SA_DBG4(("siDisableMSI_V_Interrupts:\n")); 566285242Sachim} 567285242Sachim 568285242Sachim/******************************************************************************/ 569285242Sachim/*! \brief Function to process Legacy interrupts 570285242Sachim * 571285242Sachim * siDisableLegacyInterrupts disables interrupts 572285242Sachim * called thru macro ossaDisableInterrupts 573285242Sachim * 574285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 575285242Sachim * instance of SAS/SATA hardware 576285242Sachim * \param interruptVectorIndex not used in legacy case 577285242Sachim * 578285242Sachim */ 579285242Sachim/*******************************************************************************/ 580285242SachimGLOBAL void siDisableLegacyInterrupts( 581285242Sachim agsaRoot_t *agRoot, 582285242Sachim bit32 interruptVectorIndex 583285242Sachim ) 584285242Sachim{ 585285242Sachim ossaHwRegWrite(agRoot, MSGU_ODMR, ODMR_MASK_ALL); 586285242Sachim#ifndef SA_CLEAR_ODCR_IN_INTERRUPT 587285242Sachim ossaHwRegWrite(agRoot, MSGU_ODCR, ODCR_CLEAR_ALL); 588285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 589285242Sachim} 590285242Sachim 591285242Sachim/******************************************************************************/ 592285242Sachim/*! \brief Function to process Legacy V interrupts 593285242Sachim * 594285242Sachim * siDisableLegacyInterrupts disables interrupts 595285242Sachim * called thru macro ossaDisableInterrupts 596285242Sachim * 597285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 598285242Sachim * instance of SAS/SATA hardware 599285242Sachim * \param interruptVectorIndex not used in legacy case 600285242Sachim * 601285242Sachim */ 602285242Sachim/*******************************************************************************/ 603285242SachimGLOBAL void siDisableLegacy_V_Interrupts( 604285242Sachim agsaRoot_t *agRoot, 605285242Sachim bit32 interruptVectorIndex 606285242Sachim ) 607285242Sachim{ 608285242Sachim 609285242Sachim bit64 mask; 610285242Sachim agsabit32bit64 u64; 611285242Sachim mask =( (bit64)1 << interruptVectorIndex); 612285242Sachim u64.B64 = mask; 613285242Sachim 614285242Sachim SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 615285242Sachim SA_DBG4(("siDisableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 616285242Sachim if(smIS64bInt(agRoot)) 617285242Sachim { 618285242Sachim SA_DBG4(("siDisableLegacy_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 619285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register,u64.S32[1] ); 620285242Sachim } 621285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU,u64.S32[0]); 622285242Sachim 623285242Sachim} 624285242Sachim/******************************************************************************/ 625285242Sachim/*! \brief Function to process MSIX interrupts 626285242Sachim * 627285242Sachim * siOurMSIXInterrupt checks if we generated interrupt 628285242Sachim * called thru function pointer saRoot->OurInterrupt 629285242Sachim * 630285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 631285242Sachim * instance of SAS/SATA hardware 632285242Sachim * \return always true 633285242Sachim */ 634285242Sachim/*******************************************************************************/ 635285242SachimGLOBAL bit32 siOurMSIXInterrupt( 636285242Sachim agsaRoot_t *agRoot, 637285242Sachim bit32 interruptVectorIndex 638285242Sachim ) 639285242Sachim{ 640285242Sachim return(TRUE); 641285242Sachim} 642285242Sachim 643285242Sachim/******************************************************************************/ 644285242Sachim/*! \brief Function to process MSIX V interrupts 645285242Sachim * 646285242Sachim * siOurMSIXInterrupt checks if we generated interrupt 647285242Sachim * called thru function pointer saRoot->OurInterrupt 648285242Sachim * 649285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 650285242Sachim * instance of SAS/SATA hardware 651285242Sachim * \return always true 652285242Sachim */ 653285242Sachim/*******************************************************************************/ 654285242SachimGLOBAL bit32 siOurMSIX_V_Interrupt( 655285242Sachim agsaRoot_t *agRoot, 656285242Sachim bit32 interruptVectorIndex 657285242Sachim ) 658285242Sachim{ 659285242Sachim return(TRUE); 660285242Sachim} 661285242Sachim/******************************************************************************/ 662285242Sachim/*! \brief Function to process MSI interrupts 663285242Sachim * 664285242Sachim * siOurMSIInterrupt checks if we generated interrupt 665285242Sachim * called thru function pointer saRoot->OurInterrupt 666285242Sachim * 667285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 668285242Sachim * instance of SAS/SATA hardware 669285242Sachim * \return always true 670285242Sachim */ 671285242Sachim/*******************************************************************************/ 672285242Sachimbit32 siOurMSIInterrupt( 673285242Sachim agsaRoot_t *agRoot, 674285242Sachim bit32 interruptVectorIndex 675285242Sachim ) 676285242Sachim{ 677285242Sachim return(TRUE); 678285242Sachim} 679285242Sachim 680285242Sachim/******************************************************************************/ 681285242Sachim/*! \brief Function to process MSI V interrupts 682285242Sachim * 683285242Sachim * siOurMSIInterrupt checks if we generated interrupt 684285242Sachim * called thru function pointer saRoot->OurInterrupt 685285242Sachim * 686285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 687285242Sachim * instance of SAS/SATA hardware 688285242Sachim * \return always true 689285242Sachim */ 690285242Sachim/*******************************************************************************/ 691285242Sachimbit32 siOurMSI_V_Interrupt( 692285242Sachim agsaRoot_t *agRoot, 693285242Sachim bit32 interruptVectorIndex 694285242Sachim ) 695285242Sachim{ 696285242Sachim SA_DBG4((":siOurMSI_V_Interrupt\n")); 697285242Sachim return(TRUE); 698285242Sachim} 699285242Sachim 700285242Sachim/******************************************************************************/ 701285242Sachim/*! \brief Function to process Legacy interrupts 702285242Sachim * 703285242Sachim * siOurLegacyInterrupt checks if we generated interrupt 704285242Sachim * called thru function pointer saRoot->OurInterrupt 705285242Sachim * 706285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 707285242Sachim * instance of SAS/SATA hardware 708285242Sachim * \return true if we claim interrupt 709285242Sachim */ 710285242Sachim/*******************************************************************************/ 711285242Sachimbit32 siOurLegacyInterrupt( 712285242Sachim agsaRoot_t *agRoot, 713285242Sachim bit32 interruptVectorIndex 714285242Sachim ) 715285242Sachim{ 716285242Sachim bit32 Int_masked; 717285242Sachim bit32 Int_active; 718285242Sachim Int_masked = MSGU_READ_ODMR; 719285242Sachim Int_active = MSGU_READ_ODR; 720285242Sachim 721285242Sachim if(Int_masked & 1 ) 722285242Sachim { 723285242Sachim return(FALSE); 724285242Sachim } 725285242Sachim if(Int_active & 1 ) 726285242Sachim { 727285242Sachim 728285242Sachim return(TRUE); 729285242Sachim } 730285242Sachim return(FALSE); 731285242Sachim} 732285242Sachim 733285242Sachim/******************************************************************************/ 734285242Sachim/*! \brief Function to process Legacy V interrupts 735285242Sachim * 736285242Sachim * siOurLegacyInterrupt checks if we generated interrupt 737285242Sachim * called thru function pointer saRoot->OurInterrupt 738285242Sachim * 739285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 740285242Sachim * instance of SAS/SATA hardware 741285242Sachim * \return true if we claim interrupt 742285242Sachim */ 743285242Sachim/*******************************************************************************/ 744285242Sachimbit32 siOurLegacy_V_Interrupt( 745285242Sachim agsaRoot_t *agRoot, 746285242Sachim bit32 interruptVectorIndex 747285242Sachim ) 748285242Sachim{ 749285242Sachim bit32 Int_active; 750285242Sachim Int_active = siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register ); 751285242Sachim 752285242Sachim return(Int_active ? TRUE : FALSE); 753285242Sachim} 754285242Sachim 755285242Sachim 756285242Sachim/******************************************************************************/ 757285242Sachim/*! \brief Function to process the cause of interrupt 758285242Sachim * 759285242Sachim * The saDelayedInterruptHandler() function is called after an interrupt messages has 760285242Sachim * been received it may be called by a deferred procedure call 761285242Sachim * 762285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 763285242Sachim * instance of SAS/SATA hardware 764285242Sachim * \param interruptVectorIndex - vector index for message 765285242Sachim * \param count Number of completion queue entries to consume 766285242Sachim * 767285242Sachim * \return number of messages processed 768285242Sachim * 769285242Sachim */ 770285242Sachim/*******************************************************************************/ 771285242SachimFORCEINLINE bit32 772285242SachimsaDelayedInterruptHandler( 773285242Sachim agsaRoot_t *agRoot, 774285242Sachim bit32 interruptVectorIndex, 775285242Sachim bit32 count 776285242Sachim ) 777285242Sachim{ 778285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 779285242Sachim bit32 processedMsgCount = 0; 780285242Sachim bit32 pad1 = 0; 781285242Sachim bit32 host_reg0 = 0; 782285242Sachim#if defined(SALLSDK_DEBUG) 783285242Sachim bit32 host_reg1 = 0; 784285242Sachim#endif 785285242Sachim bit8 i = 0; 786285242Sachim 787285242Sachim OSSA_OUT_ENTER(agRoot); 788285242Sachim 789285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5p"); 790285242Sachim 791285242Sachim smTrace(hpDBG_VERY_LOUD,"Vd",interruptVectorIndex); 792285242Sachim /* TP:Vd delayed VectorIndex */ 793285242Sachim smTrace(hpDBG_VERY_LOUD,"Vc",count); 794285242Sachim /* TP:Vc IOMB count*/ 795285242Sachim 796285242Sachim if( saRoot->swConfig.fatalErrorInterruptEnable && 797285242Sachim saRoot->swConfig.fatalErrorInterruptVector == interruptVectorIndex ) 798285242Sachim { 799285242Sachim pad1 = siHalRegReadExt(agRoot,GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 800285242Sachim host_reg0 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_0_Register ); 801285242Sachim 802285242Sachim 803285242Sachim if(saRoot->swConfig.hostDirectAccessMode & 2 ) 804285242Sachim { 805285242Sachim if( host_reg0 == HDA_AES_DIF_FUNC) 806285242Sachim { 807285242Sachim host_reg0 = 0; 808285242Sachim } 809285242Sachim } 810285242Sachim 811285242Sachim 812285242Sachim#if defined(SALLSDK_DEBUG) 813285242Sachim host_reg1 = ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_Rsvd_1_Register ); 814285242Sachim#endif 815285242Sachim if( (SCRATCH_PAD1_V_ERROR_STATE( pad1 ) != 0 ) && host_reg0 ) 816285242Sachim { 817285242Sachim 818285242Sachim SA_DBG1(("saDelayedInterruptHandler: vi %d Error %08X\n",interruptVectorIndex, SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 819285242Sachim SA_DBG1(("saDelayedInterruptHandler: Sp 1 %08X Hr0 %08X Hr1 %08X\n",pad1,host_reg0,host_reg1 )); 820285242Sachim SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ERROR_STATE( pad1 ))); 821285242Sachim SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_ILA_ERROR_STATE %08X\n", SCRATCH_PAD1_V_ILA_ERROR_STATE( pad1 ))); 822285242Sachim SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_RAAE_ERROR_STATE %08X\n", SCRATCH_PAD1_V_RAAE_ERROR_STATE( pad1 ))); 823285242Sachim SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP0_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP0_ERROR_STATE( pad1 ))); 824285242Sachim SA_DBG1(("saDelayedInterruptHandler: SCRATCH_PAD1_V_IOP1_ERROR_STATE %08X\n", SCRATCH_PAD1_V_IOP1_ERROR_STATE( pad1 ))); 825285242Sachim 826285242Sachim siFatalInterruptHandler( agRoot, interruptVectorIndex ); 827285242Sachim ossaDisableInterrupts(agRoot, interruptVectorIndex); 828285242Sachim 829285242Sachim } 830285242Sachim else 831285242Sachim { 832285242Sachim SA_DBG2(("saDelayedInterruptHandler: Fatal Check VI %d SCRATCH_PAD1 %08X host_reg0 %08X host_reg1 %08X\n",interruptVectorIndex, pad1,host_reg0,host_reg1)); 833285242Sachim SA_DBG2(("saDelayedInterruptHandler: ScratchPad0 0x%x ScratchPad1 0x%x\n", 834285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_0_Register), 835285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_1_Register) )); 836285242Sachim SA_DBG2(("saDelayedInterruptHandler: ScratchPad2 0x%x ScratchPad3 0x%x\n", 837285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_2_Register), 838285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0,V_Scratchpad_3_Register) )); 839285242Sachim 840285242Sachim SA_DBG2(("saDelayedInterruptHandler: Doorbell_Set %08X U %08X\n", 841285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 842285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 843285242Sachim SA_DBG2(("saDelayedInterruptHandler: Doorbell_Mask %08X U %08X\n", 844285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 845285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 846285242Sachim } 847285242Sachim 848285242Sachim } 849285242Sachim 850285242Sachim 851285242Sachim#ifdef SA_LNX_PERF_MODE 852285242Sachim return siProcessOBMsg(agRoot, count, interruptVectorIndex); 853285242Sachim#endif 854285242Sachim 855285242Sachim /* check all the configuration outbound queues within a vector bitmap */ 856285242Sachim SA_ASSERT((saRoot->QueueConfig.numOutboundQueues < 65), "numOutboundQueue"); 857285242Sachim 858285242Sachim for ( i = 0; i < saRoot->QueueConfig.numOutboundQueues; i++ ) 859285242Sachim { 860285242Sachim /* process IOMB in the outbound queue 0 to 31 if bit set in the vector bitmap */ 861285242Sachim if (i < OQ_NUM_32) 862285242Sachim { 863285242Sachim if (saRoot->interruptVecIndexBitMap[interruptVectorIndex] & (1 << i)) 864285242Sachim { 865285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 866285242Sachim } 867285242Sachim else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 868285242Sachim { 869285242Sachim /* polling mode - interruptVectorIndex = 0 only and no bit set */ 870285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 871285242Sachim } 872285242Sachim#ifdef SA_FW_TEST_INTERRUPT_REASSERT 873285242Sachim else if (saRoot->CheckAll) 874285242Sachim { 875285242Sachim /* polling mode - interruptVectorIndex = 0 only and no bit set */ 876285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 877285242Sachim } 878285242Sachim#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 879285242Sachim 880285242Sachim } 881285242Sachim else 882285242Sachim { 883285242Sachim /* process IOMB in the outbound queue 32 to 63 if bit set in the vector bitmap */ 884285242Sachim if (saRoot->interruptVecIndexBitMap1[interruptVectorIndex] & (1 << (i - OQ_NUM_32))) 885285242Sachim { 886285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 887285242Sachim } 888285242Sachim /* check interruptEnable bit for polling mode of OQ */ 889285242Sachim /* the following code can be removed, we do not care about the bit */ 890285242Sachim else if (saRoot->QueueConfig.outboundQueues[i].interruptEnable == 0) 891285242Sachim { 892285242Sachim /* polling mode - interruptVectorIndex = 0 only and no bit set */ 893285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 894285242Sachim } 895285242Sachim#ifdef SA_FW_TEST_INTERRUPT_REASSERT 896285242Sachim else if (saRoot->CheckAll) 897285242Sachim { 898285242Sachim /* polling mode - interruptVectorIndex = 0 only and no bit set */ 899285242Sachim processedMsgCount += siProcessOBMsg(agRoot, count, i); 900285242Sachim } 901285242Sachim#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 902285242Sachim } 903285242Sachim } 904285242Sachim 905285242Sachim#ifdef SA_FW_TEST_INTERRUPT_REASSERT 906285242Sachim saRoot->CheckAll = 0; 907285242Sachim#endif /* SA_FW_TEST_INTERRUPT_REASSERT */ 908285242Sachim 909285242Sachim#ifndef SA_RENABLE_IN_OSLAYER 910285242Sachim if ( agTRUE == saRoot->sysIntsActive ) 911285242Sachim { 912285242Sachim /* Allow replacement of enable interrupt */ 913285242Sachim ossaReenableInterrupts(agRoot, interruptVectorIndex); 914285242Sachim } 915285242Sachim#endif /* SA_RENABLE_IN_OSLAYER */ 916285242Sachim 917285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5p"); 918285242Sachim 919285242Sachim OSSA_OUT_LEAVE(agRoot); 920285242Sachim return processedMsgCount; 921285242Sachim} 922285242Sachim 923285242Sachim/******************************************************************************/ 924285242Sachim/*! \brief Function to reenable MSIX interrupts 925285242Sachim * 926285242Sachim * siReenableMSIXInterrupts reenableinterrupts 927285242Sachim * called thru macro ossaReenableInterrupts 928285242Sachim * 929285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 930285242Sachim * instance of SAS/SATA hardware 931285242Sachim * \param interruptVectorIndex - vector index for message 932285242Sachim * 933285242Sachim */ 934285242Sachim/*******************************************************************************/ 935285242Sachimvoid siReenableMSIXInterrupts( 936285242Sachim agsaRoot_t *agRoot, 937285242Sachim bit32 interruptVectorIndex 938285242Sachim ) 939285242Sachim{ 940285242Sachim bit32 msi_index; 941285242Sachim#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 942285242Sachim bit32 value; 943285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 944285242Sachim msi_index = interruptVectorIndex * MSIX_TABLE_ELEMENT_SIZE; 945285242Sachim msi_index += MSIX_TABLE_BASE; 946285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,msi_index, MSIX_INTERRUPT_ENABLE); 947285242Sachim 948285242Sachim SA_DBG4(("siReenableMSIXInterrupts:interruptVectorIndex %d\n",interruptVectorIndex)); 949285242Sachim 950285242Sachim#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 951285242Sachim value = (1 << interruptVectorIndex); 952285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, value); 953285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 954285242Sachim} 955285242Sachim/******************************************************************************/ 956285242Sachim/*! \brief Function to reenable MSIX interrupts 957285242Sachim * 958285242Sachim * siReenableMSIXInterrupts reenableinterrupts 959285242Sachim * called thru macro ossaReenableInterrupts 960285242Sachim * 961285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 962285242Sachim * instance of SAS/SATA hardware 963285242Sachim * \param interruptVectorIndex - vector index for message 964285242Sachim * 965285242Sachim */ 966285242Sachim/*******************************************************************************/ 967285242Sachimvoid siReenableMSIX_V_Interrupts( 968285242Sachim agsaRoot_t *agRoot, 969285242Sachim bit32 interruptVectorIndex 970285242Sachim ) 971285242Sachim{ 972285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 973285242Sachim bit64 mask; 974285242Sachim agsabit32bit64 u64; 975285242Sachim mask =( (bit64)1 << interruptVectorIndex); 976285242Sachim u64.B64 = mask; 977285242Sachim 978285242Sachim SA_DBG4(("siReenableMSIX_V_Interrupts:\n")); 979285242Sachim 980285242Sachim if(saRoot->sysIntsActive) 981285242Sachim { 982285242Sachim if(smIS64bInt(agRoot)) 983285242Sachim { 984285242Sachim SA_DBG4(("siReenableMSIX_V_Interrupts: VI %d U 0x%08X L 0x%08X\n",interruptVectorIndex,u64.S32[1],u64.S32[0])); 985285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_RegisterU,u64.S32[1] ); 986285242Sachim } 987285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register,u64.S32[0]); 988285242Sachim } 989285242Sachim else 990285242Sachim { 991285242Sachim SA_DBG1(("siReenableMSIX_V_Interrupts: VI %d sysIntsActive off\n",interruptVectorIndex)); 992285242Sachim } 993285242Sachim 994285242Sachim} 995285242Sachim 996285242Sachim/******************************************************************************/ 997285242Sachim/*! \brief Function to reenable MSI interrupts 998285242Sachim * 999285242Sachim * siReenableMSIXInterrupts reenableinterrupts 1000285242Sachim * called thru macro ossaReenableInterrupts 1001285242Sachim * 1002285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1003285242Sachim * instance of SAS/SATA hardware 1004285242Sachim * \param interruptVectorIndex - vector index for message 1005285242Sachim * 1006285242Sachim */ 1007285242Sachim/*******************************************************************************/ 1008285242SachimGLOBAL void siReenableMSIInterrupts( 1009285242Sachim agsaRoot_t *agRoot, 1010285242Sachim bit32 interruptVectorIndex 1011285242Sachim ) 1012285242Sachim{ 1013285242Sachim bit32 ODMRValue; 1014285242Sachim 1015285242Sachim ODMRValue = siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR); 1016285242Sachim ODMRValue &= ~(1 << interruptVectorIndex); 1017285242Sachim 1018285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMRValue); 1019285242Sachim} 1020285242Sachim 1021285242Sachim/******************************************************************************/ 1022285242Sachim/*! \brief Function to reenable MSI V interrupts 1023285242Sachim * 1024285242Sachim * siReenableMSIXInterrupts reenableinterrupts 1025285242Sachim * called thru macro ossaReenableInterrupts 1026285242Sachim * 1027285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1028285242Sachim * instance of SAS/SATA hardware 1029285242Sachim * \param interruptVectorIndex - vector index for message 1030285242Sachim * 1031285242Sachim */ 1032285242Sachim/*******************************************************************************/ 1033285242SachimGLOBAL void siReenableMSI_V_Interrupts( 1034285242Sachim agsaRoot_t *agRoot, 1035285242Sachim bit32 interruptVectorIndex 1036285242Sachim ) 1037285242Sachim{ 1038285242Sachim SA_ASSERT(0, "Should not be called"); 1039285242Sachim 1040285242Sachim SA_DBG4(("siReenableMSI_V_Interrupts:\n")); 1041285242Sachim 1042285242Sachim} 1043285242Sachim/******************************************************************************/ 1044285242Sachim/*! \brief Function to reenable Legacy interrupts 1045285242Sachim * 1046285242Sachim * siReenableLegacyInterrupts reenableinterrupts 1047285242Sachim * called thru macro ossaReenableInterrupts 1048285242Sachim * 1049285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1050285242Sachim * instance of SAS/SATA hardware 1051285242Sachim * \param interruptVectorIndex always zero 1052285242Sachim * 1053285242Sachim */ 1054285242Sachim/*******************************************************************************/ 1055285242SachimGLOBAL void siReenableLegacyInterrupts( 1056285242Sachim agsaRoot_t *agRoot, 1057285242Sachim bit32 interruptVectorIndex 1058285242Sachim ) 1059285242Sachim{ 1060285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, ODMR_CLEAR_ALL); 1061285242Sachim 1062285242Sachim#ifdef SA_CLEAR_ODCR_IN_INTERRUPT 1063285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR, ODCR_CLEAR_ALL); 1064285242Sachim#endif /* SA_CLEAR_ODCR_IN_INTERRUPT */ 1065285242Sachim} 1066285242Sachim 1067285242Sachim/******************************************************************************/ 1068285242Sachim/*! \brief Function to reenable Legacy V interrupts 1069285242Sachim * 1070285242Sachim * siReenableLegacyInterrupts reenableinterrupts 1071285242Sachim * called thru macro ossaReenableInterrupts 1072285242Sachim * 1073285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1074285242Sachim * instance of SAS/SATA hardware 1075285242Sachim * \param interruptVectorIndex always zero 1076285242Sachim * 1077285242Sachim */ 1078285242Sachim/*******************************************************************************/ 1079285242SachimGLOBAL void siReenableLegacy_V_Interrupts( 1080285242Sachim agsaRoot_t *agRoot, 1081285242Sachim bit32 interruptVectorIndex 1082285242Sachim ) 1083285242Sachim{ 1084285242Sachim 1085285242Sachim bit32 mask; 1086285242Sachim mask = 1 << interruptVectorIndex; 1087285242Sachim 1088285242Sachim SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register))); 1089285242Sachim SA_DBG5(("siReenableLegacy_V_Interrupts:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1090285242Sachim 1091285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Clear_Register, mask); 1092285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, mask ); 1093285242Sachim 1094285242Sachim 1095285242Sachim SA_DBG5(("siReenableLegacy_V_Interrupts:OUT MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register ))); 1096285242Sachim 1097285242Sachim} 1098285242Sachim 1099285242Sachim/******************************************************************************/ 1100285242Sachim/*! \brief Function to enable a single interrupt vector 1101285242Sachim * 1102285242Sachim * 1103285242Sachim * 1104285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1105285242Sachim * instance of SAS/SATA hardware 1106285242Sachim * \param interruptVectorIndex Interrupt vector to enable 1107285242Sachim * 1108285242Sachim */ 1109285242Sachim/*******************************************************************************/ 1110285242Sachim/******************************************************************************/ 1111285242Sachim/*! \brief saSystemInterruptsEnable 1112285242Sachim * Function to enable a single interrupt vector 1113285242Sachim * 1114285242Sachim * \param agRoot OS Layer-specific and LL Layer-specific context handles for this 1115285242Sachim * instance of SAS/SATA hardware 1116285242Sachim * \param interruptVectorIndex Interrupt vector to enable 1117285242Sachim * 1118285242Sachim */ 1119285242Sachim/*******************************************************************************/ 1120285242SachimGLOBAL FORCEINLINE 1121285242Sachimvoid saSystemInterruptsEnable( 1122285242Sachim agsaRoot_t *agRoot, 1123285242Sachim bit32 interruptVectorIndex 1124285242Sachim ) 1125285242Sachim{ 1126285242Sachim ossaReenableInterrupts(agRoot, interruptVectorIndex); 1127285242Sachim} 1128285242Sachim/******************************************************************************/ 1129285242Sachim/*! \brief Routine to handle Outbound Message 1130285242Sachim * 1131285242Sachim * The handle for outbound message 1132285242Sachim * 1133285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1134285242Sachim * \param count interrupt message count 1135285242Sachim * \param queueNum outbound queue 1136285242Sachim * 1137285242Sachim * \return 1138285242Sachim */ 1139285242Sachim/*******************************************************************************/ 1140285242SachimLOCAL FORCEINLINE bit32 1141285242SachimsiProcessOBMsg( 1142285242Sachim agsaRoot_t *agRoot, 1143285242Sachim bit32 count, 1144285242Sachim bit32 queueNum 1145285242Sachim ) 1146285242Sachim{ 1147285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1148285242Sachim mpiOCQueue_t *circularQ = agNULL; 1149285242Sachim void *pMsg1 = agNULL; 1150285242Sachim bit32 ret, processedMsgCount = 0; 1151285242Sachim bit32 ParseOBIombStatus = 0; 1152285242Sachim#ifdef SA_ENABLE_TRACE_FUNCTIONS 1153285242Sachim bit32 i = 0; 1154285242Sachim#endif 1155285242Sachim bit16 opcode = 0; 1156285242Sachim mpiMsgCategory_t category; 1157285242Sachim bit8 bc = 0; 1158285242Sachim 1159285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5r"); 1160285242Sachim 1161285242Sachim 1162285242Sachim SA_DBG3(("siProcessOBMsg: queueNum 0x%x\n", queueNum)); 1163285242Sachim 1164285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1165285242Sachim 1166285242Sachim circularQ = &saRoot->outboundQueue[queueNum]; 1167285242Sachim OSSA_READ_LE_32(circularQ->agRoot, &circularQ->producerIdx, circularQ->piPointer, 0); 1168285242Sachim 1169285242Sachim if (circularQ->producerIdx == circularQ->consumerIdx) 1170285242Sachim { 1171285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1172285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5r"); 1173285242Sachim return processedMsgCount; 1174285242Sachim } 1175285242Sachim 1176285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); 1177285242Sachim 1178285242Sachim do 1179285242Sachim { 1180285242Sachim /* ossaSingleThreadedEnter(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1181285242Sachim ret = mpiMsgConsume(circularQ, &pMsg1, &category, &opcode, &bc); 1182285242Sachim /* ossaSingleThreadedLeave(agRoot, LL_IOREQ_OBQ_LOCK + queueNum); */ 1183285242Sachim 1184285242Sachim if (AGSA_RC_SUCCESS == ret) 1185285242Sachim { 1186285242Sachim smTrace(hpDBG_IOMB,"M0",queueNum); 1187285242Sachim /* TP:M0 queueNum */ 1188285242Sachim smTrace(hpDBG_VERY_LOUD,"MA",opcode); 1189285242Sachim /* TP:MA opcode */ 1190285242Sachim smTrace(hpDBG_IOMB,"MB",category); 1191285242Sachim /* TP:MB category */ 1192285242Sachim 1193285242Sachim#ifdef SA_ENABLE_TRACE_FUNCTIONS 1194285242Sachim for (i=0; i<((bit32)bc*(circularQ->elementSize/4)); i++) 1195285242Sachim { 1196285242Sachim /* The -sizeof(mpiMsgHeader_t) is to account for mpiMsgConsume incrementing the pointer past the header*/ 1197285242Sachim smTrace(hpDBG_IOMB,"MC",*( ((bit32*)((bit8 *)pMsg1 - sizeof(mpiMsgHeader_t))) + i)); 1198285242Sachim /* TP:MC Outbound IOMB Dword */ 1199285242Sachim } 1200285242Sachim#endif 1201285242Sachim 1202285242Sachim MPI_DEBUG_TRACE( circularQ->qNumber,((circularQ->producerIdx << 16 ) | circularQ->consumerIdx),MPI_DEBUG_TRACE_OBQ, (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), circularQ->elementSize); 1203285242Sachim 1204285242Sachim ossaLogIomb(circularQ->agRoot, 1205285242Sachim circularQ->qNumber, 1206285242Sachim FALSE, 1207285242Sachim (void *)(((bit8*)pMsg1) - sizeof(mpiMsgHeader_t)), 1208285242Sachim bc*circularQ->elementSize); 1209285242Sachim 1210285242Sachim ossaQueueProcessed(agRoot, queueNum, circularQ->producerIdx, circularQ->consumerIdx); 1211285242Sachim /* process the outbound message */ 1212285242Sachim ParseOBIombStatus = mpiParseOBIomb(agRoot, (bit32 *)pMsg1, category, opcode); 1213285242Sachim if (ParseOBIombStatus == AGSA_RC_FAILURE) 1214285242Sachim { 1215285242Sachim SA_DBG1(("siProcessOBMsg, Failed Q %2d PI 0x%03x CI 0x%03x\n", queueNum, circularQ->producerIdx, circularQ->consumerIdx)); 1216285242Sachim#if defined(SALLSDK_DEBUG) 1217285242Sachim /* free the message for debug: this is a hang! */ 1218285242Sachim 1219285242Sachim mpiMsgFreeSet(circularQ, pMsg1, bc); 1220285242Sachim processedMsgCount ++; 1221285242Sachim#endif /**/ 1222285242Sachim break; 1223285242Sachim } 1224285242Sachim 1225285242Sachim /* free the message from the outbound circular buffer */ 1226285242Sachim mpiMsgFreeSet(circularQ, pMsg1, bc); 1227285242Sachim processedMsgCount ++; 1228285242Sachim } 1229285242Sachim else 1230285242Sachim //if (AGSA_RC_BUSY == ret) // always (circularQ->producerIdx == circularQ->consumerIdx) 1231285242Sachim // || (AGSA_RC_FAILURE == ret) 1232285242Sachim { 1233285242Sachim break; 1234285242Sachim } 1235285242Sachim } 1236285242Sachim /* end of message processing if hit the count */ 1237285242Sachim while(count > processedMsgCount); 1238285242Sachim 1239285242Sachim/* #define SALLSDK_FATAL_ERROR_DETECT 1 */ 1240285242Sachim/* 1241285242Sachim this comments are to be removed 1242285242Sachim fill in 0x1D 0x1e 0x1f 0x20 in MPI table for 1243285242Sachim bit32 regDumpBusBaseNum0; 1244285242Sachim bit32 regDumpOffset0; 1245285242Sachim bit32 regDumpLen0; 1246285242Sachim bit32 regDumpBusBaseNum1; 1247285242Sachim bit32 regDumpOffset1; 1248285242Sachim bit32 regDumpLen1; 1249285242Sachim in agsaFatalErrorInfo_t 1250285242Sachim 1251285242Sachim ??? regDumpBusBaseNum0 and regDumpBusBaseNum1 1252285242Sachim saRoot->mainConfigTable.regDumpPCIBAR = pcibar; 1253285242Sachim saRoot->mainConfigTable.FatalErrorDumpOffset0 = config->FatalErrorDumpOffset0; 1254285242Sachim saRoot->mainConfigTable.FatalErrorDumpLength0 = config->FatalErrorDumpLength0; 1255285242Sachim saRoot->mainConfigTable.FatalErrorDumpOffset1 = config->FatalErrorDumpOffset1; 1256285242Sachim saRoot->mainConfigTable.FatalErrorDumpLength1 = config->FatalErrorDumpLength1; 1257285242Sachim 1258285242Sachim 1259285242Sachim 1260285242Sachim*/ 1261285242Sachim#if defined(SALLSDK_FATAL_ERROR_DETECT) 1262285242Sachim 1263285242Sachim if( smIS_SPC(agRoot) ) /* SPC only */ 1264285242Sachim { 1265285242Sachim 1266285242Sachim /* any fatal error happened */ 1267285242Sachim /* executing this code impacts performance by 1% when no error is detected */ 1268285242Sachim { 1269285242Sachim agsaFatalErrorInfo_t fatal_error; 1270285242Sachim bit32 value; 1271285242Sachim bit32 value1; 1272285242Sachim 1273285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1274285242Sachim value1 = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1275285242Sachim 1276285242Sachim if( (value & SA_FATAL_ERROR_SP1_AAP1_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR || 1277285242Sachim (value1 & SA_FATAL_ERROR_SP2_IOP_ERR_MASK) == SA_FATAL_ERROR_FATAL_ERROR ) 1278285242Sachim { 1279285242Sachim si_memset(&fatal_error, 0, sizeof(agsaFatalErrorInfo_t)); 1280285242Sachim /* read detail fatal errors */ 1281285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0, MSGU_SCRATCH_PAD_0); 1282285242Sachim fatal_error.errorInfo0 = value; 1283285242Sachim SA_DBG1(("siProcessOBMsg: ScratchPad0 AAP error code 0x%x\n", value)); 1284285242Sachim 1285285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1, MSGU_SCRATCH_PAD_1); 1286285242Sachim fatal_error.errorInfo1 = value; 1287285242Sachim /* AAP error state */ 1288285242Sachim SA_DBG1(("siProcessOBMsg: AAP error state and error code 0x%x\n", value)); 1289285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2, MSGU_SCRATCH_PAD_2); 1290285242Sachim fatal_error.errorInfo2 = value; 1291285242Sachim /* IOP error state */ 1292285242Sachim SA_DBG1(("siProcessOBMsg: IOP error state and error code 0x%x\n", value)); 1293285242Sachim value = siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3, MSGU_SCRATCH_PAD_3); 1294285242Sachim SA_DBG1(("siProcessOBMsg: ScratchPad3 IOP error code 0x%x\n", value)); 1295285242Sachim fatal_error.errorInfo3 = value; 1296285242Sachim 1297285242Sachim if (agNULL != saRoot) 1298285242Sachim { 1299285242Sachim fatal_error.regDumpBusBaseNum0 = saRoot->mainConfigTable.regDumpPCIBAR; 1300285242Sachim fatal_error.regDumpOffset0 = saRoot->mainConfigTable.FatalErrorDumpOffset0; 1301285242Sachim fatal_error.regDumpLen0 = saRoot->mainConfigTable.FatalErrorDumpLength0; 1302285242Sachim fatal_error.regDumpBusBaseNum1 = saRoot->mainConfigTable.regDumpPCIBAR; 1303285242Sachim fatal_error.regDumpOffset1 = saRoot->mainConfigTable.FatalErrorDumpOffset1; 1304285242Sachim fatal_error.regDumpLen1 = saRoot->mainConfigTable.FatalErrorDumpLength1; 1305285242Sachim } 1306285242Sachim else 1307285242Sachim { 1308285242Sachim fatal_error.regDumpBusBaseNum0 = 0; 1309285242Sachim fatal_error.regDumpOffset0 = 0; 1310285242Sachim fatal_error.regDumpLen0 = 0; 1311285242Sachim fatal_error.regDumpBusBaseNum1 = 0; 1312285242Sachim fatal_error.regDumpOffset1 = 0; 1313285242Sachim fatal_error.regDumpLen1 = 0; 1314285242Sachim } 1315285242Sachim /* Call Back with error */ 1316285242Sachim SA_DBG1(("siProcessOBMsg: SALLSDK_FATAL_ERROR_DETECT \n")); 1317285242Sachim ossaHwCB(agRoot, agNULL, OSSA_HW_EVENT_MALFUNCTION, 0, (void *)&fatal_error, agNULL); 1318285242Sachim } 1319285242Sachim } 1320285242Sachim } 1321285242Sachim#endif /* SALLSDK_FATAL_ERROR_DETECT */ 1322285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5r"); 1323285242Sachim return processedMsgCount; 1324285242Sachim} 1325285242Sachim 1326285242Sachim/******************************************************************************/ 1327285242Sachim/*! \brief Function to enable/disable interrupts 1328285242Sachim * 1329285242Sachim * The saSystemInterruptsActive() function is called to indicate to the LL Layer 1330285242Sachim * whether interrupts are available. The parameter sysIntsActive indicates whether 1331285242Sachim * interrupts are available at this time. 1332285242Sachim * 1333285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1334285242Sachim * \param sysIntsActive flag for enable/disable interrupt 1335285242Sachim * 1336285242Sachim * \return -void- 1337285242Sachim * 1338285242Sachim */ 1339285242Sachim/*******************************************************************************/ 1340285242SachimGLOBAL void saSystemInterruptsActive( 1341285242Sachim agsaRoot_t *agRoot, 1342285242Sachim agBOOLEAN sysIntsActive 1343285242Sachim ) 1344285242Sachim{ 1345285242Sachim bit32 x; 1346285242Sachim agsaLLRoot_t *saRoot; 1347285242Sachim 1348285242Sachim SA_ASSERT((agNULL != agRoot), ""); 1349285242Sachim if (agRoot == agNULL) 1350285242Sachim { 1351285242Sachim SA_DBG1(("saSystemInterruptsActive: agRoot == agNULL\n")); 1352285242Sachim return; 1353285242Sachim } 1354285242Sachim saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1355285242Sachim SA_ASSERT((agNULL != saRoot), ""); 1356285242Sachim if (saRoot == agNULL) 1357285242Sachim { 1358285242Sachim SA_DBG1(("saSystemInterruptsActive: saRoot == agNULL\n")); 1359285242Sachim return; 1360285242Sachim } 1361285242Sachim 1362285242Sachim smTraceFuncEnter(hpDBG_TICK_INT,"5s"); 1363285242Sachim SA_DBG1(("saSystemInterruptsActive: now 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1364285242Sachim SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1365285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1366285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1367285242Sachim SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1368285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1369285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1370285242Sachim 1371285242Sachim if( saRoot->sysIntsActive && sysIntsActive ) 1372285242Sachim { 1373285242Sachim SA_DBG1(("saSystemInterruptsActive: Already active 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1374285242Sachim smTraceFuncExit(hpDBG_TICK_INT, 'a', "5s"); 1375285242Sachim return; 1376285242Sachim } 1377285242Sachim 1378285242Sachim if( !saRoot->sysIntsActive && !sysIntsActive ) 1379285242Sachim { 1380285242Sachim if(smIS_SPC(agRoot)) 1381285242Sachim { 1382285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1383285242Sachim } 1384285242Sachim else 1385285242Sachim { 1386285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1387285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1388285242Sachim } 1389285242Sachim SA_DBG1(("saSystemInterruptsActive: Already disabled 0x%X new 0x%x\n",saRoot->sysIntsActive,sysIntsActive)); 1390285242Sachim smTraceFuncExit(hpDBG_TICK_INT, 'b', "5s"); 1391285242Sachim return; 1392285242Sachim } 1393285242Sachim 1394285242Sachim /* Set the flag is sdkData */ 1395285242Sachim saRoot->sysIntsActive = (bit8)sysIntsActive; 1396285242Sachim 1397285242Sachim 1398285242Sachim smTrace(hpDBG_TICK_INT,"Vq",sysIntsActive); 1399285242Sachim /* TP:Vq sysIntsActive */ 1400285242Sachim /* If sysIntsActive is true */ 1401285242Sachim if ( agTRUE == sysIntsActive ) 1402285242Sachim { 1403285242Sachim 1404285242Sachim SA_DBG1(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1405285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1406285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1407285242Sachim SA_DBG1(("saSystemInterruptsActive: Doorbell_Mask_Set %08X U %08X\n", 1408285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register), 1409285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU))); 1410285242Sachim if(smIS_SPCV(agRoot)) 1411285242Sachim { 1412285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_Register, 0xFFFFFFFF); 1413285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Clear_RegisterU, 0xFFFFFFFF); 1414285242Sachim } 1415285242Sachim /* enable interrupt */ 1416285242Sachim for(x=0; x < saRoot->numInterruptVectors; x++) 1417285242Sachim { 1418285242Sachim ossaReenableInterrupts(agRoot,x ); 1419285242Sachim } 1420285242Sachim 1421285242Sachim if(saRoot->swConfig.fatalErrorInterruptEnable) 1422285242Sachim { 1423285242Sachim ossaReenableInterrupts(agRoot,saRoot->swConfig.fatalErrorInterruptVector ); 1424285242Sachim } 1425285242Sachim 1426285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR, 0); 1427285242Sachim } 1428285242Sachim /* If sysIntsActive is false */ 1429285242Sachim else 1430285242Sachim { 1431285242Sachim /* disable interrupt */ 1432285242Sachim if(smIS_SPC(agRoot)) 1433285242Sachim { 1434285242Sachim siHalRegWriteExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR,AGSA_INTERRUPT_HANDLE_ALL_CHANNELS ); 1435285242Sachim } 1436285242Sachim else 1437285242Sachim { 1438285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_Register, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1439285242Sachim ossaHwRegWriteExt(agRoot, PCIBAR0,V_Outbound_Doorbell_Mask_Set_RegisterU, AGSA_INTERRUPT_HANDLE_ALL_CHANNELS); 1440285242Sachim } 1441285242Sachim } 1442285242Sachim 1443285242Sachim SA_DBG3(("saSystemInterruptsActive: Doorbell_Set %08X U %08X\n", 1444285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_Register), 1445285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Set_RegisterU))); 1446285242Sachim SA_DBG3(("saSystemInterruptsActive: Doorbell_Mask %08X U %08X\n", 1447285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_Register ), 1448285242Sachim ossaHwRegReadExt(agRoot, PCIBAR0, V_Outbound_Doorbell_Mask_Set_RegisterU ))); 1449285242Sachim 1450285242Sachim 1451285242Sachim smTraceFuncExit(hpDBG_TICK_INT, 'c', "5s"); 1452285242Sachim} 1453285242Sachim 1454285242Sachim/******************************************************************************/ 1455285242Sachim/*! \brief Routine to handle for received SAS with data payload event 1456285242Sachim * 1457285242Sachim * The handle for received SAS with data payload event 1458285242Sachim * 1459285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1460285242Sachim * \param pRequest handles for the IOrequest 1461285242Sachim * \param pRespIU the pointer to the Response IU 1462285242Sachim * \param param Payload Length 1463285242Sachim * 1464285242Sachim * \return -void- 1465285242Sachim */ 1466285242Sachim/*******************************************************************************/ 1467285242SachimGLOBAL void siEventSSPResponseWtDataRcvd( 1468285242Sachim agsaRoot_t *agRoot, 1469285242Sachim agsaIORequestDesc_t *pRequest, 1470285242Sachim agsaSSPResponseInfoUnit_t *pRespIU, 1471285242Sachim bit32 param, 1472285242Sachim bit32 sspTag 1473285242Sachim ) 1474285242Sachim{ 1475285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1476285242Sachim agsaDeviceDesc_t *pDevice; 1477285242Sachim bit32 count = 0; 1478285242Sachim bit32 padCount; 1479285242Sachim 1480285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5g"); 1481285242Sachim 1482285242Sachim /* get frame handle */ 1483285242Sachim 1484285242Sachim /* If the request is still valid */ 1485285242Sachim if ( agTRUE == pRequest->valid ) 1486285242Sachim { 1487285242Sachim /* get device */ 1488285242Sachim pDevice = pRequest->pDevice; 1489285242Sachim 1490285242Sachim /* Delete the request from the pendingIORequests */ 1491285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1492285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1493285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1494285242Sachim 1495285242Sachim if (sspTag & SSP_RESCV_BIT) 1496285242Sachim { 1497285242Sachim /* get the pad count, bit 17 and 18 of sspTag */ 1498285242Sachim padCount = (sspTag >> SSP_RESCV_PAD_SHIFT) & 0x3; 1499285242Sachim /* get Residual Count */ 1500285242Sachim count = *(bit32 *)((bit8 *)pRespIU + param + padCount); 1501285242Sachim } 1502285242Sachim 1503285242Sachim (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1504285242Sachim pRequest->pIORequestContext, 1505285242Sachim OSSA_IO_SUCCESS, 1506285242Sachim param, 1507285242Sachim (void *)pRespIU, 1508285242Sachim (bit16)(sspTag & SSPTAG_BITS), 1509285242Sachim count); 1510285242Sachim 1511285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1512285242Sachim pRequest->valid = agFALSE; 1513285242Sachim /* return the request to free pool */ 1514285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1515285242Sachim { 1516285242Sachim SA_DBG1(("siEventSSPResponseWtDataRcvd: saving pRequest (%p) for later use\n", pRequest)); 1517285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1518285242Sachim } 1519285242Sachim else 1520285242Sachim { 1521285242Sachim /* return the request to free pool */ 1522285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1523285242Sachim } 1524285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1525285242Sachim 1526285242Sachim } 1527285242Sachim else 1528285242Sachim { 1529285242Sachim SA_DBG1(("siEventSSPResponseWtDataRcvd: pRequest->Valid not TRUE\n")); 1530285242Sachim } 1531285242Sachim 1532285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5g"); 1533285242Sachim 1534285242Sachim return; 1535285242Sachim} 1536285242Sachim 1537285242Sachim/******************************************************************************/ 1538285242Sachim/*! \brief Routine to handle successfully completed IO event 1539285242Sachim * 1540285242Sachim * Handle successfully completed IO 1541285242Sachim * 1542285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1543285242Sachim * \param pRequest Pointer of IO request of the IO 1544285242Sachim * \param status status of the IO 1545285242Sachim * 1546285242Sachim * \return -void- 1547285242Sachim */ 1548285242Sachim/*******************************************************************************/ 1549285242SachimGLOBAL FORCEINLINE void siIODone( 1550285242Sachim agsaRoot_t *agRoot, 1551285242Sachim agsaIORequestDesc_t *pRequest, 1552285242Sachim bit32 status, 1553285242Sachim bit32 sspTag 1554285242Sachim ) 1555285242Sachim{ 1556285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1557285242Sachim agsaDeviceDesc_t *pDevice = agNULL; 1558285242Sachim 1559285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5h"); 1560285242Sachim 1561285242Sachim SA_ASSERT(NULL != pRequest, "pRequest cannot be null"); 1562285242Sachim 1563285242Sachim /* If the request is still valid */ 1564285242Sachim if ( agTRUE == pRequest->valid ) 1565285242Sachim { 1566285242Sachim /* get device */ 1567285242Sachim pDevice = pRequest->pDevice; 1568285242Sachim 1569285242Sachim /* process different request type */ 1570285242Sachim switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1571285242Sachim { 1572285242Sachim case AGSA_SSP_REQTYPE: 1573285242Sachim { 1574285242Sachim SA_ASSERT(pRequest->valid, "pRequest not valid"); 1575285242Sachim pRequest->completionCB(agRoot, 1576285242Sachim pRequest->pIORequestContext, 1577285242Sachim OSSA_IO_SUCCESS, 1578285242Sachim 0, 1579285242Sachim agNULL, 1580285242Sachim (bit16)(sspTag & SSPTAG_BITS), 1581285242Sachim 0); 1582285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1583285242Sachim /* Delete the request from the pendingIORequests */ 1584285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1585285242Sachim /* return the request to free pool */ 1586285242Sachim pRequest->valid = agFALSE; 1587285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1588285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1589285242Sachim 1590285242Sachim 1591285242Sachim break; 1592285242Sachim } 1593285242Sachim case AGSA_SATA_REQTYPE: 1594285242Sachim { 1595285242Sachim SA_DBG5(("siIODone: SATA complete\n")); 1596285242Sachim 1597285242Sachim if ( agNULL != pRequest->pIORequestContext ) 1598285242Sachim { 1599285242Sachim SA_DBG5(("siIODone: Complete Request\n")); 1600285242Sachim 1601285242Sachim (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1602285242Sachim pRequest->pIORequestContext, 1603285242Sachim OSSA_IO_SUCCESS, 1604285242Sachim agNULL, 1605285242Sachim 0, 1606285242Sachim agNULL); 1607285242Sachim } 1608285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1609285242Sachim /* Delete the request from the pendingIORequests */ 1610285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1611285242Sachim /* return the request to free pool */ 1612285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1613285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1614285242Sachim 1615285242Sachim pRequest->valid = agFALSE; 1616285242Sachim 1617285242Sachim break; 1618285242Sachim } 1619285242Sachim case AGSA_SMP_REQTYPE: 1620285242Sachim { 1621285242Sachim if ( agNULL != pRequest->pIORequestContext ) 1622285242Sachim { 1623285242Sachim (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1624285242Sachim pRequest->pIORequestContext, 1625285242Sachim OSSA_IO_SUCCESS, 1626285242Sachim 0, 1627285242Sachim agNULL); 1628285242Sachim } 1629285242Sachim 1630285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1631285242Sachim /* Delete the request from the pendingSMPRequests */ 1632285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1633285242Sachim /* return the request to free pool */ 1634285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1635285242Sachim { 1636285242Sachim SA_DBG1(("siIODone: saving pRequest (%p) for later use\n", pRequest)); 1637285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1638285242Sachim } 1639285242Sachim else 1640285242Sachim { 1641285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1642285242Sachim } 1643285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1644285242Sachim 1645285242Sachim pRequest->valid = agFALSE; 1646285242Sachim 1647285242Sachim break; 1648285242Sachim } 1649285242Sachim default: 1650285242Sachim { 1651285242Sachim SA_DBG1(("siIODone: unknown request type (%x) is completed. HTag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1652285242Sachim break; 1653285242Sachim } 1654285242Sachim } 1655285242Sachim } 1656285242Sachim else 1657285242Sachim { 1658285242Sachim SA_DBG1(("siIODone: The request is not valid any more. HTag=0x%x requestType=0x%x\n", pRequest->HTag, pRequest->requestType)); 1659285242Sachim } 1660285242Sachim 1661285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5h"); 1662285242Sachim 1663285242Sachim} 1664285242Sachim 1665285242Sachim/******************************************************************************/ 1666285242Sachim/*! \brief Routine to handle abnormal completed IO/SMP event 1667285242Sachim * 1668285242Sachim * Handle abnormal completed IO/SMP 1669285242Sachim * 1670285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1671285242Sachim * \param pRequest Pointer of IO request of the IO 1672285242Sachim * \param status status of the IO 1673285242Sachim * \param param Length 1674285242Sachim * 1675285242Sachim * \return -void- 1676285242Sachim */ 1677285242Sachim/*******************************************************************************/ 1678285242SachimGLOBAL void siAbnormal( 1679285242Sachim agsaRoot_t *agRoot, 1680285242Sachim agsaIORequestDesc_t *pRequest, 1681285242Sachim bit32 status, 1682285242Sachim bit32 param, 1683285242Sachim bit32 sspTag 1684285242Sachim ) 1685285242Sachim{ 1686285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1687285242Sachim agsaDeviceDesc_t *pDevice; 1688285242Sachim 1689285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5i"); 1690285242Sachim 1691285242Sachim if (agNULL == pRequest) 1692285242Sachim { 1693285242Sachim SA_DBG1(("siAbnormal: pRequest is NULL.\n")); 1694285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5i"); 1695285242Sachim return; 1696285242Sachim } 1697285242Sachim 1698285242Sachim /* If the request is still valid */ 1699285242Sachim if ( agTRUE == pRequest->valid ) 1700285242Sachim { 1701285242Sachim /* get device */ 1702285242Sachim 1703285242Sachim SA_ASSERT((pRequest->pIORequestContext->osData != pRequest->pIORequestContext->sdkData), "pIORequestContext"); 1704285242Sachim 1705285242Sachim pDevice = pRequest->pDevice; 1706285242Sachim 1707285242Sachim /* remove the IO request from IOMap */ 1708285242Sachim saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1709285242Sachim saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1710285242Sachim saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1711285242Sachim 1712285242Sachim smTrace(hpDBG_VERY_LOUD,"P6",status ); 1713285242Sachim /* TP:P6 siAbnormal status */ 1714285242Sachim smTrace(hpDBG_VERY_LOUD,"P7",param ); 1715285242Sachim /* TP:P7 siAbnormal param */ 1716285242Sachim /* process different request type */ 1717285242Sachim switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1718285242Sachim { 1719285242Sachim case AGSA_SSP_REQTYPE: 1720285242Sachim { 1721285242Sachim (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1722285242Sachim pRequest->pIORequestContext, 1723285242Sachim status, 1724285242Sachim param, 1725285242Sachim agNULL, 1726285242Sachim (bit16)(sspTag & SSPTAG_BITS), 1727285242Sachim ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1728285242Sachim 1729285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1730285242Sachim /* Delete the request from the pendingIORequests */ 1731285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1732285242Sachim pRequest->valid = agFALSE; 1733285242Sachim /* return the request to free pool */ 1734285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1735285242Sachim { 1736285242Sachim SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1737285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1738285242Sachim } 1739285242Sachim else 1740285242Sachim { 1741285242Sachim /* return the request to free pool */ 1742285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1743285242Sachim } 1744285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1745285242Sachim 1746285242Sachim break; 1747285242Sachim } 1748285242Sachim case AGSA_SATA_REQTYPE: 1749285242Sachim { 1750285242Sachim SA_DBG5(("siAbnormal: SATA \n")); 1751285242Sachim 1752285242Sachim if ( agNULL != pRequest->pIORequestContext ) 1753285242Sachim { 1754285242Sachim SA_DBG5(("siAbnormal: Calling SATACompletedCB\n")); 1755285242Sachim 1756285242Sachim (*(ossaSATACompletedCB_t)(pRequest->completionCB))(agRoot, 1757285242Sachim pRequest->pIORequestContext, 1758285242Sachim status, 1759285242Sachim agNULL, 1760285242Sachim param, 1761285242Sachim agNULL); 1762285242Sachim } 1763285242Sachim 1764285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1765285242Sachim /* Delete the request from the pendingIORequests */ 1766285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1767285242Sachim /* return the request to free pool */ 1768285242Sachim pRequest->valid = agFALSE; 1769285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1770285242Sachim { 1771285242Sachim SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1772285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1773285242Sachim } 1774285242Sachim else 1775285242Sachim { 1776285242Sachim /* return the request to free pool */ 1777285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1778285242Sachim } 1779285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1780285242Sachim 1781285242Sachim break; 1782285242Sachim } 1783285242Sachim case AGSA_SMP_REQTYPE: 1784285242Sachim { 1785285242Sachim if ( agNULL != pRequest->pIORequestContext ) 1786285242Sachim { 1787285242Sachim (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, 1788285242Sachim pRequest->pIORequestContext, 1789285242Sachim status, 1790285242Sachim param, 1791285242Sachim agNULL); 1792285242Sachim } 1793285242Sachim 1794285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1795285242Sachim /* Delete the request from the pendingSMPRequests */ 1796285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1797285242Sachim /* return the request to free pool */ 1798285242Sachim pRequest->valid = agFALSE; 1799285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1800285242Sachim { 1801285242Sachim SA_DBG1(("siAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1802285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1803285242Sachim } 1804285242Sachim else 1805285242Sachim { 1806285242Sachim /* return the request to free pool */ 1807285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1808285242Sachim } 1809285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1810285242Sachim 1811285242Sachim break; 1812285242Sachim } 1813285242Sachim default: 1814285242Sachim { 1815285242Sachim SA_DBG1(("siAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1816285242Sachim break; 1817285242Sachim } 1818285242Sachim } 1819285242Sachim 1820285242Sachim } 1821285242Sachim else 1822285242Sachim { 1823285242Sachim SA_DBG1(("siAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1824285242Sachim } 1825285242Sachim 1826285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5i"); 1827285242Sachim 1828285242Sachim return; 1829285242Sachim} 1830285242Sachim 1831285242Sachim 1832285242Sachim/******************************************************************************/ 1833285242Sachim/*! \brief Routine to handle abnormal DIF completed IO/SMP event 1834285242Sachim * 1835285242Sachim * Handle abnormal completed IO/SMP 1836285242Sachim * 1837285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1838285242Sachim * \param pRequest Pointer of IO request of the IO 1839285242Sachim * \param status status of the IO 1840285242Sachim * \param param Length 1841285242Sachim * 1842285242Sachim * \return -void- 1843285242Sachim */ 1844285242Sachim/*******************************************************************************/ 1845285242SachimGLOBAL void siDifAbnormal( 1846285242Sachim agsaRoot_t *agRoot, 1847285242Sachim agsaIORequestDesc_t *pRequest, 1848285242Sachim bit32 status, 1849285242Sachim bit32 param, 1850285242Sachim bit32 sspTag, 1851285242Sachim bit32 *pMsg1 1852285242Sachim ) 1853285242Sachim{ 1854285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1855285242Sachim agsaDeviceDesc_t *pDevice; 1856285242Sachim 1857285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"2S"); 1858285242Sachim 1859285242Sachim if (agNULL == pRequest) 1860285242Sachim { 1861285242Sachim SA_DBG1(("siDifAbnormal: pRequest is NULL.\n")); 1862285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2S"); 1863285242Sachim return; 1864285242Sachim } 1865285242Sachim 1866285242Sachim /* If the request is still valid */ 1867285242Sachim if ( agTRUE == pRequest->valid ) 1868285242Sachim { 1869285242Sachim /* get device */ 1870285242Sachim pDevice = pRequest->pDevice; 1871285242Sachim 1872285242Sachim /* remove the IO request from IOMap */ 1873285242Sachim saRoot->IOMap[pRequest->HTag].Tag = MARK_OFF; 1874285242Sachim saRoot->IOMap[pRequest->HTag].IORequest = agNULL; 1875285242Sachim saRoot->IOMap[pRequest->HTag].agContext = agNULL; 1876285242Sachim 1877285242Sachim smTrace(hpDBG_VERY_LOUD,"P6",status ); 1878285242Sachim /* TP:P6 siDifAbnormal status */ 1879285242Sachim /* process different request type */ 1880285242Sachim switch (pRequest->requestType & AGSA_REQTYPE_MASK) 1881285242Sachim { 1882285242Sachim case AGSA_SSP_REQTYPE: 1883285242Sachim { 1884285242Sachim agsaDifDetails_t agDifDetails; 1885285242Sachim agsaSSPCompletionDifRsp_t *pIomb; 1886285242Sachim pIomb = (agsaSSPCompletionDifRsp_t *)pMsg1; 1887285242Sachim si_memset(&agDifDetails, 0, sizeof(agDifDetails)); 1888285242Sachim 1889285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.UpperLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,UpperLBA )); 1890285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.LowerLBA, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,LowerLBA )); 1891285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressHi, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressHi )); 1892285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.sasAddressLo, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,sasAddressLo)); 1893285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedCRCUDT01 )); 1894285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.ExpectedUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ExpectedUDT2345)); 1895285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.ActualCRCUDT01, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualCRCUDT01 )); 1896285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.ActualUDT2345, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ActualUDT2345)); 1897285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.DIFErrDevID, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,DIFErrDevID )); 1898285242Sachim OSSA_READ_LE_32(agRoot, &agDifDetails.ErrBoffsetEDataLen, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t,ErrBoffsetEDataLen )); 1899285242Sachim agDifDetails.frame = (void *)(bit8*)(pIomb+ OSSA_OFFSET_OF(agsaSSPCompletionDifRsp_t, EDATA_FRM)); 1900285242Sachim 1901285242Sachim (*(ossaSSPCompletedCB_t)(pRequest->completionCB))(agRoot, 1902285242Sachim pRequest->pIORequestContext, 1903285242Sachim status, 1904285242Sachim param, 1905285242Sachim &agDifDetails, 1906285242Sachim (bit16)(sspTag & SSPTAG_BITS), 1907285242Sachim ((sspTag & SSP_AGR_S_BIT)? (1 << 0) : 0)); 1908285242Sachim 1909285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1910285242Sachim pRequest->valid = agFALSE; 1911285242Sachim /* Delete the request from the pendingIORequests */ 1912285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 1913285242Sachim 1914285242Sachim /* return the request to free pool */ 1915285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 1916285242Sachim { 1917285242Sachim SA_DBG1(("siDifAbnormal: saving pRequest (%p) for later use\n", pRequest)); 1918285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 1919285242Sachim } 1920285242Sachim else 1921285242Sachim { 1922285242Sachim /* return the request to free pool */ 1923285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 1924285242Sachim } 1925285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 1926285242Sachim 1927285242Sachim break; 1928285242Sachim } 1929285242Sachim default: 1930285242Sachim { 1931285242Sachim SA_DBG1(("siDifAbnormal: unknown request type (%x) is completed. Tag=0x%x\n", pRequest->requestType, pRequest->HTag)); 1932285242Sachim break; 1933285242Sachim } 1934285242Sachim } 1935285242Sachim 1936285242Sachim } 1937285242Sachim else 1938285242Sachim { 1939285242Sachim SA_DBG1(("siDifAbnormal: The request is not valid any more. Tag=0x%x\n", pRequest->HTag)); 1940285242Sachim } 1941285242Sachim 1942285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2S"); 1943285242Sachim 1944285242Sachim return; 1945285242Sachim} 1946285242Sachim 1947285242Sachim 1948285242Sachim/******************************************************************************/ 1949285242Sachim/*! \brief Routine to handle for received SMP response event 1950285242Sachim * 1951285242Sachim * The handle for received SMP response event 1952285242Sachim * 1953285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 1954285242Sachim * \param pIomb Pointer of payload of IOMB 1955285242Sachim * \param payloadSize size of the payload 1956285242Sachim * \param tag the tag of the request SMP 1957285242Sachim * 1958285242Sachim * \return -void- 1959285242Sachim */ 1960285242Sachim/*******************************************************************************/ 1961285242SachimGLOBAL void siSMPRespRcvd( 1962285242Sachim agsaRoot_t *agRoot, 1963285242Sachim agsaSMPCompletionRsp_t *pIomb, 1964285242Sachim bit32 payloadSize, 1965285242Sachim bit32 tag 1966285242Sachim ) 1967285242Sachim{ 1968285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 1969285242Sachim agsaFrameHandle_t frameHandle; 1970285242Sachim agsaIORequestDesc_t *pRequest; 1971285242Sachim agsaDeviceDesc_t *pDevice; 1972285242Sachim agsaPort_t *pPort; 1973285242Sachim 1974285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5j"); 1975285242Sachim 1976285242Sachim /* get the request */ 1977285242Sachim pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 1978285242Sachim SA_ASSERT(pRequest, "pRequest"); 1979285242Sachim 1980285242Sachim /* get the port */ 1981285242Sachim pPort = pRequest->pPort; 1982285242Sachim SA_ASSERT(pPort, "pPort"); 1983285242Sachim 1984285242Sachim if (pRequest->IRmode == 0) 1985285242Sachim { 1986285242Sachim /* get frame handle - direct response mode */ 1987285242Sachim frameHandle = (agsaFrameHandle_t)(&(pIomb->SMPrsp[0])); 1988285242Sachim#if defined(SALLSDK_DEBUG) 1989285242Sachim SA_DBG3(("saSMPRespRcvd(direct): smpRspPtr=0x%p - len=0x%x\n", 1990285242Sachim frameHandle, 1991285242Sachim payloadSize 1992285242Sachim )); 1993285242Sachim#endif /* SALLSDK_DEBUG */ 1994285242Sachim } 1995285242Sachim else 1996285242Sachim { 1997285242Sachim /* indirect response mode */ 1998285242Sachim frameHandle = agNULL; 1999285242Sachim } 2000285242Sachim 2001285242Sachim /* If the request is still valid */ 2002285242Sachim if ( agTRUE == pRequest->valid ) 2003285242Sachim { 2004285242Sachim /* get device */ 2005285242Sachim pDevice = pRequest->pDevice; 2006285242Sachim SA_ASSERT(pDevice, "pDevice"); 2007285242Sachim 2008285242Sachim /* Delete the request from the pendingSMPRequests */ 2009285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2010285242Sachim saLlistIORemove(&(pDevice->pendingIORequests), &(pRequest->linkNode)); 2011285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2012285242Sachim 2013285242Sachim /* If the request is from OS layer */ 2014285242Sachim if ( agNULL != pRequest->pIORequestContext ) 2015285242Sachim { 2016285242Sachim if (agNULL == frameHandle) 2017285242Sachim { 2018285242Sachim /* indirect mode */ 2019285242Sachim /* call back with success */ 2020285242Sachim (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2021285242Sachim } 2022285242Sachim else 2023285242Sachim { 2024285242Sachim /* direct mode */ 2025285242Sachim /* call back with success */ 2026285242Sachim (*(ossaSMPCompletedCB_t)(pRequest->completionCB))(agRoot, pRequest->pIORequestContext, OSSA_IO_SUCCESS, payloadSize, frameHandle); 2027285242Sachim } 2028285242Sachim } 2029285242Sachim 2030285242Sachim /* remove the IO request from IOMap */ 2031285242Sachim saRoot->IOMap[tag].Tag = MARK_OFF; 2032285242Sachim saRoot->IOMap[tag].IORequest = agNULL; 2033285242Sachim saRoot->IOMap[tag].agContext = agNULL; 2034285242Sachim ossaSingleThreadedEnter(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2035285242Sachim pRequest->valid = agFALSE; 2036285242Sachim if(saLlistIOGetCount(&(saRoot->freeReservedRequests)) < SA_RESERVED_REQUEST_COUNT) 2037285242Sachim { 2038285242Sachim SA_DBG1(("siSMPRespRcvd: saving pRequest (%p) for later use\n", pRequest)); 2039285242Sachim saLlistIOAdd(&(saRoot->freeReservedRequests), &(pRequest->linkNode)); 2040285242Sachim } 2041285242Sachim else 2042285242Sachim { 2043285242Sachim /* return the request to free pool */ 2044285242Sachim saLlistIOAdd(&(saRoot->freeIORequests), &(pRequest->linkNode)); 2045285242Sachim } 2046285242Sachim ossaSingleThreadedLeave(agRoot, LL_IOREQ_LOCKEQ_LOCK); 2047285242Sachim } 2048285242Sachim 2049285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5j"); 2050285242Sachim 2051285242Sachim return; 2052285242Sachim} 2053285242Sachim 2054285242Sachim/******************************************************************************/ 2055285242Sachim/*! \brief Routine to handle for received Phy Up event 2056285242Sachim * 2057285242Sachim * The handle for received Phy Up event 2058285242Sachim * 2059285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 2060285242Sachim * \param phyId for the Phy Up event happened 2061285242Sachim * \param agSASIdentify is the remote phy Identify 2062285242Sachim * \param portId is the port context index of the phy up event 2063285242Sachim * \param deviceId is the device context index 2064285242Sachim * \param linkRate link up rate from SPC 2065285242Sachim * 2066285242Sachim * \return -void- 2067285242Sachim */ 2068285242Sachim/*******************************************************************************/ 2069285242SachimGLOBAL void siEventPhyUpRcvd( 2070285242Sachim agsaRoot_t *agRoot, 2071285242Sachim bit32 phyId, 2072285242Sachim agsaSASIdentify_t *agSASIdentify, 2073285242Sachim bit32 portId, 2074285242Sachim bit32 npipps, 2075285242Sachim bit8 linkRate 2076285242Sachim ) 2077285242Sachim{ 2078285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2079285242Sachim agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2080285242Sachim agsaPort_t *pPort; 2081285242Sachim agsaSASIdentify_t remoteIdentify; 2082285242Sachim agsaPortContext_t *agPortContext; 2083285242Sachim 2084285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5k"); 2085285242Sachim 2086285242Sachim /* Read remote SAS Identify from response message and save it */ 2087285242Sachim remoteIdentify = *agSASIdentify; 2088285242Sachim 2089285242Sachim /* get port context from portMap */ 2090285242Sachim SA_DBG2(("siEventPhyUpRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2091285242Sachim agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2092285242Sachim 2093285242Sachim SA_DBG2(("siEventPhyUpRcvd: portID %d PortContext %p linkRate 0x%X\n", portId, agPortContext,linkRate)); 2094285242Sachim if (smIS_SPCV8006(agRoot)) 2095285242Sachim { 2096285242Sachim SA_DBG1(("siEventPhyUpRcvd: SAS_PHY_UP received for SATA Controller\n")); 2097285242Sachim return; 2098285242Sachim } 2099285242Sachim 2100285242Sachim if (agNULL != agPortContext) 2101285242Sachim { 2102285242Sachim /* existing port */ 2103285242Sachim pPort = (agsaPort_t *) (agPortContext->sdkData); 2104285242Sachim pPort->portId = portId; 2105285242Sachim 2106285242Sachim /* include the phy to the port */ 2107285242Sachim pPort->phyMap[phyId] = agTRUE; 2108285242Sachim /* Set the port for the phy */ 2109285242Sachim saRoot->phys[phyId].pPort = pPort; 2110285242Sachim 2111285242Sachim /* Update port state */ 2112285242Sachim if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2113285242Sachim { 2114285242Sachim pPort->status &= ~PORT_INVALIDATING; 2115285242Sachim saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2116285242Sachim SA_DBG1(("siEventPhyUpRcvd: portID %d PortContext %p, hitting workaround\n", portId, agPortContext)); 2117285242Sachim } 2118285242Sachim } 2119285242Sachim else 2120285242Sachim { 2121285242Sachim ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2122285242Sachim /* new port */ 2123285242Sachim /* Allocate a free port */ 2124285242Sachim pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2125285242Sachim if (agNULL != pPort) 2126285242Sachim { 2127285242Sachim /* Acquire port list lock */ 2128285242Sachim saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2129285242Sachim 2130285242Sachim /* setup the port data structure */ 2131285242Sachim pPort->portContext.osData = agNULL; 2132285242Sachim pPort->portContext.sdkData = pPort; 2133285242Sachim 2134285242Sachim /* Add to valid port list */ 2135285242Sachim saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2136285242Sachim /* Release port list lock */ 2137285242Sachim ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2138285242Sachim 2139285242Sachim /* include the phy to the port */ 2140285242Sachim pPort->phyMap[phyId] = agTRUE; 2141285242Sachim /* Set the port for the phy */ 2142285242Sachim saRoot->phys[phyId].pPort = pPort; 2143285242Sachim 2144285242Sachim /* Setup portMap based on portId */ 2145285242Sachim saRoot->PortMap[portId].PortID = portId; 2146285242Sachim saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2147285242Sachim pPort->portId = portId; 2148285242Sachim 2149285242Sachim SA_DBG3(("siEventPhyUpRcvd: NewPort portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2150285242Sachim } 2151285242Sachim else 2152285242Sachim { 2153285242Sachim ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2154285242Sachim /* pPort is agNULL*/ 2155285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5k"); 2156285242Sachim return; 2157285242Sachim } 2158285242Sachim 2159285242Sachim if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2160285242Sachim { 2161285242Sachim pPort->status &= ~PORT_INVALIDATING; 2162285242Sachim saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2163285242Sachim } 2164285242Sachim else 2165285242Sachim { 2166285242Sachim SA_DBG1(("siEventPhyUpRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2167285242Sachim } 2168285242Sachim } 2169285242Sachim 2170285242Sachim /* adjust the bit fields before callback */ 2171285242Sachim phyId = (linkRate << SHIFT8) | phyId; 2172285242Sachim /* report PhyId, NPIP, PortState */ 2173285242Sachim phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2174285242Sachim ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SAS_PHY_UP, phyId, agNULL, &remoteIdentify); 2175285242Sachim 2176285242Sachim /* set PHY_UP status */ 2177285242Sachim PHY_STATUS_SET(pPhy, PHY_UP); 2178285242Sachim 2179285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5k"); 2180285242Sachim 2181285242Sachim /* return */ 2182285242Sachim return; 2183285242Sachim} 2184285242Sachim 2185285242Sachim/******************************************************************************/ 2186285242Sachim/*! \brief Routine to handle for received SATA signature event 2187285242Sachim * 2188285242Sachim * The handle for received SATA signature event 2189285242Sachim * 2190285242Sachim * \param agRoot handles for this instance of SAS/SATA hardware 2191285242Sachim * \param phyId the phy id of the phy received the frame 2192285242Sachim * \param pMsg the pointer to the message payload 2193285242Sachim * \param portId the port context index of the phy up event 2194285242Sachim * \param deviceId the device context index 2195285242Sachim * \param linkRate link up rate from SPC 2196285242Sachim * 2197285242Sachim * \return -void- 2198285242Sachim */ 2199285242Sachim/*******************************************************************************/ 2200285242SachimGLOBAL void siEventSATASignatureRcvd( 2201285242Sachim agsaRoot_t *agRoot, 2202285242Sachim bit32 phyId, 2203285242Sachim void *pMsg, 2204285242Sachim bit32 portId, 2205285242Sachim bit32 npipps, 2206285242Sachim bit8 linkRate 2207285242Sachim ) 2208285242Sachim{ 2209285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2210285242Sachim agsaPhy_t *pPhy = &(saRoot->phys[phyId]); 2211285242Sachim agsaPort_t *pPort = agNULL; 2212285242Sachim agsaPortContext_t *agPortContext; 2213285242Sachim#if defined(SALLSDK_DEBUG) 2214285242Sachim agsaFisRegDeviceToHost_t *fisD2H; 2215285242Sachim /* Read the D2H FIS */ 2216285242Sachim fisD2H = (agsaFisRegDeviceToHost_t *)pMsg; 2217285242Sachim#endif /* SALLSDK_DEBUG */ 2218285242Sachim 2219285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"5m"); 2220285242Sachim 2221285242Sachim SA_DBG5(("siEventSATASignatureRcvd: About to read the signatureFIS data\n")); 2222285242Sachim 2223285242Sachim 2224285242Sachim SA_DBG5(("agsaFisRegDeviceToHost_t:\n")); 2225285242Sachim SA_DBG5((" fisType = %x\n", fisD2H->h.fisType)); 2226285242Sachim SA_DBG5((" i_pmPort = %x\n", fisD2H->h.i_pmPort)); 2227285242Sachim SA_DBG5((" status = %x\n", fisD2H->h.status)); 2228285242Sachim SA_DBG5((" error = %x\n", fisD2H->h.error)); 2229285242Sachim 2230285242Sachim SA_DBG5((" lbaLow = %x\n", fisD2H->d.lbaLow)); 2231285242Sachim SA_DBG5((" lbaMid = %x\n", fisD2H->d.lbaMid)); 2232285242Sachim SA_DBG5((" lbaHigh = %x\n", fisD2H->d.lbaHigh)); 2233285242Sachim SA_DBG5((" device = %x\n", fisD2H->d.device)); 2234285242Sachim 2235285242Sachim SA_DBG5((" lbaLowExp = %x\n", fisD2H->d.lbaLowExp)); 2236285242Sachim SA_DBG5((" lbaMidExp = %x\n", fisD2H->d.lbaMidExp)); 2237285242Sachim SA_DBG5((" lbaHighExp = %x\n", fisD2H->d.lbaHighExp)); 2238285242Sachim SA_DBG5((" reserved4 = %x\n", fisD2H->d.reserved4)); 2239285242Sachim 2240285242Sachim SA_DBG5((" sectorCount = %x\n", fisD2H->d.sectorCount)); 2241285242Sachim SA_DBG5((" sectorCountExp = %x\n", fisD2H->d.sectorCountExp)); 2242285242Sachim SA_DBG5((" reserved5 = %x\n", fisD2H->d.reserved5)); 2243285242Sachim SA_DBG5((" reserved6 = %x\n", fisD2H->d.reserved6)); 2244285242Sachim 2245285242Sachim SA_DBG5((" reserved7 (32) = %08X\n", fisD2H->d.reserved7)); 2246285242Sachim 2247285242Sachim SA_DBG5(("siEventSATASignatureRcvd: GOOD signatureFIS data\n")); 2248285242Sachim 2249285242Sachim#if defined(SALLSDK_DEBUG) 2250285242Sachim /* read signature */ 2251285242Sachim pPhy->remoteSignature[0] = (bit8) fisD2H->d.sectorCount; 2252285242Sachim pPhy->remoteSignature[1] = (bit8) fisD2H->d.lbaLow; 2253285242Sachim pPhy->remoteSignature[2] = (bit8) fisD2H->d.lbaMid; 2254285242Sachim pPhy->remoteSignature[3] = (bit8) fisD2H->d.lbaHigh; 2255285242Sachim pPhy->remoteSignature[4] = (bit8) fisD2H->d.device; 2256285242Sachim#endif 2257285242Sachim 2258285242Sachim /* get port context from portMap */ 2259285242Sachim SA_DBG2(("siEventSATASignatureRcvd:PortID 0x%x PortStatus 0x%x PortContext %p\n",saRoot->PortMap[portId & PORTID_MASK].PortID,saRoot->PortMap[portId & PORTID_MASK].PortStatus,saRoot->PortMap[portId & PORTID_MASK].PortContext)); 2260285242Sachim agPortContext = (agsaPortContext_t *)saRoot->PortMap[portId].PortContext; 2261285242Sachim 2262285242Sachim SA_DBG2(("siEventSATASignatureRcvd: portID %d PortContext %p\n", portId, agPortContext)); 2263285242Sachim 2264285242Sachim if (agNULL != agPortContext) 2265285242Sachim { 2266285242Sachim /* exist port */ 2267285242Sachim pPort = (agsaPort_t *) (agPortContext->sdkData); 2268285242Sachim pPort->portId = portId; 2269285242Sachim 2270285242Sachim /* include the phy to the port */ 2271285242Sachim pPort->phyMap[phyId] = agTRUE; 2272285242Sachim /* Set the port for the phy */ 2273285242Sachim saRoot->phys[phyId].pPort = pPort; 2274285242Sachim } 2275285242Sachim else 2276285242Sachim { 2277285242Sachim ossaSingleThreadedEnter(agRoot, LL_PORT_LOCK); 2278285242Sachim /* new port */ 2279285242Sachim /* Allocate a free port */ 2280285242Sachim pPort = (agsaPort_t *) saLlistGetHead(&(saRoot->freePorts)); 2281285242Sachim if (agNULL != pPort) 2282285242Sachim { 2283285242Sachim /* Acquire port list lock */ 2284285242Sachim saLlistRemove(&(saRoot->freePorts), &(pPort->linkNode)); 2285285242Sachim 2286285242Sachim /* setup the port data structure */ 2287285242Sachim pPort->portContext.osData = agNULL; 2288285242Sachim pPort->portContext.sdkData = pPort; 2289285242Sachim 2290285242Sachim /* Add to valid port list */ 2291285242Sachim saLlistAdd(&(saRoot->validPorts), &(pPort->linkNode)); 2292285242Sachim /* Release port list lock */ 2293285242Sachim ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2294285242Sachim 2295285242Sachim /* include the phy to the port */ 2296285242Sachim pPort->phyMap[phyId] = agTRUE; 2297285242Sachim /* Set the port for the phy */ 2298285242Sachim saRoot->phys[phyId].pPort = pPort; 2299285242Sachim 2300285242Sachim /* Setup portMap based on portId */ 2301285242Sachim saRoot->PortMap[portId].PortID = portId; 2302285242Sachim saRoot->PortMap[portId].PortContext = &(pPort->portContext); 2303285242Sachim pPort->portId = portId; 2304285242Sachim SA_DBG3(("siEventSATASignatureRcvd: NewPort portID %d portContect %p\n", portId, saRoot->PortMap[portId].PortContext)); 2305285242Sachim } 2306285242Sachim else 2307285242Sachim { 2308285242Sachim ossaSingleThreadedLeave(agRoot, LL_PORT_LOCK); 2309285242Sachim /* pPort is agNULL*/ 2310285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5m"); 2311285242Sachim return; 2312285242Sachim } 2313285242Sachim 2314285242Sachim if (OSSA_PORT_VALID == (npipps & PORT_STATE_MASK)) 2315285242Sachim { 2316285242Sachim pPort->status &= ~PORT_INVALIDATING; 2317285242Sachim saRoot->PortMap[portId].PortStatus &= ~PORT_INVALIDATING; 2318285242Sachim } 2319285242Sachim else 2320285242Sachim { 2321285242Sachim SA_DBG1(("siEventSATASignatureRcvd: PortInvalid portID %d PortContext %p\n", portId, saRoot->PortMap[portId].PortContext)); 2322285242Sachim } 2323285242Sachim } 2324285242Sachim 2325285242Sachim /* adjust the bit fields before callback */ 2326285242Sachim phyId = (linkRate << SHIFT8) | phyId; 2327285242Sachim /* report PhyId, NPIP, PortState */ 2328285242Sachim phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16); 2329285242Sachim ossaHwCB(agRoot, &(pPort->portContext), OSSA_HW_EVENT_SATA_PHY_UP, phyId, agNULL, pMsg); 2330285242Sachim 2331285242Sachim /* set PHY_UP status */ 2332285242Sachim PHY_STATUS_SET(pPhy, PHY_UP); 2333285242Sachim 2334285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5m"); 2335285242Sachim 2336285242Sachim /* return */ 2337285242Sachim return; 2338285242Sachim} 2339285242Sachim 2340285242Sachim 2341285242Sachim/******************************************************************************/ 2342285242Sachim/*! \brief Process Outbound IOMB Message 2343285242Sachim * 2344285242Sachim * Process Outbound IOMB from SPC 2345285242Sachim * 2346285242Sachim * \param agRoot Handles for this instance of SAS/SATA LL Layer 2347285242Sachim * \param pMsg1 Pointer of Response IOMB message 1 2348285242Sachim * \param category category of outbpond IOMB header 2349285242Sachim * \param opcode Opcode of Outbound IOMB header 2350285242Sachim * \param bc buffer count of IOMB header 2351285242Sachim * 2352285242Sachim * \return success or fail 2353285242Sachim * 2354285242Sachim */ 2355285242Sachim/*******************************************************************************/ 2356285242SachimGLOBAL bit32 mpiParseOBIomb( 2357285242Sachim agsaRoot_t *agRoot, 2358285242Sachim bit32 *pMsg1, 2359285242Sachim mpiMsgCategory_t category, 2360285242Sachim bit16 opcode 2361285242Sachim ) 2362285242Sachim{ 2363285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2364285242Sachim bit32 ret = AGSA_RC_SUCCESS; 2365285242Sachim bit32 parserStatus = AGSA_RC_SUCCESS; 2366285242Sachim 2367285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD, "2f"); 2368285242Sachim 2369285242Sachim switch (opcode) 2370285242Sachim { 2371285242Sachim case OPC_OUB_COMBINED_SSP_COMP: 2372285242Sachim { 2373285242Sachim agsaSSPCoalescedCompletionRsp_t *pIomb = (agsaSSPCoalescedCompletionRsp_t *)pMsg1; 2374285242Sachim agsaIORequestDesc_t *pRequest = agNULL; 2375285242Sachim bit32 tag = 0; 2376285242Sachim bit32 sspTag = 0; 2377285242Sachim bit32 count = 0; 2378285242Sachim 2379285242Sachim#ifdef SALL_API_TEST 2380285242Sachim saRoot->LLCounters.IOCounter.numSSPCompleted++; 2381285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2382285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2383285242Sachim#else 2384285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP Response received IOMB=%p\n", pMsg1)); 2385285242Sachim#endif 2386285242Sachim /* get Tag */ 2387285242Sachim for (count = 0; count < pIomb->coalescedCount; count++) 2388285242Sachim { 2389285242Sachim tag = pIomb->sspComplCxt[count].tag; 2390285242Sachim sspTag = pIomb->sspComplCxt[count].SSPTag; 2391285242Sachim pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2392285242Sachim SA_ASSERT((pRequest), "pRequest"); 2393285242Sachim 2394285242Sachim if(pRequest == agNULL) 2395285242Sachim { 2396285242Sachim SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SSP_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2397285242Sachim#ifdef SA_ENABLE_PCI_TRIGGER 2398285242Sachim if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_IOMB_ERROR ) 2399285242Sachim { 2400285242Sachim siPCITriger(agRoot); 2401285242Sachim } 2402285242Sachim#endif /* SA_ENABLE_PCI_TRIGGER */ 2403285242Sachim return(AGSA_RC_FAILURE); 2404285242Sachim } 2405285242Sachim SA_ASSERT((pRequest->valid), "pRequest->valid"); 2406285242Sachim 2407285242Sachim#ifdef SA_ENABLE_PCI_TRIGGER 2408285242Sachim if(!pRequest->valid) 2409285242Sachim { 2410285242Sachim if( saRoot->swConfig.PCI_trigger & PCI_TRIGGER_COAL_INVALID ) 2411285242Sachim { 2412285242Sachim siPCITriger(agRoot); 2413285242Sachim } 2414285242Sachim } 2415285242Sachim#endif /* SA_ENABLE_PCI_TRIGGER */ 2416285242Sachim 2417285242Sachim 2418285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SSP_COMP IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, OSSA_IO_SUCCESS, 0, sspTag)); 2419285242Sachim 2420285242Sachim /* Completion of SSP without Response Data */ 2421285242Sachim siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 2422285242Sachim } 2423285242Sachim } 2424285242Sachim break; 2425285242Sachim 2426285242Sachim case OPC_OUB_SSP_COMP: 2427285242Sachim { 2428285242Sachim#ifdef SALL_API_TEST 2429285242Sachim saRoot->LLCounters.IOCounter.numSSPCompleted++; 2430285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p %d\n", 2431285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2432285242Sachim#else 2433285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_COMP Response received IOMB=%p\n", pMsg1)); 2434285242Sachim#endif 2435285242Sachim /* process the SSP IO Completed response message */ 2436285242Sachim mpiSSPCompletion(agRoot, pMsg1); 2437285242Sachim break; 2438285242Sachim } 2439285242Sachim case OPC_OUB_COMBINED_SATA_COMP: 2440285242Sachim { 2441285242Sachim agsaSATACoalescedCompletionRsp_t *pIomb; 2442285242Sachim agsaIORequestDesc_t *pRequest; 2443285242Sachim bit32 tag; 2444285242Sachim bit32 count; 2445285242Sachim 2446285242Sachim #ifdef SALL_API_TEST 2447285242Sachim saRoot->LLCounters.IOCounter.numSSPCompleted++; 2448285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p %d\n", 2449285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSSPCompleted)); 2450285242Sachim #else 2451285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP Response received IOMB=%p\n", pMsg1)); 2452285242Sachim #endif 2453285242Sachim 2454285242Sachim pIomb = (agsaSATACoalescedCompletionRsp_t *)pMsg1; 2455285242Sachim /* get Tag */ 2456285242Sachim for (count = 0; count < pIomb->coalescedCount; count++) 2457285242Sachim { 2458285242Sachim tag = pIomb->stpComplCxt[count].tag; 2459285242Sachim pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 2460285242Sachim SA_ASSERT((pRequest), "pRequest"); 2461285242Sachim 2462285242Sachim if(pRequest == agNULL) 2463285242Sachim { 2464285242Sachim SA_DBG1(("mpiParseOBIomb,OPC_OUB_COMBINED_SATA_COMP Resp IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2465285242Sachim return(AGSA_RC_FAILURE); 2466285242Sachim } 2467285242Sachim SA_ASSERT((pRequest->valid), "pRequest->valid"); 2468285242Sachim 2469285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_COMBINED_SATA_COMP IOMB tag=0x%x, status=0x%x, param=0x%x\n", tag, OSSA_IO_SUCCESS, 0)); 2470285242Sachim 2471285242Sachim /* Completion of SATA without Response Data */ 2472285242Sachim siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 2473285242Sachim } 2474285242Sachim break; 2475285242Sachim } 2476285242Sachim case OPC_OUB_SATA_COMP: 2477285242Sachim { 2478285242Sachim#ifdef SALL_API_TEST 2479285242Sachim saRoot->LLCounters.IOCounter.numSataCompleted++; 2480285242Sachim SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p %d\n", 2481285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSataCompleted)); 2482285242Sachim#else 2483285242Sachim SA_DBG3(("mpiParseOBIomb, SATA_COMP Response received IOMB=%p\n", pMsg1)); 2484285242Sachim#endif 2485285242Sachim /* process the response message */ 2486285242Sachim mpiSATACompletion(agRoot, pMsg1); 2487285242Sachim break; 2488285242Sachim } 2489285242Sachim case OPC_OUB_SSP_ABORT_RSP: 2490285242Sachim { 2491285242Sachim#ifdef SALL_API_TEST 2492285242Sachim saRoot->LLCounters.IOCounter.numSSPAbortedCB++; 2493285242Sachim#else 2494285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_ABORT Response received IOMB=%p\n", pMsg1)); 2495285242Sachim#endif 2496285242Sachim /* process the response message */ 2497285242Sachim parserStatus = mpiSSPAbortRsp(agRoot, (agsaSSPAbortRsp_t *)pMsg1); 2498285242Sachim if(parserStatus != AGSA_RC_SUCCESS) 2499285242Sachim { 2500285242Sachim SA_DBG3(("mpiParseOBIomb, mpiSSPAbortRsp FAIL IOMB=%p\n", pMsg1)); 2501285242Sachim } 2502285242Sachim 2503285242Sachim break; 2504285242Sachim } 2505285242Sachim case OPC_OUB_SATA_ABORT_RSP: 2506285242Sachim { 2507285242Sachim#ifdef SALL_API_TEST 2508285242Sachim saRoot->LLCounters.IOCounter.numSataAbortedCB++; 2509285242Sachim#else 2510285242Sachim SA_DBG3(("mpiParseOBIomb, SATA_ABORT Response received IOMB=%p\n", pMsg1)); 2511285242Sachim#endif 2512285242Sachim /* process the response message */ 2513285242Sachim mpiSATAAbortRsp(agRoot, (agsaSATAAbortRsp_t *)pMsg1); 2514285242Sachim break; 2515285242Sachim } 2516285242Sachim case OPC_OUB_SATA_EVENT: 2517285242Sachim { 2518285242Sachim SA_DBG3(("mpiParseOBIomb, SATA_EVENT Response received IOMB=%p\n", pMsg1)); 2519285242Sachim /* process the response message */ 2520285242Sachim mpiSATAEvent(agRoot, (agsaSATAEventRsp_t *)pMsg1); 2521285242Sachim break; 2522285242Sachim } 2523285242Sachim case OPC_OUB_SSP_EVENT: 2524285242Sachim { 2525285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_EVENT Response received IOMB=%p\n", pMsg1)); 2526285242Sachim /* process the response message */ 2527285242Sachim mpiSSPEvent(agRoot, (agsaSSPEventRsp_t *)pMsg1); 2528285242Sachim break; 2529285242Sachim } 2530285242Sachim case OPC_OUB_SMP_COMP: 2531285242Sachim { 2532285242Sachim#ifdef SALL_API_TEST 2533285242Sachim saRoot->LLCounters.IOCounter.numSMPCompleted++; 2534285242Sachim SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p, %d\n", 2535285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSMPCompleted)); 2536285242Sachim#else 2537285242Sachim SA_DBG3(("mpiParseOBIomb, SMP_COMP Response received IOMB=%p\n", pMsg1)); 2538285242Sachim#endif 2539285242Sachim /* process the response message */ 2540285242Sachim mpiSMPCompletion(agRoot, (agsaSMPCompletionRsp_t *)pMsg1); 2541285242Sachim break; 2542285242Sachim } 2543285242Sachim case OPC_OUB_ECHO: 2544285242Sachim { 2545285242Sachim#ifdef SALL_API_TEST 2546285242Sachim saRoot->LLCounters.IOCounter.numEchoCB++; 2547285242Sachim SA_DBG3(("mpiParseOBIomb, ECHO Response received %d\n", saRoot->LLCounters.IOCounter.numEchoCB)); 2548285242Sachim#else 2549285242Sachim SA_DBG3(("mpiParseOBIomb, ECHO Response received\n")); 2550285242Sachim#endif 2551285242Sachim /* process the response message */ 2552285242Sachim mpiEchoRsp(agRoot, (agsaEchoRsp_t *)pMsg1); 2553285242Sachim break; 2554285242Sachim } 2555285242Sachim case OPC_OUB_GET_NVMD_DATA: 2556285242Sachim { 2557285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2558285242Sachim /* process the response message */ 2559285242Sachim mpiGetNVMDataRsp(agRoot, (agsaGetNVMDataRsp_t *)pMsg1); 2560285242Sachim break; 2561285242Sachim } 2562285242Sachim case OPC_OUB_SPC_HW_EVENT: 2563285242Sachim { 2564285242Sachim SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2565285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_HW_EVENT Response received IOMB=%p\n", pMsg1)); 2566285242Sachim /* process the response message */ 2567285242Sachim mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2568285242Sachim break; 2569285242Sachim } 2570285242Sachim case OPC_OUB_HW_EVENT: 2571285242Sachim { 2572285242Sachim SA_DBG3(("mpiParseOBIomb, HW_EVENT Response received IOMB=%p\n", pMsg1)); 2573285242Sachim /* process the response message */ 2574285242Sachim mpiHWevent(agRoot, (agsaHWEvent_SPC_OUB_t *)pMsg1); 2575285242Sachim break; 2576285242Sachim } 2577285242Sachim case OPC_OUB_PHY_START_RESPONSE: 2578285242Sachim { 2579285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_START_RESPONSE Response received IOMB=%p\n", pMsg1)); 2580285242Sachim /* process the response message */ 2581285242Sachim mpiPhyStartEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2582285242Sachim 2583285242Sachim break; 2584285242Sachim } 2585285242Sachim case OPC_OUB_PHY_STOP_RESPONSE: 2586285242Sachim { 2587285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_PHY_STOP_RESPONSE Response received IOMB=%p\n", pMsg1)); 2588285242Sachim /* process the response message */ 2589285242Sachim mpiPhyStopEvent( agRoot, (agsaHWEvent_Phy_OUB_t *)pMsg1 ); 2590285242Sachim break; 2591285242Sachim } 2592285242Sachim 2593285242Sachim case OPC_OUB_LOCAL_PHY_CNTRL: 2594285242Sachim { 2595285242Sachim SA_DBG3(("mpiParseOBIomb, PHY CONTROL Response received IOMB=%p\n", pMsg1)); 2596285242Sachim /* process the response message */ 2597285242Sachim mpiPhyCntrlRsp(agRoot, (agsaLocalPhyCntrlRsp_t *)pMsg1); 2598285242Sachim break; 2599285242Sachim } 2600285242Sachim case OPC_OUB_SPC_DEV_REGIST: 2601285242Sachim { 2602285242Sachim SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2603285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SPC_DEV_REGIST Response received IOMB=%p\n", pMsg1)); 2604285242Sachim /* process the response message */ 2605285242Sachim mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2606285242Sachim break; 2607285242Sachim } 2608285242Sachim case OPC_OUB_DEV_REGIST: 2609285242Sachim { 2610285242Sachim SA_DBG2(("mpiParseOBIomb, DEV_REGISTRATION Response received IOMB=%p\n", pMsg1)); 2611285242Sachim /* process the response message */ 2612285242Sachim mpiDeviceRegRsp(agRoot, (agsaDeviceRegistrationRsp_t *)pMsg1); 2613285242Sachim break; 2614285242Sachim } 2615285242Sachim case OPC_OUB_DEREG_DEV: 2616285242Sachim { 2617285242Sachim SA_DBG3(("mpiParseOBIomb, DEREGISTRATION DEVICE Response received IOMB=%p\n", pMsg1)); 2618285242Sachim /* process the response message */ 2619285242Sachim mpiDeregDevHandleRsp(agRoot, (agsaDeregDevHandleRsp_t *)pMsg1); 2620285242Sachim break; 2621285242Sachim } 2622285242Sachim case OPC_OUB_GET_DEV_HANDLE: 2623285242Sachim { 2624285242Sachim SA_DBG3(("mpiParseOBIomb, GET_DEV_HANDLE Response received IOMB=%p\n", pMsg1)); 2625285242Sachim /* process the response message */ 2626285242Sachim mpiGetDevHandleRsp(agRoot, (agsaGetDevHandleRsp_t *)pMsg1); 2627285242Sachim break; 2628285242Sachim } 2629285242Sachim case OPC_OUB_SPC_DEV_HANDLE_ARRIV: 2630285242Sachim { 2631285242Sachim SA_DBG3(("mpiParseOBIomb, SPC_DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2632285242Sachim /* process the response message */ 2633285242Sachim mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2634285242Sachim break; 2635285242Sachim } 2636285242Sachim case OPC_OUB_DEV_HANDLE_ARRIV: 2637285242Sachim { 2638285242Sachim SA_DBG3(("mpiParseOBIomb, DEV_HANDLE_ARRIV Response received IOMB=%p\n", pMsg1)); 2639285242Sachim /* process the response message */ 2640285242Sachim mpiDeviceHandleArrived(agRoot, (agsaDeviceHandleArrivedNotify_t *)pMsg1); 2641285242Sachim break; 2642285242Sachim } 2643285242Sachim case OPC_OUB_SSP_RECV_EVENT: 2644285242Sachim { 2645285242Sachim SA_DBG3(("mpiParseOBIomb, SSP_RECV_EVENT Response received IOMB=%p\n", pMsg1)); 2646285242Sachim /* process the response message */ 2647285242Sachim mpiSSPReqReceivedNotify(agRoot, (agsaSSPReqReceivedNotify_t *)pMsg1); 2648285242Sachim break; 2649285242Sachim } 2650285242Sachim case OPC_OUB_DEV_INFO: 2651285242Sachim { 2652285242Sachim SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2653285242Sachim SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2654285242Sachim /* process the response message */ 2655285242Sachim mpiGetDevInfoRsp(agRoot, (agsaGetDevInfoRspV_t *)pMsg1); 2656285242Sachim break; 2657285242Sachim } 2658285242Sachim case OPC_OUB_GET_PHY_PROFILE_RSP: 2659285242Sachim { 2660285242Sachim SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2661285242Sachim SA_DBG2(("mpiParseOBIomb, OPC_OUB_GET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2662285242Sachim /* process the response message */ 2663285242Sachim mpiGetPhyProfileRsp(agRoot, (agsaGetPhyProfileRspV_t *)pMsg1); 2664285242Sachim break; 2665285242Sachim } 2666285242Sachim case OPC_OUB_SET_PHY_PROFILE_RSP: 2667285242Sachim { 2668285242Sachim SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2669285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_PHY_PROFILE_RSP Response received IOMB=%p\n", pMsg1)); 2670285242Sachim /* process the response message */ 2671285242Sachim mpiSetPhyProfileRsp(agRoot, (agsaSetPhyProfileRspV_t *)pMsg1); 2672285242Sachim break; 2673285242Sachim } 2674285242Sachim case OPC_OUB_SPC_DEV_INFO: 2675285242Sachim { 2676285242Sachim SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2677285242Sachim SA_DBG3(("mpiParseOBIomb, DEV_INFO Response received IOMB=%p\n", pMsg1)); 2678285242Sachim /* process the response message */ 2679285242Sachim mpiGetDevInfoRspSpc(agRoot, (agsaGetDevInfoRsp_t *)pMsg1); 2680285242Sachim break; 2681285242Sachim } 2682285242Sachim case OPC_OUB_FW_FLASH_UPDATE: 2683285242Sachim { 2684285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_FLASH_UPDATE Response received IOMB=%p\n", pMsg1)); 2685285242Sachim /* process the response message */ 2686285242Sachim mpiFwFlashUpdateRsp(agRoot, (agsaFwFlashUpdateRsp_t *)pMsg1); 2687285242Sachim break; 2688285242Sachim } 2689285242Sachim case OPC_OUB_FLASH_OP_EXT_RSP: 2690285242Sachim { 2691285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_FLASH_OP_EXT_RSP Response received IOMB=%p\n", pMsg1)); 2692285242Sachim /* process the response message */ 2693285242Sachim mpiFwExtFlashUpdateRsp(agRoot, (agsaFwFlashOpExtRsp_t *)pMsg1); 2694285242Sachim break; 2695285242Sachim } 2696285242Sachim#ifdef SPC_ENABLE_PROFILE 2697285242Sachim case OPC_OUB_FW_PROFILE: 2698285242Sachim { 2699285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_FW_PROFILE Response received IOMB=%p\n", pMsg1)); 2700285242Sachim /* process the response message */ 2701285242Sachim mpiFwProfileRsp(agRoot, (agsaFwProfileRsp_t *)pMsg1); 2702285242Sachim break; 2703285242Sachim } 2704285242Sachim#endif 2705285242Sachim case OPC_OUB_SET_NVMD_DATA: 2706285242Sachim { 2707285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_NVMD_DATA received IOMB=%p\n", pMsg1)); 2708285242Sachim /* process the response message */ 2709285242Sachim mpiSetNVMDataRsp(agRoot, (agsaSetNVMDataRsp_t *)pMsg1); 2710285242Sachim break; 2711285242Sachim } 2712285242Sachim case OPC_OUB_GPIO_RESPONSE: 2713285242Sachim { 2714285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2715285242Sachim /* process the response message */ 2716285242Sachim mpiGPIORsp(agRoot, (agsaGPIORsp_t *)pMsg1); 2717285242Sachim break; 2718285242Sachim } 2719285242Sachim case OPC_OUB_GPIO_EVENT: 2720285242Sachim { 2721285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2722285242Sachim /* process the response message */ 2723285242Sachim mpiGPIOEventRsp(agRoot, (agsaGPIOEvent_t *)pMsg1); 2724285242Sachim break; 2725285242Sachim } 2726285242Sachim case OPC_OUB_GENERAL_EVENT: 2727285242Sachim { 2728285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_GENERAL_EVENT Response received IOMB=%p\n", pMsg1)); 2729285242Sachim /* process the response message */ 2730285242Sachim mpiGeneralEventRsp(agRoot, (agsaGeneralEventRsp_t *)pMsg1); 2731285242Sachim break; 2732285242Sachim } 2733285242Sachim case OPC_OUB_SAS_DIAG_MODE_START_END: 2734285242Sachim { 2735285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_MODE_START_END Response received IOMB=%p\n", pMsg1)); 2736285242Sachim /* process the response message */ 2737285242Sachim mpiSASDiagStartEndRsp(agRoot, (agsaSASDiagStartEndRsp_t *)pMsg1); 2738285242Sachim break; 2739285242Sachim } 2740285242Sachim case OPC_OUB_SAS_DIAG_EXECUTE: 2741285242Sachim { 2742285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_DIAG_EXECUTE_RSP Response received IOMB=%p\n", pMsg1)); 2743285242Sachim /* process the response message */ 2744285242Sachim mpiSASDiagExecuteRsp(agRoot, (agsaSASDiagExecuteRsp_t *)pMsg1); 2745285242Sachim break; 2746285242Sachim } 2747285242Sachim case OPC_OUB_GET_TIME_STAMP: 2748285242Sachim { 2749285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_TIME_STAMP Response received IOMB=%p\n", pMsg1)); 2750285242Sachim /* process the response message */ 2751285242Sachim mpiGetTimeStampRsp(agRoot, (agsaGetTimeStampRsp_t *)pMsg1); 2752285242Sachim break; 2753285242Sachim } 2754285242Sachim 2755285242Sachim case OPC_OUB_SPC_SAS_HW_EVENT_ACK: 2756285242Sachim { 2757285242Sachim SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2758285242Sachim SA_DBG3(("mpiParseOBIomb,OPC_OUB_SPC_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2759285242Sachim /* process the response message */ 2760285242Sachim mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2761285242Sachim break; 2762285242Sachim } 2763285242Sachim 2764285242Sachim case OPC_OUB_SAS_HW_EVENT_ACK: 2765285242Sachim { 2766285242Sachim SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2767285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_SAS_HW_EVENT_ACK Response received IOMB=%p\n", pMsg1)); 2768285242Sachim /* process the response message */ 2769285242Sachim mpiSASHwEventAckRsp(agRoot, (agsaSASHwEventAckRsp_t *)pMsg1); 2770285242Sachim break; 2771285242Sachim } 2772285242Sachim case OPC_OUB_PORT_CONTROL: 2773285242Sachim { 2774285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_PORT_CONTROL Response received IOMB=%p\n", pMsg1)); 2775285242Sachim /* process the response message */ 2776285242Sachim mpiPortControlRsp(agRoot, (agsaPortControlRsp_t *)pMsg1); 2777285242Sachim break; 2778285242Sachim } 2779285242Sachim case OPC_OUB_SMP_ABORT_RSP: 2780285242Sachim { 2781285242Sachim#ifdef SALL_API_TEST 2782285242Sachim saRoot->LLCounters.IOCounter.numSMPAbortedCB++; 2783285242Sachim SA_DBG3(("mpiParseOBIomb, SMP_ABORT Response received IOMB=%p, %d\n", 2784285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numSMPAbortedCB)); 2785285242Sachim#else 2786285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SMP_ABORT_RSP Response received IOMB=%p\n", pMsg1)); 2787285242Sachim#endif 2788285242Sachim /* process the response message */ 2789285242Sachim mpiSMPAbortRsp(agRoot, (agsaSMPAbortRsp_t *)pMsg1); 2790285242Sachim break; 2791285242Sachim } 2792285242Sachim case OPC_OUB_DEVICE_HANDLE_REMOVAL: 2793285242Sachim { 2794285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEVICE_HANDLE_REMOVAL received IOMB=%p\n", pMsg1)); 2795285242Sachim /* process the response message */ 2796285242Sachim mpiDeviceHandleRemoval(agRoot, (agsaDeviceHandleRemoval_t *)pMsg1); 2797285242Sachim break; 2798285242Sachim } 2799285242Sachim case OPC_OUB_SET_DEVICE_STATE: 2800285242Sachim { 2801285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2802285242Sachim /* process the response message */ 2803285242Sachim mpiSetDeviceStateRsp(agRoot, (agsaSetDeviceStateRsp_t *)pMsg1); 2804285242Sachim break; 2805285242Sachim } 2806285242Sachim case OPC_OUB_GET_DEVICE_STATE: 2807285242Sachim { 2808285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DEVICE_STATE received IOMB=%p\n", pMsg1)); 2809285242Sachim /* process the response message */ 2810285242Sachim mpiGetDeviceStateRsp(agRoot, (agsaGetDeviceStateRsp_t *)pMsg1); 2811285242Sachim break; 2812285242Sachim } 2813285242Sachim case OPC_OUB_SET_DEV_INFO: 2814285242Sachim { 2815285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_DEV_INFO received IOMB=%p\n", pMsg1)); 2816285242Sachim /* process the response message */ 2817285242Sachim mpiSetDevInfoRsp(agRoot, (agsaSetDeviceInfoRsp_t *)pMsg1); 2818285242Sachim break; 2819285242Sachim } 2820285242Sachim case OPC_OUB_SAS_RE_INITIALIZE: 2821285242Sachim { 2822285242Sachim SA_ASSERT((smIS_SPC(agRoot)), "smIS_SPC"); 2823285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SAS_RE_INITIALIZE received IOMB=%p\n", pMsg1)); 2824285242Sachim /* process the response message */ 2825285242Sachim mpiSasReInitializeRsp(agRoot, (agsaSasReInitializeRsp_t *)pMsg1); 2826285242Sachim break; 2827285242Sachim } 2828285242Sachim 2829285242Sachim case OPC_OUB_SGPIO_RESPONSE: 2830285242Sachim { 2831285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SGPIO_RESPONSE Response received IOMB=%p\n", pMsg1)); 2832285242Sachim /* process the response message */ 2833285242Sachim mpiSGpioRsp(agRoot, (agsaSGpioRsp_t *)pMsg1); 2834285242Sachim break; 2835285242Sachim } 2836285242Sachim 2837285242Sachim case OPC_OUB_PCIE_DIAG_EXECUTE: 2838285242Sachim { 2839285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_PCIE_DIAG_EXECUTE Response received IOMB=%p\n", pMsg1)); 2840285242Sachim /* process the response message */ 2841285242Sachim mpiPCIeDiagExecuteRsp(agRoot, (agsaPCIeDiagExecuteRsp_t *)pMsg1); 2842285242Sachim break; 2843285242Sachim } 2844285242Sachim 2845285242Sachim case OPC_OUB_GET_VIST_CAP_RSP: 2846285242Sachim { 2847285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2848285242Sachim /* process the response message */ 2849285242Sachim mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2850285242Sachim break; 2851285242Sachim } 2852285242Sachim case 2104: 2853285242Sachim { 2854285242Sachim if(smIS_SPC6V(agRoot)) 2855285242Sachim { 2856285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_DFE_DATA_RSP Response received IOMB=%p\n", pMsg1)); 2857285242Sachim /* process the response message */ 2858285242Sachim mpiGetDFEDataRsp(agRoot, (agsaGetDDEFDataRsp_t *)pMsg1); 2859285242Sachim } 2860285242Sachim if(smIS_SPC12V(agRoot)) 2861285242Sachim { 2862285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_INB_GET_VIST_CAP Response received IOMB=%p\n", pMsg1)); 2863285242Sachim /* process the response message */ 2864285242Sachim mpiGetVHistRsp(agRoot, (agsaGetVHistCapRsp_t *)pMsg1); 2865285242Sachim } 2866285242Sachim else 2867285242Sachim { 2868285242Sachim SA_DBG1(("mpiParseOBIomb, 2104 Response received IOMB=%p\n", pMsg1)); 2869285242Sachim /* process the response message */ 2870285242Sachim } 2871285242Sachim break; 2872285242Sachim } 2873285242Sachim case OPC_OUB_SET_CONTROLLER_CONFIG: 2874285242Sachim { 2875285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_SET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2876285242Sachim mpiSetControllerConfigRsp(agRoot, (agsaSetControllerConfigRsp_t *)pMsg1); 2877285242Sachim break; 2878285242Sachim } 2879285242Sachim case OPC_OUB_GET_CONTROLLER_CONFIG: 2880285242Sachim { 2881285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_GET_CONTROLLER_CONFIG Response received IOMB=%p\n", pMsg1)); 2882285242Sachim mpiGetControllerConfigRsp(agRoot, (agsaGetControllerConfigRsp_t *)pMsg1); 2883285242Sachim break; 2884285242Sachim } 2885285242Sachim case OPC_OUB_KEK_MANAGEMENT: 2886285242Sachim { 2887285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_KEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2888285242Sachim mpiKekManagementRsp(agRoot, (agsaKekManagementRsp_t *)pMsg1); 2889285242Sachim break; 2890285242Sachim } 2891285242Sachim case OPC_OUB_DEK_MANAGEMENT: 2892285242Sachim { 2893285242Sachim SA_DBG3(("mpiParseOBIomb, OPC_OUB_DEK_MANAGEMENT Response received IOMB=%p\n", pMsg1)); 2894285242Sachim mpiDekManagementRsp(agRoot, (agsaDekManagementRsp_t *)pMsg1); 2895285242Sachim break; 2896285242Sachim } 2897285242Sachim case OPC_OUB_OPR_MGMT: 2898285242Sachim { 2899285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_OPR_MGMT Response received IOMB=%p\n", pMsg1)); 2900285242Sachim mpiOperatorManagementRsp(agRoot, (agsaOperatorMangmenRsp_t *)pMsg1); 2901285242Sachim break; 2902285242Sachim } 2903285242Sachim case OPC_OUB_ENC_TEST_EXECUTE: 2904285242Sachim { 2905285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_ENC_TEST_EXECUTE Response received IOMB=%p\n", pMsg1)); 2906285242Sachim mpiBistRsp(agRoot, (agsaEncryptBistRsp_t *)pMsg1); 2907285242Sachim break; 2908285242Sachim } 2909285242Sachim case OPC_OUB_SET_OPERATOR: 2910285242Sachim { 2911285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_SET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2912285242Sachim mpiSetOperatorRsp(agRoot, (agsaSetOperatorRsp_t *)pMsg1); 2913285242Sachim break; 2914285242Sachim } 2915285242Sachim case OPC_OUB_GET_OPERATOR: 2916285242Sachim { 2917285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_GET_OPERATOR Response received IOMB=%p\n", pMsg1)); 2918285242Sachim mpiGetOperatorRsp(agRoot, (agsaGetOperatorRsp_t *)pMsg1); 2919285242Sachim break; 2920285242Sachim } 2921285242Sachim case OPC_OUB_DIF_ENC_OFFLOAD_RSP: 2922285242Sachim { 2923285242Sachim SA_ASSERT((smIS_SPCV(agRoot)), "smIS_SPCV"); 2924285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_DIF_ENC_OFFLOAD_RSP Response received IOMB=%p\n", pMsg1)); 2925285242Sachim /* process the response message */ 2926285242Sachim mpiDifEncOffloadRsp(agRoot, (agsaDifEncOffloadRspV_t *)pMsg1); 2927285242Sachim break; 2928285242Sachim } 2929285242Sachim default: 2930285242Sachim { 2931285242Sachim#ifdef SALL_API_TEST 2932285242Sachim saRoot->LLCounters.IOCounter.numUNKNWRespIOMB++; 2933285242Sachim SA_DBG1(("mpiParseOBIomb, UnKnown Response received IOMB=%p, %d\n", 2934285242Sachim pMsg1, saRoot->LLCounters.IOCounter.numUNKNWRespIOMB)); 2935285242Sachim#else 2936285242Sachim SA_DBG1(("mpiParseOBIomb, Unknown IOMB Response received opcode 0x%X IOMB=%p\n",opcode, pMsg1)); 2937285242Sachim#endif 2938285242Sachim break; 2939285242Sachim } 2940285242Sachim } /* switch */ 2941285242Sachim 2942285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2f"); 2943285242Sachim 2944285242Sachim return ret; 2945285242Sachim 2946285242Sachim} 2947285242Sachim 2948285242Sachim 2949285242Sachim/******************************************************************************/ 2950285242Sachim/*! \brief SPC MPI SATA Completion 2951285242Sachim * 2952285242Sachim * This function handles the SATA completion. 2953285242Sachim * 2954285242Sachim * \param agRoot Handles for this instance of SAS/SATA LLL 2955285242Sachim * \param pIomb1 Pointer of Message1 2956285242Sachim * \param bc buffer count 2957285242Sachim * 2958285242Sachim * \return The read value 2959285242Sachim * 2960285242Sachim */ 2961285242Sachim/*******************************************************************************/ 2962285242SachimGLOBAL FORCEINLINE 2963285242Sachimbit32 mpiSATACompletion( 2964285242Sachim agsaRoot_t *agRoot, 2965285242Sachim bit32 *pIomb1 2966285242Sachim ) 2967285242Sachim{ 2968285242Sachim bit32 ret = AGSA_RC_SUCCESS; 2969285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 2970285242Sachim bit32 status; 2971285242Sachim bit32 tag; 2972285242Sachim bit32 param; 2973285242Sachim agsaIORequestDesc_t *pRequest; 2974285242Sachim bit32 *agFirstDword; 2975285242Sachim bit32 *pResp; 2976285242Sachim 2977285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD,"2s"); 2978285242Sachim 2979285242Sachim OSSA_READ_LE_32(AGROOT, &tag, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, tag)) ; 2980285242Sachim OSSA_READ_LE_32(AGROOT, &status, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, status)) ; 2981285242Sachim OSSA_READ_LE_32(AGROOT, ¶m, pIomb1, OSSA_OFFSET_OF(agsaSATACompletionRsp_t, param)) ; 2982285242Sachim 2983285242Sachim SA_DBG3(("mpiSATACompletion: start, HTAG=0x%x\n", tag)); 2984285242Sachim 2985285242Sachim /* get IOrequest from IOMap */ 2986285242Sachim pRequest = (agsaIORequestDesc_t*)saRoot->IOMap[tag].IORequest; 2987285242Sachim SA_ASSERT((pRequest), "pRequest"); 2988285242Sachim 2989285242Sachim if(agNULL == pRequest) 2990285242Sachim { 2991285242Sachim SA_DBG1(("mpiSATACompletion: agNULL == pRequest tag 0x%X status 0x%X\n",tag, status )); 2992285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "2s"); 2993285242Sachim return AGSA_RC_FAILURE; 2994285242Sachim } 2995285242Sachim 2996285242Sachim SA_ASSERT((pRequest->valid), "pRequest->valid"); 2997285242Sachim if(!pRequest->valid) 2998285242Sachim { 2999285242Sachim SA_DBG1(("mpiSATACompletion: not valid IOMB tag=0x%x status=0x%x param=0x%x Device =0x%x\n", tag, status, param, 3000285242Sachim pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3001285242Sachim } 3002285242Sachim 3003285242Sachim switch (status) 3004285242Sachim { 3005285242Sachim case OSSA_IO_SUCCESS: 3006285242Sachim { 3007285242Sachim SA_DBG3(("mpiSATACompletion: OSSA_IO_SUCCESS, param=0x%x\n", param)); 3008285242Sachim if (!param) 3009285242Sachim { 3010285242Sachim /* SATA request completion */ 3011285242Sachim siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, 0); 3012285242Sachim } 3013285242Sachim else 3014285242Sachim { 3015285242Sachim /* param number bytes of SATA Rsp */ 3016285242Sachim agFirstDword = &pIomb1[3]; 3017285242Sachim pResp = &pIomb1[4]; 3018285242Sachim 3019285242Sachim /* CB function to the up layer */ 3020285242Sachim /* Response Length not include firstDW */ 3021285242Sachim saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3022285242Sachim SA_DBG2(("mpiSATACompletion: param 0x%x agFirstDwordResp 0x%x Resp 0x%x tag 0x%x\n",param,*agFirstDword,*pResp ,tag)); 3023285242Sachim siEventSATAResponseWtDataRcvd(agRoot, pRequest, agFirstDword, pResp, (param - 4)); 3024285242Sachim } 3025285242Sachim 3026285242Sachim break; 3027285242Sachim } 3028285242Sachim case OSSA_IO_ABORTED: 3029285242Sachim { 3030285242Sachim SA_DBG2(("mpiSATACompletion: OSSA_IO_ABORTED tag 0x%X\n", tag)); 3031285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3032285242Sachim siAbnormal(agRoot, pRequest, status, param, 0); 3033285242Sachim break; 3034285242Sachim } 3035285242Sachim case OSSA_IO_UNDERFLOW: 3036285242Sachim { 3037285242Sachim /* SATA Completion with error */ 3038285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_UNDERFLOW tag 0x%X\n", tag)); 3039285242Sachim /*underflow means underrun, treat it as success*/ 3040285242Sachim saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++; 3041285242Sachim siAbnormal(agRoot, pRequest, status, param, 0); 3042285242Sachim break; 3043285242Sachim } 3044285242Sachim case OSSA_IO_NO_DEVICE: 3045285242Sachim { 3046285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_NO_DEVICE tag 0x%X\n", tag)); 3047285242Sachim saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3048285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3049285242Sachim break; 3050285242Sachim } 3051285242Sachim case OSSA_IO_XFER_ERROR_BREAK: 3052285242Sachim { 3053285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_BREAK SPC tag 0x%X\n", tag)); 3054285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3055285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3056285242Sachim break; 3057285242Sachim } 3058285242Sachim case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3059285242Sachim { 3060285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%X\n", tag)); 3061285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3062285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3063285242Sachim break; 3064285242Sachim } 3065285242Sachim case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3066285242Sachim { 3067285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%X\n", tag)); 3068285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3069285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3070285242Sachim break; 3071285242Sachim } 3072285242Sachim case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3073285242Sachim { 3074285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%X\n", tag)); 3075285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3076285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3077285242Sachim break; 3078285242Sachim } 3079285242Sachim case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3080285242Sachim { 3081285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BREAK SPC tag 0x%X\n", tag)); 3082285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3083285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3084285242Sachim break; 3085285242Sachim } 3086285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3087285242Sachim { 3088285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%X\n", tag)); 3089285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3090285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3091285242Sachim break; 3092285242Sachim } 3093285242Sachim case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3094285242Sachim { 3095285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%X\n", tag)); 3096285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3097285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3098285242Sachim break; 3099285242Sachim } 3100285242Sachim case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3101285242Sachim { 3102285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%X\n", tag)); 3103285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3104285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3105285242Sachim break; 3106285242Sachim } 3107285242Sachim case OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 3108285242Sachim { 3109285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY tag 0x%X\n", tag)); 3110285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY++; 3111285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3112285242Sachim break; 3113285242Sachim } 3114285242Sachim case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3115285242Sachim { 3116285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%X\n", tag)); 3117285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3118285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3119285242Sachim break; 3120285242Sachim } 3121285242Sachim case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3122285242Sachim { 3123285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%X\n", tag)); 3124285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3125285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3126285242Sachim break; 3127285242Sachim } 3128285242Sachim case OSSA_IO_XFER_ERROR_DMA: 3129285242Sachim { 3130285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_DMA tag 0x%X\n", tag)); 3131285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3132285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3133285242Sachim break; 3134285242Sachim } 3135285242Sachim case OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT: 3136285242Sachim { 3137285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT tag 0x%X\n", tag)); 3138285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT++; 3139285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3140285242Sachim break; 3141285242Sachim } 3142285242Sachim case OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE: 3143285242Sachim { 3144285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE tag 0x%X\n", tag)); 3145285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE++; 3146285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3147285242Sachim break; 3148285242Sachim } 3149285242Sachim case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3150285242Sachim { 3151285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%X\n", tag)); 3152285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3153285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3154285242Sachim break; 3155285242Sachim } 3156285242Sachim case OSSA_IO_PORT_IN_RESET: 3157285242Sachim { 3158285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_PORT_IN_RESET tag 0x%X\n", tag)); 3159285242Sachim saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3160285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3161285242Sachim break; 3162285242Sachim } 3163285242Sachim case OSSA_IO_DS_NON_OPERATIONAL: 3164285242Sachim { 3165285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%X\n", tag)); 3166285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3167285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3168285242Sachim break; 3169285242Sachim } 3170285242Sachim case OSSA_IO_DS_IN_RECOVERY: 3171285242Sachim { 3172285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%X\n", tag)); 3173285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3174285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3175285242Sachim break; 3176285242Sachim } 3177285242Sachim case OSSA_IO_DS_IN_ERROR: 3178285242Sachim { 3179285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_IN_ERROR tag 0x%X\n", tag)); 3180285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3181285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3182285242Sachim break; 3183285242Sachim } 3184285242Sachim 3185285242Sachim case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3186285242Sachim { 3187285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%X\n", tag)); 3188285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3189285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3190285242Sachim break; 3191285242Sachim } 3192285242Sachim case OSSA_IO_ABORT_IN_PROGRESS: 3193285242Sachim { 3194285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%X\n", tag)); 3195285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3196285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3197285242Sachim break; 3198285242Sachim } 3199285242Sachim case OSSA_IO_ABORT_DELAYED: 3200285242Sachim { 3201285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_ABORT_DELAYED tag 0x%X\n", tag)); 3202285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3203285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3204285242Sachim break; 3205285242Sachim } 3206285242Sachim case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3207285242Sachim { 3208285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%X\n", tag)); 3209285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3210285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3211285242Sachim break; 3212285242Sachim } 3213285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3214285242Sachim { 3215285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x\n", tag)); 3216285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3217285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3218285242Sachim break; 3219285242Sachim } 3220285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3221285242Sachim { 3222285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x\n", tag)); 3223285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3224285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0 ); 3225285242Sachim break; 3226285242Sachim } 3227285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3228285242Sachim { 3229285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x\n", tag)); 3230285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3231285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0 ); 3232285242Sachim break; 3233285242Sachim } 3234285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3235285242Sachim { 3236285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x\n", tag)); 3237285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3238285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0 ); 3239285242Sachim break; 3240285242Sachim } 3241285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3242285242Sachim { 3243285242Sachim SA_DBG1(("mpiSATACompletion, OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x\n", tag)); 3244285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3245285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0 ); 3246285242Sachim break; 3247285242Sachim } 3248285242Sachim case OSSA_IO_DS_INVALID: 3249285242Sachim { 3250285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_DS_INVALID tag 0x%X\n", tag)); 3251285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3252285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3253285242Sachim break; 3254285242Sachim } 3255285242Sachim case OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR: 3256285242Sachim { 3257285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR tag 0x%X\n", tag)); 3258285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR++; 3259285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3260285242Sachim break; 3261285242Sachim } 3262285242Sachim case OSSA_MPI_IO_RQE_BUSY_FULL: 3263285242Sachim { 3264285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%X\n", tag)); 3265285242Sachim saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3266285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3267285242Sachim break; 3268285242Sachim } 3269285242Sachim#ifdef REMOVED 3270285242Sachim case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3271285242Sachim { 3272285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x\n", tag)); 3273285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3274285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3275285242Sachim break; 3276285242Sachim } 3277285242Sachim#endif 3278285242Sachim case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3279285242Sachim { 3280285242Sachim SA_DBG1(("mpiSATACompletion: OPC_OUB_SATA_COMP:OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE \n")); 3281285242Sachim saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3282285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3283285242Sachim break; 3284285242Sachim } 3285285242Sachim case OSSA_MPI_ERR_ATAPI_DEVICE_BUSY: 3286285242Sachim { 3287285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_MPI_ERR_ATAPI_DEVICE_BUSY tag 0x%X\n", tag)); 3288285242Sachim saRoot->IoErrorCount.agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY++; 3289285242Sachim siAbnormal(agRoot, pRequest, status, param, 0 ); 3290285242Sachim break; 3291285242Sachim } 3292285242Sachim case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3293285242Sachim { 3294285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%X\n", tag)); 3295285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3296285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3297285242Sachim break; 3298285242Sachim } 3299285242Sachim case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3300285242Sachim { 3301285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%X\n", tag)); 3302285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3303285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3304285242Sachim break; 3305285242Sachim } 3306285242Sachim case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3307285242Sachim { 3308285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%X\n", tag)); 3309285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3310285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3311285242Sachim break; 3312285242Sachim } 3313285242Sachim case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3314285242Sachim { 3315285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%X\n", tag)); 3316285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3317285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3318285242Sachim break; 3319285242Sachim } 3320285242Sachim case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3321285242Sachim { 3322285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%X\n", tag)); 3323285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3324285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3325285242Sachim break; 3326285242Sachim } 3327285242Sachim 3328285242Sachim case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3329285242Sachim { 3330285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%X\n", tag)); 3331285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3332285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3333285242Sachim break; 3334285242Sachim } 3335285242Sachim case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3336285242Sachim { 3337285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%X\n", tag)); 3338285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3339285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3340285242Sachim break; 3341285242Sachim } 3342285242Sachim case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3343285242Sachim { 3344285242Sachim SA_DBG1(("mpiSATACompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%X\n", tag)); 3345285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3346285242Sachim siAbnormal(agRoot, pRequest, status, 0, 0); 3347285242Sachim break; 3348285242Sachim } 3349285242Sachim 3350285242Sachim default: 3351285242Sachim { 3352285242Sachim SA_DBG1(("mpiSATACompletion: Unknown status 0x%x tag 0x%x\n", status, tag)); 3353285242Sachim saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3354285242Sachim siAbnormal(agRoot, pRequest, status, param, 0); 3355285242Sachim break; 3356285242Sachim } 3357285242Sachim } 3358285242Sachim 3359285242Sachim /* The HTag should equal to the IOMB tag */ 3360285242Sachim if (pRequest->HTag != tag) 3361285242Sachim { 3362285242Sachim SA_DBG1(("mpiSATACompletion: Error Htag %d not equal IOMBtag %d\n", pRequest->HTag, tag)); 3363285242Sachim } 3364285242Sachim 3365285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "2s"); 3366285242Sachim return ret; 3367285242Sachim} 3368285242Sachim 3369285242Sachim/******************************************************************************/ 3370285242Sachim/*! \brief SPC MPI SSP Completion 3371285242Sachim * 3372285242Sachim * This function handles the SSP completion. 3373285242Sachim * 3374285242Sachim * \param agRoot Handles for this instance of SAS/SATA LLL 3375285242Sachim * \param pIomb1 Pointer of Message1 3376285242Sachim * \param bc buffer count 3377285242Sachim * 3378285242Sachim * \return The read value 3379285242Sachim * 3380285242Sachim */ 3381285242Sachim/*******************************************************************************/ 3382285242SachimGLOBAL FORCEINLINE 3383285242Sachimbit32 mpiSSPCompletion( 3384285242Sachim agsaRoot_t *agRoot, 3385285242Sachim bit32 *pIomb1 3386285242Sachim ) 3387285242Sachim{ 3388285242Sachim agsaLLRoot_t *saRoot = (agsaLLRoot_t *)(agRoot->sdkData); 3389285242Sachim agsaSSPCompletionRsp_t *pIomb = (agsaSSPCompletionRsp_t *)pIomb1; 3390285242Sachim agsaIORequestDesc_t *pRequest = agNULL; 3391285242Sachim agsaSSPResponseInfoUnit_t *pRespIU = agNULL; 3392285242Sachim bit32 tag = 0; 3393285242Sachim bit32 sspTag = 0; 3394285242Sachim bit32 status, param = 0; 3395285242Sachim bit32 ret = AGSA_RC_SUCCESS; 3396285242Sachim 3397285242Sachim smTraceFuncEnter(hpDBG_VERY_LOUD, "5A"); 3398285242Sachim 3399285242Sachim /* get Tag */ 3400285242Sachim OSSA_READ_LE_32(agRoot, &tag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, tag)); 3401285242Sachim OSSA_READ_LE_32(agRoot, &status, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, status)); 3402285242Sachim OSSA_READ_LE_32(agRoot, ¶m, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, param)); 3403285242Sachim OSSA_READ_LE_32(agRoot, &sspTag, pIomb, OSSA_OFFSET_OF(agsaSSPCompletionRsp_t, SSPTag)); 3404285242Sachim /* get SSP_START IOrequest from IOMap */ 3405285242Sachim pRequest = (agsaIORequestDesc_t *)saRoot->IOMap[tag].IORequest; 3406285242Sachim SA_ASSERT((pRequest), "pRequest"); 3407285242Sachim 3408285242Sachim if(pRequest == agNULL) 3409285242Sachim { 3410285242Sachim SA_DBG1(("mpiSSPCompletion,AGSA_RC_FAILURE SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x\n", tag, status, param, sspTag)); 3411285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'a', "5A"); 3412285242Sachim return(AGSA_RC_FAILURE); 3413285242Sachim } 3414285242Sachim SA_ASSERT((pRequest->valid), "pRequest->valid"); 3415285242Sachim 3416285242Sachim if(!pRequest->valid) 3417285242Sachim { 3418285242Sachim SA_DBG1(("mpiSSPCompletion, SSP Resp IOMB tag=0x%x, status=0x%x, param=0x%x, SSPTag=0x%x Device =0x%x\n", tag, status, param, sspTag, 3419285242Sachim pRequest->pDevice ? pRequest->pDevice->DeviceMapIndex : -1)); 3420285242Sachim } 3421285242Sachim 3422285242Sachim switch (status) 3423285242Sachim { 3424285242Sachim case OSSA_IO_SUCCESS: 3425285242Sachim { 3426285242Sachim if (!param) 3427285242Sachim { 3428285242Sachim /* Completion of SSP without Response Data */ 3429285242Sachim siIODone( agRoot, pRequest, OSSA_IO_SUCCESS, sspTag); 3430285242Sachim } 3431285242Sachim else 3432285242Sachim { 3433285242Sachim /* Get SSP Response with Response Data */ 3434285242Sachim pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3435285242Sachim if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3436285242Sachim pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3437285242Sachim { 3438285242Sachim /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3439285242Sachim saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3440285242Sachim SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3441285242Sachim } 3442285242Sachim siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3443285242Sachim } 3444285242Sachim 3445285242Sachim break; 3446285242Sachim } 3447285242Sachim 3448285242Sachim case OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME: 3449285242Sachim { 3450285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3451285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME++; 3452285242Sachim /* Get SSP Response with Response Data */ 3453285242Sachim pRespIU = (agsaSSPResponseInfoUnit_t *)&(pIomb->SSPrsp); 3454285242Sachim if (pRespIU->status == 0x02 || pRespIU->status == 0x18 || 3455285242Sachim pRespIU->status == 0x30 || pRespIU->status == 0x40 ) 3456285242Sachim { 3457285242Sachim /* SCSI status is CHECK_CONDITION, RESV_CONFLICT, ACA_ACTIVE, TASK_ABORTED */ 3458285242Sachim saRoot->IoErrorCount.agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS++; 3459285242Sachim SA_DBG2(("mpiSSPCompletion: pRespIU->status 0x%x tag 0x%x\n", pRespIU->status,tag)); 3460285242Sachim } 3461285242Sachim siEventSSPResponseWtDataRcvd(agRoot, pRequest, pRespIU, param, sspTag); 3462285242Sachim 3463285242Sachim break; 3464285242Sachim } 3465285242Sachim 3466285242Sachim case OSSA_IO_ABORTED: 3467285242Sachim { 3468285242Sachim#ifdef SALL_API_TEST 3469285242Sachim saRoot->LLCounters.IOCounter.numSSPAborted++; 3470285242Sachim SA_DBG3(("mpiSSPCompletion, OSSA_IO_ABORTED Response received IOMB=%p %d\n", 3471285242Sachim pIomb1, saRoot->LLCounters.IOCounter.numSSPAborted)); 3472285242Sachim#endif 3473285242Sachim SA_DBG2(("mpiSSPCompletion, OSSA_IO_ABORTED IOMB tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3474285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORTED++; 3475285242Sachim /* SSP Abort CB */ 3476285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3477285242Sachim break; 3478285242Sachim } 3479285242Sachim case OSSA_IO_UNDERFLOW: 3480285242Sachim { 3481285242Sachim /* SSP Completion with error */ 3482285242Sachim SA_DBG2(("mpiSSPCompletion, OSSA_IO_UNDERFLOW tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3483285242Sachim /*saRoot->IoErrorCount.agOSSA_IO_UNDERFLOW++;*/ 3484285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3485285242Sachim break; 3486285242Sachim } 3487285242Sachim case OSSA_IO_NO_DEVICE: 3488285242Sachim { 3489285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_NO_DEVICE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3490285242Sachim saRoot->IoErrorCount.agOSSA_IO_NO_DEVICE++; 3491285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3492285242Sachim break; 3493285242Sachim } 3494285242Sachim case OSSA_IO_XFER_ERROR_BREAK: 3495285242Sachim { 3496285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3497285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_BREAK++; 3498285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3499285242Sachim break; 3500285242Sachim } 3501285242Sachim case OSSA_IO_XFER_ERROR_PHY_NOT_READY: 3502285242Sachim { 3503285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_PHY_NOT_READY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3504285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_PHY_NOT_READY++; 3505285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3506285242Sachim break; 3507285242Sachim } 3508285242Sachim case OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: 3509285242Sachim { 3510285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3511285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED++; 3512285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3513285242Sachim break; 3514285242Sachim } 3515285242Sachim case OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION: 3516285242Sachim { 3517285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION++; 3518285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3519285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3520285242Sachim break; 3521285242Sachim } 3522285242Sachim case OSSA_IO_OPEN_CNX_ERROR_BREAK: 3523285242Sachim { 3524285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BREAK tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3525285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BREAK++; 3526285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3527285242Sachim break; 3528285242Sachim } 3529285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 3530285242Sachim { 3531285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3532285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS++; 3533285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3534285242Sachim break; 3535285242Sachim } 3536285242Sachim case OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION: 3537285242Sachim { 3538285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3539285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION++; 3540285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3541285242Sachim break; 3542285242Sachim } 3543285242Sachim case OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 3544285242Sachim { 3545285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3546285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED++; 3547285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3548285242Sachim break; 3549285242Sachim } 3550285242Sachim case OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION: 3551285242Sachim { 3552285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3553285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION++; 3554285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3555285242Sachim break; 3556285242Sachim } 3557285242Sachim case OSSA_IO_XFER_ERROR_NAK_RECEIVED: 3558285242Sachim { 3559285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_NAK_RECEIVED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3560285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_NAK_RECEIVED++; 3561285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3562285242Sachim break; 3563285242Sachim } 3564285242Sachim case OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT: 3565285242Sachim { 3566285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3567285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT++; 3568285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3569285242Sachim break; 3570285242Sachim } 3571285242Sachim case OSSA_IO_XFER_ERROR_DMA: 3572285242Sachim { 3573285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DMA tag 0x%x ssptag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3574285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DMA++; 3575285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3576285242Sachim break; 3577285242Sachim } 3578285242Sachim case OSSA_IO_XFER_OPEN_RETRY_TIMEOUT: 3579285242Sachim { 3580285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_OPEN_RETRY_TIMEOUT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3581285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT++; 3582285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3583285242Sachim break; 3584285242Sachim } 3585285242Sachim case OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE: 3586285242Sachim { 3587285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_UNEXPECTED_PHASE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3588285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE++; 3589285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3590285242Sachim break; 3591285242Sachim } 3592285242Sachim case OSSA_IO_XFER_ERROR_OFFSET_MISMATCH: 3593285242Sachim { 3594285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_OFFSET_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3595285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH++; 3596285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3597285242Sachim break; 3598285242Sachim } 3599285242Sachim case OSSA_IO_PORT_IN_RESET: 3600285242Sachim { 3601285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_PORT_IN_RESET tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3602285242Sachim saRoot->IoErrorCount.agOSSA_IO_PORT_IN_RESET++; 3603285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3604285242Sachim break; 3605285242Sachim } 3606285242Sachim case OSSA_IO_DS_NON_OPERATIONAL: 3607285242Sachim { 3608285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_NON_OPERATIONAL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3609285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_NON_OPERATIONAL++; 3610285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3611285242Sachim break; 3612285242Sachim } 3613285242Sachim case OSSA_IO_DS_IN_RECOVERY: 3614285242Sachim { 3615285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_RECOVERY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3616285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_IN_RECOVERY++; 3617285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3618285242Sachim break; 3619285242Sachim } 3620285242Sachim case OSSA_IO_TM_TAG_NOT_FOUND: 3621285242Sachim { 3622285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_TM_TAG_NOT_FOUND tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3623285242Sachim saRoot->IoErrorCount.agOSSA_IO_TM_TAG_NOT_FOUND++; 3624285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3625285242Sachim break; 3626285242Sachim } 3627285242Sachim case OSSA_IO_XFER_PIO_SETUP_ERROR: 3628285242Sachim { 3629285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_PIO_SETUP_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3630285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_PIO_SETUP_ERROR++; 3631285242Sachim /* not allowed case. Therefore, return failed status */ 3632285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3633285242Sachim break; 3634285242Sachim } 3635285242Sachim case OSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR: 3636285242Sachim { 3637285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_SSP_IU_ZERO_LEN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3638285242Sachim saRoot->IoErrorCount.agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR++; 3639285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3640285242Sachim break; 3641285242Sachim } 3642285242Sachim case OSSA_IO_DS_IN_ERROR: 3643285242Sachim { 3644285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_IN_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3645285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_IN_ERROR++; 3646285242Sachim /* not allowed case. Therefore, return failed status */ 3647285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3648285242Sachim break; 3649285242Sachim } 3650285242Sachim case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 3651285242Sachim { 3652285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3653285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY++; 3654285242Sachim /* not allowed case. Therefore, return failed status */ 3655285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3656285242Sachim break; 3657285242Sachim } 3658285242Sachim case OSSA_IO_ABORT_IN_PROGRESS: 3659285242Sachim { 3660285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_IN_PROGRESS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3661285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORT_IN_PROGRESS++; 3662285242Sachim /* not allowed case. Therefore, return failed status */ 3663285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3664285242Sachim break; 3665285242Sachim } 3666285242Sachim case OSSA_IO_ABORT_DELAYED: 3667285242Sachim { 3668285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_ABORT_DELAYED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3669285242Sachim saRoot->IoErrorCount.agOSSA_IO_ABORT_DELAYED++; 3670285242Sachim /* not allowed case. Therefore, return failed status */ 3671285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3672285242Sachim break; 3673285242Sachim } 3674285242Sachim case OSSA_IO_INVALID_LENGTH: 3675285242Sachim { 3676285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_INVALID_LENGTH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3677285242Sachim saRoot->IoErrorCount.agOSSA_IO_INVALID_LENGTH++; 3678285242Sachim /* not allowed case. Therefore, return failed status */ 3679285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3680285242Sachim break; 3681285242Sachim } 3682285242Sachim case OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT: 3683285242Sachim { 3684285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3685285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT++; 3686285242Sachim /* not allowed case. Therefore, return failed status */ 3687285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3688285242Sachim break; 3689285242Sachim } 3690285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: 3691285242Sachim { 3692285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED HTAG = 0x%x ssptag = 0x%x\n", tag, sspTag)); 3693285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED++; 3694285242Sachim siAbnormal(agRoot, pRequest, status, 0, sspTag); 3695285242Sachim break; 3696285242Sachim } 3697285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: 3698285242Sachim { 3699285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3700285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO++; 3701285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3702285242Sachim break; 3703285242Sachim } 3704285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: 3705285242Sachim { 3706285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3707285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST++; 3708285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3709285242Sachim break; 3710285242Sachim } 3711285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: 3712285242Sachim { 3713285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3714285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE++; 3715285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3716285242Sachim break; 3717285242Sachim } 3718285242Sachim case OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: 3719285242Sachim { 3720285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3721285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED++; 3722285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3723285242Sachim break; 3724285242Sachim } 3725285242Sachim case OSSA_IO_DS_INVALID: 3726285242Sachim { 3727285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_DS_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3728285242Sachim saRoot->IoErrorCount.agOSSA_IO_DS_INVALID++; 3729285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3730285242Sachim break; 3731285242Sachim } 3732285242Sachim case OSSA_MPI_IO_RQE_BUSY_FULL: 3733285242Sachim { 3734285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_MPI_IO_RQE_BUSY_FULL tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3735285242Sachim saRoot->IoErrorCount.agOSSA_MPI_IO_RQE_BUSY_FULL++; 3736285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3737285242Sachim break; 3738285242Sachim } 3739285242Sachim case OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE: 3740285242Sachim { 3741285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3742285242Sachim saRoot->IoErrorCount.agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE++; 3743285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3744285242Sachim break; 3745285242Sachim } 3746285242Sachim case OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS: 3747285242Sachim { 3748285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3749285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS++; 3750285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3751285242Sachim break; 3752285242Sachim } 3753285242Sachim case OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH: 3754285242Sachim { 3755285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3756285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH++; 3757285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3758285242Sachim break; 3759285242Sachim } 3760285242Sachim case OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID: 3761285242Sachim { 3762285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3763285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID++; 3764285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3765285242Sachim break; 3766285242Sachim } 3767285242Sachim case OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH: 3768285242Sachim { 3769285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_IV_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3770285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH++; 3771285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3772285242Sachim break; 3773285242Sachim } 3774285242Sachim case OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR: 3775285242Sachim { 3776285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3777285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR++; 3778285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3779285242Sachim break; 3780285242Sachim } 3781285242Sachim case OSSA_IO_XFR_ERROR_INTERNAL_RAM: 3782285242Sachim { 3783285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_INTERNAL_RAM tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3784285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_INTERNAL_RAM++; 3785285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3786285242Sachim break; 3787285242Sachim } 3788285242Sachim case OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS: 3789285242Sachim { 3790285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3791285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS++; 3792285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3793285242Sachim break; 3794285242Sachim } 3795285242Sachim case OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE: 3796285242Sachim { 3797285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3798285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE++; 3799285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3800285242Sachim break; 3801285242Sachim } 3802285242Sachim#ifdef SA_TESTBASE_EXTRA 3803285242Sachim /* TestBase */ 3804285242Sachim case OSSA_IO_HOST_BST_INVALID: 3805285242Sachim { 3806285242Sachim SA_DBG1(("mpiParseOBIomb, OPC_OUB_SSP_COMP: OSSA_IO_HOST_BST_INVALID 0x%x\n", status)); 3807285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3808285242Sachim break; 3809285242Sachim } 3810285242Sachim#endif /* SA_TESTBASE_EXTRA */ 3811285242Sachim case OSSA_IO_XFR_ERROR_DIF_MISMATCH: 3812285242Sachim { 3813285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3814285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_MISMATCH++; 3815285242Sachim siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3816285242Sachim break; 3817285242Sachim } 3818285242Sachim case OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH: 3819285242Sachim { 3820285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3821285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH++; 3822285242Sachim siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3823285242Sachim break; 3824285242Sachim } 3825285242Sachim case OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH: 3826285242Sachim { 3827285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3828285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH++; 3829285242Sachim siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3830285242Sachim break; 3831285242Sachim } 3832285242Sachim case OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH: 3833285242Sachim { 3834285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3835285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH++; 3836285242Sachim siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3837285242Sachim break; 3838285242Sachim } 3839285242Sachim case OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR: 3840285242Sachim { 3841285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3842285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR++; 3843285242Sachim siDifAbnormal(agRoot, pRequest, status, param, sspTag, pIomb1); 3844285242Sachim break; 3845285242Sachim } 3846285242Sachim case OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN: 3847285242Sachim { 3848285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_XFER_ERR_EOB_DATA_OVERRUN tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3849285242Sachim saRoot->IoErrorCount.agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN++; 3850285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3851285242Sachim break; 3852285242Sachim } 3853285242Sachim case OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED: 3854285242Sachim { 3855285242Sachim SA_DBG1(("mpiSSPCompletion: OSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3856285242Sachim saRoot->IoErrorCount.agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED++; 3857285242Sachim siAbnormal(agRoot, pRequest, status, param, sspTag); 3858285242Sachim break; 3859285242Sachim } 3860285242Sachim default: 3861285242Sachim { 3862285242Sachim SA_DBG1(("mpiSSPCompletion: Unknown tag 0x%x sspTag 0x%x status 0x%x param 0x%x\n", tag,sspTag,status,param)); 3863285242Sachim /* not allowed case. Therefore, return failed status */ 3864285242Sachim saRoot->IoErrorCount.agOSSA_IO_UNKNOWN_ERROR++; 3865285242Sachim siAbnormal(agRoot, pRequest, OSSA_IO_FAILED, param, sspTag); 3866285242Sachim break; 3867285242Sachim } 3868285242Sachim } 3869285242Sachim 3870285242Sachim smTraceFuncExit(hpDBG_VERY_LOUD, 'b', "5A"); 3871285242Sachim return ret; 3872285242Sachim} 3873