pdqreg.h revision 67899
1/*- 2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the author may not be used to endorse or promote products 11 * derived from this software withough specific prior written permission 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * $FreeBSD: head/sys/dev/pdq/pdqreg.h 67899 2000-10-29 16:57:42Z phk $ 25 * 26 */ 27 28/* 29 * DEC PDQ FDDI Controller; PDQ port driver definitions 30 * 31 */ 32 33#ifndef _PDQREG_H 34#define _PDQREG_H 35 36#if defined(PDQTEST) && !defined(PDQ_NDEBUG) 37#include <assert.h> 38#define PDQ_ASSERT assert 39#else 40#define PDQ_ASSERT(x) do { } while(0) 41#endif 42 43#define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 44#define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 45#define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1) 46#define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n)) 47 48#define PDQ_FDDI_MAX 4495 49#define PDQ_FDDI_LLC_MIN 20 50#define PDQ_FDDI_SMT_MIN 37 51 52#define PDQ_FDDI_SMT 0x40 53#define PDQ_FDDI_LLC_ASYNC 0x50 54#define PDQ_FDDI_LLC_SYNC 0xD0 55#define PDQ_FDDI_IMP_ASYNC 0x60 56#define PDQ_FDDI_IMP_SYNC 0xE0 57 58#define PDQ_FDDIFC_C 0x80 59#define PDQ_FDDIFC_L 0x40 60#define PDQ_FDDIFC_F 0x30 61#define PDQ_FDDIFC_Z 0x0F 62 63#define PDQ_FDDI_PH0 0x20 64#define PDQ_FDDI_PH1 0x38 65#define PDQ_FDDI_PH2 0x00 66 67typedef pdq_uint32_t pdq_physaddr_t; 68 69struct _pdq_lanaddr_t { 70 pdq_uint8_t lanaddr_bytes[8]; 71}; 72 73typedef struct { 74 pdq_uint8_t fwrev_bytes[4]; 75} pdq_fwrev_t; 76 77enum _pdq_state_t { 78 PDQS_RESET=0, 79 PDQS_UPGRADE=1, 80 PDQS_DMA_UNAVAILABLE=2, 81 PDQS_DMA_AVAILABLE=3, 82 PDQS_LINK_AVAILABLE=4, 83 PDQS_LINK_UNAVAILABLE=5, 84 PDQS_HALTED=6, 85 PDQS_RING_MEMBER=7 86}; 87 88struct _pdq_csrs_t { 89 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */ 90 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */ 91 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */ 92 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */ 93 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */ 94 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */ 95 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */ 96 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */ 97 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */ 98 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */ 99 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */ 100 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */ 101 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */ 102 pdq_bus_t csr_bus; 103 pdq_bus_memaddr_t csr_base; 104}; 105 106struct _pdq_pci_csrs_t { 107 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */ 108 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */ 109 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */ 110 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */ 111 pdq_bus_t csr_bus; 112 pdq_bus_memaddr_t csr_base; 113}; 114 115#define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */ 116#define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */ 117#define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */ 118 119#define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */ 120#define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */ 121 122#define PDQ_EISA_BURST_HOLDOFF 0x0040 123#define PDQ_EISA_SLOT_ID 0x0C80 124#define PDQ_EISA_SLOT_CTRL 0x0C84 125#define PDQ_EISA_MEM_ADD_CMP_0 0x0C85 126#define PDQ_EISA_MEM_ADD_CMP_1 0x0C86 127#define PDQ_EISA_MEM_ADD_CMP_2 0x0C87 128#define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88 129#define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89 130#define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A 131#define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B 132#define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C 133#define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D 134#define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E 135#define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F 136#define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90 137#define PDQ_EISA_IO_CMP_0_0 0x0C91 138#define PDQ_EISA_IO_CMP_0_1 0x0C92 139#define PDQ_EISA_IO_CMP_1_0 0x0C93 140#define PDQ_EISA_IO_CMP_1_1 0x0C94 141#define PDQ_EISA_IO_CMP_2_0 0x0C95 142#define PDQ_EISA_IO_CMP_2_1 0x0C96 143#define PDQ_EISA_IO_CMP_3_0 0x0C97 144#define PDQ_EISA_IO_CMP_3_1 0x0C98 145#define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99 146#define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A 147#define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B 148#define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C 149#define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D 150#define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E 151#define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F 152#define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0 153#define PDQ_EISA_MOD_CONFIG_1 0x0CA1 154#define PDQ_EISA_MOD_CONFIG_2 0x0CA2 155#define PDQ_EISA_MOD_CONFIG_3 0x0CA3 156#define PDQ_EISA_MOD_CONFIG_4 0x0CA4 157#define PDQ_EISA_MOD_CONFIG_5 0x0CA5 158#define PDQ_EISA_MOD_CONFIG_6 0x0CA6 159#define PDQ_EISA_MOD_CONFIG_7 0x0CA7 160#define PDQ_EISA_DIP_SWITCH 0x0CA8 161#define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9 162#define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA 163#define PDQ_EISA_DMA_CONFIG 0x0CAB 164#define PDQ_EISA_INPUT_PORT 0x0CAC 165#define PDQ_EISA_OUTPUT_PORT 0x0CAD 166#define PDQ_EISA_FUNCTION_CTRL 0x0CAE 167 168#define PDQ_TC_CSR_OFFSET 0x00100000 169#define PDQ_TC_CSR_SPACE 0x0040 170#define PDQ_FBUS_CSR_OFFSET 0x00200000 171#define PDQ_FBUS_CSR_SPACE 0x0080 172 173/* 174 * Port Reset Data A Definitions 175 */ 176#define PDQ_PRESET_SKIP_SELFTEST 0x0004 177#define PDQ_PRESET_SOFT_RESET 0x0002 178#define PDQ_PRESET_UPGRADE 0x0001 179/* 180 * Port Control Register Definitions 181 */ 182#define PDQ_PCTL_CMD_ERROR 0x8000 183#define PDQ_PCTL_FLASH_BLAST 0x4000 184#define PDQ_PCTL_HALT 0x2000 185#define PDQ_PCTL_COPY_DATA 0x1000 186#define PDQ_PCTL_ERROR_LOG_START 0x0800 187#define PDQ_PCTL_ERROR_LOG_READ 0x0400 188#define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200 189#define PDQ_PCTL_DMA_INIT 0x0100 190#define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02 191#define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01 192#define PDQ_PCTL_INIT_START 0x0080 193#define PDQ_PCTL_CONSUMER_BLOCK 0x0040 194#define PDQ_PCTL_DMA_UNINIT 0x0020 195#define PDQ_PCTL_RING_MEMBER 0x0010 196#define PDQ_PCTL_MLA_READ 0x0008 197#define PDQ_PCTL_FW_REV_READ 0x0004 198#define PDQ_PCTL_DEVICE_SPECIFIC 0x0002 199#define PDQ_PCTL_SUB_CMD 0x0001 200 201typedef enum { 202 PDQ_SUB_CMD_LINK_UNINIT=1, 203 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2, 204 PDQ_SUB_CMD_PDQ_REV_GET=4 205} pdq_sub_cmd_t; 206 207typedef enum { 208 PDQ_DMA_BURST_4LW=0, 209 PDQ_DMA_BURST_8LW=1, 210 PDQ_DMA_BURST_16LW=2, 211 PDQ_DMA_BURST_32LW=3 212} pdq_dma_burst_size_t; 213 214typedef enum { 215 PDQ_CHIP_REV_A_B_OR_C=0, 216 PDQ_CHIP_REV_D=2, 217 PDQ_CHIP_REV_E=4 218} pdq_chip_rev_t; 219/* 220 * Port Status Register Definitions 221 */ 222#define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul 223#define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul 224#define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul 225#define PDQ_PSTS_UNSOL_PENDING 0x10000000ul 226#define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul 227#define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul 228#define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul 229#define PDQ_PSTS_INTR_PENDING 0xFE000000ul 230#define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07)) 231#define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF)) 232/* 233 * Host Interrupt Register Definitions 234 */ 235#define PDQ_HOST_INT_TX_ENABLE 0x80000000ul 236#define PDQ_HOST_INT_RX_ENABLE 0x40000000ul 237#define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul 238#define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul 239#define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul 240#define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul 241 242#define PDQ_HOST_INT_1MS 0x80 243#define PDQ_HOST_INT_20MS 0x40 244#define PDQ_HOST_INT_CSR_CMD_DONE 0x20 245#define PDQ_HOST_INT_STATE_CHANGE 0x10 246#define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08 247#define PDQ_HOST_INT_NXM 0x04 248#define PDQ_HOST_INT_PM_PARITY_ERROR 0x02 249#define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01 250#define PDQ_HOST_INT_FATAL_ERROR 0x07 251 252typedef enum { 253 PDQH_SELFTEST_TIMEOUT=0, 254 PDQH_HOST_BUS_PARITY_ERROR=1, 255 PDQH_HOST_DIRECTED_HALT=2, 256 PDQH_SOFTWARE_FAULT=3, 257 PDQH_HARDWARE_FAULT=4, 258 PDQH_PC_TRACE_PATH_TEST=5, 259 PDQH_DMA_ERROR=6, 260 PDQH_IMAGE_CRC_ERROR=7, 261 PDQH_ADAPTER_PROCESSOR_ERROR=8, 262 PDQH_MAX=9 263} pdq_halt_code_t; 264 265typedef struct { 266 pdq_uint16_t pdqcb_receives; 267 pdq_uint16_t pdqcb_transmits; 268 pdq_uint32_t pdqcb__filler1; 269 pdq_uint32_t pdqcb_host_smt; 270 pdq_uint32_t pdqcb__filler2; 271 pdq_uint32_t pdqcb_unsolicited_event; 272 pdq_uint32_t pdqcb__filler3; 273 pdq_uint32_t pdqcb_command_response; 274 pdq_uint32_t pdqcb__filler4; 275 pdq_uint32_t pdqcb_command_request; 276 pdq_uint32_t pdqcb__filler5[7]; 277} pdq_consumer_block_t; 278 279#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 280#define PDQ_BITFIELD2(a, b) b, a 281#define PDQ_BITFIELD3(a, b, c) c, b, a 282#define PDQ_BITFIELD4(a, b, c, d) d, c, b, a 283#define PDQ_BITFIELD5(a, b, c, d, e) e, d, c, b, a 284#define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \ 285 l, k, j, i, h, g, f, e, d, c, b, a 286#else 287#define PDQ_BITFIELD2(a, b) a, b 288#define PDQ_BITFIELD3(a, b, c) a, b, c 289#define PDQ_BITFIELD4(a, b, c, d) a, b, c, d 290#define PDQ_BITFIELD5(a, b, c, d, e) a, b, c, d, e 291#define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \ 292 a, b, c, d, e, f, g, h, i, j, k, l 293#endif 294 295typedef struct { 296 pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16, 297 rxd_seg_cnt : 4, 298 rxd_seg_len_hi : 9, 299 rxd_seg_len_lo : 2, 300 rxd_sop : 1); 301 pdq_uint32_t rxd_pa_lo; 302} pdq_rxdesc_t; 303 304typedef union { 305 pdq_uint32_t rxs_status; 306 pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13, 307 rxs_rcc_ss : 2, 308 rxs_rcc_dd : 2, 309 rxs_rcc_reason : 3, 310 rxs_rcc_badcrc : 1, 311 rxs_rcc_badpdu : 1, 312 rxs_fsb__reserved : 2, 313 rxs_fsb_c : 1, 314 rxs_fsb_a : 1, 315 rxs_fsb_e : 1, 316 rxs_fsc : 3, 317 rxs__reserved : 2); 318} pdq_rxstatus_t; 319 320typedef struct { 321 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16, 322 txd_seg_len : 13, 323 txd_mbz : 1, 324 txd_eop : 1, 325 txd_sop : 1); 326 pdq_uint32_t txd_pa_lo; 327} pdq_txdesc_t; 328 329typedef struct { 330 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */ 331 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */ 332 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */ 333 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */ 334 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */ 335 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */ 336 /* 337 * The rest of the descriptor block is unused. 338 * As such we could use it for other things. 339 */ 340 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x1380..0x13BF */ 341 void *pdqdb_receive_buffers[256]; /* 1024/2048; 0x13C0..0x17BF 0x13C0..0x1BBF */ 342 void *pdqdb_host_smt_buffers[64]; /* 256/ 512; 0x17C0..0x18BF 0x1BC0..0x1DBF */ 343 /* 344 * The maximum command size is 512 so as long as thes 345 * command is at least that long all will be fine. 346 */ 347#if defined(__alpha) || defined(__alpha__) 348 pdq_uint32_t pdqdb_command_pool[144]; 349#else 350 pdq_uint32_t pdqdb_command_pool[464]; 351#endif 352} pdq_descriptor_block_t; 353 354typedef struct { 355 /* 356 * These value manage the available space in command/response 357 * buffer area. 358 */ 359 pdq_physaddr_t ci_pa_bufstart; 360 pdq_uint8_t *ci_bufstart; 361 /* 362 * Bitmask of commands to sent to the PDQ 363 */ 364 pdq_uint32_t ci_pending_commands; 365 /* 366 * Variables to maintain the PDQ queues. 367 */ 368 pdq_uint32_t ci_command_active; 369 pdq_uint32_t ci_request_producer; 370 pdq_uint32_t ci_response_producer; 371 pdq_uint32_t ci_request_completion; 372 pdq_uint32_t ci_response_completion; 373} pdq_command_info_t; 374 375#define PDQ_SIZE_UNSOLICITED_EVENT 512 376#define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT) 377 378typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t; 379 380typedef struct { 381 pdq_physaddr_t ui_pa_bufstart; 382 pdq_unsolicited_event_t *ui_events; 383 384 pdq_uint32_t ui_free; 385 pdq_uint32_t ui_producer; 386 pdq_uint32_t ui_completion; 387} pdq_unsolicited_info_t; 388 389#define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3) 390#define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE) 391#define PDQ_DO_TYPE2_PRODUCER(pdq) \ 392 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \ 393 ((pdq)->pdq_rx_info.rx_producer << 0) \ 394 | ((pdq)->pdq_tx_info.tx_producer << 8) \ 395 | ((pdq)->pdq_rx_info.rx_completion << 16) \ 396 | ((pdq)->pdq_tx_info.tx_completion << 24)) 397 398#define PDQ_DO_HOST_SMT_PRODUCER(pdq) \ 399 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \ 400 ((pdq)->pdq_host_smt_info.rx_producer << 0) \ 401 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\ 402 403#define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m)) 404 405typedef struct { 406 void *q_head; 407 void *q_tail; 408} pdq_databuf_queue_t; 409 410typedef struct { 411 void *rx_buffers; 412 413 pdq_uint32_t rx_target; 414 pdq_uint32_t rx_free; 415 pdq_uint32_t rx_producer; 416 pdq_uint32_t rx_completion; 417} pdq_rx_info_t; 418 419typedef struct { 420 pdq_databuf_queue_t tx_txq; 421 pdq_txdesc_t tx_hdrdesc; 422 pdq_uint8_t tx_descriptor_count[256]; 423 424 pdq_uint32_t tx_free; 425 pdq_uint32_t tx_producer; 426 pdq_uint32_t tx_completion; 427} pdq_tx_info_t; 428 429struct _pdq_t { 430 pdq_csrs_t pdq_csrs; 431 pdq_pci_csrs_t pdq_pci_csrs; 432 pdq_type_t pdq_type; 433 pdq_chip_rev_t pdq_chip_rev; 434 pdq_lanaddr_t pdq_hwaddr; 435 pdq_fwrev_t pdq_fwrev; 436 pdq_descriptor_block_t *pdq_dbp; 437 volatile pdq_consumer_block_t *pdq_cbp; 438 pdq_uint32_t pdq_flags; 439#define PDQ_PROMISC 0x0001 440#define PDQ_ALLMULTI 0x0002 441#define PDQ_PASS_SMT 0x0004 442#define PDQ_RUNNING 0x0008 443#define PDQ_PRINTCHARS 0x0010 444#define PDQ_TXOK 0x0020 445 const char *pdq_os_name; 446 void *pdq_os_ctx; 447 pdq_uint32_t pdq_unit; 448 pdq_command_info_t pdq_command_info; 449 pdq_unsolicited_info_t pdq_unsolicited_info; 450 pdq_tx_info_t pdq_tx_info; 451 pdq_rx_info_t pdq_rx_info; 452 pdq_rx_info_t pdq_host_smt_info; 453 pdq_uint8_t pdq_tx_hdr[3]; 454}; 455 456typedef enum { 457 PDQC_START=0, 458 PDQC_FILTER_SET=1, 459 PDQC_FILTER_GET=2, 460 PDQC_CHARS_SET=3, 461 PDQC_STATUS_CHARS_GET=4, 462 PDQC_COUNTERS_GET=5, 463 PDQC_COUNTERS_SET=6, 464 PDQC_ADDR_FILTER_SET=7, 465 PDQC_ADDR_FILTER_GET=8, 466 PDQC_ERROR_LOG_CLEAR=9, 467 PDQC_ERROR_LOG_GET=10, 468 PDQC_FDDI_MIB_GET=11, 469 PDQC_DEC_EXT_MIB_GET=12, 470 PDQC_DEV_SPECIFIC_GET=13, 471 PDQC_SNMP_SET=14, 472 PDQC_SMT_MIB_GET=16, 473 PDQC_SMT_MIB_SET=17 474} pdq_cmd_code_t; 475 476typedef enum { 477 PDQR_SUCCESS=0, 478 PDQR_FAILURE=1, 479 PDQR_WARNING=2, 480 PDQR_LOOP_MODE_BAD=3, 481 PDQR_ITEM_CODE_BAD=4, 482 PDQR_TVX_BAD=5, 483 PDQR_TREQ_BAD=6, 484 PDQR_RESTRICTED_TOKEN_BAD=7, 485 PDQR_NO_EOL=12, 486 PDQR_FILTER_STATE_BAD=13, 487 PDQR_CMD_TYPE_BAD=14, 488 PDQR_ADAPTER_STATE_BAD=15, 489 PDQR_RING_PURGER_BAD=16, 490 PDQR_LEM_THRESHOLD_BAD=17, 491 PDQR_LOOP_NOT_SUPPORTED=18, 492 PDQR_FLUSH_TIME_BAD=19, 493 PDQR_NOT_YET_IMPLEMENTED=20, 494 PDQR_CONFIG_POLICY_BAD=21, 495 PDQR_STATION_ACTION_BAD=22, 496 PDQR_MAC_ACTION_BAD=23, 497 PDQR_CON_POLICIES_BAD=24, 498 PDQR_MAC_LOOP_TIME_BAD=25, 499 PDQR_TB_MAX_BAD=26, 500 PDQR_LER_CUTOFF_BAD=27, 501 PDQR_LER_ALARM_BAD=28, 502 PDQR_MAC_PATHS_REQ_BAD=29, 503 PDQR_MAC_T_REQ_BAD=30, 504 PDQR_EMAC_RING_PURGER_BAD=31, 505 PDQR_EMAC_RTOKEN_TIMOUT_AD=32, 506 PDQR_NO_SUCH_ENTRY=33, 507 PDQR_T_NOTIFY_BAD=34, 508 PDQR_TR_MAX_EXP_BAD=35, 509 PDQR_FRAME_ERR_THRESHOLD_BAD=36, 510 PDQR_MAX_TREQ_BAD=37, 511 PDQR_FULL_DUPLEX_ENABLE_BAD=38, 512 PDQR_ITEM_INDEX_BAD=39 513} pdq_response_code_t; 514 515typedef enum { 516 PDQI_EOL=0, 517 PDQI_T_REQ=1, 518 PDQI_TVX=2, 519 PDQI_RESTRICTED_TOKEN=3, 520 PDQI_LEM_THRESHOLD=4, 521 PDQI_RING_PURGER=5, 522 PDQI_COUNTER_INTERVAL=6, 523 PDQI_IND_GROUP_PROM=7, 524 PDQI_GROUP_PROM=8, 525 PDQI_BROADCAST=9, 526 PDQI_SMT_PROM=10, 527 PDQI_SMT_USER=11, 528 PDQI_RESERVED=12, 529 PDQI_IMPLEMENTOR=13, 530 PDQI_LOOPBACK_MODE=14, 531 PDQI_SMT_CONFIG_POLICY=16, 532 PDQI_SMT_CONNECTION_POLICY=17, 533 PDQI_SMT_T_NOTIFY=18, 534 PDQI_SMT_STATION_ACTION=19, 535 PDQI_MAC_PATHS_REQUESTED=21, 536 PDQI_MAC_ACTION=23, 537 PDQI_PORT_CONNECTION_POLICIES=24, 538 PDQI_PORT_PATHS_REQUESTED=25, 539 PDQI_PORT_MAC_LOOP_TIME=26, 540 PDQI_PORT_TB_MAX=27, 541 PDQI_PORT_LER_CUTOFF=28, 542 PDQI_PORT_LER_ALARM=29, 543 PDQI_PORT_ACTION=30, 544 PDQI_FLUSH_TIME=32, 545 PDQI_SMT_USER_DATA=33, 546 PDQI_SMT_STATUS_REPORT_POLICY=34, 547 PDQI_SMT_TRACE_MAX_EXPIRATION=35, 548 PDQI_MAC_FRAME_ERR_THRESHOLD=36, 549 PDQI_MAC_UNIT_DATA_ENABLE=37, 550 PDQI_PATH_TVX_LOWER_BOUND=38, 551 PDQI_PATH_TMAX_LOWER_BOUND=39, 552 PDQI_PATH_MAX_TREQ=40, 553 PDQI_MAC_TREQ=41, 554 PDQI_EMAC_RING_PURGER=42, 555 PDQI_EMAC_RTOKEN_TIMEOUT=43, 556 PDQI_FULL_DUPLEX_ENABLE=44 557} pdq_item_code_t; 558 559enum _pdq_boolean_t { 560 PDQ_FALSE=0, 561 PDQ_TRUE=1 562}; 563 564typedef enum { 565 PDQ_FILTER_BLOCK=0, 566 PDQ_FILTER_PASS=1 567} pdq_filter_state_t; 568 569typedef enum { 570 PDQ_STATION_TYPE_SAS=0, 571 PDQ_STATION_TYPE_DAC=1, 572 PDQ_STATION_TYPE_SAC=2, 573 PDQ_STATION_TYPE_NAC=3, 574 PDQ_STATION_TYPE_DAS=4 575} pdq_station_type_t; 576 577typedef enum { 578 PDQ_STATION_STATE_OFF=0, 579 PDQ_STATION_STATE_ON=1, 580 PDQ_STATION_STATE_LOOPBACK=2 581} pdq_station_state_t; 582 583typedef enum { 584 PDQ_LINK_STATE_OFF_READY=1, 585 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2, 586 PDQ_LINK_STATE_ON_RING_INIT=3, 587 PDQ_LINK_STATE_ON_RING_RUN=4, 588 PDQ_LINK_STATE_BROKEN=5 589} pdq_link_state_t; 590 591typedef enum { 592 PDQ_DA_TEST_STATE_UNKNOWN=0, 593 PDQ_DA_TEST_STATE_SUCCESS=1, 594 PDQ_DA_TEST_STATE_DUPLICATE=2 595} pdq_da_test_state_t; 596 597typedef enum { 598 PDQ_RING_PURGER_STATE_OFF=0, 599 PDQ_RING_PURGER_STATE_CANDIDATE=1, 600 PDQ_RING_PURGER_STATE_NON_PURGER=2, 601 PDQ_RING_PURGER_STATE_PURGER=3 602} pdq_ring_purger_state_t; 603 604typedef enum { 605 PDQ_FRAME_STRING_MODE_SA_MATCH=0, 606 PDQ_FRAME_STRING_MODE_FCI_STRIP=1 607} pdq_frame_strip_mode_t; 608 609typedef enum { 610 PDQ_RING_ERROR_REASON_NO_ERROR=0, 611 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5, 612 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6, 613 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7, 614 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8, 615 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9, 616 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10, 617 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11, 618 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12, 619 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13, 620 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14, 621 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15 622} pdq_ring_error_reason_t; 623 624typedef enum { 625 PDQ_STATION_MODE_NORMAL=0, 626 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1 627} pdq_station_mode_t; 628 629typedef enum { 630 PDQ_PHY_TYPE_A=0, 631 PDQ_PHY_TYPE_B=1, 632 PDQ_PHY_TYPE_S=2, 633 PDQ_PHY_TYPE_M=3, 634 PDQ_PHY_TYPE_UNKNOWN=4 635} pdq_phy_type_t; 636 637typedef enum { 638 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0, 639 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1, 640 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2, 641 PDQ_PMD_TYPE_ANSI_SONET=3, 642 PDQ_PMD_TYPE_LOW_POWER=100, 643 PDQ_PMD_TYPE_THINWIRE=101, 644 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102, 645 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103 646} pdq_pmd_type_t; 647 648typedef enum { 649 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0, 650 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1, 651 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2, 652 PDQ_PMD_CLASS_SONET=3, 653 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4, 654 PDQ_PMD_CLASS_TWISTED_PAIR=5, 655 PDQ_PMD_CLASS_UNKNOWN=6, 656 PDQ_PMD_CLASS_UNSPECIFIED=7 657} pdq_pmd_class_t; 658 659typedef enum { 660 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0, 661 PDQ_PHY_STATE_BROKEN=1, 662 PDQ_PHY_STATE_OFF_READY=2, 663 PDQ_PHY_STATE_WAITING=3, 664 PDQ_PHY_STATE_STARTING=4, 665 PDQ_PHY_STATE_FAILED=5, 666 PDQ_PHY_STATE_WATCH=6, 667 PDQ_PHY_STATE_INUSE=7 668} pdq_phy_state_t; 669 670typedef enum { 671 PDQ_REJECT_REASON_NONE=0, 672 PDQ_REJECT_REASON_LOCAL_LCT=1, 673 PDQ_REJECT_REASON_REMOTE_LCT=2, 674 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3, 675 PDQ_REJECT_REASON_LEM_REJECT=4, 676 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5, 677 PDQ_REJECT_REASON_NOISE_REJECT=6, 678 PDQ_REJECT_REASON_REMOTE_REJECT=7, 679 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8, 680 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9, 681 PDQ_REJECT_REASON_STANDBY=10, 682 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11 683} pdq_reject_reason_t; 684 685typedef enum { 686 PDQ_BROKEN_REASON_NONE=0 687} pdq_broken_reason_t; 688 689typedef enum { 690 PDQ_RI_REASON_TVX_EXPIRED=0, 691 PDQ_RI_REASON_TRT_EXPIRED=1, 692 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2, 693 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3, 694 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4 695} pdq_ri_reason_t; 696 697typedef enum { 698 PDQ_LCT_DIRECTION_LOCAL_LCT=0, 699 PDQ_LCT_DIRECTION_REMOTE_LCT=1, 700 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2 701} pdq_lct_direction_t; 702 703typedef enum { 704 PDQ_PORT_A=0, 705 PDQ_PORT_B=1 706} pdq_port_type_t; 707 708typedef struct { 709 pdq_uint8_t station_id_bytes[8]; 710} pdq_station_id_t; 711 712typedef pdq_uint32_t pdq_fdditimer_t; 713/* 714 * Command format for Start, Filter_Get, ... commands 715 */ 716typedef struct { 717 pdq_cmd_code_t generic_op; 718} pdq_cmd_generic_t; 719 720/* 721 * Response format for Start, Filter_Set, ... commands 722 */ 723typedef struct { 724 pdq_uint32_t generic_reserved; 725 pdq_cmd_code_t generic_op; 726 pdq_response_code_t generic_status; 727} pdq_response_generic_t; 728 729/* 730 * Command format for Filter_Set command 731 */ 732typedef struct { 733 pdq_cmd_code_t filter_set_op; 734 struct { 735 pdq_item_code_t item_code; 736 pdq_filter_state_t filter_state; 737 } filter_set_items[7]; 738 pdq_item_code_t filter_set_eol_item_code; 739} pdq_cmd_filter_set_t; 740 741/* 742 * Response format for Filter_Get command. 743 */ 744typedef struct { 745 pdq_uint32_t filter_get_reserved; 746 pdq_cmd_code_t filter_get_op; 747 pdq_response_code_t filter_get_status; 748 pdq_filter_state_t filter_get_ind_group_prom; 749 pdq_filter_state_t filter_get_group_prom; 750 pdq_filter_state_t filter_get_broadcast_all; 751 pdq_filter_state_t filter_get_smt_prom; 752 pdq_filter_state_t filter_get_smt_user; 753 pdq_filter_state_t filter_get_reserved_all; 754 pdq_filter_state_t filter_get_implementor_all; 755} pdq_response_filter_get_t; 756 757#define PDQ_SIZE_RESPONSE_FILTER_GET 0x28 758 759typedef struct { 760 pdq_cmd_code_t chars_set_op; 761 struct { 762 pdq_item_code_t item_code; 763 pdq_uint32_t item_value; 764 pdq_port_type_t item_port; 765 } chars_set_items[1]; 766 pdq_item_code_t chars_set_eol_item_code; 767} pdq_cmd_chars_set_t; 768 769typedef struct { 770 pdq_cmd_code_t addr_filter_set_op; 771 pdq_lanaddr_t addr_filter_set_addresses[62]; 772} pdq_cmd_addr_filter_set_t; 773 774#define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4 775 776typedef struct { 777 pdq_uint32_t addr_filter_get_reserved; 778 pdq_cmd_code_t addr_filter_get_op; 779 pdq_response_code_t addr_filter_get_status; 780 pdq_lanaddr_t addr_filter_get_addresses[62]; 781} pdq_response_addr_filter_get_t; 782 783#define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC 784 785typedef struct { 786 pdq_uint32_t status_chars_get_reserved; 787 pdq_cmd_code_t status_chars_get_op; 788 pdq_response_code_t status_chars_get_status; 789 struct { 790 /* Station Characteristic Attributes */ 791 pdq_station_id_t station_id; 792 pdq_station_type_t station_type; 793 pdq_uint32_t smt_version_id; 794 pdq_uint32_t smt_max_version_id; 795 pdq_uint32_t smt_min_version_id; 796 /* Station Status Attributes */ 797 pdq_station_state_t station_state; 798 /* Link Characteristic Attributes */ 799 pdq_lanaddr_t link_address; 800 pdq_fdditimer_t t_req; 801 pdq_fdditimer_t tvx; 802 pdq_fdditimer_t restricted_token_timeout; 803 pdq_boolean_t ring_purger_enable; 804 pdq_link_state_t link_state; 805 pdq_fdditimer_t negotiated_trt; 806 pdq_da_test_state_t dup_addr_flag; 807 /* Link Status Attributes */ 808 pdq_lanaddr_t upstream_neighbor; 809 pdq_lanaddr_t old_upstream_neighbor; 810 pdq_boolean_t upstream_neighbor_dup_addr_flag; 811 pdq_lanaddr_t downstream_neighbor; 812 pdq_lanaddr_t old_downstream_neighbor; 813 pdq_ring_purger_state_t ring_purger_state; 814 pdq_frame_strip_mode_t frame_strip_mode; 815 pdq_ring_error_reason_t ring_error_reason; 816 pdq_boolean_t loopback; 817 pdq_fdditimer_t ring_latency; 818 pdq_lanaddr_t last_dir_beacon_sa; 819 pdq_lanaddr_t last_dir_beacon_una; 820 /* Phy Characteristic Attributes */ 821 pdq_phy_type_t phy_type[2]; 822 pdq_pmd_type_t pmd_type[2]; 823 pdq_uint32_t lem_threshold[2]; 824 /* Phy Status Attributes */ 825 pdq_phy_state_t phy_state[2]; 826 pdq_phy_type_t neighbor_phy_type[2]; 827 pdq_uint32_t link_error_estimate[2]; 828 pdq_broken_reason_t broken_reason[2]; 829 pdq_reject_reason_t reject_reason[2]; 830 /* Miscellaneous */ 831 pdq_uint32_t counter_interval; 832 pdq_fwrev_t module_rev; 833 pdq_fwrev_t firmware_rev; 834 pdq_uint32_t mop_device_type; 835 pdq_uint32_t fddi_led[2]; 836 pdq_uint32_t flush; 837 } status_chars_get; 838} pdq_response_status_chars_get_t; 839 840#define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0 841 842typedef struct { 843 pdq_uint32_t fddi_mib_get_reserved; 844 pdq_cmd_code_t fddi_mib_get_op; 845 pdq_response_code_t fddi_mib_get_status; 846 struct { 847 /* SMT Objects */ 848 pdq_station_id_t smt_station_id; 849 pdq_uint32_t smt_op_version_id; 850 pdq_uint32_t smt_hi_version_id; 851 pdq_uint32_t smt_lo_version_id; 852 pdq_uint32_t smt_mac_ct; 853 pdq_uint32_t smt_non_master_ct; 854 pdq_uint32_t smt_master_ct; 855 pdq_uint32_t smt_paths_available; 856 pdq_uint32_t smt_config_capabilities; 857 pdq_uint32_t smt_config_policy; 858 pdq_uint32_t smt_connection_policy; 859 pdq_uint32_t smt_t_notify; 860 pdq_uint32_t smt_status_reporting; 861 pdq_uint32_t smt_ecm_state; 862 pdq_uint32_t smt_cf_state; 863 pdq_uint32_t smt_hold_state; 864 pdq_uint32_t smt_remote_disconnect_flag; 865 pdq_uint32_t smt_station_action; 866 /* MAC Objects */ 867 pdq_uint32_t mac_frame_status_capabilities; 868 pdq_uint32_t mac_t_max_greatest_lower_bound; 869 pdq_uint32_t mac_tvx_greatest_lower_bound; 870 pdq_uint32_t mac_paths_available; 871 pdq_uint32_t mac_current_path; 872 pdq_lanaddr_t mac_upstream_neighbor; 873 pdq_lanaddr_t mac_old_upstream_neighbor; 874 pdq_uint32_t mac_dup_addr_test; 875 pdq_uint32_t mac_paths_requested; 876 pdq_uint32_t mac_downstream_port_type; 877 pdq_lanaddr_t mac_smt_address; 878 pdq_uint32_t mac_t_req; 879 pdq_uint32_t mac_t_neg; 880 pdq_uint32_t mac_t_max; 881 pdq_uint32_t mac_tvx_value; 882 pdq_uint32_t mac_t_min; 883 pdq_uint32_t mac_current_frame_status; 884 pdq_uint32_t mac_frame_error_threshold; 885 pdq_uint32_t mac_frame_error_ratio; 886 pdq_uint32_t mac_rmt_state; 887 pdq_uint32_t mac_da_flag; 888 pdq_uint32_t mac_una_da_flag; 889 pdq_uint32_t mac_frame_condition; 890 pdq_uint32_t mac_chip_set; 891 pdq_uint32_t mac_action; 892 /* Port Objects */ 893 pdq_uint32_t port_pc_type[2]; 894 pdq_uint32_t port_pc_neighbor[2]; 895 pdq_uint32_t port_connection_policies[2]; 896 pdq_uint32_t port_remote_mac_indicated[2]; 897 pdq_uint32_t port_ce_state[2]; 898 pdq_uint32_t port_paths_requested[2]; 899 pdq_uint32_t port_mac_placement[2]; 900 pdq_uint32_t port_available_paths[2]; 901 pdq_uint32_t port_mac_loop_time[2]; 902 pdq_uint32_t port_tb_max[2]; 903 pdq_uint32_t port_bs_flag[2]; 904 pdq_uint32_t port_ler_estimate[2]; 905 pdq_uint32_t port_ler_cutoff[2]; 906 pdq_uint32_t port_ler_alarm[2]; 907 pdq_uint32_t port_connect_state[2]; 908 pdq_uint32_t port_pcm_state[2]; 909 pdq_uint32_t port_pc_withhold[2]; 910 pdq_uint32_t port_ler_condition[2]; 911 pdq_uint32_t port_chip_set[2]; 912 pdq_uint32_t port_action[2]; 913 /* Attachment Objects */ 914 pdq_uint32_t attachment_class; 915 pdq_uint32_t attachment_optical_bypass_present; 916 pdq_uint32_t attachment_imax_expiration; 917 pdq_uint32_t attachment_inserted_status; 918 pdq_uint32_t attachment_insert_policy; 919 } fddi_mib_get; 920} pdq_response_fddi_mib_get_t; 921 922#define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C 923 924typedef enum { 925 PDQ_FDX_STATE_IDLE=0, 926 PDQ_FDX_STATE_REQUEST=1, 927 PDQ_FDX_STATE_CONFIRM=2, 928 PDQ_FDX_STATE_OPERATION=3 929} pdq_fdx_state_t; 930 931typedef struct { 932 pdq_uint32_t dec_ext_mib_get_reserved; 933 pdq_cmd_code_t dec_ext_mib_get_op; 934 pdq_response_code_t dec_ext_mib_get_response; 935 struct { 936 /* SMT Objects */ 937 pdq_uint32_t esmt_station_type; 938 /* MAC Objects */ 939 pdq_uint32_t emac_link_state; 940 pdq_uint32_t emac_ring_purger_state; 941 pdq_uint32_t emac_ring_purger_enable; 942 pdq_uint32_t emac_frame_strip_mode; 943 pdq_uint32_t emac_ring_error_reason; 944 pdq_uint32_t emac_upstream_nbr_dupl_address_flag; 945 pdq_uint32_t emac_restricted_token_timeout; 946 /* Port Objects */ 947 pdq_uint32_t eport_pmd_type[2]; 948 pdq_uint32_t eport_phy_state[2]; 949 pdq_uint32_t eport_reject_reason[2]; 950 /* Full Duplex Objects */ 951 pdq_boolean_t fdx_enable; 952 pdq_boolean_t fdx_operational; 953 pdq_fdx_state_t fdx_state; 954 } dec_ext_mib_get; 955} pdq_response_dec_ext_mib_get_t; 956 957#define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50 958 959typedef enum { 960 PDQ_CALLER_ID_NONE=0, 961 PDQ_CALLER_ID_SELFTEST=1, 962 PDQ_CALLER_ID_MFG=2, 963 PDQ_CALLER_ID_FIRMWARE=5, 964 PDQ_CALLER_ID_CONSOLE=8 965} pdq_caller_id_t; 966 967typedef struct { 968 pdq_uint32_t error_log_get__reserved; 969 pdq_cmd_code_t error_log_get_op; 970 pdq_response_code_t error_log_get_status; 971 /* Error Header */ 972 pdq_uint32_t error_log_get_event_status; 973 /* Event Information Block */ 974 pdq_caller_id_t error_log_get_caller_id; 975 pdq_uint32_t error_log_get_timestamp[2]; 976 pdq_uint32_t error_log_get_write_count; 977 /* Diagnostic Information */ 978 pdq_uint32_t error_log_get_fru_implication_mask; 979 pdq_uint32_t error_log_get_test_id; 980 pdq_uint32_t error_log_get_diag_reserved[6]; 981 /* Firmware Information */ 982 pdq_uint32_t error_log_get_fw_reserved[112]; 983} pdq_response_error_log_get_t; 984 985 986/* 987 * Definitions for the Unsolicited Event Queue. 988 */ 989typedef enum { 990 PDQ_UNSOLICITED_EVENT=0, 991 PDQ_UNSOLICITED_COUNTERS=1 992} pdq_event_t; 993 994typedef enum { 995 PDQ_ENTITY_STATION=0, 996 PDQ_ENTITY_LINK=1, 997 PDQ_ENTITY_PHY_PORT=2 998} pdq_entity_t; 999 1000typedef enum { 1001 PDQ_STATION_EVENT_TRACE_RECEIVED=1 1002} pdq_station_event_t; 1003 1004typedef enum { 1005 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */ 1006 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF 1007} pdq_station_event_argument_t; 1008 1009typedef enum { 1010 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0, 1011 PDQ_LINK_EVENT_TRANSMIT_FAILED=1, 1012 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2, 1013 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3, 1014 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4, 1015 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7, 1016 PDQ_LINK_EVENT_NO_USER_BUFFER=9, 1017 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10, 1018 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11, 1019 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12, 1020 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13, 1021 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14, 1022 PDQ_LINK_EVENT_RING_PURGE_ERROR=15, 1023 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16, 1024 PDQ_LINK_EVENT_TRACE_INITIATED=17, 1025 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18 1026} pdq_link_event_t; 1027 1028typedef enum { 1029 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */ 1030 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */ 1031 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */ 1032 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */ 1033 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF 1034} pdq_link_event_argument_t; 1035 1036typedef enum { 1037 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0, 1038 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1, 1039 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2 1040} pdq_phy_event_t; 1041 1042typedef enum { 1043 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */ 1044 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF 1045} pdq_phy_event_arguments; 1046 1047struct _pdq_unsolicited_event_t { 1048 pdq_uint32_t rvent_reserved; 1049 pdq_event_t event_type; 1050 pdq_entity_t event_entity; 1051 pdq_uint32_t event_index; 1052 union { 1053 pdq_station_event_t station_event; 1054 pdq_link_event_t link_event; 1055 pdq_phy_event_t phy_event; 1056 pdq_uint32_t value; 1057 } event_code; 1058 /* 1059 * The remainder of this event is an argument list. 1060 */ 1061 pdq_uint32_t event__filler[123]; 1062}; 1063 1064#endif /* _PDQREG_H */ 1065