pcireg.h revision 7233
1232922Stheraven/************************************************************************** 2232922Stheraven** 3232922Stheraven** $Id: pcireg.h,v 1.4 1995/02/02 22:01:40 se Exp $ 4232922Stheraven** 5232922Stheraven** Names for PCI configuration space registers. 6232922Stheraven** 7232922Stheraven** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 8232922Stheraven** 9232922Stheraven** 10232922Stheraven** Redistribution and use in source and binary forms, with or without 11232922Stheraven** modification, are permitted provided that the following conditions 12232922Stheraven** are met: 13232922Stheraven** 1. Redistributions of source code must retain the above copyright 14232922Stheraven** notice, this list of conditions and the following disclaimer. 15232922Stheraven** 2. Redistributions in binary form must reproduce the above copyright 16232922Stheraven** notice, this list of conditions and the following disclaimer in the 17232922Stheraven** documentation and/or other materials provided with the distribution. 18232922Stheraven** 3. The name of the author may not be used to endorse or promote products 19232922Stheraven** derived from this software without specific prior written permission. 20232922Stheraven** 21232922Stheraven** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22232922Stheraven** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23232922Stheraven** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24232922Stheraven** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25232922Stheraven** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26232922Stheraven** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27227825Stheraven** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28227825Stheraven** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29227825Stheraven** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30227825Stheraven** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31227825Stheraven** 32227825Stheraven*************************************************************************** 33227825Stheraven*/ 34227825Stheraven 35227825Stheraven#ifndef __PCI_REG_H__ 36227825Stheraven#define __PCI_REG_H__ "pl2 95/03/21" 37227825Stheraven 38227825Stheraven/* 39227825Stheraven** Device identification register; contains a vendor ID and a device ID. 40227825Stheraven** We have little need to distinguish the two parts. 41227825Stheraven*/ 42227825Stheraven#define PCI_ID_REG 0x00 43227825Stheraven 44227825Stheraven/* 45227825Stheraven** Command and status register. 46227825Stheraven*/ 47227825Stheraven#define PCI_COMMAND_STATUS_REG 0x04 48227825Stheraven 49227825Stheraven#define PCI_COMMAND_IO_ENABLE 0x00000001 50227825Stheraven#define PCI_COMMAND_MEM_ENABLE 0x00000002 51227825Stheraven#define PCI_COMMAND_MASTER_ENABLE 0x00000004 52227825Stheraven#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 53227825Stheraven#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 54227825Stheraven#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 55227825Stheraven#define PCI_COMMAND_PARITY_ENABLE 0x00000040 56227825Stheraven#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 57227825Stheraven#define PCI_COMMAND_SERR_ENABLE 0x00000100 58227825Stheraven#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 59227825Stheraven 60227825Stheraven#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 61227825Stheraven#define PCI_STATUS_PARITY_ERROR 0x01000000 62227825Stheraven#define PCI_STATUS_DEVSEL_FAST 0x00000000 63227825Stheraven#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 64227825Stheraven#define PCI_STATUS_DEVSEL_SLOW 0x04000000 65227825Stheraven#define PCI_STATUS_DEVSEL_MASK 0x06000000 66227825Stheraven#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 67227825Stheraven#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 68253145Stheraven#define PCI_STATUS_MASTER_ABORT 0x20000000 69253145Stheraven#define PCI_STATUS_SPECIAL_ERROR 0x40000000 70253145Stheraven#define PCI_STATUS_PARITY_DETECT 0x80000000 71253145Stheraven 72253145Stheraven/* 73253145Stheraven** Class register; defines basic type of device. 74253145Stheraven*/ 75253145Stheraven#define PCI_CLASS_REG 0x08 76253145Stheraven 77253145Stheraven#define PCI_CLASS_MASK 0xff000000 78276375Sdim#define PCI_SUBCLASS_MASK 0x00ff0000 79276375Sdim 80276375Sdim/* base classes */ 81276375Sdim#define PCI_CLASS_PREHISTORIC 0x00000000 82276375Sdim#define PCI_CLASS_MASS_STORAGE 0x01000000 83#define PCI_CLASS_NETWORK 0x02000000 84#define PCI_CLASS_DISPLAY 0x03000000 85#define PCI_CLASS_MULTIMEDIA 0x04000000 86#define PCI_CLASS_MEMORY 0x05000000 87#define PCI_CLASS_BRIDGE 0x06000000 88#define PCI_CLASS_UNDEFINED 0xff000000 89 90/* 0x00 prehistoric subclasses */ 91#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00000000 92#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 93 94/* 0x01 mass storage subclasses */ 95#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 96#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x00010000 97#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x00020000 98#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x00030000 99#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x00800000 100 101/* 0x02 network subclasses */ 102#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00000000 103#define PCI_SUBCLASS_NETWORK_TOKENRING 0x00010000 104#define PCI_SUBCLASS_NETWORK_FDDI 0x00020000 105#define PCI_SUBCLASS_NETWORK_MISC 0x00800000 106 107/* 0x03 display subclasses */ 108#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 109#define PCI_SUBCLASS_DISPLAY_XGA 0x00010000 110#define PCI_SUBCLASS_DISPLAY_MISC 0x00800000 111 112/* 0x04 multimedia subclasses */ 113#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00000000 114#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x00010000 115#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x00800000 116 117/* 0x05 memory subclasses */ 118#define PCI_SUBCLASS_MEMORY_RAM 0x00000000 119#define PCI_SUBCLASS_MEMORY_FLASH 0x00010000 120#define PCI_SUBCLASS_MEMORY_MISC 0x00800000 121 122/* 0x06 bridge subclasses */ 123#define PCI_SUBCLASS_BRIDGE_HOST 0x00000000 124#define PCI_SUBCLASS_BRIDGE_ISA 0x00010000 125#define PCI_SUBCLASS_BRIDGE_EISA 0x00020000 126#define PCI_SUBCLASS_BRIDGE_MC 0x00030000 127#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 128#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x00050000 129#define PCI_SUBCLASS_BRIDGE_MISC 0x00800000 130 131/* 132** Mapping registers 133*/ 134#define PCI_MAP_REG_START 0x10 135#define PCI_MAP_REG_END 0x28 136 137#define PCI_MAP_MEMORY 0x00000000 138#define PCI_MAP_IO 0x00000001 139 140#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 141#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 142#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 143#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 144#define PCI_MAP_MEMORY_CACHABLE 0x00000008 145#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 146 147#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc 148/* 149** PCI-PCI bridge mapping registers 150*/ 151#define PCI_PCI_BRIDGE_BUS_REG 0x18 152#define PCI_PCI_BRIDGE_IO_REG 0x1c 153#define PCI_PCI_BRIDGE_MEM_REG 0x20 154#define PCI_PCI_BRIDGE_PMEM_REG 0x24 155 156 157#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 158#define PCI_SECONDARY_BUS_MASK 0x0000ff00 159#define PCI_PRIMARY_BUS_MASK 0x000000ff 160 161#define PCI_SUBORDINATE_BUS_EXTRACT(x) (((x) > 16) & 0xff) 162#define PCI_SECONDARY_BUS_EXTRACT(x) (((x) > 8) & 0xff) 163#define PCI_PRIMARY_BUS_EXTRACT(x) (((x) ) & 0xff) 164 165#define PCI_PRIMARY_BUS_INSERT(x, y) (((x) & ~PCI_PRIMARY_BUS_MASK) | ((y) << 0)) 166#define PCI_SECONDARY_BUS_INSERT(x, y) (((x) & ~PCI_SECONDARY_BUS_MASK) | ((y) << 8)) 167#define PCI_SUBORDINATE_BUS_INSERT(x, y) (((x) & ~PCI_SUBORDINATE_BUS_MASK) | ((y) << 16)) 168 169#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00) 170#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00) 171 172#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000) 173#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000) 174 175/* 176** Interrupt configuration register 177*/ 178#define PCI_INTERRUPT_REG 0x3c 179 180#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 181#define PCI_INTERRUPT_PIN_EXTRACT(x) ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) 182#define PCI_INTERRUPT_PIN_NONE 0x00 183#define PCI_INTERRUPT_PIN_A 0x01 184#define PCI_INTERRUPT_PIN_B 0x02 185#define PCI_INTERRUPT_PIN_C 0x03 186#define PCI_INTERRUPT_PIN_D 0x04 187 188#define PCI_INTERRUPT_LINE_MASK 0x000000ff 189#define PCI_INTERRUPT_LINE_EXTRACT(x) ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) 190#define PCI_INTERRUPT_LINE_INSERT(x,v) (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) 191 192#endif /* __PCI_REG_H__ */ 193