pcireg.h revision 331149
1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: stable/11/sys/dev/pci/pcireg.h 331149 2018-03-18 22:29:41Z eadler $ 29 * 30 */ 31 32/* 33 * PCIM_xxx: mask to locate subfield in register 34 * PCIR_xxx: config register offset 35 * PCIC_xxx: device class 36 * PCIS_xxx: device subclass 37 * PCIP_xxx: device programming interface 38 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 39 * PCID_xxx: device ID 40 * PCIY_xxx: capability identification number 41 * PCIZ_xxx: extended capability identification number 42 */ 43 44/* some PCI bus constants */ 45#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 46#define PCI_BUSMAX 255 /* highest supported bus number */ 47#define PCI_SLOTMAX 31 /* highest supported slot number */ 48#define PCI_FUNCMAX 7 /* highest supported function number */ 49#define PCI_REGMAX 255 /* highest supported config register addr. */ 50#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 51#define PCI_MAXHDRTYPE 2 52 53#define PCIE_ARI_SLOTMAX 0 54#define PCIE_ARI_FUNCMAX 255 55 56#define PCI_RID_DOMAIN_SHIFT 16 57#define PCI_RID_BUS_SHIFT 8 58#define PCI_RID_SLOT_SHIFT 3 59#define PCI_RID_FUNC_SHIFT 0 60 61#define PCI_RID(bus, slot, func) \ 62 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 63 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 64 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 65 66#define PCI_ARI_RID(bus, func) \ 67 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 68 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 69 70#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 71#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 72#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 73 74#define PCIE_ARI_RID2SLOT(rid) (0) 75#define PCIE_ARI_RID2FUNC(rid) \ 76 (((rid) >> PCI_RID_FUNC_SHIFT) & PCIE_ARI_FUNCMAX) 77 78#define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 79#define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 80 81/* PCI config header registers for all devices */ 82 83#define PCIR_DEVVENDOR 0x00 84#define PCIR_VENDOR 0x00 85#define PCIR_DEVICE 0x02 86#define PCIR_COMMAND 0x04 87#define PCIM_CMD_PORTEN 0x0001 88#define PCIM_CMD_MEMEN 0x0002 89#define PCIM_CMD_BUSMASTEREN 0x0004 90#define PCIM_CMD_SPECIALEN 0x0008 91#define PCIM_CMD_MWRICEN 0x0010 92#define PCIM_CMD_PERRESPEN 0x0040 93#define PCIM_CMD_SERRESPEN 0x0100 94#define PCIM_CMD_BACKTOBACK 0x0200 95#define PCIM_CMD_INTxDIS 0x0400 96#define PCIR_STATUS 0x06 97#define PCIM_STATUS_INTxSTATE 0x0008 98#define PCIM_STATUS_CAPPRESENT 0x0010 99#define PCIM_STATUS_66CAPABLE 0x0020 100#define PCIM_STATUS_BACKTOBACK 0x0080 101#define PCIM_STATUS_MDPERR 0x0100 102#define PCIM_STATUS_SEL_FAST 0x0000 103#define PCIM_STATUS_SEL_MEDIMUM 0x0200 104#define PCIM_STATUS_SEL_SLOW 0x0400 105#define PCIM_STATUS_SEL_MASK 0x0600 106#define PCIM_STATUS_STABORT 0x0800 107#define PCIM_STATUS_RTABORT 0x1000 108#define PCIM_STATUS_RMABORT 0x2000 109#define PCIM_STATUS_SERR 0x4000 110#define PCIM_STATUS_PERR 0x8000 111#define PCIR_REVID 0x08 112#define PCIR_PROGIF 0x09 113#define PCIR_SUBCLASS 0x0a 114#define PCIR_CLASS 0x0b 115#define PCIR_CACHELNSZ 0x0c 116#define PCIR_LATTIMER 0x0d 117#define PCIR_HDRTYPE 0x0e 118#define PCIM_HDRTYPE 0x7f 119#define PCIM_HDRTYPE_NORMAL 0x00 120#define PCIM_HDRTYPE_BRIDGE 0x01 121#define PCIM_HDRTYPE_CARDBUS 0x02 122#define PCIM_MFDEV 0x80 123#define PCIR_BIST 0x0f 124 125/* Capability Register Offsets */ 126 127#define PCICAP_ID 0x0 128#define PCICAP_NEXTPTR 0x1 129 130/* Capability Identification Numbers */ 131 132#define PCIY_PMG 0x01 /* PCI Power Management */ 133#define PCIY_AGP 0x02 /* AGP */ 134#define PCIY_VPD 0x03 /* Vital Product Data */ 135#define PCIY_SLOTID 0x04 /* Slot Identification */ 136#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 137#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 138#define PCIY_PCIX 0x07 /* PCI-X */ 139#define PCIY_HT 0x08 /* HyperTransport */ 140#define PCIY_VENDOR 0x09 /* Vendor Unique */ 141#define PCIY_DEBUG 0x0a /* Debug port */ 142#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 143#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 144#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 145#define PCIY_AGP8X 0x0e /* AGP 8x */ 146#define PCIY_SECDEV 0x0f /* Secure Device */ 147#define PCIY_EXPRESS 0x10 /* PCI Express */ 148#define PCIY_MSIX 0x11 /* MSI-X */ 149#define PCIY_SATA 0x12 /* SATA */ 150#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 151#define PCIY_EA 0x14 /* PCI Extended Allocation */ 152 153/* Extended Capability Register Fields */ 154 155#define PCIR_EXTCAP 0x100 156#define PCIM_EXTCAP_ID 0x0000ffff 157#define PCIM_EXTCAP_VER 0x000f0000 158#define PCIM_EXTCAP_NEXTPTR 0xfff00000 159#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 160#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 161#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 162 163/* Extended Capability Identification Numbers */ 164 165#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 166#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 167#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 168#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 169#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 170#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 171#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 172#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 173#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 174#define PCIZ_RCRB 0x000a /* RCRB Header */ 175#define PCIZ_VENDOR 0x000b /* Vendor Unique */ 176#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 177#define PCIZ_ACS 0x000d /* Access Control Services */ 178#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 179#define PCIZ_ATS 0x000f /* Address Translation Services */ 180#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 181#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 182#define PCIZ_MULTICAST 0x0012 /* Multicast */ 183#define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 184#define PCIZ_AMD 0x0014 /* Reserved for AMD */ 185#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 186#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 187#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 188#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 189#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 190#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 191#define PCIZ_PASID 0x001b /* Process Address Space ID */ 192#define PCIZ_LN_REQ 0x001c /* LN Requester */ 193#define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 194#define PCIZ_L1PM 0x001e /* L1 PM Substates */ 195 196/* config registers for header type 0 devices */ 197 198#define PCIR_BARS 0x10 199#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 200#define PCIR_MAX_BAR_0 5 201#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 202#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 203#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 204#define PCIM_BAR_SPACE 0x00000001 205#define PCIM_BAR_MEM_SPACE 0 206#define PCIM_BAR_IO_SPACE 1 207#define PCIM_BAR_MEM_TYPE 0x00000006 208#define PCIM_BAR_MEM_32 0 209#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 210#define PCIM_BAR_MEM_64 4 211#define PCIM_BAR_MEM_PREFETCH 0x00000008 212#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 213#define PCIM_BAR_IO_RESERVED 0x00000002 214#define PCIM_BAR_IO_BASE 0xfffffffc 215#define PCIR_CIS 0x28 216#define PCIM_CIS_ASI_MASK 0x00000007 217#define PCIM_CIS_ASI_CONFIG 0 218#define PCIM_CIS_ASI_BAR0 1 219#define PCIM_CIS_ASI_BAR1 2 220#define PCIM_CIS_ASI_BAR2 3 221#define PCIM_CIS_ASI_BAR3 4 222#define PCIM_CIS_ASI_BAR4 5 223#define PCIM_CIS_ASI_BAR5 6 224#define PCIM_CIS_ASI_ROM 7 225#define PCIM_CIS_ADDR_MASK 0x0ffffff8 226#define PCIM_CIS_ROM_MASK 0xf0000000 227#define PCIM_CIS_CONFIG_MASK 0xff 228#define PCIR_SUBVEND_0 0x2c 229#define PCIR_SUBDEV_0 0x2e 230#define PCIR_BIOS 0x30 231#define PCIM_BIOS_ENABLE 0x01 232#define PCIM_BIOS_ADDR_MASK 0xfffff800 233#define PCIR_CAP_PTR 0x34 234#define PCIR_INTLINE 0x3c 235#define PCIR_INTPIN 0x3d 236#define PCIR_MINGNT 0x3e 237#define PCIR_MAXLAT 0x3f 238 239/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 240 241#define PCIR_MAX_BAR_1 1 242#define PCIR_SECSTAT_1 0x1e 243 244#define PCIR_PRIBUS_1 0x18 245#define PCIR_SECBUS_1 0x19 246#define PCIR_SUBBUS_1 0x1a 247#define PCIR_SECLAT_1 0x1b 248 249#define PCIR_IOBASEL_1 0x1c 250#define PCIR_IOLIMITL_1 0x1d 251#define PCIR_IOBASEH_1 0x30 252#define PCIR_IOLIMITH_1 0x32 253#define PCIM_BRIO_16 0x0 254#define PCIM_BRIO_32 0x1 255#define PCIM_BRIO_MASK 0xf 256 257#define PCIR_MEMBASE_1 0x20 258#define PCIR_MEMLIMIT_1 0x22 259 260#define PCIR_PMBASEL_1 0x24 261#define PCIR_PMLIMITL_1 0x26 262#define PCIR_PMBASEH_1 0x28 263#define PCIR_PMLIMITH_1 0x2c 264#define PCIM_BRPM_32 0x0 265#define PCIM_BRPM_64 0x1 266#define PCIM_BRPM_MASK 0xf 267 268#define PCIR_BIOS_1 0x38 269#define PCIR_BRIDGECTL_1 0x3e 270 271#define PCI_PPBMEMBASE(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 272#define PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff) 273#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 274#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 275 276/* config registers for header type 2 (CardBus) devices */ 277 278#define PCIR_MAX_BAR_2 0 279#define PCIR_CAP_PTR_2 0x14 280#define PCIR_SECSTAT_2 0x16 281 282#define PCIR_PRIBUS_2 0x18 283#define PCIR_SECBUS_2 0x19 284#define PCIR_SUBBUS_2 0x1a 285#define PCIR_SECLAT_2 0x1b 286 287#define PCIR_MEMBASE0_2 0x1c 288#define PCIR_MEMLIMIT0_2 0x20 289#define PCIR_MEMBASE1_2 0x24 290#define PCIR_MEMLIMIT1_2 0x28 291#define PCIR_IOBASE0_2 0x2c 292#define PCIR_IOLIMIT0_2 0x30 293#define PCIR_IOBASE1_2 0x34 294#define PCIR_IOLIMIT1_2 0x38 295#define PCIM_CBBIO_16 0x0 296#define PCIM_CBBIO_32 0x1 297#define PCIM_CBBIO_MASK 0x3 298 299#define PCIR_BRIDGECTL_2 0x3e 300 301#define PCIR_SUBVEND_2 0x40 302#define PCIR_SUBDEV_2 0x42 303 304#define PCIR_PCCARDIF_2 0x44 305 306#define PCI_CBBMEMBASE(l) ((l) & ~0xfffff) 307#define PCI_CBBMEMLIMIT(l) ((l) | 0xfffff) 308#define PCI_CBBIOBASE(l) ((l) & ~0x3) 309#define PCI_CBBIOLIMIT(l) ((l) | 0x3) 310 311/* PCI device class, subclass and programming interface definitions */ 312 313#define PCIC_OLD 0x00 314#define PCIS_OLD_NONVGA 0x00 315#define PCIS_OLD_VGA 0x01 316 317#define PCIC_STORAGE 0x01 318#define PCIS_STORAGE_SCSI 0x00 319#define PCIS_STORAGE_IDE 0x01 320#define PCIP_STORAGE_IDE_MODEPRIM 0x01 321#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 322#define PCIP_STORAGE_IDE_MODESEC 0x04 323#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 324#define PCIP_STORAGE_IDE_MASTERDEV 0x80 325#define PCIS_STORAGE_FLOPPY 0x02 326#define PCIS_STORAGE_IPI 0x03 327#define PCIS_STORAGE_RAID 0x04 328#define PCIS_STORAGE_ATA_ADMA 0x05 329#define PCIS_STORAGE_SATA 0x06 330#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 331#define PCIS_STORAGE_SAS 0x07 332#define PCIS_STORAGE_NVM 0x08 333#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 334#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 335#define PCIS_STORAGE_OTHER 0x80 336 337#define PCIC_NETWORK 0x02 338#define PCIS_NETWORK_ETHERNET 0x00 339#define PCIS_NETWORK_TOKENRING 0x01 340#define PCIS_NETWORK_FDDI 0x02 341#define PCIS_NETWORK_ATM 0x03 342#define PCIS_NETWORK_ISDN 0x04 343#define PCIS_NETWORK_WORLDFIP 0x05 344#define PCIS_NETWORK_PICMG 0x06 345#define PCIS_NETWORK_OTHER 0x80 346 347#define PCIC_DISPLAY 0x03 348#define PCIS_DISPLAY_VGA 0x00 349#define PCIS_DISPLAY_XGA 0x01 350#define PCIS_DISPLAY_3D 0x02 351#define PCIS_DISPLAY_OTHER 0x80 352 353#define PCIC_MULTIMEDIA 0x04 354#define PCIS_MULTIMEDIA_VIDEO 0x00 355#define PCIS_MULTIMEDIA_AUDIO 0x01 356#define PCIS_MULTIMEDIA_TELE 0x02 357#define PCIS_MULTIMEDIA_HDA 0x03 358#define PCIS_MULTIMEDIA_OTHER 0x80 359 360#define PCIC_MEMORY 0x05 361#define PCIS_MEMORY_RAM 0x00 362#define PCIS_MEMORY_FLASH 0x01 363#define PCIS_MEMORY_OTHER 0x80 364 365#define PCIC_BRIDGE 0x06 366#define PCIS_BRIDGE_HOST 0x00 367#define PCIS_BRIDGE_ISA 0x01 368#define PCIS_BRIDGE_EISA 0x02 369#define PCIS_BRIDGE_MCA 0x03 370#define PCIS_BRIDGE_PCI 0x04 371#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 372#define PCIS_BRIDGE_PCMCIA 0x05 373#define PCIS_BRIDGE_NUBUS 0x06 374#define PCIS_BRIDGE_CARDBUS 0x07 375#define PCIS_BRIDGE_RACEWAY 0x08 376#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 377#define PCIS_BRIDGE_INFINIBAND 0x0a 378#define PCIS_BRIDGE_OTHER 0x80 379 380#define PCIC_SIMPLECOMM 0x07 381#define PCIS_SIMPLECOMM_UART 0x00 382#define PCIP_SIMPLECOMM_UART_8250 0x00 383#define PCIP_SIMPLECOMM_UART_16450A 0x01 384#define PCIP_SIMPLECOMM_UART_16550A 0x02 385#define PCIP_SIMPLECOMM_UART_16650A 0x03 386#define PCIP_SIMPLECOMM_UART_16750A 0x04 387#define PCIP_SIMPLECOMM_UART_16850A 0x05 388#define PCIP_SIMPLECOMM_UART_16950A 0x06 389#define PCIS_SIMPLECOMM_PAR 0x01 390#define PCIS_SIMPLECOMM_MULSER 0x02 391#define PCIS_SIMPLECOMM_MODEM 0x03 392#define PCIS_SIMPLECOMM_GPIB 0x04 393#define PCIS_SIMPLECOMM_SMART_CARD 0x05 394#define PCIS_SIMPLECOMM_OTHER 0x80 395 396#define PCIC_BASEPERIPH 0x08 397#define PCIS_BASEPERIPH_PIC 0x00 398#define PCIP_BASEPERIPH_PIC_8259A 0x00 399#define PCIP_BASEPERIPH_PIC_ISA 0x01 400#define PCIP_BASEPERIPH_PIC_EISA 0x02 401#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 402#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 403#define PCIS_BASEPERIPH_DMA 0x01 404#define PCIS_BASEPERIPH_TIMER 0x02 405#define PCIS_BASEPERIPH_RTC 0x03 406#define PCIS_BASEPERIPH_PCIHOT 0x04 407#define PCIS_BASEPERIPH_SDHC 0x05 408#define PCIS_BASEPERIPH_IOMMU 0x06 409#define PCIS_BASEPERIPH_OTHER 0x80 410 411#define PCIC_INPUTDEV 0x09 412#define PCIS_INPUTDEV_KEYBOARD 0x00 413#define PCIS_INPUTDEV_DIGITIZER 0x01 414#define PCIS_INPUTDEV_MOUSE 0x02 415#define PCIS_INPUTDEV_SCANNER 0x03 416#define PCIS_INPUTDEV_GAMEPORT 0x04 417#define PCIS_INPUTDEV_OTHER 0x80 418 419#define PCIC_DOCKING 0x0a 420#define PCIS_DOCKING_GENERIC 0x00 421#define PCIS_DOCKING_OTHER 0x80 422 423#define PCIC_PROCESSOR 0x0b 424#define PCIS_PROCESSOR_386 0x00 425#define PCIS_PROCESSOR_486 0x01 426#define PCIS_PROCESSOR_PENTIUM 0x02 427#define PCIS_PROCESSOR_ALPHA 0x10 428#define PCIS_PROCESSOR_POWERPC 0x20 429#define PCIS_PROCESSOR_MIPS 0x30 430#define PCIS_PROCESSOR_COPROC 0x40 431 432#define PCIC_SERIALBUS 0x0c 433#define PCIS_SERIALBUS_FW 0x00 434#define PCIS_SERIALBUS_ACCESS 0x01 435#define PCIS_SERIALBUS_SSA 0x02 436#define PCIS_SERIALBUS_USB 0x03 437#define PCIP_SERIALBUS_USB_UHCI 0x00 438#define PCIP_SERIALBUS_USB_OHCI 0x10 439#define PCIP_SERIALBUS_USB_EHCI 0x20 440#define PCIP_SERIALBUS_USB_XHCI 0x30 441#define PCIP_SERIALBUS_USB_DEVICE 0xfe 442#define PCIS_SERIALBUS_FC 0x04 443#define PCIS_SERIALBUS_SMBUS 0x05 444#define PCIS_SERIALBUS_INFINIBAND 0x06 445#define PCIS_SERIALBUS_IPMI 0x07 446#define PCIP_SERIALBUS_IPMI_SMIC 0x00 447#define PCIP_SERIALBUS_IPMI_KCS 0x01 448#define PCIP_SERIALBUS_IPMI_BT 0x02 449#define PCIS_SERIALBUS_SERCOS 0x08 450#define PCIS_SERIALBUS_CANBUS 0x09 451 452#define PCIC_WIRELESS 0x0d 453#define PCIS_WIRELESS_IRDA 0x00 454#define PCIS_WIRELESS_IR 0x01 455#define PCIS_WIRELESS_RF 0x10 456#define PCIS_WIRELESS_BLUETOOTH 0x11 457#define PCIS_WIRELESS_BROADBAND 0x12 458#define PCIS_WIRELESS_80211A 0x20 459#define PCIS_WIRELESS_80211B 0x21 460#define PCIS_WIRELESS_OTHER 0x80 461 462#define PCIC_INTELLIIO 0x0e 463#define PCIS_INTELLIIO_I2O 0x00 464 465#define PCIC_SATCOM 0x0f 466#define PCIS_SATCOM_TV 0x01 467#define PCIS_SATCOM_AUDIO 0x02 468#define PCIS_SATCOM_VOICE 0x03 469#define PCIS_SATCOM_DATA 0x04 470 471#define PCIC_CRYPTO 0x10 472#define PCIS_CRYPTO_NETCOMP 0x00 473#define PCIS_CRYPTO_ENTERTAIN 0x10 474#define PCIS_CRYPTO_OTHER 0x80 475 476#define PCIC_DASP 0x11 477#define PCIS_DASP_DPIO 0x00 478#define PCIS_DASP_PERFCNTRS 0x01 479#define PCIS_DASP_COMM_SYNC 0x10 480#define PCIS_DASP_MGMT_CARD 0x20 481#define PCIS_DASP_OTHER 0x80 482 483#define PCIC_ACCEL 0x12 484#define PCIS_ACCEL_PROCESSING 0x00 485 486#define PCIC_INSTRUMENT 0x13 487 488#define PCIC_OTHER 0xff 489 490/* Bridge Control Values. */ 491#define PCIB_BCR_PERR_ENABLE 0x0001 492#define PCIB_BCR_SERR_ENABLE 0x0002 493#define PCIB_BCR_ISA_ENABLE 0x0004 494#define PCIB_BCR_VGA_ENABLE 0x0008 495#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 496#define PCIB_BCR_SECBUS_RESET 0x0040 497#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 498#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 499#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 500#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 501#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 502 503#define CBB_BCR_PERR_ENABLE 0x0001 504#define CBB_BCR_SERR_ENABLE 0x0002 505#define CBB_BCR_ISA_ENABLE 0x0004 506#define CBB_BCR_VGA_ENABLE 0x0008 507#define CBB_BCR_MASTER_ABORT_MODE 0x0020 508#define CBB_BCR_CARDBUS_RESET 0x0040 509#define CBB_BCR_IREQ_INT_ENABLE 0x0080 510#define CBB_BCR_PREFETCH_0_ENABLE 0x0100 511#define CBB_BCR_PREFETCH_1_ENABLE 0x0200 512#define CBB_BCR_WRITE_POSTING_ENABLE 0x0400 513 514/* PCI power manangement */ 515#define PCIR_POWER_CAP 0x2 516#define PCIM_PCAP_SPEC 0x0007 517#define PCIM_PCAP_PMEREQCLK 0x0008 518#define PCIM_PCAP_DEVSPECINIT 0x0020 519#define PCIM_PCAP_AUXPWR_0 0x0000 520#define PCIM_PCAP_AUXPWR_55 0x0040 521#define PCIM_PCAP_AUXPWR_100 0x0080 522#define PCIM_PCAP_AUXPWR_160 0x00c0 523#define PCIM_PCAP_AUXPWR_220 0x0100 524#define PCIM_PCAP_AUXPWR_270 0x0140 525#define PCIM_PCAP_AUXPWR_320 0x0180 526#define PCIM_PCAP_AUXPWR_375 0x01c0 527#define PCIM_PCAP_AUXPWRMASK 0x01c0 528#define PCIM_PCAP_D1SUPP 0x0200 529#define PCIM_PCAP_D2SUPP 0x0400 530#define PCIM_PCAP_D0PME 0x0800 531#define PCIM_PCAP_D1PME 0x1000 532#define PCIM_PCAP_D2PME 0x2000 533#define PCIM_PCAP_D3PME_HOT 0x4000 534#define PCIM_PCAP_D3PME_COLD 0x8000 535 536#define PCIR_POWER_STATUS 0x4 537#define PCIM_PSTAT_D0 0x0000 538#define PCIM_PSTAT_D1 0x0001 539#define PCIM_PSTAT_D2 0x0002 540#define PCIM_PSTAT_D3 0x0003 541#define PCIM_PSTAT_DMASK 0x0003 542#define PCIM_PSTAT_NOSOFTRESET 0x0008 543#define PCIM_PSTAT_PMEENABLE 0x0100 544#define PCIM_PSTAT_D0POWER 0x0000 545#define PCIM_PSTAT_D1POWER 0x0200 546#define PCIM_PSTAT_D2POWER 0x0400 547#define PCIM_PSTAT_D3POWER 0x0600 548#define PCIM_PSTAT_D0HEAT 0x0800 549#define PCIM_PSTAT_D1HEAT 0x0a00 550#define PCIM_PSTAT_D2HEAT 0x0c00 551#define PCIM_PSTAT_D3HEAT 0x0e00 552#define PCIM_PSTAT_DATASELMASK 0x1e00 553#define PCIM_PSTAT_DATAUNKN 0x0000 554#define PCIM_PSTAT_DATADIV10 0x2000 555#define PCIM_PSTAT_DATADIV100 0x4000 556#define PCIM_PSTAT_DATADIV1000 0x6000 557#define PCIM_PSTAT_DATADIVMASK 0x6000 558#define PCIM_PSTAT_PME 0x8000 559 560#define PCIR_POWER_BSE 0x6 561#define PCIM_PMCSR_BSE_D3B3 0x00 562#define PCIM_PMCSR_BSE_D3B2 0x40 563#define PCIM_PMCSR_BSE_BPCCE 0x80 564 565#define PCIR_POWER_DATA 0x7 566 567/* VPD capability registers */ 568#define PCIR_VPD_ADDR 0x2 569#define PCIR_VPD_DATA 0x4 570 571/* PCI Message Signalled Interrupts (MSI) */ 572#define PCIR_MSI_CTRL 0x2 573#define PCIM_MSICTRL_VECTOR 0x0100 574#define PCIM_MSICTRL_64BIT 0x0080 575#define PCIM_MSICTRL_MME_MASK 0x0070 576#define PCIM_MSICTRL_MME_1 0x0000 577#define PCIM_MSICTRL_MME_2 0x0010 578#define PCIM_MSICTRL_MME_4 0x0020 579#define PCIM_MSICTRL_MME_8 0x0030 580#define PCIM_MSICTRL_MME_16 0x0040 581#define PCIM_MSICTRL_MME_32 0x0050 582#define PCIM_MSICTRL_MMC_MASK 0x000E 583#define PCIM_MSICTRL_MMC_1 0x0000 584#define PCIM_MSICTRL_MMC_2 0x0002 585#define PCIM_MSICTRL_MMC_4 0x0004 586#define PCIM_MSICTRL_MMC_8 0x0006 587#define PCIM_MSICTRL_MMC_16 0x0008 588#define PCIM_MSICTRL_MMC_32 0x000A 589#define PCIM_MSICTRL_MSI_ENABLE 0x0001 590#define PCIR_MSI_ADDR 0x4 591#define PCIR_MSI_ADDR_HIGH 0x8 592#define PCIR_MSI_DATA 0x8 593#define PCIR_MSI_DATA_64BIT 0xc 594#define PCIR_MSI_MASK 0x10 595#define PCIR_MSI_PENDING 0x14 596 597/* PCI Enhanced Allocation registers */ 598#define PCIR_EA_NUM_ENT 2 /* Number of Capability Entries */ 599#define PCIM_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */ 600#define PCIR_EA_FIRST_ENT 4 /* First EA Entry in List */ 601#define PCIR_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */ 602#define PCIM_EA_ES 0x00000007 /* Entry Size */ 603#define PCIM_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ 604#define PCIM_EA_BEI_OFFSET 4 605/* 0-5 map to BARs 0-5 respectively */ 606#define PCIM_EA_BEI_BAR_0 0 607#define PCIM_EA_BEI_BAR_5 5 608#define PCIM_EA_BEI_BAR(x) (((x) >> PCIM_EA_BEI_OFFSET) & 0xf) 609#define PCIM_EA_BEI_BRIDGE 0x6 /* Resource behind bridge */ 610#define PCIM_EA_BEI_ENI 0x7 /* Equivalent Not Indicated */ 611#define PCIM_EA_BEI_ROM 0x8 /* Expansion ROM */ 612/* 9-14 map to VF BARs 0-5 respectively */ 613#define PCIM_EA_BEI_VF_BAR_0 9 614#define PCIM_EA_BEI_VF_BAR_5 14 615#define PCIM_EA_BEI_RESERVED 0xf /* Reserved - Treat like ENI */ 616#define PCIM_EA_PP 0x0000ff00 /* Primary Properties */ 617#define PCIM_EA_PP_OFFSET 8 618#define PCIM_EA_SP_OFFSET 16 619#define PCIM_EA_SP 0x00ff0000 /* Secondary Properties */ 620#define PCIM_EA_P_MEM 0x00 /* Non-Prefetch Memory */ 621#define PCIM_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */ 622#define PCIM_EA_P_IO 0x02 /* I/O Space */ 623#define PCIM_EA_P_VF_MEM_PREFETCH 0x03 /* VF Prefetchable Memory */ 624#define PCIM_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */ 625#define PCIM_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */ 626#define PCIM_EA_P_BRIDGE_MEM_PREFETCH 0x06 /* Bridge Prefetchable Memory */ 627#define PCIM_EA_P_BRIDGE_IO 0x07 /* Bridge I/O Space */ 628/* 0x08-0xfc reserved */ 629#define PCIM_EA_P_MEM_RESERVED 0xfd /* Reserved Memory */ 630#define PCIM_EA_P_IO_RESERVED 0xfe /* Reserved I/O Space */ 631#define PCIM_EA_P_UNAVAILABLE 0xff /* Entry Unavailable */ 632#define PCIM_EA_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */ 633#define PCIM_EA_ENABLE 0x80000000 /* Enable for this entry */ 634#define PCIM_EA_BASE 4 /* Base Address Offset */ 635#define PCIM_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */ 636/* bit 0 is reserved */ 637#define PCIM_EA_IS_64 0x00000002 /* 64-bit field flag */ 638#define PCIM_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ 639/* Bridge config register */ 640#define PCIM_EA_SEC_NR(reg) ((reg) & 0xff) 641#define PCIM_EA_SUB_NR(reg) (((reg) >> 8) & 0xff) 642 643/* PCI-X definitions */ 644 645/* For header type 0 devices */ 646#define PCIXR_COMMAND 0x2 647#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 648#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 649#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 650#define PCIXM_COMMAND_MAX_READ_512 0x0000 651#define PCIXM_COMMAND_MAX_READ_1024 0x0004 652#define PCIXM_COMMAND_MAX_READ_2048 0x0008 653#define PCIXM_COMMAND_MAX_READ_4096 0x000c 654#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 655#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 656#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 657#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 658#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 659#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 660#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 661#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 662#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 663#define PCIXM_COMMAND_VERSION 0x3000 664#define PCIXR_STATUS 0x4 665#define PCIXM_STATUS_DEVFN 0x000000FF 666#define PCIXM_STATUS_BUS 0x0000FF00 667#define PCIXM_STATUS_64BIT 0x00010000 668#define PCIXM_STATUS_133CAP 0x00020000 669#define PCIXM_STATUS_SC_DISCARDED 0x00040000 670#define PCIXM_STATUS_UNEXP_SC 0x00080000 671#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 672#define PCIXM_STATUS_MAX_READ 0x00600000 673#define PCIXM_STATUS_MAX_READ_512 0x00000000 674#define PCIXM_STATUS_MAX_READ_1024 0x00200000 675#define PCIXM_STATUS_MAX_READ_2048 0x00400000 676#define PCIXM_STATUS_MAX_READ_4096 0x00600000 677#define PCIXM_STATUS_MAX_SPLITS 0x03800000 678#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 679#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 680#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 681#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 682#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 683#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 684#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 685#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 686#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 687#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 688#define PCIXM_STATUS_266CAP 0x40000000 689#define PCIXM_STATUS_533CAP 0x80000000 690 691/* For header type 1 devices (PCI-X bridges) */ 692#define PCIXR_SEC_STATUS 0x2 693#define PCIXM_SEC_STATUS_64BIT 0x0001 694#define PCIXM_SEC_STATUS_133CAP 0x0002 695#define PCIXM_SEC_STATUS_SC_DISC 0x0004 696#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 697#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 698#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 699#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 700#define PCIXM_SEC_STATUS_VERSION 0x3000 701#define PCIXM_SEC_STATUS_266CAP 0x4000 702#define PCIXM_SEC_STATUS_533CAP 0x8000 703#define PCIXR_BRIDGE_STATUS 0x4 704#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 705#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 706#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 707#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 708#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 709#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 710#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 711#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 712#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 713#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 714#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 715 716/* HT (HyperTransport) Capability definitions */ 717#define PCIR_HT_COMMAND 0x2 718#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 719#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 720#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 721#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 722#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 723#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 724#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 725#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 726#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 727#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 728#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 729#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 730#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 731#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 732#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 733#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 734#define PCIM_HTCAP_PM 0xe000 /* 11100 */ 735#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 736 737/* HT MSI Mapping Capability definitions. */ 738#define PCIM_HTCMD_MSI_ENABLE 0x0001 739#define PCIM_HTCMD_MSI_FIXED 0x0002 740#define PCIR_HTMSI_ADDRESS_LO 0x4 741#define PCIR_HTMSI_ADDRESS_HI 0x8 742 743/* PCI Vendor capability definitions */ 744#define PCIR_VENDOR_LENGTH 0x2 745#define PCIR_VENDOR_DATA 0x3 746 747/* PCI Device capability definitions */ 748#define PCIR_DEVICE_LENGTH 0x2 749 750/* PCI EHCI Debug Port definitions */ 751#define PCIR_DEBUG_PORT 0x2 752#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 753#define PCIM_DEBUG_PORT_BAR 0xe000 754 755/* PCI-PCI Bridge Subvendor definitions */ 756#define PCIR_SUBVENDCAP_ID 0x4 757 758/* PCI Express definitions */ 759#define PCIER_FLAGS 0x2 760#define PCIEM_FLAGS_VERSION 0x000F 761#define PCIEM_FLAGS_TYPE 0x00F0 762#define PCIEM_TYPE_ENDPOINT 0x0000 763#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 764#define PCIEM_TYPE_ROOT_PORT 0x0040 765#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 766#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 767#define PCIEM_TYPE_PCI_BRIDGE 0x0070 768#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 769#define PCIEM_TYPE_ROOT_INT_EP 0x0090 770#define PCIEM_TYPE_ROOT_EC 0x00a0 771#define PCIEM_FLAGS_SLOT 0x0100 772#define PCIEM_FLAGS_IRQ 0x3e00 773#define PCIER_DEVICE_CAP 0x4 774#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 775#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 776#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 777#define PCIEM_CAP_L0S_LATENCY 0x000001c0 778#define PCIEM_CAP_L1_LATENCY 0x00000e00 779#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 780#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 781#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 782#define PCIEM_CAP_FLR 0x10000000 783#define PCIER_DEVICE_CTL 0x8 784#define PCIEM_CTL_COR_ENABLE 0x0001 785#define PCIEM_CTL_NFER_ENABLE 0x0002 786#define PCIEM_CTL_FER_ENABLE 0x0004 787#define PCIEM_CTL_URR_ENABLE 0x0008 788#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 789#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 790#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 791#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 792#define PCIEM_CTL_AUX_POWER_PM 0x0400 793#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 794#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 795#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 796#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 797#define PCIER_DEVICE_STA 0xa 798#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 799#define PCIEM_STA_NON_FATAL_ERROR 0x0002 800#define PCIEM_STA_FATAL_ERROR 0x0004 801#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 802#define PCIEM_STA_AUX_POWER 0x0010 803#define PCIEM_STA_TRANSACTION_PND 0x0020 804#define PCIER_LINK_CAP 0xc 805#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 806#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 807#define PCIEM_LINK_CAP_ASPM 0x00000c00 808#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 809#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 810#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 811#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 812#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 813#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 814#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 815#define PCIEM_LINK_CAP_PORT 0xff000000 816#define PCIER_LINK_CTL 0x10 817#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 818#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 819#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 820#define PCIEM_LINK_CTL_ASPMC 0x0003 821#define PCIEM_LINK_CTL_RCB 0x0008 822#define PCIEM_LINK_CTL_LINK_DIS 0x0010 823#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 824#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 825#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 826#define PCIEM_LINK_CTL_ECPM 0x0100 827#define PCIEM_LINK_CTL_HAWD 0x0200 828#define PCIEM_LINK_CTL_LBMIE 0x0400 829#define PCIEM_LINK_CTL_LABIE 0x0800 830#define PCIER_LINK_STA 0x12 831#define PCIEM_LINK_STA_SPEED 0x000f 832#define PCIEM_LINK_STA_WIDTH 0x03f0 833#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 834#define PCIEM_LINK_STA_TRAINING 0x0800 835#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 836#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 837#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 838#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 839#define PCIER_SLOT_CAP 0x14 840#define PCIEM_SLOT_CAP_APB 0x00000001 841#define PCIEM_SLOT_CAP_PCP 0x00000002 842#define PCIEM_SLOT_CAP_MRLSP 0x00000004 843#define PCIEM_SLOT_CAP_AIP 0x00000008 844#define PCIEM_SLOT_CAP_PIP 0x00000010 845#define PCIEM_SLOT_CAP_HPS 0x00000020 846#define PCIEM_SLOT_CAP_HPC 0x00000040 847#define PCIEM_SLOT_CAP_SPLV 0x00007f80 848#define PCIEM_SLOT_CAP_SPLS 0x00018000 849#define PCIEM_SLOT_CAP_EIP 0x00020000 850#define PCIEM_SLOT_CAP_NCCS 0x00040000 851#define PCIEM_SLOT_CAP_PSN 0xfff80000 852#define PCIER_SLOT_CTL 0x18 853#define PCIEM_SLOT_CTL_ABPE 0x0001 854#define PCIEM_SLOT_CTL_PFDE 0x0002 855#define PCIEM_SLOT_CTL_MRLSCE 0x0004 856#define PCIEM_SLOT_CTL_PDCE 0x0008 857#define PCIEM_SLOT_CTL_CCIE 0x0010 858#define PCIEM_SLOT_CTL_HPIE 0x0020 859#define PCIEM_SLOT_CTL_AIC 0x00c0 860#define PCIEM_SLOT_CTL_AI_ON 0x0040 861#define PCIEM_SLOT_CTL_AI_BLINK 0x0080 862#define PCIEM_SLOT_CTL_AI_OFF 0x00c0 863#define PCIEM_SLOT_CTL_PIC 0x0300 864#define PCIEM_SLOT_CTL_PI_ON 0x0100 865#define PCIEM_SLOT_CTL_PI_BLINK 0x0200 866#define PCIEM_SLOT_CTL_PI_OFF 0x0300 867#define PCIEM_SLOT_CTL_PCC 0x0400 868#define PCIEM_SLOT_CTL_PC_ON 0x0000 869#define PCIEM_SLOT_CTL_PC_OFF 0x0400 870#define PCIEM_SLOT_CTL_EIC 0x0800 871#define PCIEM_SLOT_CTL_DLLSCE 0x1000 872#define PCIER_SLOT_STA 0x1a 873#define PCIEM_SLOT_STA_ABP 0x0001 874#define PCIEM_SLOT_STA_PFD 0x0002 875#define PCIEM_SLOT_STA_MRLSC 0x0004 876#define PCIEM_SLOT_STA_PDC 0x0008 877#define PCIEM_SLOT_STA_CC 0x0010 878#define PCIEM_SLOT_STA_MRLSS 0x0020 879#define PCIEM_SLOT_STA_PDS 0x0040 880#define PCIEM_SLOT_STA_EIS 0x0080 881#define PCIEM_SLOT_STA_DLLSC 0x0100 882#define PCIER_ROOT_CTL 0x1c 883#define PCIEM_ROOT_CTL_SERR_CORR 0x0001 884#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 885#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 886#define PCIEM_ROOT_CTL_PME 0x0008 887#define PCIEM_ROOT_CTL_CRS_VIS 0x0010 888#define PCIER_ROOT_CAP 0x1e 889#define PCIEM_ROOT_CAP_CRS_VIS 0x0001 890#define PCIER_ROOT_STA 0x20 891#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 892#define PCIEM_ROOT_STA_PME_STATUS 0x00010000 893#define PCIEM_ROOT_STA_PME_PEND 0x00020000 894#define PCIER_DEVICE_CAP2 0x24 895#define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f 896#define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001 897#define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002 898#define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004 899#define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008 900#define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010 901#define PCIEM_CAP2_ARI 0x00000020 902#define PCIER_DEVICE_CTL2 0x28 903#define PCIEM_CTL2_COMP_TIMO_VAL 0x000f 904#define PCIEM_CTL2_COMP_TIMO_50MS 0x0000 905#define PCIEM_CTL2_COMP_TIMO_100US 0x0001 906#define PCIEM_CTL2_COMP_TIMO_10MS 0x0002 907#define PCIEM_CTL2_COMP_TIMO_55MS 0x0005 908#define PCIEM_CTL2_COMP_TIMO_210MS 0x0006 909#define PCIEM_CTL2_COMP_TIMO_900MS 0x0009 910#define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a 911#define PCIEM_CTL2_COMP_TIMO_13S 0x000d 912#define PCIEM_CTL2_COMP_TIMO_64S 0x000e 913#define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010 914#define PCIEM_CTL2_ARI 0x0020 915#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 916#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 917#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 918#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 919#define PCIEM_CTL2_LTR_ENABLE 0x0400 920#define PCIEM_CTL2_OBFF 0x6000 921#define PCIEM_OBFF_DISABLE 0x0000 922#define PCIEM_OBFF_MSGA_ENABLE 0x2000 923#define PCIEM_OBFF_MSGB_ENABLE 0x4000 924#define PCIEM_OBFF_WAKE_ENABLE 0x6000 925#define PCIEM_CTL2_END2END_TLP 0x8000 926#define PCIER_DEVICE_STA2 0x2a 927#define PCIER_LINK_CAP2 0x2c 928#define PCIER_LINK_CTL2 0x30 929#define PCIER_LINK_STA2 0x32 930#define PCIER_SLOT_CAP2 0x34 931#define PCIER_SLOT_CTL2 0x38 932#define PCIER_SLOT_STA2 0x3a 933 934/* MSI-X definitions */ 935#define PCIR_MSIX_CTRL 0x2 936#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 937#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 938#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 939#define PCIR_MSIX_TABLE 0x4 940#define PCIR_MSIX_PBA 0x8 941#define PCIM_MSIX_BIR_MASK 0x7 942#define PCIM_MSIX_BIR_BAR_10 0 943#define PCIM_MSIX_BIR_BAR_14 1 944#define PCIM_MSIX_BIR_BAR_18 2 945#define PCIM_MSIX_BIR_BAR_1C 3 946#define PCIM_MSIX_BIR_BAR_20 4 947#define PCIM_MSIX_BIR_BAR_24 5 948#define PCIM_MSIX_VCTRL_MASK 0x1 949 950/* PCI Advanced Features definitions */ 951#define PCIR_PCIAF_CAP 0x3 952#define PCIM_PCIAFCAP_TP 0x01 953#define PCIM_PCIAFCAP_FLR 0x02 954#define PCIR_PCIAF_CTRL 0x4 955#define PCIR_PCIAFCTRL_FLR 0x01 956#define PCIR_PCIAF_STATUS 0x5 957#define PCIR_PCIAFSTATUS_TP 0x01 958 959/* Advanced Error Reporting */ 960#define PCIR_AER_UC_STATUS 0x04 961#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 962#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 963#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 964#define PCIM_AER_UC_POISONED_TLP 0x00001000 965#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 966#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 967#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 968#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 969#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 970#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 971#define PCIM_AER_UC_ECRC_ERROR 0x00080000 972#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 973#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 974#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 975#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 976#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 977#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 978#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 979#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 980#define PCIR_AER_COR_STATUS 0x10 981#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 982#define PCIM_AER_COR_BAD_TLP 0x00000040 983#define PCIM_AER_COR_BAD_DLLP 0x00000080 984#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 985#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 986#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 987#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 988#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 989#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 990#define PCIR_AER_CAP_CONTROL 0x18 991#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 992#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 993#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 994#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 995#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 996#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 997#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 998#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 999#define PCIR_AER_HEADER_LOG 0x1c 1000#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 1001#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 1002#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 1003#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 1004#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 1005#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 1006#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 1007#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 1008#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 1009#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 1010#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 1011#define PCIM_AER_ROOTERR_F_ERR 0x00000040 1012#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 1013#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 1014#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 1015#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 1016 1017/* Virtual Channel definitions */ 1018#define PCIR_VC_CAP1 0x04 1019#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 1020#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 1021#define PCIR_VC_CAP2 0x08 1022#define PCIR_VC_CONTROL 0x0C 1023#define PCIR_VC_STATUS 0x0E 1024#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 1025#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 1026#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 1027 1028/* Serial Number definitions */ 1029#define PCIR_SERIAL_LOW 0x04 1030#define PCIR_SERIAL_HIGH 0x08 1031 1032/* SR-IOV definitions */ 1033#define PCIR_SRIOV_CTL 0x08 1034#define PCIM_SRIOV_VF_EN 0x01 1035#define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */ 1036#define PCIM_SRIOV_ARI_EN 0x10 1037#define PCIR_SRIOV_TOTAL_VFS 0x0E 1038#define PCIR_SRIOV_NUM_VFS 0x10 1039#define PCIR_SRIOV_VF_OFF 0x14 1040#define PCIR_SRIOV_VF_STRIDE 0x16 1041#define PCIR_SRIOV_VF_DID 0x1A 1042#define PCIR_SRIOV_PAGE_CAP 0x1C 1043#define PCIR_SRIOV_PAGE_SIZE 0x20 1044 1045#define PCI_SRIOV_BASE_PAGE_SHIFT 12 1046 1047#define PCIR_SRIOV_BARS 0x24 1048#define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) 1049 1050