pcireg.h revision 264007
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 264007 2014-04-01 15:47:24Z rstone $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42/* some PCI bus constants */ 43#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44#define PCI_BUSMAX 255 /* highest supported bus number */ 45#define PCI_SLOTMAX 31 /* highest supported slot number */ 46#define PCI_FUNCMAX 7 /* highest supported function number */ 47#define PCI_REGMAX 255 /* highest supported config register addr. */ 48#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49#define PCI_MAXHDRTYPE 2 50 51#define PCI_RID_BUS_SHIFT 8 52#define PCI_RID_SLOT_SHIFT 3 53#define PCI_RID_FUNC_SHIFT 0 54 55#define PCI_RID(bus, slot, func) \ 56 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 57 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 58 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 59 60#define PCI_ARI_RID(bus, func) \ 61 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 62 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 63 64#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 65#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 66#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 67 68/* PCI config header registers for all devices */ 69 70#define PCIR_DEVVENDOR 0x00 71#define PCIR_VENDOR 0x00 72#define PCIR_DEVICE 0x02 73#define PCIR_COMMAND 0x04 74#define PCIM_CMD_PORTEN 0x0001 75#define PCIM_CMD_MEMEN 0x0002 76#define PCIM_CMD_BUSMASTEREN 0x0004 77#define PCIM_CMD_SPECIALEN 0x0008 78#define PCIM_CMD_MWRICEN 0x0010 79#define PCIM_CMD_PERRESPEN 0x0040 80#define PCIM_CMD_SERRESPEN 0x0100 81#define PCIM_CMD_BACKTOBACK 0x0200 82#define PCIM_CMD_INTxDIS 0x0400 83#define PCIR_STATUS 0x06 84#define PCIM_STATUS_INTxSTATE 0x0008 85#define PCIM_STATUS_CAPPRESENT 0x0010 86#define PCIM_STATUS_66CAPABLE 0x0020 87#define PCIM_STATUS_BACKTOBACK 0x0080 88#define PCIM_STATUS_MDPERR 0x0100 89#define PCIM_STATUS_SEL_FAST 0x0000 90#define PCIM_STATUS_SEL_MEDIMUM 0x0200 91#define PCIM_STATUS_SEL_SLOW 0x0400 92#define PCIM_STATUS_SEL_MASK 0x0600 93#define PCIM_STATUS_STABORT 0x0800 94#define PCIM_STATUS_RTABORT 0x1000 95#define PCIM_STATUS_RMABORT 0x2000 96#define PCIM_STATUS_SERR 0x4000 97#define PCIM_STATUS_PERR 0x8000 98#define PCIR_REVID 0x08 99#define PCIR_PROGIF 0x09 100#define PCIR_SUBCLASS 0x0a 101#define PCIR_CLASS 0x0b 102#define PCIR_CACHELNSZ 0x0c 103#define PCIR_LATTIMER 0x0d 104#define PCIR_HDRTYPE 0x0e 105#define PCIM_HDRTYPE 0x7f 106#define PCIM_HDRTYPE_NORMAL 0x00 107#define PCIM_HDRTYPE_BRIDGE 0x01 108#define PCIM_HDRTYPE_CARDBUS 0x02 109#define PCIM_MFDEV 0x80 110#define PCIR_BIST 0x0f 111 112/* Capability Register Offsets */ 113 114#define PCICAP_ID 0x0 115#define PCICAP_NEXTPTR 0x1 116 117/* Capability Identification Numbers */ 118 119#define PCIY_PMG 0x01 /* PCI Power Management */ 120#define PCIY_AGP 0x02 /* AGP */ 121#define PCIY_VPD 0x03 /* Vital Product Data */ 122#define PCIY_SLOTID 0x04 /* Slot Identification */ 123#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 124#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 125#define PCIY_PCIX 0x07 /* PCI-X */ 126#define PCIY_HT 0x08 /* HyperTransport */ 127#define PCIY_VENDOR 0x09 /* Vendor Unique */ 128#define PCIY_DEBUG 0x0a /* Debug port */ 129#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 130#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 131#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 132#define PCIY_AGP8X 0x0e /* AGP 8x */ 133#define PCIY_SECDEV 0x0f /* Secure Device */ 134#define PCIY_EXPRESS 0x10 /* PCI Express */ 135#define PCIY_MSIX 0x11 /* MSI-X */ 136#define PCIY_SATA 0x12 /* SATA */ 137#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 138 139/* Extended Capability Register Fields */ 140 141#define PCIR_EXTCAP 0x100 142#define PCIM_EXTCAP_ID 0x0000ffff 143#define PCIM_EXTCAP_VER 0x000f0000 144#define PCIM_EXTCAP_NEXTPTR 0xfff00000 145#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 146#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 147#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 148 149/* Extended Capability Identification Numbers */ 150 151#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 152#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 153#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 154#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 155#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 156#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 157#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 158#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 159#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 160#define PCIZ_RCRB 0x000a /* RCRB Header */ 161#define PCIZ_VENDOR 0x000b /* Vendor Unique */ 162#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 163#define PCIZ_ACS 0x000d /* Access Control Services */ 164#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 165#define PCIZ_ATS 0x000f /* Address Translation Services */ 166#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 167#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 168#define PCIZ_MULTICAST 0x0012 /* Multicast */ 169#define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 170#define PCIZ_AMD 0x0014 /* Reserved for AMD */ 171#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 172#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 173#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 174#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 175#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 176#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 177#define PCIZ_PASID 0x001b /* Process Address Space ID */ 178#define PCIZ_LN_REQ 0x001c /* LN Requester */ 179#define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 180#define PCIZ_L1PM 0x001e /* L1 PM Substates */ 181 182/* config registers for header type 0 devices */ 183 184#define PCIR_BARS 0x10 185#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 186#define PCIR_MAX_BAR_0 5 187#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 188#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 189#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 190#define PCIM_BAR_SPACE 0x00000001 191#define PCIM_BAR_MEM_SPACE 0 192#define PCIM_BAR_IO_SPACE 1 193#define PCIM_BAR_MEM_TYPE 0x00000006 194#define PCIM_BAR_MEM_32 0 195#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 196#define PCIM_BAR_MEM_64 4 197#define PCIM_BAR_MEM_PREFETCH 0x00000008 198#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 199#define PCIM_BAR_IO_RESERVED 0x00000002 200#define PCIM_BAR_IO_BASE 0xfffffffc 201#define PCIR_CIS 0x28 202#define PCIM_CIS_ASI_MASK 0x00000007 203#define PCIM_CIS_ASI_CONFIG 0 204#define PCIM_CIS_ASI_BAR0 1 205#define PCIM_CIS_ASI_BAR1 2 206#define PCIM_CIS_ASI_BAR2 3 207#define PCIM_CIS_ASI_BAR3 4 208#define PCIM_CIS_ASI_BAR4 5 209#define PCIM_CIS_ASI_BAR5 6 210#define PCIM_CIS_ASI_ROM 7 211#define PCIM_CIS_ADDR_MASK 0x0ffffff8 212#define PCIM_CIS_ROM_MASK 0xf0000000 213#define PCIM_CIS_CONFIG_MASK 0xff 214#define PCIR_SUBVEND_0 0x2c 215#define PCIR_SUBDEV_0 0x2e 216#define PCIR_BIOS 0x30 217#define PCIM_BIOS_ENABLE 0x01 218#define PCIM_BIOS_ADDR_MASK 0xfffff800 219#define PCIR_CAP_PTR 0x34 220#define PCIR_INTLINE 0x3c 221#define PCIR_INTPIN 0x3d 222#define PCIR_MINGNT 0x3e 223#define PCIR_MAXLAT 0x3f 224 225/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 226 227#define PCIR_MAX_BAR_1 1 228#define PCIR_SECSTAT_1 0x1e 229 230#define PCIR_PRIBUS_1 0x18 231#define PCIR_SECBUS_1 0x19 232#define PCIR_SUBBUS_1 0x1a 233#define PCIR_SECLAT_1 0x1b 234 235#define PCIR_IOBASEL_1 0x1c 236#define PCIR_IOLIMITL_1 0x1d 237#define PCIR_IOBASEH_1 0x30 238#define PCIR_IOLIMITH_1 0x32 239#define PCIM_BRIO_16 0x0 240#define PCIM_BRIO_32 0x1 241#define PCIM_BRIO_MASK 0xf 242 243#define PCIR_MEMBASE_1 0x20 244#define PCIR_MEMLIMIT_1 0x22 245 246#define PCIR_PMBASEL_1 0x24 247#define PCIR_PMLIMITL_1 0x26 248#define PCIR_PMBASEH_1 0x28 249#define PCIR_PMLIMITH_1 0x2c 250#define PCIM_BRPM_32 0x0 251#define PCIM_BRPM_64 0x1 252#define PCIM_BRPM_MASK 0xf 253 254#define PCIR_BIOS_1 0x38 255#define PCIR_BRIDGECTL_1 0x3e 256 257/* config registers for header type 2 (CardBus) devices */ 258 259#define PCIR_MAX_BAR_2 0 260#define PCIR_CAP_PTR_2 0x14 261#define PCIR_SECSTAT_2 0x16 262 263#define PCIR_PRIBUS_2 0x18 264#define PCIR_SECBUS_2 0x19 265#define PCIR_SUBBUS_2 0x1a 266#define PCIR_SECLAT_2 0x1b 267 268#define PCIR_MEMBASE0_2 0x1c 269#define PCIR_MEMLIMIT0_2 0x20 270#define PCIR_MEMBASE1_2 0x24 271#define PCIR_MEMLIMIT1_2 0x28 272#define PCIR_IOBASE0_2 0x2c 273#define PCIR_IOLIMIT0_2 0x30 274#define PCIR_IOBASE1_2 0x34 275#define PCIR_IOLIMIT1_2 0x38 276 277#define PCIR_BRIDGECTL_2 0x3e 278 279#define PCIR_SUBVEND_2 0x40 280#define PCIR_SUBDEV_2 0x42 281 282#define PCIR_PCCARDIF_2 0x44 283 284/* PCI device class, subclass and programming interface definitions */ 285 286#define PCIC_OLD 0x00 287#define PCIS_OLD_NONVGA 0x00 288#define PCIS_OLD_VGA 0x01 289 290#define PCIC_STORAGE 0x01 291#define PCIS_STORAGE_SCSI 0x00 292#define PCIS_STORAGE_IDE 0x01 293#define PCIP_STORAGE_IDE_MODEPRIM 0x01 294#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 295#define PCIP_STORAGE_IDE_MODESEC 0x04 296#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 297#define PCIP_STORAGE_IDE_MASTERDEV 0x80 298#define PCIS_STORAGE_FLOPPY 0x02 299#define PCIS_STORAGE_IPI 0x03 300#define PCIS_STORAGE_RAID 0x04 301#define PCIS_STORAGE_ATA_ADMA 0x05 302#define PCIS_STORAGE_SATA 0x06 303#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 304#define PCIS_STORAGE_SAS 0x07 305#define PCIS_STORAGE_NVM 0x08 306#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 307#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 308#define PCIS_STORAGE_OTHER 0x80 309 310#define PCIC_NETWORK 0x02 311#define PCIS_NETWORK_ETHERNET 0x00 312#define PCIS_NETWORK_TOKENRING 0x01 313#define PCIS_NETWORK_FDDI 0x02 314#define PCIS_NETWORK_ATM 0x03 315#define PCIS_NETWORK_ISDN 0x04 316#define PCIS_NETWORK_WORLDFIP 0x05 317#define PCIS_NETWORK_PICMG 0x06 318#define PCIS_NETWORK_OTHER 0x80 319 320#define PCIC_DISPLAY 0x03 321#define PCIS_DISPLAY_VGA 0x00 322#define PCIS_DISPLAY_XGA 0x01 323#define PCIS_DISPLAY_3D 0x02 324#define PCIS_DISPLAY_OTHER 0x80 325 326#define PCIC_MULTIMEDIA 0x04 327#define PCIS_MULTIMEDIA_VIDEO 0x00 328#define PCIS_MULTIMEDIA_AUDIO 0x01 329#define PCIS_MULTIMEDIA_TELE 0x02 330#define PCIS_MULTIMEDIA_HDA 0x03 331#define PCIS_MULTIMEDIA_OTHER 0x80 332 333#define PCIC_MEMORY 0x05 334#define PCIS_MEMORY_RAM 0x00 335#define PCIS_MEMORY_FLASH 0x01 336#define PCIS_MEMORY_OTHER 0x80 337 338#define PCIC_BRIDGE 0x06 339#define PCIS_BRIDGE_HOST 0x00 340#define PCIS_BRIDGE_ISA 0x01 341#define PCIS_BRIDGE_EISA 0x02 342#define PCIS_BRIDGE_MCA 0x03 343#define PCIS_BRIDGE_PCI 0x04 344#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 345#define PCIS_BRIDGE_PCMCIA 0x05 346#define PCIS_BRIDGE_NUBUS 0x06 347#define PCIS_BRIDGE_CARDBUS 0x07 348#define PCIS_BRIDGE_RACEWAY 0x08 349#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 350#define PCIS_BRIDGE_INFINIBAND 0x0a 351#define PCIS_BRIDGE_OTHER 0x80 352 353#define PCIC_SIMPLECOMM 0x07 354#define PCIS_SIMPLECOMM_UART 0x00 355#define PCIP_SIMPLECOMM_UART_8250 0x00 356#define PCIP_SIMPLECOMM_UART_16450A 0x01 357#define PCIP_SIMPLECOMM_UART_16550A 0x02 358#define PCIP_SIMPLECOMM_UART_16650A 0x03 359#define PCIP_SIMPLECOMM_UART_16750A 0x04 360#define PCIP_SIMPLECOMM_UART_16850A 0x05 361#define PCIP_SIMPLECOMM_UART_16950A 0x06 362#define PCIS_SIMPLECOMM_PAR 0x01 363#define PCIS_SIMPLECOMM_MULSER 0x02 364#define PCIS_SIMPLECOMM_MODEM 0x03 365#define PCIS_SIMPLECOMM_GPIB 0x04 366#define PCIS_SIMPLECOMM_SMART_CARD 0x05 367#define PCIS_SIMPLECOMM_OTHER 0x80 368 369#define PCIC_BASEPERIPH 0x08 370#define PCIS_BASEPERIPH_PIC 0x00 371#define PCIP_BASEPERIPH_PIC_8259A 0x00 372#define PCIP_BASEPERIPH_PIC_ISA 0x01 373#define PCIP_BASEPERIPH_PIC_EISA 0x02 374#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 375#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 376#define PCIS_BASEPERIPH_DMA 0x01 377#define PCIS_BASEPERIPH_TIMER 0x02 378#define PCIS_BASEPERIPH_RTC 0x03 379#define PCIS_BASEPERIPH_PCIHOT 0x04 380#define PCIS_BASEPERIPH_SDHC 0x05 381#define PCIS_BASEPERIPH_OTHER 0x80 382 383#define PCIC_INPUTDEV 0x09 384#define PCIS_INPUTDEV_KEYBOARD 0x00 385#define PCIS_INPUTDEV_DIGITIZER 0x01 386#define PCIS_INPUTDEV_MOUSE 0x02 387#define PCIS_INPUTDEV_SCANNER 0x03 388#define PCIS_INPUTDEV_GAMEPORT 0x04 389#define PCIS_INPUTDEV_OTHER 0x80 390 391#define PCIC_DOCKING 0x0a 392#define PCIS_DOCKING_GENERIC 0x00 393#define PCIS_DOCKING_OTHER 0x80 394 395#define PCIC_PROCESSOR 0x0b 396#define PCIS_PROCESSOR_386 0x00 397#define PCIS_PROCESSOR_486 0x01 398#define PCIS_PROCESSOR_PENTIUM 0x02 399#define PCIS_PROCESSOR_ALPHA 0x10 400#define PCIS_PROCESSOR_POWERPC 0x20 401#define PCIS_PROCESSOR_MIPS 0x30 402#define PCIS_PROCESSOR_COPROC 0x40 403 404#define PCIC_SERIALBUS 0x0c 405#define PCIS_SERIALBUS_FW 0x00 406#define PCIS_SERIALBUS_ACCESS 0x01 407#define PCIS_SERIALBUS_SSA 0x02 408#define PCIS_SERIALBUS_USB 0x03 409#define PCIP_SERIALBUS_USB_UHCI 0x00 410#define PCIP_SERIALBUS_USB_OHCI 0x10 411#define PCIP_SERIALBUS_USB_EHCI 0x20 412#define PCIP_SERIALBUS_USB_XHCI 0x30 413#define PCIP_SERIALBUS_USB_DEVICE 0xfe 414#define PCIS_SERIALBUS_FC 0x04 415#define PCIS_SERIALBUS_SMBUS 0x05 416#define PCIS_SERIALBUS_INFINIBAND 0x06 417#define PCIS_SERIALBUS_IPMI 0x07 418#define PCIP_SERIALBUS_IPMI_SMIC 0x00 419#define PCIP_SERIALBUS_IPMI_KCS 0x01 420#define PCIP_SERIALBUS_IPMI_BT 0x02 421#define PCIS_SERIALBUS_SERCOS 0x08 422#define PCIS_SERIALBUS_CANBUS 0x09 423 424#define PCIC_WIRELESS 0x0d 425#define PCIS_WIRELESS_IRDA 0x00 426#define PCIS_WIRELESS_IR 0x01 427#define PCIS_WIRELESS_RF 0x10 428#define PCIS_WIRELESS_BLUETOOTH 0x11 429#define PCIS_WIRELESS_BROADBAND 0x12 430#define PCIS_WIRELESS_80211A 0x20 431#define PCIS_WIRELESS_80211B 0x21 432#define PCIS_WIRELESS_OTHER 0x80 433 434#define PCIC_INTELLIIO 0x0e 435#define PCIS_INTELLIIO_I2O 0x00 436 437#define PCIC_SATCOM 0x0f 438#define PCIS_SATCOM_TV 0x01 439#define PCIS_SATCOM_AUDIO 0x02 440#define PCIS_SATCOM_VOICE 0x03 441#define PCIS_SATCOM_DATA 0x04 442 443#define PCIC_CRYPTO 0x10 444#define PCIS_CRYPTO_NETCOMP 0x00 445#define PCIS_CRYPTO_ENTERTAIN 0x10 446#define PCIS_CRYPTO_OTHER 0x80 447 448#define PCIC_DASP 0x11 449#define PCIS_DASP_DPIO 0x00 450#define PCIS_DASP_PERFCNTRS 0x01 451#define PCIS_DASP_COMM_SYNC 0x10 452#define PCIS_DASP_MGMT_CARD 0x20 453#define PCIS_DASP_OTHER 0x80 454 455#define PCIC_OTHER 0xff 456 457/* Bridge Control Values. */ 458#define PCIB_BCR_PERR_ENABLE 0x0001 459#define PCIB_BCR_SERR_ENABLE 0x0002 460#define PCIB_BCR_ISA_ENABLE 0x0004 461#define PCIB_BCR_VGA_ENABLE 0x0008 462#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 463#define PCIB_BCR_SECBUS_RESET 0x0040 464#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 465#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 466#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 467#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 468#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 469 470/* PCI power manangement */ 471#define PCIR_POWER_CAP 0x2 472#define PCIM_PCAP_SPEC 0x0007 473#define PCIM_PCAP_PMEREQCLK 0x0008 474#define PCIM_PCAP_DEVSPECINIT 0x0020 475#define PCIM_PCAP_AUXPWR_0 0x0000 476#define PCIM_PCAP_AUXPWR_55 0x0040 477#define PCIM_PCAP_AUXPWR_100 0x0080 478#define PCIM_PCAP_AUXPWR_160 0x00c0 479#define PCIM_PCAP_AUXPWR_220 0x0100 480#define PCIM_PCAP_AUXPWR_270 0x0140 481#define PCIM_PCAP_AUXPWR_320 0x0180 482#define PCIM_PCAP_AUXPWR_375 0x01c0 483#define PCIM_PCAP_AUXPWRMASK 0x01c0 484#define PCIM_PCAP_D1SUPP 0x0200 485#define PCIM_PCAP_D2SUPP 0x0400 486#define PCIM_PCAP_D0PME 0x0800 487#define PCIM_PCAP_D1PME 0x1000 488#define PCIM_PCAP_D2PME 0x2000 489#define PCIM_PCAP_D3PME_HOT 0x4000 490#define PCIM_PCAP_D3PME_COLD 0x8000 491 492#define PCIR_POWER_STATUS 0x4 493#define PCIM_PSTAT_D0 0x0000 494#define PCIM_PSTAT_D1 0x0001 495#define PCIM_PSTAT_D2 0x0002 496#define PCIM_PSTAT_D3 0x0003 497#define PCIM_PSTAT_DMASK 0x0003 498#define PCIM_PSTAT_NOSOFTRESET 0x0008 499#define PCIM_PSTAT_PMEENABLE 0x0100 500#define PCIM_PSTAT_D0POWER 0x0000 501#define PCIM_PSTAT_D1POWER 0x0200 502#define PCIM_PSTAT_D2POWER 0x0400 503#define PCIM_PSTAT_D3POWER 0x0600 504#define PCIM_PSTAT_D0HEAT 0x0800 505#define PCIM_PSTAT_D1HEAT 0x0a00 506#define PCIM_PSTAT_D2HEAT 0x0c00 507#define PCIM_PSTAT_D3HEAT 0x0e00 508#define PCIM_PSTAT_DATASELMASK 0x1e00 509#define PCIM_PSTAT_DATAUNKN 0x0000 510#define PCIM_PSTAT_DATADIV10 0x2000 511#define PCIM_PSTAT_DATADIV100 0x4000 512#define PCIM_PSTAT_DATADIV1000 0x6000 513#define PCIM_PSTAT_DATADIVMASK 0x6000 514#define PCIM_PSTAT_PME 0x8000 515 516#define PCIR_POWER_BSE 0x6 517#define PCIM_PMCSR_BSE_D3B3 0x00 518#define PCIM_PMCSR_BSE_D3B2 0x40 519#define PCIM_PMCSR_BSE_BPCCE 0x80 520 521#define PCIR_POWER_DATA 0x7 522 523/* VPD capability registers */ 524#define PCIR_VPD_ADDR 0x2 525#define PCIR_VPD_DATA 0x4 526 527/* PCI Message Signalled Interrupts (MSI) */ 528#define PCIR_MSI_CTRL 0x2 529#define PCIM_MSICTRL_VECTOR 0x0100 530#define PCIM_MSICTRL_64BIT 0x0080 531#define PCIM_MSICTRL_MME_MASK 0x0070 532#define PCIM_MSICTRL_MME_1 0x0000 533#define PCIM_MSICTRL_MME_2 0x0010 534#define PCIM_MSICTRL_MME_4 0x0020 535#define PCIM_MSICTRL_MME_8 0x0030 536#define PCIM_MSICTRL_MME_16 0x0040 537#define PCIM_MSICTRL_MME_32 0x0050 538#define PCIM_MSICTRL_MMC_MASK 0x000E 539#define PCIM_MSICTRL_MMC_1 0x0000 540#define PCIM_MSICTRL_MMC_2 0x0002 541#define PCIM_MSICTRL_MMC_4 0x0004 542#define PCIM_MSICTRL_MMC_8 0x0006 543#define PCIM_MSICTRL_MMC_16 0x0008 544#define PCIM_MSICTRL_MMC_32 0x000A 545#define PCIM_MSICTRL_MSI_ENABLE 0x0001 546#define PCIR_MSI_ADDR 0x4 547#define PCIR_MSI_ADDR_HIGH 0x8 548#define PCIR_MSI_DATA 0x8 549#define PCIR_MSI_DATA_64BIT 0xc 550#define PCIR_MSI_MASK 0x10 551#define PCIR_MSI_PENDING 0x14 552 553/* PCI-X definitions */ 554 555/* For header type 0 devices */ 556#define PCIXR_COMMAND 0x2 557#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 558#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 559#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 560#define PCIXM_COMMAND_MAX_READ_512 0x0000 561#define PCIXM_COMMAND_MAX_READ_1024 0x0004 562#define PCIXM_COMMAND_MAX_READ_2048 0x0008 563#define PCIXM_COMMAND_MAX_READ_4096 0x000c 564#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 565#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 566#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 567#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 568#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 569#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 570#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 571#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 572#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 573#define PCIXM_COMMAND_VERSION 0x3000 574#define PCIXR_STATUS 0x4 575#define PCIXM_STATUS_DEVFN 0x000000FF 576#define PCIXM_STATUS_BUS 0x0000FF00 577#define PCIXM_STATUS_64BIT 0x00010000 578#define PCIXM_STATUS_133CAP 0x00020000 579#define PCIXM_STATUS_SC_DISCARDED 0x00040000 580#define PCIXM_STATUS_UNEXP_SC 0x00080000 581#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 582#define PCIXM_STATUS_MAX_READ 0x00600000 583#define PCIXM_STATUS_MAX_READ_512 0x00000000 584#define PCIXM_STATUS_MAX_READ_1024 0x00200000 585#define PCIXM_STATUS_MAX_READ_2048 0x00400000 586#define PCIXM_STATUS_MAX_READ_4096 0x00600000 587#define PCIXM_STATUS_MAX_SPLITS 0x03800000 588#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 589#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 590#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 591#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 592#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 593#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 594#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 595#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 596#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 597#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 598#define PCIXM_STATUS_266CAP 0x40000000 599#define PCIXM_STATUS_533CAP 0x80000000 600 601/* For header type 1 devices (PCI-X bridges) */ 602#define PCIXR_SEC_STATUS 0x2 603#define PCIXM_SEC_STATUS_64BIT 0x0001 604#define PCIXM_SEC_STATUS_133CAP 0x0002 605#define PCIXM_SEC_STATUS_SC_DISC 0x0004 606#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 607#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 608#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 609#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 610#define PCIXM_SEC_STATUS_VERSION 0x3000 611#define PCIXM_SEC_STATUS_266CAP 0x4000 612#define PCIXM_SEC_STATUS_533CAP 0x8000 613#define PCIXR_BRIDGE_STATUS 0x4 614#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 615#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 616#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 617#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 618#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 619#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 620#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 621#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 622#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 623#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 624#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 625 626/* HT (HyperTransport) Capability definitions */ 627#define PCIR_HT_COMMAND 0x2 628#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 629#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 630#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 631#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 632#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 633#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 634#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 635#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 636#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 637#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 638#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 639#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 640#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 641#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 642#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 643#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 644#define PCIM_HTCAP_PM 0xe000 /* 11100 */ 645#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 646 647/* HT MSI Mapping Capability definitions. */ 648#define PCIM_HTCMD_MSI_ENABLE 0x0001 649#define PCIM_HTCMD_MSI_FIXED 0x0002 650#define PCIR_HTMSI_ADDRESS_LO 0x4 651#define PCIR_HTMSI_ADDRESS_HI 0x8 652 653/* PCI Vendor capability definitions */ 654#define PCIR_VENDOR_LENGTH 0x2 655#define PCIR_VENDOR_DATA 0x3 656 657/* PCI EHCI Debug Port definitions */ 658#define PCIR_DEBUG_PORT 0x2 659#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 660#define PCIM_DEBUG_PORT_BAR 0xe000 661 662/* PCI-PCI Bridge Subvendor definitions */ 663#define PCIR_SUBVENDCAP_ID 0x4 664 665/* PCI Express definitions */ 666#define PCIER_FLAGS 0x2 667#define PCIEM_FLAGS_VERSION 0x000F 668#define PCIEM_FLAGS_TYPE 0x00F0 669#define PCIEM_TYPE_ENDPOINT 0x0000 670#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 671#define PCIEM_TYPE_ROOT_PORT 0x0040 672#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 673#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 674#define PCIEM_TYPE_PCI_BRIDGE 0x0070 675#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 676#define PCIEM_TYPE_ROOT_INT_EP 0x0090 677#define PCIEM_TYPE_ROOT_EC 0x00a0 678#define PCIEM_FLAGS_SLOT 0x0100 679#define PCIEM_FLAGS_IRQ 0x3e00 680#define PCIER_DEVICE_CAP 0x4 681#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 682#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 683#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 684#define PCIEM_CAP_L0S_LATENCY 0x000001c0 685#define PCIEM_CAP_L1_LATENCY 0x00000e00 686#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 687#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 688#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 689#define PCIEM_CAP_FLR 0x10000000 690#define PCIER_DEVICE_CTL 0x8 691#define PCIEM_CTL_COR_ENABLE 0x0001 692#define PCIEM_CTL_NFER_ENABLE 0x0002 693#define PCIEM_CTL_FER_ENABLE 0x0004 694#define PCIEM_CTL_URR_ENABLE 0x0008 695#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 696#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 697#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 698#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 699#define PCIEM_CTL_AUX_POWER_PM 0x0400 700#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 701#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 702#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 703#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 704#define PCIER_DEVICE_STA 0xa 705#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 706#define PCIEM_STA_NON_FATAL_ERROR 0x0002 707#define PCIEM_STA_FATAL_ERROR 0x0004 708#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 709#define PCIEM_STA_AUX_POWER 0x0010 710#define PCIEM_STA_TRANSACTION_PND 0x0020 711#define PCIER_LINK_CAP 0xc 712#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 713#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 714#define PCIEM_LINK_CAP_ASPM 0x00000c00 715#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 716#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 717#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 718#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 719#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 720#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 721#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 722#define PCIEM_LINK_CAP_PORT 0xff000000 723#define PCIER_LINK_CTL 0x10 724#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 725#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 726#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 727#define PCIEM_LINK_CTL_ASPMC 0x0003 728#define PCIEM_LINK_CTL_RCB 0x0008 729#define PCIEM_LINK_CTL_LINK_DIS 0x0010 730#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 731#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 732#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 733#define PCIEM_LINK_CTL_ECPM 0x0100 734#define PCIEM_LINK_CTL_HAWD 0x0200 735#define PCIEM_LINK_CTL_LBMIE 0x0400 736#define PCIEM_LINK_CTL_LABIE 0x0800 737#define PCIER_LINK_STA 0x12 738#define PCIEM_LINK_STA_SPEED 0x000f 739#define PCIEM_LINK_STA_WIDTH 0x03f0 740#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 741#define PCIEM_LINK_STA_TRAINING 0x0800 742#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 743#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 744#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 745#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 746#define PCIER_SLOT_CAP 0x14 747#define PCIEM_SLOT_CAP_APB 0x00000001 748#define PCIEM_SLOT_CAP_PCP 0x00000002 749#define PCIEM_SLOT_CAP_MRLSP 0x00000004 750#define PCIEM_SLOT_CAP_AIP 0x00000008 751#define PCIEM_SLOT_CAP_PIP 0x00000010 752#define PCIEM_SLOT_CAP_HPS 0x00000020 753#define PCIEM_SLOT_CAP_HPC 0x00000040 754#define PCIEM_SLOT_CAP_SPLV 0x00007f80 755#define PCIEM_SLOT_CAP_SPLS 0x00018000 756#define PCIEM_SLOT_CAP_EIP 0x00020000 757#define PCIEM_SLOT_CAP_NCCS 0x00040000 758#define PCIEM_SLOT_CAP_PSN 0xfff80000 759#define PCIER_SLOT_CTL 0x18 760#define PCIEM_SLOT_CTL_ABPE 0x0001 761#define PCIEM_SLOT_CTL_PFDE 0x0002 762#define PCIEM_SLOT_CTL_MRLSCE 0x0004 763#define PCIEM_SLOT_CTL_PDCE 0x0008 764#define PCIEM_SLOT_CTL_CCIE 0x0010 765#define PCIEM_SLOT_CTL_HPIE 0x0020 766#define PCIEM_SLOT_CTL_AIC 0x00c0 767#define PCIEM_SLOT_CTL_PIC 0x0300 768#define PCIEM_SLOT_CTL_PCC 0x0400 769#define PCIEM_SLOT_CTL_EIC 0x0800 770#define PCIEM_SLOT_CTL_DLLSCE 0x1000 771#define PCIER_SLOT_STA 0x1a 772#define PCIEM_SLOT_STA_ABP 0x0001 773#define PCIEM_SLOT_STA_PFD 0x0002 774#define PCIEM_SLOT_STA_MRLSC 0x0004 775#define PCIEM_SLOT_STA_PDC 0x0008 776#define PCIEM_SLOT_STA_CC 0x0010 777#define PCIEM_SLOT_STA_MRLSS 0x0020 778#define PCIEM_SLOT_STA_PDS 0x0040 779#define PCIEM_SLOT_STA_EIS 0x0080 780#define PCIEM_SLOT_STA_DLLSC 0x0100 781#define PCIER_ROOT_CTL 0x1c 782#define PCIEM_ROOT_CTL_SERR_CORR 0x0001 783#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 784#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 785#define PCIEM_ROOT_CTL_PME 0x0008 786#define PCIEM_ROOT_CTL_CRS_VIS 0x0010 787#define PCIER_ROOT_CAP 0x1e 788#define PCIEM_ROOT_CAP_CRS_VIS 0x0001 789#define PCIER_ROOT_STA 0x20 790#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 791#define PCIEM_ROOT_STA_PME_STATUS 0x00010000 792#define PCIEM_ROOT_STA_PME_PEND 0x00020000 793#define PCIER_DEVICE_CAP2 0x24 794#define PCIER_DEVICE_CTL2 0x28 795#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 796#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 797#define PCIEM_CTL2_ARI 0x0020 798#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 799#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 800#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 801#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 802#define PCIEM_CTL2_LTR_ENABLE 0x0400 803#define PCIEM_CTL2_OBFF 0x6000 804#define PCIEM_OBFF_DISABLE 0x0000 805#define PCIEM_OBFF_MSGA_ENABLE 0x2000 806#define PCIEM_OBFF_MSGB_ENABLE 0x4000 807#define PCIEM_OBFF_WAKE_ENABLE 0x6000 808#define PCIEM_CTL2_END2END_TLP 0x8000 809#define PCIER_DEVICE_STA2 0x2a 810#define PCIER_LINK_CAP2 0x2c 811#define PCIER_LINK_CTL2 0x30 812#define PCIER_LINK_STA2 0x32 813#define PCIER_SLOT_CAP2 0x34 814#define PCIER_SLOT_CTL2 0x38 815#define PCIER_SLOT_STA2 0x3a 816 817/* MSI-X definitions */ 818#define PCIR_MSIX_CTRL 0x2 819#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 820#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 821#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 822#define PCIR_MSIX_TABLE 0x4 823#define PCIR_MSIX_PBA 0x8 824#define PCIM_MSIX_BIR_MASK 0x7 825#define PCIM_MSIX_BIR_BAR_10 0 826#define PCIM_MSIX_BIR_BAR_14 1 827#define PCIM_MSIX_BIR_BAR_18 2 828#define PCIM_MSIX_BIR_BAR_1C 3 829#define PCIM_MSIX_BIR_BAR_20 4 830#define PCIM_MSIX_BIR_BAR_24 5 831#define PCIM_MSIX_VCTRL_MASK 0x1 832 833/* PCI Advanced Features definitions */ 834#define PCIR_PCIAF_CAP 0x3 835#define PCIM_PCIAFCAP_TP 0x01 836#define PCIM_PCIAFCAP_FLR 0x02 837#define PCIR_PCIAF_CTRL 0x4 838#define PCIR_PCIAFCTRL_FLR 0x01 839#define PCIR_PCIAF_STATUS 0x5 840#define PCIR_PCIAFSTATUS_TP 0x01 841 842/* Advanced Error Reporting */ 843#define PCIR_AER_UC_STATUS 0x04 844#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 845#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 846#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 847#define PCIM_AER_UC_POISONED_TLP 0x00001000 848#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 849#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 850#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 851#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 852#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 853#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 854#define PCIM_AER_UC_ECRC_ERROR 0x00080000 855#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 856#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 857#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 858#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 859#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 860#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 861#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 862#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 863#define PCIR_AER_COR_STATUS 0x10 864#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 865#define PCIM_AER_COR_BAD_TLP 0x00000040 866#define PCIM_AER_COR_BAD_DLLP 0x00000080 867#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 868#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 869#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 870#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 871#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 872#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 873#define PCIR_AER_CAP_CONTROL 0x18 874#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 875#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 876#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 877#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 878#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 879#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 880#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 881#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 882#define PCIR_AER_HEADER_LOG 0x1c 883#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 884#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 885#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 886#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 887#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 888#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 889#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 890#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 891#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 892#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 893#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 894#define PCIM_AER_ROOTERR_F_ERR 0x00000040 895#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 896#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 897#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 898#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 899 900/* Virtual Channel definitions */ 901#define PCIR_VC_CAP1 0x04 902#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 903#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 904#define PCIR_VC_CAP2 0x08 905#define PCIR_VC_CONTROL 0x0C 906#define PCIR_VC_STATUS 0x0E 907#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 908#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 909#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 910 911/* Serial Number definitions */ 912#define PCIR_SERIAL_LOW 0x04 913#define PCIR_SERIAL_HIGH 0x08 914