pcireg.h revision 26159
1#ifndef PCI_COMPAT 2#define PCI_COMPAT 3#endif 4/* 5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $Id$ 30 * 31 */ 32 33/* 34 * PCIM_xxx: mask to locate subfield in register 35 * PCIR_xxx: config register offset 36 * PCIC_xxx: device class 37 * PCIS_xxx: device subclass 38 * PCIP_xxx: device programming interface 39 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 40 * PCID_xxx: device ID 41 */ 42 43/* some PCI bus constants */ 44 45#define PCI_BUSMAX 255 46#define PCI_SLOTMAX 31 47#define PCI_FUNCMAX 7 48#define PCI_REGMAX 255 49 50/* PCI config header registers for all devices */ 51 52#define PCIR_DEVVENDOR 0x00 53#define PCIR_VENDOR 0x00 54#define PCIR_DEVICE 0x02 55#define PCIR_COMMAND 0x04 56#define PCIR_STATUS 0x06 57#define PCIR_REVID 0x08 58#define PCIR_PROGIF 0x09 59#define PCIR_SUBCLASS 0x0a 60#define PCIR_CLASS 0x0b 61#define PCIR_CACHELNSZ 0x0c 62#define PCIR_LATTIMER 0x0d 63#define PCIR_HEADERTYPE 0x0e 64#define PCIM_MFDEV 0x80 65#define PCIR_BIST 0x0f 66 67/* config registers for header type 0 devices */ 68 69#define PCIR_MAPS 0x10 70#define PCIR_CARDBUSCIS 0x28 71#define PCIR_SUBVEND_0 0x2c 72#define PCIR_SUBDEV_0 0x2e 73#define PCIR_INTLINE 0x3c 74#define PCIR_INTPIN 0x3d 75#define PCIR_MINGNT 0x3e 76#define PCIR_MAXLAT 0x3f 77 78/* config registers for header type 1 devices */ 79 80#define PCIR_SECSTAT_1 0 /**/ 81 82#define PCIR_PRIBUS_1 0x18 83#define PCIR_SECBUS_1 0x19 84#define PCIR_SUBBUS_1 0x1a 85#define PCIR_SECLAT_1 0x1b 86 87#define PCIR_IOBASEL_1 0x1c 88#define PCIR_IOLIMITL_1 0x1d 89#define PCIR_IOBASEH_1 0 /**/ 90#define PCIR_IOLIMITH_1 0 /**/ 91 92#define PCIR_MEMBASE_1 0x20 93#define PCIR_MEMLIMIT_1 0x22 94 95#define PCIR_PMBASEL_1 0x24 96#define PCIR_PMLIMITL_1 0x26 97#define PCIR_PMBASEH_1 0 /**/ 98#define PCIR_PMLIMITH_1 0 /**/ 99 100#define PCIR_BRIDGECTL_1 0 /**/ 101 102#define PCIR_SUBVEND_1 0x34 103#define PCIR_SUBDEV_1 0x36 104 105/* config registers for header type 2 devices */ 106 107#define PCIR_SECSTAT_2 0x16 108 109#define PCIR_PRIBUS_2 0x18 110#define PCIR_SECBUS_2 0x19 111#define PCIR_SUBBUS_2 0x1a 112#define PCIR_SECLAT_2 0x1b 113 114#define PCIR_MEMBASE0_2 0x1c 115#define PCIR_MEMLIMIT0_2 0x20 116#define PCIR_MEMBASE1_2 0x24 117#define PCIR_MEMLIMIT1_2 0x28 118#define PCIR_IOBASE0_2 0x2c 119#define PCIR_IOLIMIT0_2 0x30 120#define PCIR_IOBASE1_2 0x34 121#define PCIR_IOLIMIT1_2 0x38 122 123#define PCIR_BRIDGECTL_2 0x3e 124 125#define PCIR_SUBVEND_2 0x40 126#define PCIR_SUBDEV_2 0x42 127 128#define PCIR_PCCARDIF_2 0x44 129 130/* PCI device class, subclass and programming interface definitions */ 131 132#define PCIC_OLD 0x00 133#define PCIS_OLD_NONVGA 0x00 134#define PCIS_OLD_VGA 0x01 135 136#define PCIC_STORAGE 0x01 137#define PCIS_STORAGE_SCSI 0x00 138#define PCIS_STORAGE_IDE 0x01 139#define PCIP_STORAGE_IDE_MODEPRIM 0x01 140#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 141#define PCIP_STORAGE_IDE_MODESEC 0x04 142#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 143#define PCIP_STORAGE_IDE_MASTERDEV 0x80 144#define PCIS_STORAGE_FLOPPY 0x02 145#define PCIS_STORAGE_IPI 0x03 146#define PCIS_STORAGE_RAID 0x04 147#define PCIS_STORAGE_OTHER 0x80 148 149#define PCIC_NETWORK 0x02 150#define PCIS_NETWORK_ETHERNET 0x00 151#define PCIS_NETWORK_TOKENRING 0x01 152#define PCIS_NETWORK_FDDI 0x02 153#define PCIS_NETWORK_ATM 0x03 154#define PCIS_NETWORK_OTHER 0x80 155 156#define PCIC_DISPLAY 0x03 157#define PCIS_DISPLAY_VGA 0x00 158#define PCIS_DISPLAY_XGA 0x01 159#define PCIS_DISPLAY_OTHER 0x80 160 161#define PCIC_MULTIMEDIA 0x04 162#define PCIS_MULTIMEDIA_VIDEO 0x00 163#define PCIS_MULTIMEDIA_AUDIO 0x01 164#define PCIS_MULTIMEDIA_OTHER 0x80 165 166#define PCIC_MEMORY 0x05 167#define PCIS_MEMORY_RAM 0x00 168#define PCIS_MEMORY_FLASH 0x01 169#define PCIS_MEMORY_OTHER 0x80 170 171#define PCIC_BRIDGE 0x06 172#define PCIS_BRDIGE_HOST 0x00 173#define PCIS_BRIDGE_ISA 0x01 174#define PCIS_BRIDGE_EISA 0x02 175#define PCIS_BRIDGE_MCA 0x03 176#define PCIS_BRIDGE_PCI 0x04 177#define PCIS_BRIDGE_PCMCIA 0x05 178#define PCIS_BRIDGE_NUBUS 0x06 179#define PCIS_BRIDGE_CARDBUS 0x07 180#define PCIS_BRIDGE_OTHER 0x80 181 182#define PCIC_SIMPLECOMM 0x07 183#define PCIS_SIMPLECOMM_UART 0x00 184#define PCIS_SIMPLECOMM_PAR 0x01 185#define PCIS_SIMPLECOMM_OTHER 0x80 186 187#define PCIC_BASEPERIPH 0x08 188#define PCIS_BASEPERIPH_PIC 0x00 189#define PCIS_BASEPERIPH_DMA 0x01 190#define PCIS_BASEPERIPH_TIMER 0x02 191#define PCIS_BASEPERIPH_RTC 0x03 192#define PCIS_BASEPERIPH_OTHER 0x80 193 194#define PCIC_INPUTDEV 0x09 195#define PCIS_INPUTDEV_KEYBOARD 0x00 196#define PCIS_INPUTDEV_DIGITIZER 0x01 197#define PCIS_INPUTDEV_MOUSE 0x02 198#define PCIS_INPUTDEV_OTHER 0x80 199 200#define PCIC_DOCKING 0x0a 201#define PCIS_DOCKING_GENERIC 0x00 202#define PCIS_DOCKING_OTHER 0x80 203 204#define PCIC_PROCESSOR 0x0b 205#define PCIS_PROCESSOR_386 0x00 206#define PCIS_PROCESSOR_486 0x01 207#define PCIS_PROCESSOR_PENTIUM 0x02 208#define PCIS_PROCESSOR_ALPHA 0x10 209#define PCIS_PROCESSOR_POWERPC 0x20 210#define PCIS_PROCESSOR_COPROC 0x40 211 212#define PCIC_SERIALBUS 0x0c 213#define PCIS_SERIALBUS_FW 0x00 214#define PCIS_SERIALBUS_ACCESS 0x01 215#define PCIS_SERIALBUS_SSA 0x02 216#define PCIS_SERIALBUS_USB 0x03 217#define PCIS_SERIALBUS_FC 0x04 218#define PCIS_SERIALBUS 219#define PCIS_SERIALBUS 220 221#define PCIC_OTHER 0xff 222 223/* some PCI vendor definitions (only used to identify ancient devices !!! */ 224 225#define PCIV_INTEL 0x8086 226 227#define PCID_INTEL_SATURN 0x0483 228#define PCID_INTEL_ORION 0x84c4 229 230/* for compatibility to FreeBSD-2.2 version of PCI code */ 231 232#ifdef PCI_COMPAT 233 234#define PCI_ID_REG 0x00 235#define PCI_COMMAND_STATUS_REG 0x04 236#define PCI_COMMAND_IO_ENABLE 0x00000001 237#define PCI_CLASS_REG 0x08 238#define PCI_CLASS_MASK 0xff000000 239#define PCI_SUBCLASS_MASK 0x00ff0000 240#define PCI_CLASS_PREHISTORIC 0x00000000 241#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 242#define PCI_CLASS_DISPLAY 0x03000000 243#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 244#define PCI_CLASS_BRIDGE 0x06000000 245#define PCI_MAP_REG_START 0x10 246#define PCI_MAP_REG_END 0x28 247#define PCI_MAP_IO 0x00000001 248#define PCI_INTERRUPT_REG 0x3c 249 250#endif /* PCI_COMPAT */ 251