pcireg.h revision 25121
1169691Skan/************************************************************************** 2169691Skan** 3169691Skan** $Id: pcireg.h,v 1.13 1997/04/20 06:57:43 phk Exp $ 4169691Skan** 5169691Skan** Names for PCI configuration space registers. 6169691Skan** 7169691Skan** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 8169691Skan** 9169691Skan** 10169691Skan** Redistribution and use in source and binary forms, with or without 11169691Skan** modification, are permitted provided that the following conditions 12169691Skan** are met: 13169691Skan** 1. Redistributions of source code must retain the above copyright 14169691Skan** notice, this list of conditions and the following disclaimer. 15169691Skan** 2. Redistributions in binary form must reproduce the above copyright 16169691Skan** notice, this list of conditions and the following disclaimer in the 17169691Skan** documentation and/or other materials provided with the distribution. 18169691Skan** 3. The name of the author may not be used to endorse or promote products 19169691Skan** derived from this software without specific prior written permission. 20169691Skan** 21169691Skan** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22169691Skan** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23169691Skan** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24169691Skan** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25169691Skan** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26169691Skan** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27169691Skan** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28169691Skan** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29169691Skan** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30169691Skan** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31169691Skan** 32169691Skan*************************************************************************** 33169691Skan*/ 34169691Skan 35169691Skan#ifndef __PCI_REG_H__ 36169691Skan#define __PCI_REG_H__ "pl2 95/03/21" 37169691Skan 38169691Skan/* 39169691Skan** Device identification register; contains a vendor ID and a device ID. 40169691Skan** We have little need to distinguish the two parts. 41169691Skan*/ 42169691Skan#define PCI_ID_REG 0x00 43169691Skan 44169691Skan/* 45169691Skan** Command and status register. 46169691Skan*/ 47169691Skan#define PCI_COMMAND_STATUS_REG 0x04 48169691Skan 49169691Skan#define PCI_COMMAND_IO_ENABLE 0x00000001 50169691Skan#define PCI_COMMAND_MEM_ENABLE 0x00000002 51169691Skan#define PCI_COMMAND_MASTER_ENABLE 0x00000004 52169691Skan#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 53169691Skan#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 54169691Skan#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 55169691Skan#define PCI_COMMAND_PARITY_ENABLE 0x00000040 56169691Skan#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 57169691Skan#define PCI_COMMAND_SERR_ENABLE 0x00000100 58169691Skan#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 59169691Skan 60169691Skan#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 61169691Skan#define PCI_STATUS_PARITY_ERROR 0x01000000 62169691Skan#define PCI_STATUS_DEVSEL_FAST 0x00000000 63169691Skan#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 64169691Skan#define PCI_STATUS_DEVSEL_SLOW 0x04000000 65169691Skan#define PCI_STATUS_DEVSEL_MASK 0x06000000 66169691Skan#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 67169691Skan#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 68169691Skan#define PCI_STATUS_MASTER_ABORT 0x20000000 69169691Skan#define PCI_STATUS_SPECIAL_ERROR 0x40000000 70169691Skan#define PCI_STATUS_PARITY_DETECT 0x80000000 71169691Skan 72169691Skan/* 73169691Skan** Class register; defines basic type of device. 74169691Skan*/ 75169691Skan#define PCI_CLASS_REG 0x08 76169691Skan 77169691Skan#define PCI_CLASS_MASK 0xff000000 78169691Skan#define PCI_SUBCLASS_MASK 0x00ff0000 79169691Skan 80169691Skan/* base classes */ 81169691Skan#define PCI_CLASS_PREHISTORIC 0x00000000 82169691Skan#define PCI_CLASS_MASS_STORAGE 0x01000000 83169691Skan#define PCI_CLASS_NETWORK 0x02000000 84169691Skan#define PCI_CLASS_DISPLAY 0x03000000 85169691Skan#define PCI_CLASS_MULTIMEDIA 0x04000000 86169691Skan#define PCI_CLASS_MEMORY 0x05000000 87169691Skan#define PCI_CLASS_BRIDGE 0x06000000 88169691Skan#define PCI_CLASS_UNDEFINED 0xff000000 89169691Skan 90169691Skan/* 0x00 prehistoric subclasses */ 91169691Skan#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00000000 92169691Skan#define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000 93169691Skan 94169691Skan/* 0x01 mass storage subclasses */ 95169691Skan#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000 96169691Skan#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x00010000 97169691Skan#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x00020000 98169691Skan#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x00030000 99169691Skan#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x00800000 100169691Skan 101169691Skan/* 0x02 network subclasses */ 102169691Skan#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00000000 103169691Skan#define PCI_SUBCLASS_NETWORK_TOKENRING 0x00010000 104169691Skan#define PCI_SUBCLASS_NETWORK_FDDI 0x00020000 105169691Skan#define PCI_SUBCLASS_NETWORK_MISC 0x00800000 106169691Skan 107169691Skan/* 0x03 display subclasses */ 108169691Skan#define PCI_SUBCLASS_DISPLAY_VGA 0x00000000 109169691Skan#define PCI_SUBCLASS_DISPLAY_XGA 0x00010000 110169691Skan#define PCI_SUBCLASS_DISPLAY_MISC 0x00800000 111169691Skan 112169691Skan/* 0x04 multimedia subclasses */ 113169691Skan#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00000000 114169691Skan#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x00010000 115169691Skan#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x00800000 116169691Skan 117169691Skan/* 0x05 memory subclasses */ 118169691Skan#define PCI_SUBCLASS_MEMORY_RAM 0x00000000 119169691Skan#define PCI_SUBCLASS_MEMORY_FLASH 0x00010000 120169691Skan#define PCI_SUBCLASS_MEMORY_MISC 0x00800000 121169691Skan 122169691Skan/* 0x06 bridge subclasses */ 123169691Skan#define PCI_SUBCLASS_BRIDGE_HOST 0x00000000 124169691Skan#define PCI_SUBCLASS_BRIDGE_ISA 0x00010000 125169691Skan#define PCI_SUBCLASS_BRIDGE_EISA 0x00020000 126169691Skan#define PCI_SUBCLASS_BRIDGE_MC 0x00030000 127169691Skan#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 128169691Skan#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x00050000 129169691Skan#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x00070000 130169691Skan#define PCI_SUBCLASS_BRIDGE_MISC 0x00800000 131169691Skan 132169691Skan/* 133169691Skan** Header registers 134169691Skan*/ 135169691Skan#define PCI_HEADER_MISC 0x0c 136169691Skan 137169691Skan#define PCI_HEADER_MULTIFUNCTION 0x00800000 138169691Skan 139169691Skan/* 140169691Skan** Mapping registers 141169691Skan*/ 142169691Skan#define PCI_MAP_REG_START 0x10 143169691Skan#define PCI_MAP_REG_END 0x28 144169691Skan 145169691Skan#define PCI_MAP_MEMORY 0x00000000 146169691Skan#define PCI_MAP_IO 0x00000001 147169691Skan 148169691Skan#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 149169691Skan#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 150169691Skan#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 151169691Skan#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 152169691Skan#define PCI_MAP_MEMORY_CACHABLE 0x00000008 153169691Skan#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 154169691Skan 155169691Skan#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc 156169691Skan/* 157169691Skan** PCI-PCI bridge mapping registers 158169691Skan*/ 159#define PCI_PCI_BRIDGE_BUS_REG 0x18 160#define PCI_PCI_BRIDGE_IO_REG 0x1c 161#define PCI_PCI_BRIDGE_MEM_REG 0x20 162#define PCI_PCI_BRIDGE_PMEM_REG 0x24 163 164#define PCI_SUBID_REG0 0x2c 165#define PCI_SUBID_REG1 0x34 166#define PCI_SUBID_REG2 0x40 167 168#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 169#define PCI_SECONDARY_BUS_MASK 0x0000ff00 170#define PCI_PRIMARY_BUS_MASK 0x000000ff 171 172#define PCI_SUBORDINATE_BUS_EXTRACT(x) (((x) >> 16) & 0xff) 173#define PCI_SECONDARY_BUS_EXTRACT(x) (((x) >> 8) & 0xff) 174#define PCI_PRIMARY_BUS_EXTRACT(x) (((x) ) & 0xff) 175 176#define PCI_PRIMARY_BUS_INSERT(x, y) (((x) & ~PCI_PRIMARY_BUS_MASK) | ((y) << 0)) 177#define PCI_SECONDARY_BUS_INSERT(x, y) (((x) & ~PCI_SECONDARY_BUS_MASK) | ((y) << 8)) 178#define PCI_SUBORDINATE_BUS_INSERT(x, y) (((x) & ~PCI_SUBORDINATE_BUS_MASK) | ((y) << 16)) 179 180#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xF000) 181#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xF000 | 0x0FFF) 182 183#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFF00000) 184#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFF00000 | 0x000FFFFF) 185 186/* 187** PCI-Cardbus bridge mapping registers 188*/ 189#define PCI_CARDBUS_SOCKET_REG 0x10 190 191/* 192** Interrupt configuration register 193*/ 194#define PCI_INTERRUPT_REG 0x3c 195 196#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 197#define PCI_INTERRUPT_PIN_EXTRACT(x) ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) 198#define PCI_INTERRUPT_PIN_NONE 0x00 199#define PCI_INTERRUPT_PIN_A 0x01 200#define PCI_INTERRUPT_PIN_B 0x02 201#define PCI_INTERRUPT_PIN_C 0x03 202#define PCI_INTERRUPT_PIN_D 0x04 203 204#define PCI_INTERRUPT_LINE_MASK 0x000000ff 205#define PCI_INTERRUPT_LINE_EXTRACT(x) ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) 206#define PCI_INTERRUPT_LINE_INSERT(x,v) (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) 207 208#endif /* __PCI_REG_H__ */ 209