pcireg.h revision 212368
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 212368 2010-09-09 18:19:15Z jhb $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42/* some PCI bus constants */ 43#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44#define PCI_BUSMAX 255 /* highest supported bus number */ 45#define PCI_SLOTMAX 31 /* highest supported slot number */ 46#define PCI_FUNCMAX 7 /* highest supported function number */ 47#define PCI_REGMAX 255 /* highest supported config register addr. */ 48#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49#define PCI_MAXHDRTYPE 2 50 51/* PCI config header registers for all devices */ 52 53#define PCIR_DEVVENDOR 0x00 54#define PCIR_VENDOR 0x00 55#define PCIR_DEVICE 0x02 56#define PCIR_COMMAND 0x04 57#define PCIM_CMD_PORTEN 0x0001 58#define PCIM_CMD_MEMEN 0x0002 59#define PCIM_CMD_BUSMASTEREN 0x0004 60#define PCIM_CMD_SPECIALEN 0x0008 61#define PCIM_CMD_MWRICEN 0x0010 62#define PCIM_CMD_PERRESPEN 0x0040 63#define PCIM_CMD_SERRESPEN 0x0100 64#define PCIM_CMD_BACKTOBACK 0x0200 65#define PCIM_CMD_INTxDIS 0x0400 66#define PCIR_STATUS 0x06 67#define PCIM_STATUS_CAPPRESENT 0x0010 68#define PCIM_STATUS_66CAPABLE 0x0020 69#define PCIM_STATUS_BACKTOBACK 0x0080 70#define PCIM_STATUS_MDPERR 0x0100 71#define PCIM_STATUS_SEL_FAST 0x0000 72#define PCIM_STATUS_SEL_MEDIMUM 0x0200 73#define PCIM_STATUS_SEL_SLOW 0x0400 74#define PCIM_STATUS_SEL_MASK 0x0600 75#define PCIM_STATUS_STABORT 0x0800 76#define PCIM_STATUS_RTABORT 0x1000 77#define PCIM_STATUS_RMABORT 0x2000 78#define PCIM_STATUS_SERR 0x4000 79#define PCIM_STATUS_PERR 0x8000 80#define PCIR_REVID 0x08 81#define PCIR_PROGIF 0x09 82#define PCIR_SUBCLASS 0x0a 83#define PCIR_CLASS 0x0b 84#define PCIR_CACHELNSZ 0x0c 85#define PCIR_LATTIMER 0x0d 86#define PCIR_HDRTYPE 0x0e 87#define PCIM_HDRTYPE 0x7f 88#define PCIM_HDRTYPE_NORMAL 0x00 89#define PCIM_HDRTYPE_BRIDGE 0x01 90#define PCIM_HDRTYPE_CARDBUS 0x02 91#define PCIM_MFDEV 0x80 92#define PCIR_BIST 0x0f 93 94/* Capability Register Offsets */ 95 96#define PCICAP_ID 0x0 97#define PCICAP_NEXTPTR 0x1 98 99/* Capability Identification Numbers */ 100 101#define PCIY_PMG 0x01 /* PCI Power Management */ 102#define PCIY_AGP 0x02 /* AGP */ 103#define PCIY_VPD 0x03 /* Vital Product Data */ 104#define PCIY_SLOTID 0x04 /* Slot Identification */ 105#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 106#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 107#define PCIY_PCIX 0x07 /* PCI-X */ 108#define PCIY_HT 0x08 /* HyperTransport */ 109#define PCIY_VENDOR 0x09 /* Vendor Unique */ 110#define PCIY_DEBUG 0x0a /* Debug port */ 111#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 112#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 113#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 114#define PCIY_AGP8X 0x0e /* AGP 8x */ 115#define PCIY_SECDEV 0x0f /* Secure Device */ 116#define PCIY_EXPRESS 0x10 /* PCI Express */ 117#define PCIY_MSIX 0x11 /* MSI-X */ 118#define PCIY_SATA 0x12 /* SATA */ 119#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 120 121/* Extended Capability Register Fields */ 122 123#define PCIR_EXTCAP 0x100 124#define PCIM_EXTCAP_ID 0x0000ffff 125#define PCIM_EXTCAP_VER 0x000f0000 126#define PCIM_EXTCAP_NEXTPTR 0xfff00000 127#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 128#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 129#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 130 131/* Extended Capability Identification Numbers */ 132 133#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 134#define PCIZ_VC 0x0002 /* Virtual Channel */ 135#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 136#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 137#define PCIZ_VENDOR 0x000b /* Vendor Unique */ 138#define PCIZ_ACS 0x000d /* Access Control Services */ 139#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 140#define PCIZ_ATS 0x000f /* Address Translation Services */ 141#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 142 143/* config registers for header type 0 devices */ 144 145#define PCIR_BARS 0x10 146#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 147#define PCIR_MAX_BAR_0 5 148#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 149#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 150#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 151#define PCIM_BAR_SPACE 0x00000001 152#define PCIM_BAR_MEM_SPACE 0 153#define PCIM_BAR_IO_SPACE 1 154#define PCIM_BAR_MEM_TYPE 0x00000006 155#define PCIM_BAR_MEM_32 0 156#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 157#define PCIM_BAR_MEM_64 4 158#define PCIM_BAR_MEM_PREFETCH 0x00000008 159#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 160#define PCIM_BAR_IO_RESERVED 0x00000002 161#define PCIM_BAR_IO_BASE 0xfffffffc 162#define PCIR_CIS 0x28 163#define PCIM_CIS_ASI_MASK 0x00000007 164#define PCIM_CIS_ASI_CONFIG 0 165#define PCIM_CIS_ASI_BAR0 1 166#define PCIM_CIS_ASI_BAR1 2 167#define PCIM_CIS_ASI_BAR2 3 168#define PCIM_CIS_ASI_BAR3 4 169#define PCIM_CIS_ASI_BAR4 5 170#define PCIM_CIS_ASI_BAR5 6 171#define PCIM_CIS_ASI_ROM 7 172#define PCIM_CIS_ADDR_MASK 0x0ffffff8 173#define PCIM_CIS_ROM_MASK 0xf0000000 174#define PCIM_CIS_CONFIG_MASK 0xff 175#define PCIR_SUBVEND_0 0x2c 176#define PCIR_SUBDEV_0 0x2e 177#define PCIR_BIOS 0x30 178#define PCIM_BIOS_ENABLE 0x01 179#define PCIM_BIOS_ADDR_MASK 0xfffff800 180#define PCIR_CAP_PTR 0x34 181#define PCIR_INTLINE 0x3c 182#define PCIR_INTPIN 0x3d 183#define PCIR_MINGNT 0x3e 184#define PCIR_MAXLAT 0x3f 185 186/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 187 188#define PCIR_MAX_BAR_1 1 189#define PCIR_SECSTAT_1 0x1e 190 191#define PCIR_PRIBUS_1 0x18 192#define PCIR_SECBUS_1 0x19 193#define PCIR_SUBBUS_1 0x1a 194#define PCIR_SECLAT_1 0x1b 195 196#define PCIR_IOBASEL_1 0x1c 197#define PCIR_IOLIMITL_1 0x1d 198#define PCIR_IOBASEH_1 0x30 199#define PCIR_IOLIMITH_1 0x32 200#define PCIM_BRIO_16 0x0 201#define PCIM_BRIO_32 0x1 202#define PCIM_BRIO_MASK 0xf 203 204#define PCIR_MEMBASE_1 0x20 205#define PCIR_MEMLIMIT_1 0x22 206 207#define PCIR_PMBASEL_1 0x24 208#define PCIR_PMLIMITL_1 0x26 209#define PCIR_PMBASEH_1 0x28 210#define PCIR_PMLIMITH_1 0x2c 211#define PCIM_BRPM_32 0x0 212#define PCIM_BRPM_64 0x1 213#define PCIM_BRPM_MASK 0xf 214 215#define PCIR_BRIDGECTL_1 0x3e 216 217/* config registers for header type 2 (CardBus) devices */ 218 219#define PCIR_MAX_BAR_2 0 220#define PCIR_CAP_PTR_2 0x14 221#define PCIR_SECSTAT_2 0x16 222 223#define PCIR_PRIBUS_2 0x18 224#define PCIR_SECBUS_2 0x19 225#define PCIR_SUBBUS_2 0x1a 226#define PCIR_SECLAT_2 0x1b 227 228#define PCIR_MEMBASE0_2 0x1c 229#define PCIR_MEMLIMIT0_2 0x20 230#define PCIR_MEMBASE1_2 0x24 231#define PCIR_MEMLIMIT1_2 0x28 232#define PCIR_IOBASE0_2 0x2c 233#define PCIR_IOLIMIT0_2 0x30 234#define PCIR_IOBASE1_2 0x34 235#define PCIR_IOLIMIT1_2 0x38 236 237#define PCIR_BRIDGECTL_2 0x3e 238 239#define PCIR_SUBVEND_2 0x40 240#define PCIR_SUBDEV_2 0x42 241 242#define PCIR_PCCARDIF_2 0x44 243 244/* PCI device class, subclass and programming interface definitions */ 245 246#define PCIC_OLD 0x00 247#define PCIS_OLD_NONVGA 0x00 248#define PCIS_OLD_VGA 0x01 249 250#define PCIC_STORAGE 0x01 251#define PCIS_STORAGE_SCSI 0x00 252#define PCIS_STORAGE_IDE 0x01 253#define PCIP_STORAGE_IDE_MODEPRIM 0x01 254#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 255#define PCIP_STORAGE_IDE_MODESEC 0x04 256#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 257#define PCIP_STORAGE_IDE_MASTERDEV 0x80 258#define PCIS_STORAGE_FLOPPY 0x02 259#define PCIS_STORAGE_IPI 0x03 260#define PCIS_STORAGE_RAID 0x04 261#define PCIS_STORAGE_ATA_ADMA 0x05 262#define PCIS_STORAGE_SATA 0x06 263#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 264#define PCIS_STORAGE_SAS 0x07 265#define PCIS_STORAGE_OTHER 0x80 266 267#define PCIC_NETWORK 0x02 268#define PCIS_NETWORK_ETHERNET 0x00 269#define PCIS_NETWORK_TOKENRING 0x01 270#define PCIS_NETWORK_FDDI 0x02 271#define PCIS_NETWORK_ATM 0x03 272#define PCIS_NETWORK_ISDN 0x04 273#define PCIS_NETWORK_WORLDFIP 0x05 274#define PCIS_NETWORK_PICMG 0x06 275#define PCIS_NETWORK_OTHER 0x80 276 277#define PCIC_DISPLAY 0x03 278#define PCIS_DISPLAY_VGA 0x00 279#define PCIS_DISPLAY_XGA 0x01 280#define PCIS_DISPLAY_3D 0x02 281#define PCIS_DISPLAY_OTHER 0x80 282 283#define PCIC_MULTIMEDIA 0x04 284#define PCIS_MULTIMEDIA_VIDEO 0x00 285#define PCIS_MULTIMEDIA_AUDIO 0x01 286#define PCIS_MULTIMEDIA_TELE 0x02 287#define PCIS_MULTIMEDIA_HDA 0x03 288#define PCIS_MULTIMEDIA_OTHER 0x80 289 290#define PCIC_MEMORY 0x05 291#define PCIS_MEMORY_RAM 0x00 292#define PCIS_MEMORY_FLASH 0x01 293#define PCIS_MEMORY_OTHER 0x80 294 295#define PCIC_BRIDGE 0x06 296#define PCIS_BRIDGE_HOST 0x00 297#define PCIS_BRIDGE_ISA 0x01 298#define PCIS_BRIDGE_EISA 0x02 299#define PCIS_BRIDGE_MCA 0x03 300#define PCIS_BRIDGE_PCI 0x04 301#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 302#define PCIS_BRIDGE_PCMCIA 0x05 303#define PCIS_BRIDGE_NUBUS 0x06 304#define PCIS_BRIDGE_CARDBUS 0x07 305#define PCIS_BRIDGE_RACEWAY 0x08 306#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 307#define PCIS_BRIDGE_INFINIBAND 0x0a 308#define PCIS_BRIDGE_OTHER 0x80 309 310#define PCIC_SIMPLECOMM 0x07 311#define PCIS_SIMPLECOMM_UART 0x00 312#define PCIP_SIMPLECOMM_UART_8250 0x00 313#define PCIP_SIMPLECOMM_UART_16450A 0x01 314#define PCIP_SIMPLECOMM_UART_16550A 0x02 315#define PCIP_SIMPLECOMM_UART_16650A 0x03 316#define PCIP_SIMPLECOMM_UART_16750A 0x04 317#define PCIP_SIMPLECOMM_UART_16850A 0x05 318#define PCIP_SIMPLECOMM_UART_16950A 0x06 319#define PCIS_SIMPLECOMM_PAR 0x01 320#define PCIS_SIMPLECOMM_MULSER 0x02 321#define PCIS_SIMPLECOMM_MODEM 0x03 322#define PCIS_SIMPLECOMM_GPIB 0x04 323#define PCIS_SIMPLECOMM_SMART_CARD 0x05 324#define PCIS_SIMPLECOMM_OTHER 0x80 325 326#define PCIC_BASEPERIPH 0x08 327#define PCIS_BASEPERIPH_PIC 0x00 328#define PCIP_BASEPERIPH_PIC_8259A 0x00 329#define PCIP_BASEPERIPH_PIC_ISA 0x01 330#define PCIP_BASEPERIPH_PIC_EISA 0x02 331#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 332#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 333#define PCIS_BASEPERIPH_DMA 0x01 334#define PCIS_BASEPERIPH_TIMER 0x02 335#define PCIS_BASEPERIPH_RTC 0x03 336#define PCIS_BASEPERIPH_PCIHOT 0x04 337#define PCIS_BASEPERIPH_SDHC 0x05 338#define PCIS_BASEPERIPH_OTHER 0x80 339 340#define PCIC_INPUTDEV 0x09 341#define PCIS_INPUTDEV_KEYBOARD 0x00 342#define PCIS_INPUTDEV_DIGITIZER 0x01 343#define PCIS_INPUTDEV_MOUSE 0x02 344#define PCIS_INPUTDEV_SCANNER 0x03 345#define PCIS_INPUTDEV_GAMEPORT 0x04 346#define PCIS_INPUTDEV_OTHER 0x80 347 348#define PCIC_DOCKING 0x0a 349#define PCIS_DOCKING_GENERIC 0x00 350#define PCIS_DOCKING_OTHER 0x80 351 352#define PCIC_PROCESSOR 0x0b 353#define PCIS_PROCESSOR_386 0x00 354#define PCIS_PROCESSOR_486 0x01 355#define PCIS_PROCESSOR_PENTIUM 0x02 356#define PCIS_PROCESSOR_ALPHA 0x10 357#define PCIS_PROCESSOR_POWERPC 0x20 358#define PCIS_PROCESSOR_MIPS 0x30 359#define PCIS_PROCESSOR_COPROC 0x40 360 361#define PCIC_SERIALBUS 0x0c 362#define PCIS_SERIALBUS_FW 0x00 363#define PCIS_SERIALBUS_ACCESS 0x01 364#define PCIS_SERIALBUS_SSA 0x02 365#define PCIS_SERIALBUS_USB 0x03 366#define PCIP_SERIALBUS_USB_UHCI 0x00 367#define PCIP_SERIALBUS_USB_OHCI 0x10 368#define PCIP_SERIALBUS_USB_EHCI 0x20 369#define PCIP_SERIALBUS_USB_DEVICE 0xfe 370#define PCIS_SERIALBUS_FC 0x04 371#define PCIS_SERIALBUS_SMBUS 0x05 372#define PCIS_SERIALBUS_INFINIBAND 0x06 373#define PCIS_SERIALBUS_IPMI 0x07 374#define PCIP_SERIALBUS_IPMI_SMIC 0x00 375#define PCIP_SERIALBUS_IPMI_KCS 0x01 376#define PCIP_SERIALBUS_IPMI_BT 0x02 377#define PCIS_SERIALBUS_SERCOS 0x08 378#define PCIS_SERIALBUS_CANBUS 0x09 379 380#define PCIC_WIRELESS 0x0d 381#define PCIS_WIRELESS_IRDA 0x00 382#define PCIS_WIRELESS_IR 0x01 383#define PCIS_WIRELESS_RF 0x10 384#define PCIS_WIRELESS_BLUETOOTH 0x11 385#define PCIS_WIRELESS_BROADBAND 0x12 386#define PCIS_WIRELESS_80211A 0x20 387#define PCIS_WIRELESS_80211B 0x21 388#define PCIS_WIRELESS_OTHER 0x80 389 390#define PCIC_INTELLIIO 0x0e 391#define PCIS_INTELLIIO_I2O 0x00 392 393#define PCIC_SATCOM 0x0f 394#define PCIS_SATCOM_TV 0x01 395#define PCIS_SATCOM_AUDIO 0x02 396#define PCIS_SATCOM_VOICE 0x03 397#define PCIS_SATCOM_DATA 0x04 398 399#define PCIC_CRYPTO 0x10 400#define PCIS_CRYPTO_NETCOMP 0x00 401#define PCIS_CRYPTO_ENTERTAIN 0x10 402#define PCIS_CRYPTO_OTHER 0x80 403 404#define PCIC_DASP 0x11 405#define PCIS_DASP_DPIO 0x00 406#define PCIS_DASP_PERFCNTRS 0x01 407#define PCIS_DASP_COMM_SYNC 0x10 408#define PCIS_DASP_MGMT_CARD 0x20 409#define PCIS_DASP_OTHER 0x80 410 411#define PCIC_OTHER 0xff 412 413/* Bridge Control Values. */ 414#define PCIB_BCR_PERR_ENABLE 0x0001 415#define PCIB_BCR_SERR_ENABLE 0x0002 416#define PCIB_BCR_ISA_ENABLE 0x0004 417#define PCIB_BCR_VGA_ENABLE 0x0008 418#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 419#define PCIB_BCR_SECBUS_RESET 0x0040 420#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 421#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 422#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 423#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 424#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 425 426/* PCI power manangement */ 427#define PCIR_POWER_CAP 0x2 428#define PCIM_PCAP_SPEC 0x0007 429#define PCIM_PCAP_PMEREQCLK 0x0008 430#define PCIM_PCAP_PMEREQPWR 0x0010 431#define PCIM_PCAP_DEVSPECINIT 0x0020 432#define PCIM_PCAP_DYNCLOCK 0x0040 433#define PCIM_PCAP_SECCLOCK 0x00c0 434#define PCIM_PCAP_CLOCKMASK 0x00c0 435#define PCIM_PCAP_REQFULLCLOCK 0x0100 436#define PCIM_PCAP_D1SUPP 0x0200 437#define PCIM_PCAP_D2SUPP 0x0400 438#define PCIM_PCAP_D0PME 0x0800 439#define PCIM_PCAP_D1PME 0x1000 440#define PCIM_PCAP_D2PME 0x2000 441#define PCIM_PCAP_D3PME_HOT 0x4000 442#define PCIM_PCAP_D3PME_COLD 0x8000 443 444#define PCIR_POWER_STATUS 0x4 445#define PCIM_PSTAT_D0 0x0000 446#define PCIM_PSTAT_D1 0x0001 447#define PCIM_PSTAT_D2 0x0002 448#define PCIM_PSTAT_D3 0x0003 449#define PCIM_PSTAT_DMASK 0x0003 450#define PCIM_PSTAT_REPENABLE 0x0010 451#define PCIM_PSTAT_PMEENABLE 0x0100 452#define PCIM_PSTAT_D0POWER 0x0000 453#define PCIM_PSTAT_D1POWER 0x0200 454#define PCIM_PSTAT_D2POWER 0x0400 455#define PCIM_PSTAT_D3POWER 0x0600 456#define PCIM_PSTAT_D0HEAT 0x0800 457#define PCIM_PSTAT_D1HEAT 0x1000 458#define PCIM_PSTAT_D2HEAT 0x1200 459#define PCIM_PSTAT_D3HEAT 0x1400 460#define PCIM_PSTAT_DATAUNKN 0x0000 461#define PCIM_PSTAT_DATADIV10 0x2000 462#define PCIM_PSTAT_DATADIV100 0x4000 463#define PCIM_PSTAT_DATADIV1000 0x6000 464#define PCIM_PSTAT_DATADIVMASK 0x6000 465#define PCIM_PSTAT_PME 0x8000 466 467#define PCIR_POWER_PMCSR 0x6 468#define PCIM_PMCSR_DCLOCK 0x10 469#define PCIM_PMCSR_B2SUPP 0x20 470#define PCIM_BMCSR_B3SUPP 0x40 471#define PCIM_BMCSR_BPCE 0x80 472 473#define PCIR_POWER_DATA 0x7 474 475/* VPD capability registers */ 476#define PCIR_VPD_ADDR 0x2 477#define PCIR_VPD_DATA 0x4 478 479/* PCI Message Signalled Interrupts (MSI) */ 480#define PCIR_MSI_CTRL 0x2 481#define PCIM_MSICTRL_VECTOR 0x0100 482#define PCIM_MSICTRL_64BIT 0x0080 483#define PCIM_MSICTRL_MME_MASK 0x0070 484#define PCIM_MSICTRL_MME_1 0x0000 485#define PCIM_MSICTRL_MME_2 0x0010 486#define PCIM_MSICTRL_MME_4 0x0020 487#define PCIM_MSICTRL_MME_8 0x0030 488#define PCIM_MSICTRL_MME_16 0x0040 489#define PCIM_MSICTRL_MME_32 0x0050 490#define PCIM_MSICTRL_MMC_MASK 0x000E 491#define PCIM_MSICTRL_MMC_1 0x0000 492#define PCIM_MSICTRL_MMC_2 0x0002 493#define PCIM_MSICTRL_MMC_4 0x0004 494#define PCIM_MSICTRL_MMC_8 0x0006 495#define PCIM_MSICTRL_MMC_16 0x0008 496#define PCIM_MSICTRL_MMC_32 0x000A 497#define PCIM_MSICTRL_MSI_ENABLE 0x0001 498#define PCIR_MSI_ADDR 0x4 499#define PCIR_MSI_ADDR_HIGH 0x8 500#define PCIR_MSI_DATA 0x8 501#define PCIR_MSI_DATA_64BIT 0xc 502#define PCIR_MSI_MASK 0x10 503#define PCIR_MSI_PENDING 0x14 504 505/* PCI-X definitions */ 506 507/* For header type 0 devices */ 508#define PCIXR_COMMAND 0x2 509#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 510#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 511#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 512#define PCIXM_COMMAND_MAX_READ_512 0x0000 513#define PCIXM_COMMAND_MAX_READ_1024 0x0004 514#define PCIXM_COMMAND_MAX_READ_2048 0x0008 515#define PCIXM_COMMAND_MAX_READ_4096 0x000c 516#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 517#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 518#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 519#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 520#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 521#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 522#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 523#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 524#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 525#define PCIXM_COMMAND_VERSION 0x3000 526#define PCIXR_STATUS 0x4 527#define PCIXM_STATUS_DEVFN 0x000000FF 528#define PCIXM_STATUS_BUS 0x0000FF00 529#define PCIXM_STATUS_64BIT 0x00010000 530#define PCIXM_STATUS_133CAP 0x00020000 531#define PCIXM_STATUS_SC_DISCARDED 0x00040000 532#define PCIXM_STATUS_UNEXP_SC 0x00080000 533#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 534#define PCIXM_STATUS_MAX_READ 0x00600000 535#define PCIXM_STATUS_MAX_READ_512 0x00000000 536#define PCIXM_STATUS_MAX_READ_1024 0x00200000 537#define PCIXM_STATUS_MAX_READ_2048 0x00400000 538#define PCIXM_STATUS_MAX_READ_4096 0x00600000 539#define PCIXM_STATUS_MAX_SPLITS 0x03800000 540#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 541#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 542#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 543#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 544#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 545#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 546#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 547#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 548#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 549#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 550#define PCIXM_STATUS_266CAP 0x40000000 551#define PCIXM_STATUS_533CAP 0x80000000 552 553/* For header type 1 devices (PCI-X bridges) */ 554#define PCIXR_SEC_STATUS 0x2 555#define PCIXM_SEC_STATUS_64BIT 0x0001 556#define PCIXM_SEC_STATUS_133CAP 0x0002 557#define PCIXM_SEC_STATUS_SC_DISC 0x0004 558#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 559#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 560#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 561#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 562#define PCIXM_SEC_STATUS_VERSION 0x3000 563#define PCIXM_SEC_STATUS_266CAP 0x4000 564#define PCIXM_SEC_STATUS_533CAP 0x8000 565#define PCIXR_BRIDGE_STATUS 0x4 566#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 567#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 568#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 569#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 570#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 571#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 572#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 573#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 574#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 575#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 576#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 577 578/* HT (HyperTransport) Capability definitions */ 579#define PCIR_HT_COMMAND 0x2 580#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 581#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 582#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 583#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 584#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 585#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 586#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 587#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 588#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 589#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 590#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 591#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 592#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 593#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 594 595/* HT MSI Mapping Capability definitions. */ 596#define PCIM_HTCMD_MSI_ENABLE 0x0001 597#define PCIM_HTCMD_MSI_FIXED 0x0002 598#define PCIR_HTMSI_ADDRESS_LO 0x4 599#define PCIR_HTMSI_ADDRESS_HI 0x8 600 601/* PCI Vendor capability definitions */ 602#define PCIR_VENDOR_LENGTH 0x2 603#define PCIR_VENDOR_DATA 0x3 604 605/* PCI EHCI Debug Port definitions */ 606#define PCIR_DEBUG_PORT 0x2 607#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 608#define PCIM_DEBUG_PORT_BAR 0xe000 609 610/* PCI-PCI Bridge Subvendor definitions */ 611#define PCIR_SUBVENDCAP_ID 0x4 612 613/* PCI Express definitions */ 614#define PCIR_EXPRESS_FLAGS 0x2 615#define PCIM_EXP_FLAGS_VERSION 0x000F 616#define PCIM_EXP_FLAGS_TYPE 0x00F0 617#define PCIM_EXP_TYPE_ENDPOINT 0x0000 618#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 619#define PCIM_EXP_TYPE_ROOT_PORT 0x0040 620#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 621#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 622#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 623#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 624#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 625#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 626#define PCIM_EXP_FLAGS_SLOT 0x0100 627#define PCIM_EXP_FLAGS_IRQ 0x3e00 628#define PCIR_EXPRESS_DEVICE_CAP 0x4 629#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 630#define PCIR_EXPRESS_DEVICE_CTL 0x8 631#define PCIM_EXP_CTL_NFER_ENABLE 0x0002 632#define PCIM_EXP_CTL_FER_ENABLE 0x0004 633#define PCIM_EXP_CTL_URR_ENABLE 0x0008 634#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 635#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 636#define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 637#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 638#define PCIR_EXPRESS_DEVICE_STA 0xa 639#define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 640#define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 641#define PCIM_EXP_STA_FATAL_ERROR 0x0004 642#define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008 643#define PCIM_EXP_STA_AUX_POWER 0x0010 644#define PCIM_EXP_STA_TRANSACTION_PND 0x0020 645#define PCIR_EXPRESS_LINK_CAP 0xc 646#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f 647#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 648#define PCIM_LINK_CAP_ASPM 0x00000c00 649#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 650#define PCIM_LINK_CAP_L1_EXIT 0x00038000 651#define PCIM_LINK_CAP_PORT 0xff000000 652#define PCIR_EXPRESS_LINK_CTL 0x10 653#define PCIR_EXPRESS_LINK_STA 0x12 654#define PCIM_LINK_STA_SPEED 0x000f 655#define PCIM_LINK_STA_WIDTH 0x03f0 656#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 657#define PCIM_LINK_STA_TRAINING 0x0800 658#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 659#define PCIR_EXPRESS_SLOT_CAP 0x14 660#define PCIR_EXPRESS_SLOT_CTL 0x18 661#define PCIR_EXPRESS_SLOT_STA 0x1a 662#define PCIR_EXPRESS_ROOT_CTL 0x1c 663#define PCIR_EXPRESS_ROOT_STA 0x20 664 665/* MSI-X definitions */ 666#define PCIR_MSIX_CTRL 0x2 667#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 668#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 669#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 670#define PCIR_MSIX_TABLE 0x4 671#define PCIR_MSIX_PBA 0x8 672#define PCIM_MSIX_BIR_MASK 0x7 673#define PCIM_MSIX_BIR_BAR_10 0 674#define PCIM_MSIX_BIR_BAR_14 1 675#define PCIM_MSIX_BIR_BAR_18 2 676#define PCIM_MSIX_BIR_BAR_1C 3 677#define PCIM_MSIX_BIR_BAR_20 4 678#define PCIM_MSIX_BIR_BAR_24 5 679#define PCIM_MSIX_VCTRL_MASK 0x1 680 681/* PCI Advanced Features definitions */ 682#define PCIR_PCIAF_CAP 0x3 683#define PCIM_PCIAFCAP_TP 0x01 684#define PCIM_PCIAFCAP_FLR 0x02 685#define PCIR_PCIAF_CTRL 0x4 686#define PCIR_PCIAFCTRL_FLR 0x01 687#define PCIR_PCIAF_STATUS 0x5 688#define PCIR_PCIAFSTATUS_TP 0x01 689 690/* Advanced Error Reporting */ 691#define PCIR_AER_UC_STATUS 0x04 692#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 693#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 694#define PCIM_AER_UC_POISONED_TLP 0x00001000 695#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 696#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 697#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 698#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 699#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 700#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 701#define PCIM_AER_UC_ECRC_ERROR 0x00080000 702#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 703#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 704#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 705#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 706#define PCIR_AER_COR_STATUS 0x10 707#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 708#define PCIM_AER_COR_BAD_TLP 0x00000040 709#define PCIM_AER_COR_BAD_DLLP 0x00000080 710#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 711#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 712#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 713#define PCIR_AER_CAP_CONTROL 0x18 714#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 715#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 716#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 717#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 718#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 719#define PCIR_AER_HEADER_LOG 0x1c 720#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 721#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 722#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 723#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 724#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 725#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 726#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 727#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 728#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 729#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 730#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 731#define PCIM_AER_ROOTERR_F_ERR 0x00000040 732#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 733#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 734#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 735 736/* Virtual Channel definitions */ 737#define PCIR_VC_CAP1 0x04 738#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 739#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 740#define PCIR_VC_CAP2 0x08 741#define PCIR_VC_CONTROL 0x0C 742#define PCIR_VC_STATUS 0x0E 743#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 744#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 745#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 746 747/* Serial Number definitions */ 748#define PCIR_SERIAL_LOW 0x04 749#define PCIR_SERIAL_HIGH 0x08 750