pcireg.h revision 197450
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 197450 2009-09-24 07:11:23Z avg $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 */ 40 41/* some PCI bus constants */ 42#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 43#define PCI_BUSMAX 255 /* highest supported bus number */ 44#define PCI_SLOTMAX 31 /* highest supported slot number */ 45#define PCI_FUNCMAX 7 /* highest supported function number */ 46#define PCI_REGMAX 255 /* highest supported config register addr. */ 47#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 48#define PCI_MAXHDRTYPE 2 49 50/* PCI config header registers for all devices */ 51 52#define PCIR_DEVVENDOR 0x00 53#define PCIR_VENDOR 0x00 54#define PCIR_DEVICE 0x02 55#define PCIR_COMMAND 0x04 56#define PCIM_CMD_PORTEN 0x0001 57#define PCIM_CMD_MEMEN 0x0002 58#define PCIM_CMD_BUSMASTEREN 0x0004 59#define PCIM_CMD_SPECIALEN 0x0008 60#define PCIM_CMD_MWRICEN 0x0010 61#define PCIM_CMD_PERRESPEN 0x0040 62#define PCIM_CMD_SERRESPEN 0x0100 63#define PCIM_CMD_BACKTOBACK 0x0200 64#define PCIM_CMD_INTxDIS 0x0400 65#define PCIR_STATUS 0x06 66#define PCIM_STATUS_CAPPRESENT 0x0010 67#define PCIM_STATUS_66CAPABLE 0x0020 68#define PCIM_STATUS_BACKTOBACK 0x0080 69#define PCIM_STATUS_PERRREPORT 0x0100 70#define PCIM_STATUS_SEL_FAST 0x0000 71#define PCIM_STATUS_SEL_MEDIMUM 0x0200 72#define PCIM_STATUS_SEL_SLOW 0x0400 73#define PCIM_STATUS_SEL_MASK 0x0600 74#define PCIM_STATUS_STABORT 0x0800 75#define PCIM_STATUS_RTABORT 0x1000 76#define PCIM_STATUS_RMABORT 0x2000 77#define PCIM_STATUS_SERR 0x4000 78#define PCIM_STATUS_PERR 0x8000 79#define PCIR_REVID 0x08 80#define PCIR_PROGIF 0x09 81#define PCIR_SUBCLASS 0x0a 82#define PCIR_CLASS 0x0b 83#define PCIR_CACHELNSZ 0x0c 84#define PCIR_LATTIMER 0x0d 85#define PCIR_HDRTYPE 0x0e 86#define PCIM_HDRTYPE 0x7f 87#define PCIM_HDRTYPE_NORMAL 0x00 88#define PCIM_HDRTYPE_BRIDGE 0x01 89#define PCIM_HDRTYPE_CARDBUS 0x02 90#define PCIM_MFDEV 0x80 91#define PCIR_BIST 0x0f 92 93/* Capability Register Offsets */ 94 95#define PCICAP_ID 0x0 96#define PCICAP_NEXTPTR 0x1 97 98/* Capability Identification Numbers */ 99 100#define PCIY_PMG 0x01 /* PCI Power Management */ 101#define PCIY_AGP 0x02 /* AGP */ 102#define PCIY_VPD 0x03 /* Vital Product Data */ 103#define PCIY_SLOTID 0x04 /* Slot Identification */ 104#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 105#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 106#define PCIY_PCIX 0x07 /* PCI-X */ 107#define PCIY_HT 0x08 /* HyperTransport */ 108#define PCIY_VENDOR 0x09 /* Vendor Unique */ 109#define PCIY_DEBUG 0x0a /* Debug port */ 110#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 111#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 112#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 113#define PCIY_AGP8X 0x0e /* AGP 8x */ 114#define PCIY_SECDEV 0x0f /* Secure Device */ 115#define PCIY_EXPRESS 0x10 /* PCI Express */ 116#define PCIY_MSIX 0x11 /* MSI-X */ 117#define PCIY_SATA 0x12 /* SATA */ 118#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 119 120/* config registers for header type 0 devices */ 121 122#define PCIR_BARS 0x10 123#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 124#define PCIR_MAX_BAR_0 5 125#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 126#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 127#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 128#define PCIM_BAR_SPACE 0x00000001 129#define PCIM_BAR_MEM_SPACE 0 130#define PCIM_BAR_IO_SPACE 1 131#define PCIM_BAR_MEM_TYPE 0x00000006 132#define PCIM_BAR_MEM_32 0 133#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 134#define PCIM_BAR_MEM_64 4 135#define PCIM_BAR_MEM_PREFETCH 0x00000008 136#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 137#define PCIM_BAR_IO_RESERVED 0x00000002 138#define PCIM_BAR_IO_BASE 0xfffffffc 139#define PCIR_CIS 0x28 140#define PCIM_CIS_ASI_MASK 0x00000007 141#define PCIM_CIS_ASI_CONFIG 0 142#define PCIM_CIS_ASI_BAR0 1 143#define PCIM_CIS_ASI_BAR1 2 144#define PCIM_CIS_ASI_BAR2 3 145#define PCIM_CIS_ASI_BAR3 4 146#define PCIM_CIS_ASI_BAR4 5 147#define PCIM_CIS_ASI_BAR5 6 148#define PCIM_CIS_ASI_ROM 7 149#define PCIM_CIS_ADDR_MASK 0x0ffffff8 150#define PCIM_CIS_ROM_MASK 0xf0000000 151#define PCIM_CIS_CONFIG_MASK 0xff 152#define PCIR_SUBVEND_0 0x2c 153#define PCIR_SUBDEV_0 0x2e 154#define PCIR_BIOS 0x30 155#define PCIM_BIOS_ENABLE 0x01 156#define PCIM_BIOS_ADDR_MASK 0xfffff800 157#define PCIR_CAP_PTR 0x34 158#define PCIR_INTLINE 0x3c 159#define PCIR_INTPIN 0x3d 160#define PCIR_MINGNT 0x3e 161#define PCIR_MAXLAT 0x3f 162 163/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 164 165#define PCIR_MAX_BAR_1 1 166#define PCIR_SECSTAT_1 0x1e 167 168#define PCIR_PRIBUS_1 0x18 169#define PCIR_SECBUS_1 0x19 170#define PCIR_SUBBUS_1 0x1a 171#define PCIR_SECLAT_1 0x1b 172 173#define PCIR_IOBASEL_1 0x1c 174#define PCIR_IOLIMITL_1 0x1d 175#define PCIR_IOBASEH_1 0x30 176#define PCIR_IOLIMITH_1 0x32 177#define PCIM_BRIO_16 0x0 178#define PCIM_BRIO_32 0x1 179#define PCIM_BRIO_MASK 0xf 180 181#define PCIR_MEMBASE_1 0x20 182#define PCIR_MEMLIMIT_1 0x22 183 184#define PCIR_PMBASEL_1 0x24 185#define PCIR_PMLIMITL_1 0x26 186#define PCIR_PMBASEH_1 0x28 187#define PCIR_PMLIMITH_1 0x2c 188#define PCIM_BRPM_32 0x0 189#define PCIM_BRPM_64 0x1 190#define PCIM_BRPM_MASK 0xf 191 192#define PCIR_BRIDGECTL_1 0x3e 193 194/* config registers for header type 2 (CardBus) devices */ 195 196#define PCIR_MAX_BAR_2 0 197#define PCIR_CAP_PTR_2 0x14 198#define PCIR_SECSTAT_2 0x16 199 200#define PCIR_PRIBUS_2 0x18 201#define PCIR_SECBUS_2 0x19 202#define PCIR_SUBBUS_2 0x1a 203#define PCIR_SECLAT_2 0x1b 204 205#define PCIR_MEMBASE0_2 0x1c 206#define PCIR_MEMLIMIT0_2 0x20 207#define PCIR_MEMBASE1_2 0x24 208#define PCIR_MEMLIMIT1_2 0x28 209#define PCIR_IOBASE0_2 0x2c 210#define PCIR_IOLIMIT0_2 0x30 211#define PCIR_IOBASE1_2 0x34 212#define PCIR_IOLIMIT1_2 0x38 213 214#define PCIR_BRIDGECTL_2 0x3e 215 216#define PCIR_SUBVEND_2 0x40 217#define PCIR_SUBDEV_2 0x42 218 219#define PCIR_PCCARDIF_2 0x44 220 221/* PCI device class, subclass and programming interface definitions */ 222 223#define PCIC_OLD 0x00 224#define PCIS_OLD_NONVGA 0x00 225#define PCIS_OLD_VGA 0x01 226 227#define PCIC_STORAGE 0x01 228#define PCIS_STORAGE_SCSI 0x00 229#define PCIS_STORAGE_IDE 0x01 230#define PCIP_STORAGE_IDE_MODEPRIM 0x01 231#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 232#define PCIP_STORAGE_IDE_MODESEC 0x04 233#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 234#define PCIP_STORAGE_IDE_MASTERDEV 0x80 235#define PCIS_STORAGE_FLOPPY 0x02 236#define PCIS_STORAGE_IPI 0x03 237#define PCIS_STORAGE_RAID 0x04 238#define PCIS_STORAGE_ATA_ADMA 0x05 239#define PCIS_STORAGE_SATA 0x06 240#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 241#define PCIS_STORAGE_SAS 0x07 242#define PCIS_STORAGE_OTHER 0x80 243 244#define PCIC_NETWORK 0x02 245#define PCIS_NETWORK_ETHERNET 0x00 246#define PCIS_NETWORK_TOKENRING 0x01 247#define PCIS_NETWORK_FDDI 0x02 248#define PCIS_NETWORK_ATM 0x03 249#define PCIS_NETWORK_ISDN 0x04 250#define PCIS_NETWORK_WORLDFIP 0x05 251#define PCIS_NETWORK_PICMG 0x06 252#define PCIS_NETWORK_OTHER 0x80 253 254#define PCIC_DISPLAY 0x03 255#define PCIS_DISPLAY_VGA 0x00 256#define PCIS_DISPLAY_XGA 0x01 257#define PCIS_DISPLAY_3D 0x02 258#define PCIS_DISPLAY_OTHER 0x80 259 260#define PCIC_MULTIMEDIA 0x04 261#define PCIS_MULTIMEDIA_VIDEO 0x00 262#define PCIS_MULTIMEDIA_AUDIO 0x01 263#define PCIS_MULTIMEDIA_TELE 0x02 264#define PCIS_MULTIMEDIA_HDA 0x03 265#define PCIS_MULTIMEDIA_OTHER 0x80 266 267#define PCIC_MEMORY 0x05 268#define PCIS_MEMORY_RAM 0x00 269#define PCIS_MEMORY_FLASH 0x01 270#define PCIS_MEMORY_OTHER 0x80 271 272#define PCIC_BRIDGE 0x06 273#define PCIS_BRIDGE_HOST 0x00 274#define PCIS_BRIDGE_ISA 0x01 275#define PCIS_BRIDGE_EISA 0x02 276#define PCIS_BRIDGE_MCA 0x03 277#define PCIS_BRIDGE_PCI 0x04 278#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 279#define PCIS_BRIDGE_PCMCIA 0x05 280#define PCIS_BRIDGE_NUBUS 0x06 281#define PCIS_BRIDGE_CARDBUS 0x07 282#define PCIS_BRIDGE_RACEWAY 0x08 283#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 284#define PCIS_BRIDGE_INFINIBAND 0x0a 285#define PCIS_BRIDGE_OTHER 0x80 286 287#define PCIC_SIMPLECOMM 0x07 288#define PCIS_SIMPLECOMM_UART 0x00 289#define PCIP_SIMPLECOMM_UART_8250 0x00 290#define PCIP_SIMPLECOMM_UART_16450A 0x01 291#define PCIP_SIMPLECOMM_UART_16550A 0x02 292#define PCIP_SIMPLECOMM_UART_16650A 0x03 293#define PCIP_SIMPLECOMM_UART_16750A 0x04 294#define PCIP_SIMPLECOMM_UART_16850A 0x05 295#define PCIP_SIMPLECOMM_UART_16950A 0x06 296#define PCIS_SIMPLECOMM_PAR 0x01 297#define PCIS_SIMPLECOMM_MULSER 0x02 298#define PCIS_SIMPLECOMM_MODEM 0x03 299#define PCIS_SIMPLECOMM_GPIB 0x04 300#define PCIS_SIMPLECOMM_SMART_CARD 0x05 301#define PCIS_SIMPLECOMM_OTHER 0x80 302 303#define PCIC_BASEPERIPH 0x08 304#define PCIS_BASEPERIPH_PIC 0x00 305#define PCIP_BASEPERIPH_PIC_8259A 0x00 306#define PCIP_BASEPERIPH_PIC_ISA 0x01 307#define PCIP_BASEPERIPH_PIC_EISA 0x02 308#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 309#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 310#define PCIS_BASEPERIPH_DMA 0x01 311#define PCIS_BASEPERIPH_TIMER 0x02 312#define PCIS_BASEPERIPH_RTC 0x03 313#define PCIS_BASEPERIPH_PCIHOT 0x04 314#define PCIS_BASEPERIPH_SDHC 0x05 315#define PCIS_BASEPERIPH_OTHER 0x80 316 317#define PCIC_INPUTDEV 0x09 318#define PCIS_INPUTDEV_KEYBOARD 0x00 319#define PCIS_INPUTDEV_DIGITIZER 0x01 320#define PCIS_INPUTDEV_MOUSE 0x02 321#define PCIS_INPUTDEV_SCANNER 0x03 322#define PCIS_INPUTDEV_GAMEPORT 0x04 323#define PCIS_INPUTDEV_OTHER 0x80 324 325#define PCIC_DOCKING 0x0a 326#define PCIS_DOCKING_GENERIC 0x00 327#define PCIS_DOCKING_OTHER 0x80 328 329#define PCIC_PROCESSOR 0x0b 330#define PCIS_PROCESSOR_386 0x00 331#define PCIS_PROCESSOR_486 0x01 332#define PCIS_PROCESSOR_PENTIUM 0x02 333#define PCIS_PROCESSOR_ALPHA 0x10 334#define PCIS_PROCESSOR_POWERPC 0x20 335#define PCIS_PROCESSOR_MIPS 0x30 336#define PCIS_PROCESSOR_COPROC 0x40 337 338#define PCIC_SERIALBUS 0x0c 339#define PCIS_SERIALBUS_FW 0x00 340#define PCIS_SERIALBUS_ACCESS 0x01 341#define PCIS_SERIALBUS_SSA 0x02 342#define PCIS_SERIALBUS_USB 0x03 343#define PCIP_SERIALBUS_USB_UHCI 0x00 344#define PCIP_SERIALBUS_USB_OHCI 0x10 345#define PCIP_SERIALBUS_USB_EHCI 0x20 346#define PCIP_SERIALBUS_USB_DEVICE 0xfe 347#define PCIS_SERIALBUS_FC 0x04 348#define PCIS_SERIALBUS_SMBUS 0x05 349#define PCIS_SERIALBUS_INFINIBAND 0x06 350#define PCIS_SERIALBUS_IPMI 0x07 351#define PCIP_SERIALBUS_IPMI_SMIC 0x00 352#define PCIP_SERIALBUS_IPMI_KCS 0x01 353#define PCIP_SERIALBUS_IPMI_BT 0x02 354#define PCIS_SERIALBUS_SERCOS 0x08 355#define PCIS_SERIALBUS_CANBUS 0x09 356 357#define PCIC_WIRELESS 0x0d 358#define PCIS_WIRELESS_IRDA 0x00 359#define PCIS_WIRELESS_IR 0x01 360#define PCIS_WIRELESS_RF 0x10 361#define PCIS_WIRELESS_BLUETOOTH 0x11 362#define PCIS_WIRELESS_BROADBAND 0x12 363#define PCIS_WIRELESS_80211A 0x20 364#define PCIS_WIRELESS_80211B 0x21 365#define PCIS_WIRELESS_OTHER 0x80 366 367#define PCIC_INTELLIIO 0x0e 368#define PCIS_INTELLIIO_I2O 0x00 369 370#define PCIC_SATCOM 0x0f 371#define PCIS_SATCOM_TV 0x01 372#define PCIS_SATCOM_AUDIO 0x02 373#define PCIS_SATCOM_VOICE 0x03 374#define PCIS_SATCOM_DATA 0x04 375 376#define PCIC_CRYPTO 0x10 377#define PCIS_CRYPTO_NETCOMP 0x00 378#define PCIS_CRYPTO_ENTERTAIN 0x10 379#define PCIS_CRYPTO_OTHER 0x80 380 381#define PCIC_DASP 0x11 382#define PCIS_DASP_DPIO 0x00 383#define PCIS_DASP_PERFCNTRS 0x01 384#define PCIS_DASP_COMM_SYNC 0x10 385#define PCIS_DASP_MGMT_CARD 0x20 386#define PCIS_DASP_OTHER 0x80 387 388#define PCIC_OTHER 0xff 389 390/* Bridge Control Values. */ 391#define PCIB_BCR_PERR_ENABLE 0x0001 392#define PCIB_BCR_SERR_ENABLE 0x0002 393#define PCIB_BCR_ISA_ENABLE 0x0004 394#define PCIB_BCR_VGA_ENABLE 0x0008 395#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 396#define PCIB_BCR_SECBUS_RESET 0x0040 397#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 398#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 399#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 400#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 401#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 402 403/* PCI power manangement */ 404#define PCIR_POWER_CAP 0x2 405#define PCIM_PCAP_SPEC 0x0007 406#define PCIM_PCAP_PMEREQCLK 0x0008 407#define PCIM_PCAP_PMEREQPWR 0x0010 408#define PCIM_PCAP_DEVSPECINIT 0x0020 409#define PCIM_PCAP_DYNCLOCK 0x0040 410#define PCIM_PCAP_SECCLOCK 0x00c0 411#define PCIM_PCAP_CLOCKMASK 0x00c0 412#define PCIM_PCAP_REQFULLCLOCK 0x0100 413#define PCIM_PCAP_D1SUPP 0x0200 414#define PCIM_PCAP_D2SUPP 0x0400 415#define PCIM_PCAP_D0PME 0x0800 416#define PCIM_PCAP_D1PME 0x1000 417#define PCIM_PCAP_D2PME 0x2000 418#define PCIM_PCAP_D3PME_HOT 0x4000 419#define PCIM_PCAP_D3PME_COLD 0x8000 420 421#define PCIR_POWER_STATUS 0x4 422#define PCIM_PSTAT_D0 0x0000 423#define PCIM_PSTAT_D1 0x0001 424#define PCIM_PSTAT_D2 0x0002 425#define PCIM_PSTAT_D3 0x0003 426#define PCIM_PSTAT_DMASK 0x0003 427#define PCIM_PSTAT_REPENABLE 0x0010 428#define PCIM_PSTAT_PMEENABLE 0x0100 429#define PCIM_PSTAT_D0POWER 0x0000 430#define PCIM_PSTAT_D1POWER 0x0200 431#define PCIM_PSTAT_D2POWER 0x0400 432#define PCIM_PSTAT_D3POWER 0x0600 433#define PCIM_PSTAT_D0HEAT 0x0800 434#define PCIM_PSTAT_D1HEAT 0x1000 435#define PCIM_PSTAT_D2HEAT 0x1200 436#define PCIM_PSTAT_D3HEAT 0x1400 437#define PCIM_PSTAT_DATAUNKN 0x0000 438#define PCIM_PSTAT_DATADIV10 0x2000 439#define PCIM_PSTAT_DATADIV100 0x4000 440#define PCIM_PSTAT_DATADIV1000 0x6000 441#define PCIM_PSTAT_DATADIVMASK 0x6000 442#define PCIM_PSTAT_PME 0x8000 443 444#define PCIR_POWER_PMCSR 0x6 445#define PCIM_PMCSR_DCLOCK 0x10 446#define PCIM_PMCSR_B2SUPP 0x20 447#define PCIM_BMCSR_B3SUPP 0x40 448#define PCIM_BMCSR_BPCE 0x80 449 450#define PCIR_POWER_DATA 0x7 451 452/* VPD capability registers */ 453#define PCIR_VPD_ADDR 0x2 454#define PCIR_VPD_DATA 0x4 455 456/* PCI Message Signalled Interrupts (MSI) */ 457#define PCIR_MSI_CTRL 0x2 458#define PCIM_MSICTRL_VECTOR 0x0100 459#define PCIM_MSICTRL_64BIT 0x0080 460#define PCIM_MSICTRL_MME_MASK 0x0070 461#define PCIM_MSICTRL_MME_1 0x0000 462#define PCIM_MSICTRL_MME_2 0x0010 463#define PCIM_MSICTRL_MME_4 0x0020 464#define PCIM_MSICTRL_MME_8 0x0030 465#define PCIM_MSICTRL_MME_16 0x0040 466#define PCIM_MSICTRL_MME_32 0x0050 467#define PCIM_MSICTRL_MMC_MASK 0x000E 468#define PCIM_MSICTRL_MMC_1 0x0000 469#define PCIM_MSICTRL_MMC_2 0x0002 470#define PCIM_MSICTRL_MMC_4 0x0004 471#define PCIM_MSICTRL_MMC_8 0x0006 472#define PCIM_MSICTRL_MMC_16 0x0008 473#define PCIM_MSICTRL_MMC_32 0x000A 474#define PCIM_MSICTRL_MSI_ENABLE 0x0001 475#define PCIR_MSI_ADDR 0x4 476#define PCIR_MSI_ADDR_HIGH 0x8 477#define PCIR_MSI_DATA 0x8 478#define PCIR_MSI_DATA_64BIT 0xc 479#define PCIR_MSI_MASK 0x10 480#define PCIR_MSI_PENDING 0x14 481 482/* PCI-X definitions */ 483 484/* For header type 0 devices */ 485#define PCIXR_COMMAND 0x2 486#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 487#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 488#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 489#define PCIXM_COMMAND_MAX_READ_512 0x0000 490#define PCIXM_COMMAND_MAX_READ_1024 0x0004 491#define PCIXM_COMMAND_MAX_READ_2048 0x0008 492#define PCIXM_COMMAND_MAX_READ_4096 0x000c 493#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 494#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 495#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 496#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 497#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 498#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 499#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 500#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 501#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 502#define PCIXM_COMMAND_VERSION 0x3000 503#define PCIXR_STATUS 0x4 504#define PCIXM_STATUS_DEVFN 0x000000FF 505#define PCIXM_STATUS_BUS 0x0000FF00 506#define PCIXM_STATUS_64BIT 0x00010000 507#define PCIXM_STATUS_133CAP 0x00020000 508#define PCIXM_STATUS_SC_DISCARDED 0x00040000 509#define PCIXM_STATUS_UNEXP_SC 0x00080000 510#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 511#define PCIXM_STATUS_MAX_READ 0x00600000 512#define PCIXM_STATUS_MAX_READ_512 0x00000000 513#define PCIXM_STATUS_MAX_READ_1024 0x00200000 514#define PCIXM_STATUS_MAX_READ_2048 0x00400000 515#define PCIXM_STATUS_MAX_READ_4096 0x00600000 516#define PCIXM_STATUS_MAX_SPLITS 0x03800000 517#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 518#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 519#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 520#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 521#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 522#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 523#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 524#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 525#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 526#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 527#define PCIXM_STATUS_266CAP 0x40000000 528#define PCIXM_STATUS_533CAP 0x80000000 529 530/* For header type 1 devices (PCI-X bridges) */ 531#define PCIXR_SEC_STATUS 0x2 532#define PCIXM_SEC_STATUS_64BIT 0x0001 533#define PCIXM_SEC_STATUS_133CAP 0x0002 534#define PCIXM_SEC_STATUS_SC_DISC 0x0004 535#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 536#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 537#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 538#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 539#define PCIXM_SEC_STATUS_VERSION 0x3000 540#define PCIXM_SEC_STATUS_266CAP 0x4000 541#define PCIXM_SEC_STATUS_533CAP 0x8000 542#define PCIXR_BRIDGE_STATUS 0x4 543#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 544#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 545#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 546#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 547#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 548#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 549#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 550#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 551#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 552#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 553#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 554 555/* HT (HyperTransport) Capability definitions */ 556#define PCIR_HT_COMMAND 0x2 557#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 558#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 559#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 560#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 561#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 562#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 563#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 564#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 565#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 566#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 567#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 568#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 569#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 570#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 571 572/* HT MSI Mapping Capability definitions. */ 573#define PCIM_HTCMD_MSI_ENABLE 0x0001 574#define PCIM_HTCMD_MSI_FIXED 0x0002 575#define PCIR_HTMSI_ADDRESS_LO 0x4 576#define PCIR_HTMSI_ADDRESS_HI 0x8 577 578/* PCI Vendor capability definitions */ 579#define PCIR_VENDOR_LENGTH 0x2 580#define PCIR_VENDOR_DATA 0x3 581 582/* PCI EHCI Debug Port definitions */ 583#define PCIR_DEBUG_PORT 0x2 584#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 585#define PCIM_DEBUG_PORT_BAR 0xe000 586 587/* PCI-PCI Bridge Subvendor definitions */ 588#define PCIR_SUBVENDCAP_ID 0x4 589 590/* PCI Express definitions */ 591#define PCIR_EXPRESS_FLAGS 0x2 592#define PCIM_EXP_FLAGS_VERSION 0x000F 593#define PCIM_EXP_FLAGS_TYPE 0x00F0 594#define PCIM_EXP_TYPE_ENDPOINT 0x0000 595#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 596#define PCIM_EXP_TYPE_ROOT_PORT 0x0040 597#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 598#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 599#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 600#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 601#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 602#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 603#define PCIM_EXP_FLAGS_SLOT 0x0100 604#define PCIM_EXP_FLAGS_IRQ 0x3e00 605#define PCIR_EXPRESS_DEVICE_CAP 0x4 606#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 607#define PCIR_EXPRESS_DEVICE_CTL 0x8 608#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 609#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 610#define PCIR_EXPRESS_DEVICE_STA 0xa 611#define PCIR_EXPRESS_LINK_CAP 0xc 612#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f 613#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 614#define PCIM_LINK_CAP_ASPM 0x00000c00 615#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 616#define PCIM_LINK_CAP_L1_EXIT 0x00038000 617#define PCIM_LINK_CAP_PORT 0xff000000 618#define PCIR_EXPRESS_LINK_CTL 0x10 619#define PCIR_EXPRESS_LINK_STA 0x12 620#define PCIM_LINK_STA_SPEED 0x000f 621#define PCIM_LINK_STA_WIDTH 0x03f0 622#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 623#define PCIM_LINK_STA_TRAINING 0x0800 624#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 625#define PCIR_EXPRESS_SLOT_CAP 0x14 626#define PCIR_EXPRESS_SLOT_CTL 0x18 627#define PCIR_EXPRESS_SLOT_STA 0x1a 628#define PCIR_EXPRESS_ROOT_CTL 0x1c 629#define PCIR_EXPRESS_ROOT_STA 0x20 630 631/* MSI-X definitions */ 632#define PCIR_MSIX_CTRL 0x2 633#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 634#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 635#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 636#define PCIR_MSIX_TABLE 0x4 637#define PCIR_MSIX_PBA 0x8 638#define PCIM_MSIX_BIR_MASK 0x7 639#define PCIM_MSIX_BIR_BAR_10 0 640#define PCIM_MSIX_BIR_BAR_14 1 641#define PCIM_MSIX_BIR_BAR_18 2 642#define PCIM_MSIX_BIR_BAR_1C 3 643#define PCIM_MSIX_BIR_BAR_20 4 644#define PCIM_MSIX_BIR_BAR_24 5 645#define PCIM_MSIX_VCTRL_MASK 0x1 646 647/* PCI Advanced Features definitions */ 648#define PCIR_PCIAF_CAP 0x3 649#define PCIM_PCIAFCAP_TP 0x01 650#define PCIM_PCIAFCAP_FLR 0x02 651#define PCIR_PCIAF_CTRL 0x4 652#define PCIR_PCIAFCTRL_FLR 0x01 653#define PCIR_PCIAF_STATUS 0x5 654#define PCIR_PCIAFSTATUS_TP 0x01 655