pcireg.h revision 165131
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 165131 2006-12-12 19:33:25Z jhb $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 */ 40 41/* some PCI bus constants */ 42 43#define PCI_BUSMAX 255 44#define PCI_SLOTMAX 31 45#define PCI_FUNCMAX 7 46#define PCI_REGMAX 255 47#define PCI_MAXHDRTYPE 2 48 49/* PCI config header registers for all devices */ 50 51#define PCIR_DEVVENDOR 0x00 52#define PCIR_VENDOR 0x00 53#define PCIR_DEVICE 0x02 54#define PCIR_COMMAND 0x04 55#define PCIM_CMD_PORTEN 0x0001 56#define PCIM_CMD_MEMEN 0x0002 57#define PCIM_CMD_BUSMASTEREN 0x0004 58#define PCIM_CMD_SPECIALEN 0x0008 59#define PCIM_CMD_MWRICEN 0x0010 60#define PCIM_CMD_PERRESPEN 0x0040 61#define PCIM_CMD_SERRESPEN 0x0100 62#define PCIM_CMD_BACKTOBACK 0x0200 63#define PCIR_STATUS 0x06 64#define PCIM_STATUS_CAPPRESENT 0x0010 65#define PCIM_STATUS_66CAPABLE 0x0020 66#define PCIM_STATUS_BACKTOBACK 0x0080 67#define PCIM_STATUS_PERRREPORT 0x0100 68#define PCIM_STATUS_SEL_FAST 0x0000 69#define PCIM_STATUS_SEL_MEDIMUM 0x0200 70#define PCIM_STATUS_SEL_SLOW 0x0400 71#define PCIM_STATUS_SEL_MASK 0x0600 72#define PCIM_STATUS_STABORT 0x0800 73#define PCIM_STATUS_RTABORT 0x1000 74#define PCIM_STATUS_RMABORT 0x2000 75#define PCIM_STATUS_SERR 0x4000 76#define PCIM_STATUS_PERR 0x8000 77#define PCIR_REVID 0x08 78#define PCIR_PROGIF 0x09 79#define PCIR_SUBCLASS 0x0a 80#define PCIR_CLASS 0x0b 81#define PCIR_CACHELNSZ 0x0c 82#define PCIR_LATTIMER 0x0d 83#define PCIR_HDRTYPE 0x0e 84#define PCIM_HDRTYPE 0x7f 85#define PCIM_HDRTYPE_NORMAL 0x00 86#define PCIM_HDRTYPE_BRIDGE 0x01 87#define PCIM_HDRTYPE_CARDBUS 0x02 88#define PCIM_MFDEV 0x80 89#define PCIR_BIST 0x0f 90 91/* Capability Register Offsets */ 92 93#define PCICAP_ID 0x0 94#define PCICAP_NEXTPTR 0x1 95 96/* Capability Identification Numbers */ 97 98#define PCIY_PMG 0x01 /* PCI Power Management */ 99#define PCIY_AGP 0x02 /* AGP */ 100#define PCIY_VPD 0x03 /* Vital Product Data */ 101#define PCIY_SLOTID 0x04 /* Slot Identification */ 102#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 103#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 104#define PCIY_PCIX 0x07 /* PCI-X */ 105#define PCIY_HT 0x08 /* HyperTransport */ 106#define PCIY_VENDOR 0x09 /* Vendor Unique */ 107#define PCIY_DEBUG 0x0a /* Debug port */ 108#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 109#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 110#define PCIY_AGP8X 0x0e /* AGP 8x */ 111#define PCIY_SECDEV 0x0f /* Secure Device */ 112#define PCIY_EXPRESS 0x10 /* PCI Express */ 113#define PCIY_MSIX 0x11 /* MSI-X */ 114 115/* config registers for header type 0 devices */ 116 117#define PCIR_BARS 0x10 118#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 119#define PCI_RID2BAR(rid) (((rid)-PCIR_BARS)/4) 120#define PCIR_CIS 0x28 121#define PCIM_CIS_ASI_MASK 0x7 122#define PCIM_CIS_ASI_TUPLE 0 123#define PCIM_CIS_ASI_BAR0 1 124#define PCIM_CIS_ASI_BAR1 2 125#define PCIM_CIS_ASI_BAR2 3 126#define PCIM_CIS_ASI_BAR3 4 127#define PCIM_CIS_ASI_BAR4 5 128#define PCIM_CIS_ASI_BAR5 6 129#define PCIM_CIS_ASI_ROM 7 130#define PCIM_CIS_ADDR_MASK 0x0ffffff8 131#define PCIM_CIS_ROM_MASK 0xf0000000 132#define PCIR_SUBVEND_0 0x2c 133#define PCIR_SUBDEV_0 0x2e 134#define PCIR_BIOS 0x30 135#define PCIM_BIOS_ENABLE 0x01 136#define PCIM_BIOS_ADDR_MASK 0xfffff800 137#define PCIR_CAP_PTR 0x34 138#define PCIR_INTLINE 0x3c 139#define PCIR_INTPIN 0x3d 140#define PCIR_MINGNT 0x3e 141#define PCIR_MAXLAT 0x3f 142 143/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 144 145#define PCIR_SECSTAT_1 0x1e 146 147#define PCIR_PRIBUS_1 0x18 148#define PCIR_SECBUS_1 0x19 149#define PCIR_SUBBUS_1 0x1a 150#define PCIR_SECLAT_1 0x1b 151 152#define PCIR_IOBASEL_1 0x1c 153#define PCIR_IOLIMITL_1 0x1d 154#define PCIR_IOBASEH_1 0x30 155#define PCIR_IOLIMITH_1 0x32 156#define PCIM_BRIO_16 0x0 157#define PCIM_BRIO_32 0x1 158#define PCIM_BRIO_MASK 0xf 159 160#define PCIR_MEMBASE_1 0x20 161#define PCIR_MEMLIMIT_1 0x22 162 163#define PCIR_PMBASEL_1 0x24 164#define PCIR_PMLIMITL_1 0x26 165#define PCIR_PMBASEH_1 0x28 166#define PCIR_PMLIMITH_1 0x2c 167 168#define PCIR_BRIDGECTL_1 0x3e 169 170#define PCIR_SUBVEND_1 0x34 171#define PCIR_SUBDEV_1 0x36 172 173/* config registers for header type 2 (CardBus) devices */ 174 175#define PCIR_CAP_PTR_2 0x14 176#define PCIR_SECSTAT_2 0x16 177 178#define PCIR_PRIBUS_2 0x18 179#define PCIR_SECBUS_2 0x19 180#define PCIR_SUBBUS_2 0x1a 181#define PCIR_SECLAT_2 0x1b 182 183#define PCIR_MEMBASE0_2 0x1c 184#define PCIR_MEMLIMIT0_2 0x20 185#define PCIR_MEMBASE1_2 0x24 186#define PCIR_MEMLIMIT1_2 0x28 187#define PCIR_IOBASE0_2 0x2c 188#define PCIR_IOLIMIT0_2 0x30 189#define PCIR_IOBASE1_2 0x34 190#define PCIR_IOLIMIT1_2 0x38 191 192#define PCIR_BRIDGECTL_2 0x3e 193 194#define PCIR_SUBVEND_2 0x40 195#define PCIR_SUBDEV_2 0x42 196 197#define PCIR_PCCARDIF_2 0x44 198 199/* PCI device class, subclass and programming interface definitions */ 200 201#define PCIC_OLD 0x00 202#define PCIS_OLD_NONVGA 0x00 203#define PCIS_OLD_VGA 0x01 204 205#define PCIC_STORAGE 0x01 206#define PCIS_STORAGE_SCSI 0x00 207#define PCIS_STORAGE_IDE 0x01 208#define PCIP_STORAGE_IDE_MODEPRIM 0x01 209#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 210#define PCIP_STORAGE_IDE_MODESEC 0x04 211#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 212#define PCIP_STORAGE_IDE_MASTERDEV 0x80 213#define PCIS_STORAGE_FLOPPY 0x02 214#define PCIS_STORAGE_IPI 0x03 215#define PCIS_STORAGE_RAID 0x04 216#define PCIS_STORAGE_OTHER 0x80 217 218#define PCIC_NETWORK 0x02 219#define PCIS_NETWORK_ETHERNET 0x00 220#define PCIS_NETWORK_TOKENRING 0x01 221#define PCIS_NETWORK_FDDI 0x02 222#define PCIS_NETWORK_ATM 0x03 223#define PCIS_NETWORK_ISDN 0x04 224#define PCIS_NETWORK_OTHER 0x80 225 226#define PCIC_DISPLAY 0x03 227#define PCIS_DISPLAY_VGA 0x00 228#define PCIS_DISPLAY_XGA 0x01 229#define PCIS_DISPLAY_3D 0x02 230#define PCIS_DISPLAY_OTHER 0x80 231 232#define PCIC_MULTIMEDIA 0x04 233#define PCIS_MULTIMEDIA_VIDEO 0x00 234#define PCIS_MULTIMEDIA_AUDIO 0x01 235#define PCIS_MULTIMEDIA_TELE 0x02 236#define PCIS_MULTIMEDIA_OTHER 0x80 237 238#define PCIC_MEMORY 0x05 239#define PCIS_MEMORY_RAM 0x00 240#define PCIS_MEMORY_FLASH 0x01 241#define PCIS_MEMORY_OTHER 0x80 242 243#define PCIC_BRIDGE 0x06 244#define PCIS_BRIDGE_HOST 0x00 245#define PCIS_BRIDGE_ISA 0x01 246#define PCIS_BRIDGE_EISA 0x02 247#define PCIS_BRIDGE_MCA 0x03 248#define PCIS_BRIDGE_PCI 0x04 249#define PCIS_BRIDGE_PCMCIA 0x05 250#define PCIS_BRIDGE_NUBUS 0x06 251#define PCIS_BRIDGE_CARDBUS 0x07 252#define PCIS_BRIDGE_RACEWAY 0x08 253#define PCIS_BRIDGE_OTHER 0x80 254 255#define PCIC_SIMPLECOMM 0x07 256#define PCIS_SIMPLECOMM_UART 0x00 257#define PCIP_SIMPLECOMM_UART_16550A 0x02 258#define PCIS_SIMPLECOMM_PAR 0x01 259#define PCIS_SIMPLECOMM_MULSER 0x02 260#define PCIS_SIMPLECOMM_MODEM 0x03 261#define PCIS_SIMPLECOMM_OTHER 0x80 262 263#define PCIC_BASEPERIPH 0x08 264#define PCIS_BASEPERIPH_PIC 0x00 265#define PCIS_BASEPERIPH_DMA 0x01 266#define PCIS_BASEPERIPH_TIMER 0x02 267#define PCIS_BASEPERIPH_RTC 0x03 268#define PCIS_BASEPERIPH_PCIHOT 0x04 269#define PCIS_BASEPERIPH_SDHC 0x05 270#define PCIS_BASEPERIPH_OTHER 0x80 271 272#define PCIC_INPUTDEV 0x09 273#define PCIS_INPUTDEV_KEYBOARD 0x00 274#define PCIS_INPUTDEV_DIGITIZER 0x01 275#define PCIS_INPUTDEV_MOUSE 0x02 276#define PCIS_INPUTDEV_SCANNER 0x03 277#define PCIS_INPUTDEV_GAMEPORT 0x04 278#define PCIS_INPUTDEV_OTHER 0x80 279 280#define PCIC_DOCKING 0x0a 281#define PCIS_DOCKING_GENERIC 0x00 282#define PCIS_DOCKING_OTHER 0x80 283 284#define PCIC_PROCESSOR 0x0b 285#define PCIS_PROCESSOR_386 0x00 286#define PCIS_PROCESSOR_486 0x01 287#define PCIS_PROCESSOR_PENTIUM 0x02 288#define PCIS_PROCESSOR_ALPHA 0x10 289#define PCIS_PROCESSOR_POWERPC 0x20 290#define PCIS_PROCESSOR_MIPS 0x30 291#define PCIS_PROCESSOR_COPROC 0x40 292 293#define PCIC_SERIALBUS 0x0c 294#define PCIS_SERIALBUS_FW 0x00 295#define PCIS_SERIALBUS_ACCESS 0x01 296#define PCIS_SERIALBUS_SSA 0x02 297#define PCIS_SERIALBUS_USB 0x03 298#define PCIP_SERIALBUS_USB_UHCI 0x00 299#define PCIP_SERIALBUS_USB_OHCI 0x10 300#define PCIP_SERIALBUS_USB_EHCI 0x20 301#define PCIS_SERIALBUS_FC 0x04 302#define PCIS_SERIALBUS_SMBUS 0x05 303 304#define PCIC_WIRELESS 0x0d 305#define PCIS_WIRELESS_IRDA 0x00 306#define PCIS_WIRELESS_IR 0x01 307#define PCIS_WIRELESS_RF 0x10 308#define PCIS_WIRELESS_OTHER 0x80 309 310#define PCIC_INTELLIIO 0x0e 311#define PCIS_INTELLIIO_I2O 0x00 312 313#define PCIC_SATCOM 0x0f 314#define PCIS_SATCOM_TV 0x01 315#define PCIS_SATCOM_AUDIO 0x02 316#define PCIS_SATCOM_VOICE 0x03 317#define PCIS_SATCOM_DATA 0x04 318 319#define PCIC_CRYPTO 0x10 320#define PCIS_CRYPTO_NETCOMP 0x00 321#define PCIS_CRYPTO_ENTERTAIN 0x10 322#define PCIS_CRYPTO_OTHER 0x80 323 324#define PCIC_DASP 0x11 325#define PCIS_DASP_DPIO 0x00 326#define PCIS_DASP_OTHER 0x80 327 328#define PCIC_OTHER 0xff 329 330/* Bridge Control Values. */ 331#define PCIB_BCR_PERR_ENABLE 0x0001 332#define PCIB_BCR_SERR_ENABLE 0x0002 333#define PCIB_BCR_ISA_ENABLE 0x0004 334#define PCIB_BCR_VGA_ENABLE 0x0008 335#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 336#define PCIB_BCR_SECBUS_RESET 0x0040 337#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 338#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 339#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 340#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 341#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 342 343/* PCI power manangement */ 344 345#define PCIR_POWER_CAP 0x2 346#define PCIM_PCAP_SPEC 0x0007 347#define PCIM_PCAP_PMEREQCLK 0x0008 348#define PCIM_PCAP_PMEREQPWR 0x0010 349#define PCIM_PCAP_DEVSPECINIT 0x0020 350#define PCIM_PCAP_DYNCLOCK 0x0040 351#define PCIM_PCAP_SECCLOCK 0x00c0 352#define PCIM_PCAP_CLOCKMASK 0x00c0 353#define PCIM_PCAP_REQFULLCLOCK 0x0100 354#define PCIM_PCAP_D1SUPP 0x0200 355#define PCIM_PCAP_D2SUPP 0x0400 356#define PCIM_PCAP_D0PME 0x1000 357#define PCIM_PCAP_D1PME 0x2000 358#define PCIM_PCAP_D2PME 0x4000 359 360#define PCIR_POWER_STATUS 0x4 361#define PCIM_PSTAT_D0 0x0000 362#define PCIM_PSTAT_D1 0x0001 363#define PCIM_PSTAT_D2 0x0002 364#define PCIM_PSTAT_D3 0x0003 365#define PCIM_PSTAT_DMASK 0x0003 366#define PCIM_PSTAT_REPENABLE 0x0010 367#define PCIM_PSTAT_PMEENABLE 0x0100 368#define PCIM_PSTAT_D0POWER 0x0000 369#define PCIM_PSTAT_D1POWER 0x0200 370#define PCIM_PSTAT_D2POWER 0x0400 371#define PCIM_PSTAT_D3POWER 0x0600 372#define PCIM_PSTAT_D0HEAT 0x0800 373#define PCIM_PSTAT_D1HEAT 0x1000 374#define PCIM_PSTAT_D2HEAT 0x1200 375#define PCIM_PSTAT_D3HEAT 0x1400 376#define PCIM_PSTAT_DATAUNKN 0x0000 377#define PCIM_PSTAT_DATADIV10 0x2000 378#define PCIM_PSTAT_DATADIV100 0x4000 379#define PCIM_PSTAT_DATADIV1000 0x6000 380#define PCIM_PSTAT_DATADIVMASK 0x6000 381#define PCIM_PSTAT_PME 0x8000 382 383#define PCIR_POWER_PMCSR 0x6 384#define PCIM_PMCSR_DCLOCK 0x10 385#define PCIM_PMCSR_B2SUPP 0x20 386#define PCIM_BMCSR_B3SUPP 0x40 387#define PCIM_BMCSR_BPCE 0x80 388 389#define PCIR_POWER_DATA 0x7 390 391/* PCI Message Signalled Interrupts (MSI) */ 392#define PCIR_MSI_CTRL 0x2 393#define PCIM_MSICTRL_VECTOR 0x0100 394#define PCIM_MSICTRL_64BIT 0x0080 395#define PCIM_MSICTRL_MME_MASK 0x0070 396#define PCIM_MSICTRL_MME_1 0x0000 397#define PCIM_MSICTRL_MME_2 0x0010 398#define PCIM_MSICTRL_MME_4 0x0020 399#define PCIM_MSICTRL_MME_8 0x0030 400#define PCIM_MSICTRL_MME_16 0x0040 401#define PCIM_MSICTRL_MME_32 0x0050 402#define PCIM_MSICTRL_MMC_MASK 0x000E 403#define PCIM_MSICTRL_MMC_1 0x0000 404#define PCIM_MSICTRL_MMC_2 0x0002 405#define PCIM_MSICTRL_MMC_4 0x0004 406#define PCIM_MSICTRL_MMC_8 0x0006 407#define PCIM_MSICTRL_MMC_16 0x0008 408#define PCIM_MSICTRL_MMC_32 0x000A 409#define PCIM_MSICTRL_MSI_ENABLE 0x0001 410#define PCIR_MSI_ADDR 0x4 411#define PCIR_MSI_ADDR_HIGH 0x8 412#define PCIR_MSI_DATA 0x8 413#define PCIR_MSI_DATA_64BIT 0xc 414#define PCIR_MSI_MASK 0x10 415#define PCIR_MSI_PENDING 0x14 416 417/* PCI-X definitions */ 418#define PCIXR_COMMAND 0x96 419#define PCIXR_DEVADDR 0x98 420#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 421#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 422#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 423#define PCIXR_STATUS 0x9A 424#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 425#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 426#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 427#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 428#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 429#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 430#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 431#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 432#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 433 434/* HT (HyperTransport) Capability definitions */ 435#define PCIR_HT_COMMAND 0x2 436#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 437#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 438#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 439#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 440#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 441#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 442#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 443#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 444#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 445#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 446#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 447#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 448#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 449 450/* HT MSI Mapping Capability definitions. */ 451#define PCIM_HTCMD_MSI_ENABLE 0x0001 452#define PCIR_HTMSI_ADDRESS_LO 0x4 453#define PCIR_HTMSI_ADDRESS_HI 0x8 454 455/* MSI-X definitions */ 456#define PCIR_MSIX_CTRL 0x2 457#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 458#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 459#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 460#define PCIR_MSIX_TABLE 0x4 461#define PCIR_MSIX_PBA 0x8 462#define PCIM_MSIX_BIR_MASK 0x7 463#define PCIM_MSIX_BIR_BAR_10 0 464#define PCIM_MSIX_BIR_BAR_14 1 465#define PCIM_MSIX_BIR_BAR_18 2 466#define PCIM_MSIX_BIR_BAR_1C 3 467#define PCIM_MSIX_BIR_BAR_20 4 468#define PCIM_MSIX_BIR_BAR_24 5 469#define PCIM_MSIX_VCTRL_MASK 0x1 470