pcireg.h revision 151787
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 151787 2005-10-28 05:57:10Z imp $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 */ 40 41/* some PCI bus constants */ 42 43#define PCI_BUSMAX 255 44#define PCI_SLOTMAX 31 45#define PCI_FUNCMAX 7 46#define PCI_REGMAX 255 47#define PCI_MAXHDRTYPE 2 48 49/* PCI config header registers for all devices */ 50 51#define PCIR_DEVVENDOR 0x00 52#define PCIR_VENDOR 0x00 53#define PCIR_DEVICE 0x02 54#define PCIR_COMMAND 0x04 55#define PCIM_CMD_PORTEN 0x0001 56#define PCIM_CMD_MEMEN 0x0002 57#define PCIM_CMD_BUSMASTEREN 0x0004 58#define PCIM_CMD_SPECIALEN 0x0008 59#define PCIM_CMD_MWRICEN 0x0010 60#define PCIM_CMD_PERRESPEN 0x0040 61#define PCIM_CMD_SERRESPEN 0x0100 62#define PCIM_CMD_BACKTOBACK 0x0200 63#define PCIR_STATUS 0x06 64#define PCIM_STATUS_CAPPRESENT 0x0010 65#define PCIM_STATUS_66CAPABLE 0x0020 66#define PCIM_STATUS_BACKTOBACK 0x0080 67#define PCIM_STATUS_PERRREPORT 0x0100 68#define PCIM_STATUS_SEL_FAST 0x0000 69#define PCIM_STATUS_SEL_MEDIMUM 0x0200 70#define PCIM_STATUS_SEL_SLOW 0x0400 71#define PCIM_STATUS_SEL_MASK 0x0600 72#define PCIM_STATUS_STABORT 0x0800 73#define PCIM_STATUS_RTABORT 0x1000 74#define PCIM_STATUS_RMABORT 0x2000 75#define PCIM_STATUS_SERR 0x4000 76#define PCIM_STATUS_PERR 0x8000 77#define PCIR_REVID 0x08 78#define PCIR_PROGIF 0x09 79#define PCIR_SUBCLASS 0x0a 80#define PCIR_CLASS 0x0b 81#define PCIR_CACHELNSZ 0x0c 82#define PCIR_LATTIMER 0x0d 83#define PCIR_HDRTYPE 0x0e 84#define PCIM_HDRTYPE 0x7f 85#define PCIM_HDRTYPE_NORMAL 0x00 86#define PCIM_HDRTYPE_BRIDGE 0x01 87#define PCIM_HDRTYPE_CARDBUS 0x02 88#define PCIM_MFDEV 0x80 89#define PCIR_BIST 0x0f 90 91/* Capability Identification Numbers */ 92 93#define PCIY_PMG 0x01 /* PCI Power Management */ 94#define PCIY_AGP 0x02 /* AGP */ 95#define PCIY_VPD 0x03 /* Vital Product Data */ 96#define PCIY_SLOTID 0x04 /* Slot Identification */ 97#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 98#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 99#define PCIY_PCIX 0x07 /* PCI-X */ 100#define PCIY_HT 0x08 /* HyperTransport */ 101#define PCIY_VENDOR 0x09 /* Vendor Unique */ 102#define PCIY_DEBUG 0x0a /* Debug port */ 103#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 104#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 105#define PCIY_AGP8X 0x0e /* AGP 8x */ 106#define PCIY_SECDEV 0x0f /* Secure Device */ 107#define PCIY_EXPRESS 0x10 /* PCI Express */ 108#define PCIY_MSIX 0x11 /* MSI-X */ 109 110/* config registers for header type 0 devices */ 111 112#define PCIR_BARS 0x10 113#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 114#define PCIR_CIS 0x28 115#define PCIM_CIS_ASI_MASK 0x7 116#define PCIM_CIS_ASI_TUPLE 0 117#define PCIM_CIS_ASI_BAR0 1 118#define PCIM_CIS_ASI_BAR1 2 119#define PCIM_CIS_ASI_BAR2 3 120#define PCIM_CIS_ASI_BAR3 4 121#define PCIM_CIS_ASI_BAR4 5 122#define PCIM_CIS_ASI_BAR5 6 123#define PCIM_CIS_ASI_ROM 7 124#define PCIM_CIS_ADDR_MASK 0x0ffffff8 125#define PCIM_CIS_ROM_MASK 0xf0000000 126#define PCIR_SUBVEND_0 0x2c 127#define PCIR_SUBDEV_0 0x2e 128#define PCIR_BIOS 0x30 129#define PCIM_BIOS_ENABLE 0x01 130#define PCIR_CAP_PTR 0x34 131#define PCIR_INTLINE 0x3c 132#define PCIR_INTPIN 0x3d 133#define PCIR_MINGNT 0x3e 134#define PCIR_MAXLAT 0x3f 135 136/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 137 138#define PCIR_SECSTAT_1 0x1e 139 140#define PCIR_PRIBUS_1 0x18 141#define PCIR_SECBUS_1 0x19 142#define PCIR_SUBBUS_1 0x1a 143#define PCIR_SECLAT_1 0x1b 144 145#define PCIR_IOBASEL_1 0x1c 146#define PCIR_IOLIMITL_1 0x1d 147#define PCIR_IOBASEH_1 0x30 148#define PCIR_IOLIMITH_1 0x32 149#define PCIM_BRIO_16 0x0 150#define PCIM_BRIO_32 0x1 151#define PCIM_BRIO_MASK 0xf 152 153#define PCIR_MEMBASE_1 0x20 154#define PCIR_MEMLIMIT_1 0x22 155 156#define PCIR_PMBASEL_1 0x24 157#define PCIR_PMLIMITL_1 0x26 158#define PCIR_PMBASEH_1 0x28 159#define PCIR_PMLIMITH_1 0x2c 160 161#define PCIR_BRIDGECTL_1 0x3e 162 163#define PCIR_SUBVEND_1 0x34 164#define PCIR_SUBDEV_1 0x36 165 166/* config registers for header type 2 (CardBus) devices */ 167 168#define PCIR_SECSTAT_2 0x16 169 170#define PCIR_PRIBUS_2 0x18 171#define PCIR_SECBUS_2 0x19 172#define PCIR_SUBBUS_2 0x1a 173#define PCIR_SECLAT_2 0x1b 174 175#define PCIR_MEMBASE0_2 0x1c 176#define PCIR_MEMLIMIT0_2 0x20 177#define PCIR_MEMBASE1_2 0x24 178#define PCIR_MEMLIMIT1_2 0x28 179#define PCIR_IOBASE0_2 0x2c 180#define PCIR_IOLIMIT0_2 0x30 181#define PCIR_IOBASE1_2 0x34 182#define PCIR_IOLIMIT1_2 0x38 183 184#define PCIR_BRIDGECTL_2 0x3e 185 186#define PCIR_SUBVEND_2 0x40 187#define PCIR_SUBDEV_2 0x42 188 189#define PCIR_PCCARDIF_2 0x44 190 191/* PCI device class, subclass and programming interface definitions */ 192 193#define PCIC_OLD 0x00 194#define PCIS_OLD_NONVGA 0x00 195#define PCIS_OLD_VGA 0x01 196 197#define PCIC_STORAGE 0x01 198#define PCIS_STORAGE_SCSI 0x00 199#define PCIS_STORAGE_IDE 0x01 200#define PCIP_STORAGE_IDE_MODEPRIM 0x01 201#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 202#define PCIP_STORAGE_IDE_MODESEC 0x04 203#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 204#define PCIP_STORAGE_IDE_MASTERDEV 0x80 205#define PCIS_STORAGE_FLOPPY 0x02 206#define PCIS_STORAGE_IPI 0x03 207#define PCIS_STORAGE_RAID 0x04 208#define PCIS_STORAGE_OTHER 0x80 209 210#define PCIC_NETWORK 0x02 211#define PCIS_NETWORK_ETHERNET 0x00 212#define PCIS_NETWORK_TOKENRING 0x01 213#define PCIS_NETWORK_FDDI 0x02 214#define PCIS_NETWORK_ATM 0x03 215#define PCIS_NETWORK_ISDN 0x04 216#define PCIS_NETWORK_OTHER 0x80 217 218#define PCIC_DISPLAY 0x03 219#define PCIS_DISPLAY_VGA 0x00 220#define PCIS_DISPLAY_XGA 0x01 221#define PCIS_DISPLAY_3D 0x02 222#define PCIS_DISPLAY_OTHER 0x80 223 224#define PCIC_MULTIMEDIA 0x04 225#define PCIS_MULTIMEDIA_VIDEO 0x00 226#define PCIS_MULTIMEDIA_AUDIO 0x01 227#define PCIS_MULTIMEDIA_TELE 0x02 228#define PCIS_MULTIMEDIA_OTHER 0x80 229 230#define PCIC_MEMORY 0x05 231#define PCIS_MEMORY_RAM 0x00 232#define PCIS_MEMORY_FLASH 0x01 233#define PCIS_MEMORY_OTHER 0x80 234 235#define PCIC_BRIDGE 0x06 236#define PCIS_BRIDGE_HOST 0x00 237#define PCIS_BRIDGE_ISA 0x01 238#define PCIS_BRIDGE_EISA 0x02 239#define PCIS_BRIDGE_MCA 0x03 240#define PCIS_BRIDGE_PCI 0x04 241#define PCIS_BRIDGE_PCMCIA 0x05 242#define PCIS_BRIDGE_NUBUS 0x06 243#define PCIS_BRIDGE_CARDBUS 0x07 244#define PCIS_BRIDGE_RACEWAY 0x08 245#define PCIS_BRIDGE_OTHER 0x80 246 247#define PCIC_SIMPLECOMM 0x07 248#define PCIS_SIMPLECOMM_UART 0x00 249#define PCIP_SIMPLECOMM_UART_16550A 0x02 250#define PCIS_SIMPLECOMM_PAR 0x01 251#define PCIS_SIMPLECOMM_MULSER 0x02 252#define PCIS_SIMPLECOMM_MODEM 0x03 253#define PCIS_SIMPLECOMM_OTHER 0x80 254 255#define PCIC_BASEPERIPH 0x08 256#define PCIS_BASEPERIPH_PIC 0x00 257#define PCIS_BASEPERIPH_DMA 0x01 258#define PCIS_BASEPERIPH_TIMER 0x02 259#define PCIS_BASEPERIPH_RTC 0x03 260#define PCIS_BASEPERIPH_PCIHOT 0x04 261#define PCIS_BASEPERIPH_OTHER 0x80 262 263#define PCIC_INPUTDEV 0x09 264#define PCIS_INPUTDEV_KEYBOARD 0x00 265#define PCIS_INPUTDEV_DIGITIZER 0x01 266#define PCIS_INPUTDEV_MOUSE 0x02 267#define PCIS_INPUTDEV_SCANNER 0x03 268#define PCIS_INPUTDEV_GAMEPORT 0x04 269#define PCIS_INPUTDEV_OTHER 0x80 270 271#define PCIC_DOCKING 0x0a 272#define PCIS_DOCKING_GENERIC 0x00 273#define PCIS_DOCKING_OTHER 0x80 274 275#define PCIC_PROCESSOR 0x0b 276#define PCIS_PROCESSOR_386 0x00 277#define PCIS_PROCESSOR_486 0x01 278#define PCIS_PROCESSOR_PENTIUM 0x02 279#define PCIS_PROCESSOR_ALPHA 0x10 280#define PCIS_PROCESSOR_POWERPC 0x20 281#define PCIS_PROCESSOR_MIPS 0x30 282#define PCIS_PROCESSOR_COPROC 0x40 283 284#define PCIC_SERIALBUS 0x0c 285#define PCIS_SERIALBUS_FW 0x00 286#define PCIS_SERIALBUS_ACCESS 0x01 287#define PCIS_SERIALBUS_SSA 0x02 288#define PCIS_SERIALBUS_USB 0x03 289#define PCIP_SERIALBUS_USB_UHCI 0x00 290#define PCIP_SERIALBUS_USB_OHCI 0x10 291#define PCIP_SERIALBUS_USB_EHCI 0x20 292#define PCIS_SERIALBUS_FC 0x04 293#define PCIS_SERIALBUS_SMBUS 0x05 294 295#define PCIC_WIRELESS 0x0d 296#define PCIS_WIRELESS_IRDA 0x00 297#define PCIS_WIRELESS_IR 0x01 298#define PCIS_WIRELESS_RF 0x10 299#define PCIS_WIRELESS_OTHER 0x80 300 301#define PCIC_INTELLIIO 0x0e 302#define PCIS_INTELLIIO_I2O 0x00 303 304#define PCIC_SATCOM 0x0f 305#define PCIS_SATCOM_TV 0x01 306#define PCIS_SATCOM_AUDIO 0x02 307#define PCIS_SATCOM_VOICE 0x03 308#define PCIS_SATCOM_DATA 0x04 309 310#define PCIC_CRYPTO 0x10 311#define PCIS_CRYPTO_NETCOMP 0x00 312#define PCIS_CRYPTO_ENTERTAIN 0x10 313#define PCIS_CRYPTO_OTHER 0x80 314 315#define PCIC_DASP 0x11 316#define PCIS_DASP_DPIO 0x00 317#define PCIS_DASP_OTHER 0x80 318 319#define PCIC_OTHER 0xff 320 321/* Bridge Control Values. */ 322#define PCIB_BCR_PERR_ENABLE 0x0001 323#define PCIB_BCR_SERR_ENABLE 0x0002 324#define PCIB_BCR_ISA_ENABLE 0x0004 325#define PCIB_BCR_VGA_ENABLE 0x0008 326#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 327#define PCIB_BCR_SECBUS_RESET 0x0040 328#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 329#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 330#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 331#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 332#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 333 334/* PCI power manangement */ 335 336#define PCIR_POWER_CAP 0x2 337#define PCIM_PCAP_SPEC 0x0007 338#define PCIM_PCAP_PMEREQCLK 0x0008 339#define PCIM_PCAP_PMEREQPWR 0x0010 340#define PCIM_PCAP_DEVSPECINIT 0x0020 341#define PCIM_PCAP_DYNCLOCK 0x0040 342#define PCIM_PCAP_SECCLOCK 0x00c0 343#define PCIM_PCAP_CLOCKMASK 0x00c0 344#define PCIM_PCAP_REQFULLCLOCK 0x0100 345#define PCIM_PCAP_D1SUPP 0x0200 346#define PCIM_PCAP_D2SUPP 0x0400 347#define PCIM_PCAP_D0PME 0x1000 348#define PCIM_PCAP_D1PME 0x2000 349#define PCIM_PCAP_D2PME 0x4000 350 351#define PCIR_POWER_STATUS 0x4 352#define PCIM_PSTAT_D0 0x0000 353#define PCIM_PSTAT_D1 0x0001 354#define PCIM_PSTAT_D2 0x0002 355#define PCIM_PSTAT_D3 0x0003 356#define PCIM_PSTAT_DMASK 0x0003 357#define PCIM_PSTAT_REPENABLE 0x0010 358#define PCIM_PSTAT_PMEENABLE 0x0100 359#define PCIM_PSTAT_D0POWER 0x0000 360#define PCIM_PSTAT_D1POWER 0x0200 361#define PCIM_PSTAT_D2POWER 0x0400 362#define PCIM_PSTAT_D3POWER 0x0600 363#define PCIM_PSTAT_D0HEAT 0x0800 364#define PCIM_PSTAT_D1HEAT 0x1000 365#define PCIM_PSTAT_D2HEAT 0x1200 366#define PCIM_PSTAT_D3HEAT 0x1400 367#define PCIM_PSTAT_DATAUNKN 0x0000 368#define PCIM_PSTAT_DATADIV10 0x2000 369#define PCIM_PSTAT_DATADIV100 0x4000 370#define PCIM_PSTAT_DATADIV1000 0x6000 371#define PCIM_PSTAT_DATADIVMASK 0x6000 372#define PCIM_PSTAT_PME 0x8000 373 374#define PCIR_POWER_PMCSR 0x6 375#define PCIM_PMCSR_DCLOCK 0x10 376#define PCIM_PMCSR_B2SUPP 0x20 377#define PCIM_BMCSR_B3SUPP 0x40 378#define PCIM_BMCSR_BPCE 0x80 379 380#define PCIR_POWER_DATA 0x7 381 382/* PCI Message Signalled Interrupts (MSI) */ 383#define PCIR_MSI_CTRL 0x2 384#define PCIM_MSICTRL_VECTOR 0x0100 385#define PCIM_MSICTRL_64BIT 0x0080 386#define PCIM_MSICTRL_MME_MASK 0x0070 387#define PCIM_MSICTRL_MME_1 0x0000 388#define PCIM_MSICTRL_MME_2 0x0010 389#define PCIM_MSICTRL_MME_4 0x0020 390#define PCIM_MSICTRL_MME_8 0x0030 391#define PCIM_MSICTRL_MME_16 0x0040 392#define PCIM_MSICTRL_MME_32 0x0050 393#define PCIM_MSICTRL_MMC_MASK 0x000E 394#define PCIM_MSICTRL_MMC_1 0x0000 395#define PCIM_MSICTRL_MMC_2 0x0002 396#define PCIM_MSICTRL_MMC_4 0x0004 397#define PCIM_MSICTRL_MMC_8 0x0006 398#define PCIM_MSICTRL_MMC_16 0x0008 399#define PCIM_MSICTRL_MMC_32 0x000A 400#define PCIM_MSICTRL_MSI_ENABLE 0x0001 401#define PCIR_MSI_ADDR 0x4 402#define PCIR_MSI_ADDR_HIGH 0x8 403#define PCIR_MSI_DATA 0x8 404#define PCIR_MSI_DATA_64BIT 0xc 405#define PCIR_MSI_MASK 0x10 406#define PCIR_MSI_PENDING 0x14 407 408/* PCI-X definitions */ 409#define PCIXR_COMMAND 0x96 410#define PCIXR_DEVADDR 0x98 411#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 412#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 413#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 414#define PCIXR_STATUS 0x9A 415#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 416#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 417#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 418#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 419#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 420#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 421#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 422#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 423#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 424