pcireg.h revision 118327
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 118327 2003-08-01 21:45:56Z imp $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 */ 39 40/* some PCI bus constants */ 41 42#define PCI_BUSMAX 255 43#define PCI_SLOTMAX 31 44#define PCI_FUNCMAX 7 45#define PCI_REGMAX 255 46#define PCI_MAXHDRTYPE 2 47 48/* PCI config header registers for all devices */ 49 50#define PCIR_DEVVENDOR 0x00 51#define PCIR_VENDOR 0x00 52#define PCIR_DEVICE 0x02 53#define PCIR_COMMAND 0x04 54#define PCIM_CMD_PORTEN 0x0001 55#define PCIM_CMD_MEMEN 0x0002 56#define PCIM_CMD_BUSMASTEREN 0x0004 57#define PCIM_CMD_SPECIALEN 0x0008 58#define PCIM_CMD_MWRICEN 0x0010 59#define PCIM_CMD_PERRESPEN 0x0040 60#define PCIM_CMD_SERRESPEN 0x0100 61#define PCIM_CMD_BACKTOBACK 0x0200 62#define PCIR_STATUS 0x06 63#define PCIM_STATUS_CAPPRESENT 0x0010 64#define PCIM_STATUS_66CAPABLE 0x0020 65#define PCIM_STATUS_BACKTOBACK 0x0080 66#define PCIM_STATUS_PERRREPORT 0x0100 67#define PCIM_STATUS_SEL_FAST 0x0000 68#define PCIM_STATUS_SEL_MEDIMUM 0x0200 69#define PCIM_STATUS_SEL_SLOW 0x0400 70#define PCIM_STATUS_SEL_MASK 0x0600 71#define PCIM_STATUS_STABORT 0x0800 72#define PCIM_STATUS_RTABORT 0x1000 73#define PCIM_STATUS_RMABORT 0x2000 74#define PCIM_STATUS_SERR 0x4000 75#define PCIM_STATUS_PERR 0x8000 76#define PCIR_REVID 0x08 77#define PCIR_PROGIF 0x09 78#define PCIR_SUBCLASS 0x0a 79#define PCIR_CLASS 0x0b 80#define PCIR_CACHELNSZ 0x0c 81#define PCIR_LATTIMER 0x0d 82#define PCIR_HEADERTYPE 0x0e 83#define PCIM_MFDEV 0x80 84#define PCIR_BIST 0x0f 85 86/* config registers for header type 0 devices */ 87 88#define PCIR_MAPS 0x10 89#define PCIR_CARDBUSCIS 0x28 90#define PCIR_SUBVEND_0 0x2c 91#define PCIR_SUBDEV_0 0x2e 92#define PCIR_BIOS 0x30 93#define PCIM_BIOS_ENABLE 0x01 94#define PCIR_CAP_PTR 0x34 95#define PCIR_INTLINE 0x3c 96#define PCIR_INTPIN 0x3d 97#define PCIR_MINGNT 0x3e 98#define PCIR_MAXLAT 0x3f 99 100/* config registers for header type 1 devices */ 101 102#define PCIR_SECSTAT_1 0x1e 103 104#define PCIR_PRIBUS_1 0x18 105#define PCIR_SECBUS_1 0x19 106#define PCIR_SUBBUS_1 0x1a 107#define PCIR_SECLAT_1 0x1b 108 109#define PCIR_IOBASEL_1 0x1c 110#define PCIR_IOLIMITL_1 0x1d 111#define PCIR_IOBASEH_1 0x30 112#define PCIR_IOLIMITH_1 0x32 113#define PCIM_BRIO_16 0x0 114#define PCIM_BRIO_32 0x1 115#define PCIM_BRIO_MASK 0xf 116 117#define PCIR_MEMBASE_1 0x20 118#define PCIR_MEMLIMIT_1 0x22 119 120#define PCIR_PMBASEL_1 0x24 121#define PCIR_PMLIMITL_1 0x26 122#define PCIR_PMBASEH_1 0x28 123#define PCIR_PMLIMITH_1 0x2c 124 125#define PCIR_BRIDGECTL_1 0x3e 126 127#define PCIR_SUBVEND_1 0x34 128#define PCIR_SUBDEV_1 0x36 129 130/* config registers for header type 2 devices */ 131 132#define PCIR_SECSTAT_2 0x16 133 134#define PCIR_PRIBUS_2 0x18 135#define PCIR_SECBUS_2 0x19 136#define PCIR_SUBBUS_2 0x1a 137#define PCIR_SECLAT_2 0x1b 138 139#define PCIR_MEMBASE0_2 0x1c 140#define PCIR_MEMLIMIT0_2 0x20 141#define PCIR_MEMBASE1_2 0x24 142#define PCIR_MEMLIMIT1_2 0x28 143#define PCIR_IOBASE0_2 0x2c 144#define PCIR_IOLIMIT0_2 0x30 145#define PCIR_IOBASE1_2 0x34 146#define PCIR_IOLIMIT1_2 0x38 147 148#define PCIR_BRIDGECTL_2 0x3e 149 150#define PCIR_SUBVEND_2 0x40 151#define PCIR_SUBDEV_2 0x42 152 153#define PCIR_PCCARDIF_2 0x44 154 155/* PCI device class, subclass and programming interface definitions */ 156 157#define PCIC_OLD 0x00 158#define PCIS_OLD_NONVGA 0x00 159#define PCIS_OLD_VGA 0x01 160 161#define PCIC_STORAGE 0x01 162#define PCIS_STORAGE_SCSI 0x00 163#define PCIS_STORAGE_IDE 0x01 164#define PCIP_STORAGE_IDE_MODEPRIM 0x01 165#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 166#define PCIP_STORAGE_IDE_MODESEC 0x04 167#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 168#define PCIP_STORAGE_IDE_MASTERDEV 0x80 169#define PCIS_STORAGE_FLOPPY 0x02 170#define PCIS_STORAGE_IPI 0x03 171#define PCIS_STORAGE_RAID 0x04 172#define PCIS_STORAGE_OTHER 0x80 173 174#define PCIC_NETWORK 0x02 175#define PCIS_NETWORK_ETHERNET 0x00 176#define PCIS_NETWORK_TOKENRING 0x01 177#define PCIS_NETWORK_FDDI 0x02 178#define PCIS_NETWORK_ATM 0x03 179#define PCIS_NETWORK_OTHER 0x80 180 181#define PCIC_DISPLAY 0x03 182#define PCIS_DISPLAY_VGA 0x00 183#define PCIS_DISPLAY_XGA 0x01 184#define PCIS_DISPLAY_OTHER 0x80 185 186#define PCIC_MULTIMEDIA 0x04 187#define PCIS_MULTIMEDIA_VIDEO 0x00 188#define PCIS_MULTIMEDIA_AUDIO 0x01 189#define PCIS_MULTIMEDIA_OTHER 0x80 190 191#define PCIC_MEMORY 0x05 192#define PCIS_MEMORY_RAM 0x00 193#define PCIS_MEMORY_FLASH 0x01 194#define PCIS_MEMORY_OTHER 0x80 195 196#define PCIC_BRIDGE 0x06 197#define PCIS_BRIDGE_HOST 0x00 198#define PCIS_BRIDGE_ISA 0x01 199#define PCIS_BRIDGE_EISA 0x02 200#define PCIS_BRIDGE_MCA 0x03 201#define PCIS_BRIDGE_PCI 0x04 202#define PCIS_BRIDGE_PCMCIA 0x05 203#define PCIS_BRIDGE_NUBUS 0x06 204#define PCIS_BRIDGE_CARDBUS 0x07 205#define PCIS_BRIDGE_OTHER 0x80 206 207#define PCIC_SIMPLECOMM 0x07 208#define PCIS_SIMPLECOMM_UART 0x00 209#define PCIP_SIMPLECOMM_UART_16550A 0x02 210#define PCIS_SIMPLECOMM_PAR 0x01 211#define PCIS_SIMPLECOMM_OTHER 0x80 212 213#define PCIC_BASEPERIPH 0x08 214#define PCIS_BASEPERIPH_PIC 0x00 215#define PCIS_BASEPERIPH_DMA 0x01 216#define PCIS_BASEPERIPH_TIMER 0x02 217#define PCIS_BASEPERIPH_RTC 0x03 218#define PCIS_BASEPERIPH_OTHER 0x80 219 220#define PCIC_INPUTDEV 0x09 221#define PCIS_INPUTDEV_KEYBOARD 0x00 222#define PCIS_INPUTDEV_DIGITIZER 0x01 223#define PCIS_INPUTDEV_MOUSE 0x02 224#define PCIS_INPUTDEV_OTHER 0x80 225 226#define PCIC_DOCKING 0x0a 227#define PCIS_DOCKING_GENERIC 0x00 228#define PCIS_DOCKING_OTHER 0x80 229 230#define PCIC_PROCESSOR 0x0b 231#define PCIS_PROCESSOR_386 0x00 232#define PCIS_PROCESSOR_486 0x01 233#define PCIS_PROCESSOR_PENTIUM 0x02 234#define PCIS_PROCESSOR_ALPHA 0x10 235#define PCIS_PROCESSOR_POWERPC 0x20 236#define PCIS_PROCESSOR_COPROC 0x40 237 238#define PCIC_SERIALBUS 0x0c 239#define PCIS_SERIALBUS_FW 0x00 240#define PCIS_SERIALBUS_ACCESS 0x01 241#define PCIS_SERIALBUS_SSA 0x02 242#define PCIS_SERIALBUS_USB 0x03 243#define PCIP_SERIALBUS_USB_UHCI 0x00 244#define PCIP_SERIALBUS_USB_OHCI 0x10 245#define PCIP_SERIALBUS_USB_EHCI 0x20 246#define PCIS_SERIALBUS_FC 0x04 247#define PCIS_SERIALBUS_SMBUS 0x05 248 249#define PCIC_OTHER 0xff 250 251/* PCI power manangement */ 252 253#define PCIR_POWER_CAP 0x2 254#define PCIM_PCAP_SPEC 0x0007 255#define PCIM_PCAP_PMEREQCLK 0x0008 256#define PCIM_PCAP_PMEREQPWR 0x0010 257#define PCIM_PCAP_DEVSPECINIT 0x0020 258#define PCIM_PCAP_DYNCLOCK 0x0040 259#define PCIM_PCAP_SECCLOCK 0x00c0 260#define PCIM_PCAP_CLOCKMASK 0x00c0 261#define PCIM_PCAP_REQFULLCLOCK 0x0100 262#define PCIM_PCAP_D1SUPP 0x0200 263#define PCIM_PCAP_D2SUPP 0x0400 264#define PCIM_PCAP_D0PME 0x1000 265#define PCIM_PCAP_D1PME 0x2000 266#define PCIM_PCAP_D2PME 0x4000 267 268#define PCIR_POWER_STATUS 0x4 269#define PCIM_PSTAT_D0 0x0000 270#define PCIM_PSTAT_D1 0x0001 271#define PCIM_PSTAT_D2 0x0002 272#define PCIM_PSTAT_D3 0x0003 273#define PCIM_PSTAT_DMASK 0x0003 274#define PCIM_PSTAT_REPENABLE 0x0010 275#define PCIM_PSTAT_PMEENABLE 0x0100 276#define PCIM_PSTAT_D0POWER 0x0000 277#define PCIM_PSTAT_D1POWER 0x0200 278#define PCIM_PSTAT_D2POWER 0x0400 279#define PCIM_PSTAT_D3POWER 0x0600 280#define PCIM_PSTAT_D0HEAT 0x0800 281#define PCIM_PSTAT_D1HEAT 0x1000 282#define PCIM_PSTAT_D2HEAT 0x1200 283#define PCIM_PSTAT_D3HEAT 0x1400 284#define PCIM_PSTAT_DATAUNKN 0x0000 285#define PCIM_PSTAT_DATADIV10 0x2000 286#define PCIM_PSTAT_DATADIV100 0x4000 287#define PCIM_PSTAT_DATADIV1000 0x6000 288#define PCIM_PSTAT_DATADIVMASK 0x6000 289#define PCIM_PSTAT_PME 0x8000 290 291#define PCIR_POWER_PMCSR 0x6 292#define PCIM_PMCSR_DCLOCK 0x10 293#define PCIM_PMCSR_B2SUPP 0x20 294#define PCIM_BMCSR_B3SUPP 0x40 295#define PCIM_BMCSR_BPCE 0x80 296 297#define PCIR_POWER_DATA 0x7 298 299/* PCI-X definitions */ 300#define PCIXR_COMMAND 0x96 301#define PCIXR_DEVADDR 0x98 302#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 303#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 304#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 305#define PCIXR_STATUS 0x9A 306#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 307#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 308#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 309#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 310#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 311#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 312#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 313#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 314#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ 315