pci_subr.c revision 69783
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 69783 2000-12-08 22:11:23Z msmith $ 31 */ 32 33/* 34 * PCI:PCI bridge support. 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41 42#include <machine/resource.h> 43 44#include <pci/pcivar.h> 45#include <pci/pcireg.h> 46 47#include "pcib_if.h" 48 49/* 50 * Bridge-specific data. 51 */ 52struct pcib_softc 53{ 54 device_t dev; 55 u_int8_t secbus; /* secondary bus number */ 56 u_int8_t subbus; /* subordinate bus number */ 57 pci_addr_t pmembase; /* base address of prefetchable memory */ 58 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 59 u_int32_t membase; /* base address of memory window */ 60 u_int32_t memlimit; /* topmost address of memory window */ 61 u_int32_t iobase; /* base address of port window */ 62 u_int32_t iolimit; /* topmost address of port window */ 63 u_int16_t secstat; /* secondary bus status register */ 64 u_int16_t bridgectl; /* bridge control register */ 65 u_int8_t seclat; /* secondary bus latency timer */ 66}; 67 68static int pcib_probe(device_t dev); 69static int pcib_attach(device_t dev); 70static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 71static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 72static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 73 u_long start, u_long end, u_long count, u_int flags); 74static int pcib_maxslots(device_t dev); 75static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); 76static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); 77static int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 78 79static device_method_t pcib_methods[] = { 80 /* Device interface */ 81 DEVMETHOD(device_probe, pcib_probe), 82 DEVMETHOD(device_attach, pcib_attach), 83 DEVMETHOD(device_shutdown, bus_generic_shutdown), 84 DEVMETHOD(device_suspend, bus_generic_suspend), 85 DEVMETHOD(device_resume, bus_generic_resume), 86 87 /* Bus interface */ 88 DEVMETHOD(bus_print_child, bus_generic_print_child), 89 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 90 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 91 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 92 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 93 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 94 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 95 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 96 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 97 98 /* pcib interface */ 99 DEVMETHOD(pcib_maxslots, pcib_maxslots), 100 DEVMETHOD(pcib_read_config, pcib_read_config), 101 DEVMETHOD(pcib_write_config, pcib_write_config), 102 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 103 104 { 0, 0 } 105}; 106 107static driver_t pcib_driver = { 108 "pcib", 109 pcib_methods, 110 sizeof(struct pcib_softc), 111}; 112 113static devclass_t pcib_devclass; 114 115DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 116 117/* 118 * Generic device interface 119 */ 120static int 121pcib_probe(device_t dev) 122{ 123 if ((pci_get_class(dev) == PCIC_BRIDGE) && 124 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 125 device_set_desc(dev, "PCI-PCI bridge"); 126 return(-10000); 127 } 128 return(ENXIO); 129} 130 131static int 132pcib_attach(device_t dev) 133{ 134 struct pcib_softc *sc; 135 device_t pcib, child; 136 int b, s, f; 137 138 sc = device_get_softc(dev); 139 sc->dev = dev; 140 pcib = device_get_parent(dev); 141 b = pci_get_bus(dev); 142 s = pci_get_slot(dev); 143 f = pci_get_function(dev); 144 145 sc->secbus = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECBUS_1, 1); 146 sc->subbus = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SUBBUS_1, 1); 147 sc->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 148 sc->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 149 sc->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 150 sc->iobase = PCI_PPBIOBASE(PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASEH_1, 2), 151 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASEL_1, 1)); 152 sc->iolimit = PCI_PPBIOLIMIT(PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMITH_1, 2), 153 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMITL_1, 1)); 154 sc->membase = PCI_PPBMEMBASE(0, PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE_1, 2)); 155 sc->memlimit = PCI_PPBMEMLIMIT(0, PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT_1, 2)); 156 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 157 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 158 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,PCIR_PMLIMITH_1, 4), 159 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 160 161 if (bootverbose) { 162 device_printf(dev, " secondary bus %d\n", sc->secbus); 163 device_printf(dev, " subordinate bus %d\n", sc->subbus); 164 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 165 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 166 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 167 } 168 169 /* 170 * XXX If the secondary bus number is zero, we should assign a bus number 171 * since the BIOS hasn't, then initialise the bridge. 172 */ 173 174 /* 175 * XXX If the subordinate bus number is less than the secondary bus number, 176 * we should pick a better value. One sensible alternative would be to 177 * pick 255; the only tradeoff here is that configuration transactions 178 * would be more widely routed than absolutely necessary. 179 */ 180 181 if (sc->secbus != 0) { 182 child = device_add_child(dev, "pci", -1); 183 if (child != NULL) 184 return(bus_generic_attach(dev)); 185 } 186 187 /* no secondary bus; we should have fixed this */ 188 return(0); 189} 190 191static int 192pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 193{ 194 struct pcib_softc *sc = device_get_softc(dev); 195 196 switch (which) { 197 case PCIB_IVAR_BUS: 198 *result = sc->secbus; 199 return(0); 200 } 201 return(ENOENT); 202} 203 204static int 205pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 206{ 207 struct pcib_softc *sc = device_get_softc(dev); 208 209 switch (which) { 210 case PCIB_IVAR_BUS: 211 sc->secbus = value; 212 break; 213 } 214 return(ENOENT); 215} 216 217/* 218 * We have to trap resource allocation requests and ensure that the bridge 219 * is set up to, or capable of handling them. 220 */ 221static struct resource * 222pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 223 u_long start, u_long end, u_long count, u_int flags) 224{ 225 struct pcib_softc *sc = device_get_softc(dev); 226 227 /* 228 * If this is a "default" allocation against this rid, we can't work 229 * out where it's coming from (we should actually never see these) so we 230 * just have to punt. 231 */ 232 if ((start == 0) && (end == ~0)) { 233 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 234 *rid, device_get_name(child), device_get_unit(child)); 235 } else { 236 /* 237 * Fail the allocation for this range if it's not supported. 238 * 239 * XXX we should probably just fix up the bridge decode and soldier on. 240 */ 241 switch (type) { 242 case SYS_RES_IOPORT: 243 if ((start < sc->iobase) || (end > sc->iolimit)) { 244 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 245 " (decoding 0x%x-0x%x)\n", 246 device_get_name(child), device_get_unit(child), start, end, 247 sc->iobase, sc->iolimit); 248 return(NULL); 249 } 250 break; 251 252 /* 253 * XXX will have to decide whether the device making the request is asking 254 * for prefetchable memory or not. If it's coming from another bridge 255 * down the line, do we assume not, or ask the bridge to pass in another 256 * flag as the request bubbles up? 257 */ 258 case SYS_RES_MEMORY: 259 if (((start < sc->membase) || (end > sc->memlimit)) && 260 ((start < sc->pmembase) || (end > sc->pmemlimit))) { 261 device_printf(dev, "device %s%d requested unsupported memory range 0x%lx-0x%lx" 262 " (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 263 device_get_name(child), device_get_unit(child), start, end, 264 sc->membase, sc->memlimit, sc->pmembase, sc->pmemlimit); 265 return(NULL); 266 } 267 default: 268 } 269 } 270 device_printf(sc->dev, "resource request type %d 0x%lx-0x%lx decodes OK\n", 271 type, start, end); 272 /* 273 * Bridge is OK decoding this resource, so pass it up. 274 */ 275 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 276} 277 278/* 279 * PCIB interface. 280 */ 281static int 282pcib_maxslots(device_t dev) 283{ 284 return(31); 285} 286 287/* 288 * Since we are a child of a PCI bus, its parent must support the pcib interface. 289 */ 290static u_int32_t 291pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 292{ 293 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 294} 295 296static void 297pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 298{ 299 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 300} 301 302/* 303 * Route an interrupt across a PCI bridge. 304 */ 305static int 306pcib_route_interrupt(device_t pcib, device_t dev, int pin) 307{ 308 device_t bus; 309 int parent_intpin; 310 int intnum; 311 312 /* 313 * 314 * The PCI standard defines a swizzle of the child-side device/intpin to 315 * the parent-side intpin as follows. 316 * 317 * device = device on child bus 318 * child_intpin = intpin on child bus slot (0-3) 319 * parent_intpin = intpin on parent bus slot (0-3) 320 * 321 * parent_intpin = (device + child_intpin) % 4 322 */ 323 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 324 325 /* 326 * Our parent is a PCI bus. Its parent must export the pcib interface 327 * which includes the ability to route interrupts. 328 */ 329 bus = device_get_parent(pcib); 330 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 331 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev), 332 'A' + pin - 1, intnum); 333 return(intnum); 334} 335