pci_subr.c revision 89383
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 89383 2002-01-15 06:46:59Z imp $ 31 */ 32 33/* 34 * PCI:PCI bridge support. 35 */ 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41 42#include <machine/resource.h> 43 44#include <pci/pcivar.h> 45#include <pci/pcireg.h> 46 47#include "pcib_if.h" 48#include "opt_pci.h" 49 50/* 51 * Bridge-specific data. 52 */ 53struct pcib_softc 54{ 55 device_t dev; 56 u_int16_t command; /* command register */ 57 u_int8_t secbus; /* secondary bus number */ 58 u_int8_t subbus; /* subordinate bus number */ 59 pci_addr_t pmembase; /* base address of prefetchable memory */ 60 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 61 pci_addr_t membase; /* base address of memory window */ 62 pci_addr_t memlimit; /* topmost address of memory window */ 63 u_int32_t iobase; /* base address of port window */ 64 u_int32_t iolimit; /* topmost address of port window */ 65 u_int16_t secstat; /* secondary bus status register */ 66 u_int16_t bridgectl; /* bridge control register */ 67 u_int8_t seclat; /* secondary bus latency timer */ 68}; 69 70static int pcib_probe(device_t dev); 71static int pcib_attach(device_t dev); 72static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result); 73static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); 74static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 75 u_long start, u_long end, u_long count, u_int flags); 76static int pcib_maxslots(device_t dev); 77static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width); 78static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width); 79static int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 80 81static device_method_t pcib_methods[] = { 82 /* Device interface */ 83 DEVMETHOD(device_probe, pcib_probe), 84 DEVMETHOD(device_attach, pcib_attach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 DEVMETHOD(device_suspend, bus_generic_suspend), 87 DEVMETHOD(device_resume, bus_generic_resume), 88 89 /* Bus interface */ 90 DEVMETHOD(bus_print_child, bus_generic_print_child), 91 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 92 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 94 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 95 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 96 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 97 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 98 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 99 100 /* pcib interface */ 101 DEVMETHOD(pcib_maxslots, pcib_maxslots), 102 DEVMETHOD(pcib_read_config, pcib_read_config), 103 DEVMETHOD(pcib_write_config, pcib_write_config), 104 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 105 106 { 0, 0 } 107}; 108 109static driver_t pcib_driver = { 110 "pcib", 111 pcib_methods, 112 sizeof(struct pcib_softc), 113}; 114 115static devclass_t pcib_devclass; 116 117DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 118 119/* 120 * Generic device interface 121 */ 122static int 123pcib_probe(device_t dev) 124{ 125 if ((pci_get_class(dev) == PCIC_BRIDGE) && 126 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 127 device_set_desc(dev, "PCI-PCI bridge"); 128 return(-10000); 129 } 130 return(ENXIO); 131} 132 133static int 134pcib_attach(device_t dev) 135{ 136 struct pcib_softc *sc; 137 device_t child; 138 u_int8_t iolow; 139 140 sc = device_get_softc(dev); 141 sc->dev = dev; 142 143 /* 144 * Get current bridge configuration. 145 */ 146 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 147 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 148 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 149 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 150 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 151 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 152 153 /* 154 * Determine current I/O decode. 155 */ 156 if (sc->command & PCIM_CMD_PORTEN) { 157 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 158 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 159 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 160 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 161 } else { 162 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 163 } 164 165 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 166 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 167 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 168 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 169 } else { 170 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 171 } 172 } 173 174 /* 175 * Determine current memory decode. 176 */ 177 if (sc->command & PCIM_CMD_MEMEN) { 178 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 179 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 180 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 181 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 182 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 183 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 184 } 185 186 /* 187 * Quirk handling. 188 */ 189 switch (pci_get_devid(dev)) { 190 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 191 { 192 u_int8_t supbus; 193 194 supbus = pci_read_config(dev, 0x41, 1); 195 if (supbus != 0xff) { 196 sc->secbus = supbus + 1; 197 sc->subbus = supbus + 1; 198 } 199 } 200 break; 201 } 202 203 if (bootverbose) { 204 device_printf(dev, " secondary bus %d\n", sc->secbus); 205 device_printf(dev, " subordinate bus %d\n", sc->subbus); 206 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 207 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 208 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 209 } 210 211 /* 212 * XXX If the secondary bus number is zero, we should assign a bus number 213 * since the BIOS hasn't, then initialise the bridge. 214 */ 215 216 /* 217 * XXX If the subordinate bus number is less than the secondary bus number, 218 * we should pick a better value. One sensible alternative would be to 219 * pick 255; the only tradeoff here is that configuration transactions 220 * would be more widely routed than absolutely necessary. 221 */ 222 223 if (sc->secbus != 0) { 224 child = device_add_child(dev, "pci", -1); 225 if (child != NULL) 226 return(bus_generic_attach(dev)); 227 } 228 229 /* no secondary bus; we should have fixed this */ 230 return(0); 231} 232 233static int 234pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 235{ 236 struct pcib_softc *sc = device_get_softc(dev); 237 238 switch (which) { 239 case PCIB_IVAR_BUS: 240 *result = sc->secbus; 241 return(0); 242 } 243 return(ENOENT); 244} 245 246static int 247pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 248{ 249 struct pcib_softc *sc = device_get_softc(dev); 250 251 switch (which) { 252 case PCIB_IVAR_BUS: 253 sc->secbus = value; 254 break; 255 } 256 return(ENOENT); 257} 258 259/* 260 * We have to trap resource allocation requests and ensure that the bridge 261 * is set up to, or capable of handling them. 262 */ 263static struct resource * 264pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 265 u_long start, u_long end, u_long count, u_int flags) 266{ 267 struct pcib_softc *sc = device_get_softc(dev); 268 269 /* 270 * If this is a "default" allocation against this rid, we can't work 271 * out where it's coming from (we should actually never see these) so we 272 * just have to punt. 273 */ 274 if ((start == 0) && (end == ~0)) { 275 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 276 *rid, device_get_name(child), device_get_unit(child)); 277 } else { 278 /* 279 * Fail the allocation for this range if it's not supported. 280 * 281 * XXX we should probably just fix up the bridge decode and soldier on. 282 */ 283 switch (type) { 284 case SYS_RES_IOPORT: 285 if (start < sc->iobase) 286 start = sc->iobase; 287 if (end > sc->iolimit && start < end) 288 end = sc->iolimit; 289 if ((start < sc->iobase) || (end > sc->iolimit)) { 290 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 291 " (decoding 0x%x-0x%x)\n", 292 device_get_name(child), device_get_unit(child), start, end, 293 sc->iobase, sc->iolimit); 294#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE 295 return(NULL); 296#endif 297 } 298 if (bootverbose) 299 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 300 device_get_name(child), device_get_unit(child), start, end); 301 break; 302 303 /* 304 * XXX will have to decide whether the device making the request is asking 305 * for prefetchable memory or not. If it's coming from another bridge 306 * down the line, do we assume not, or ask the bridge to pass in another 307 * flag as the request bubbles up? 308 */ 309 case SYS_RES_MEMORY: 310 if (start < sc->membase && end > sc->membase) 311 start = sc->membase; 312 if (end > sc->memlimit && start < end) 313 end = sc->memlimit; 314 if (((start < sc->membase) || (end > sc->memlimit)) && 315 ((start < sc->pmembase) || (end > sc->pmemlimit))) { 316 device_printf(dev, "device %s%d requested unsupported memory range 0x%lx-0x%lx" 317 " (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 318 device_get_name(child), device_get_unit(child), start, end, 319 sc->membase, sc->memlimit, sc->pmembase, sc->pmemlimit); 320#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE 321 return(NULL); 322#endif 323 } 324 if (bootverbose) 325 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 326 device_get_name(child), device_get_unit(child), start, end); 327 break; 328 329 default: 330 break; 331 } 332 } 333 334 /* 335 * Bridge is OK decoding this resource, so pass it up. 336 */ 337 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 338} 339 340/* 341 * PCIB interface. 342 */ 343static int 344pcib_maxslots(device_t dev) 345{ 346 return(PCI_SLOTMAX); 347} 348 349/* 350 * Since we are a child of a PCI bus, its parent must support the pcib interface. 351 */ 352static u_int32_t 353pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 354{ 355 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 356} 357 358static void 359pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 360{ 361 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 362} 363 364/* 365 * Route an interrupt across a PCI bridge. 366 */ 367static int 368pcib_route_interrupt(device_t pcib, device_t dev, int pin) 369{ 370 device_t bus; 371 int parent_intpin; 372 int intnum; 373 374 /* 375 * 376 * The PCI standard defines a swizzle of the child-side device/intpin to 377 * the parent-side intpin as follows. 378 * 379 * device = device on child bus 380 * child_intpin = intpin on child bus slot (0-3) 381 * parent_intpin = intpin on parent bus slot (0-3) 382 * 383 * parent_intpin = (device + child_intpin) % 4 384 */ 385 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 386 387 /* 388 * Our parent is a PCI bus. Its parent must export the pcib interface 389 * which includes the ability to route interrupts. 390 */ 391 bus = device_get_parent(pcib); 392 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 393 device_printf(pcib, "routed slot %d INT%c to irq %d\n", pci_get_slot(dev), 394 'A' + pin - 1, intnum); 395 return(intnum); 396} 397