pci_subr.c revision 145661 
1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 145661 2005-04-29 06:22:41Z imp $");
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <sys/sysctl.h>
46
47#include <machine/resource.h>
48
49#include <dev/pci/pcivar.h>
50#include <dev/pci/pcireg.h>
51#include <dev/pci/pcib_private.h>
52
53#include "pcib_if.h"
54
55static int		pcib_probe(device_t dev);
56
57static device_method_t pcib_methods[] = {
58    /* Device interface */
59    DEVMETHOD(device_probe,		pcib_probe),
60    DEVMETHOD(device_attach,		pcib_attach),
61    DEVMETHOD(device_detach,		bus_generic_detach),
62    DEVMETHOD(device_shutdown,		bus_generic_shutdown),
63    DEVMETHOD(device_suspend,		bus_generic_suspend),
64    DEVMETHOD(device_resume,		bus_generic_resume),
65
66    /* Bus interface */
67    DEVMETHOD(bus_print_child,		bus_generic_print_child),
68    DEVMETHOD(bus_read_ivar,		pcib_read_ivar),
69    DEVMETHOD(bus_write_ivar,		pcib_write_ivar),
70    DEVMETHOD(bus_alloc_resource,	pcib_alloc_resource),
71    DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
72    DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
73    DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
74    DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
75    DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
76
77    /* pcib interface */
78    DEVMETHOD(pcib_maxslots,		pcib_maxslots),
79    DEVMETHOD(pcib_read_config,		pcib_read_config),
80    DEVMETHOD(pcib_write_config,	pcib_write_config),
81    DEVMETHOD(pcib_route_interrupt,	pcib_route_interrupt),
82
83    { 0, 0 }
84};
85
86static driver_t pcib_driver = {
87    "pcib",
88    pcib_methods,
89    sizeof(struct pcib_softc),
90};
91
92devclass_t pcib_devclass;
93
94DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
95
96/*
97 * Generic device interface
98 */
99static int
100pcib_probe(device_t dev)
101{
102    if ((pci_get_class(dev) == PCIC_BRIDGE) &&
103	(pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
104	device_set_desc(dev, "PCI-PCI bridge");
105	return(-10000);
106    }
107    return(ENXIO);
108}
109
110void
111pcib_attach_common(device_t dev)
112{
113    struct pcib_softc	*sc;
114    uint8_t		iolow;
115
116    sc = device_get_softc(dev);
117    sc->dev = dev;
118
119    /*
120     * Get current bridge configuration.
121     */
122    sc->command   = pci_read_config(dev, PCIR_COMMAND, 1);
123    sc->secbus    = pci_read_config(dev, PCIR_SECBUS_1, 1);
124    sc->subbus    = pci_read_config(dev, PCIR_SUBBUS_1, 1);
125    sc->secstat   = pci_read_config(dev, PCIR_SECSTAT_1, 2);
126    sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
127    sc->seclat    = pci_read_config(dev, PCIR_SECLAT_1, 1);
128
129    /*
130     * Determine current I/O decode.
131     */
132    if (sc->command & PCIM_CMD_PORTEN) {
133	iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
134	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
135	    sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
136				       pci_read_config(dev, PCIR_IOBASEL_1, 1));
137	} else {
138	    sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
139	}
140
141	iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
142	if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
143	    sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
144					 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
145	} else {
146	    sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
147	}
148    }
149
150    /*
151     * Determine current memory decode.
152     */
153    if (sc->command & PCIM_CMD_MEMEN) {
154	sc->membase   = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
155	sc->memlimit  = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
156	sc->pmembase  = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
157				       pci_read_config(dev, PCIR_PMBASEL_1, 2));
158	sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
159					pci_read_config(dev, PCIR_PMLIMITL_1, 2));
160    }
161
162    /*
163     * Quirk handling.
164     */
165    switch (pci_get_devid(dev)) {
166    case 0x12258086:		/* Intel 82454KX/GX (Orion) */
167	{
168	    uint8_t	supbus;
169
170	    supbus = pci_read_config(dev, 0x41, 1);
171	    if (supbus != 0xff) {
172		sc->secbus = supbus + 1;
173		sc->subbus = supbus + 1;
174	    }
175	    break;
176	}
177
178    /*
179     * The i82380FB mobile docking controller is a PCI-PCI bridge,
180     * and it is a subtractive bridge.  However, the ProgIf is wrong
181     * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
182     * happen.  There's also a Toshiba bridge that behaves this
183     * way.
184     */
185    case 0x124b8086:		/* Intel 82380FB Mobile */
186    case 0x060513d7:		/* Toshiba ???? */
187	sc->flags |= PCIB_SUBTRACTIVE;
188	break;
189    }
190
191    /*
192     * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
193     * but have a ProgIF of 0x80.  The 82801 family (AA, AB, BAM/CAM,
194     * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
195     * This means they act as if they were subtractively decoding
196     * bridges and pass all transactions.  Mark them and real ProgIf 1
197     * parts as subtractive.
198     */
199    if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
200      pci_read_config(dev, PCIR_PROGIF, 1) == 1)
201	sc->flags |= PCIB_SUBTRACTIVE;
202
203    if (bootverbose) {
204	device_printf(dev, "  secondary bus     %d\n", sc->secbus);
205	device_printf(dev, "  subordinate bus   %d\n", sc->subbus);
206	device_printf(dev, "  I/O decode        0x%x-0x%x\n", sc->iobase, sc->iolimit);
207	device_printf(dev, "  memory decode     0x%x-0x%x\n", sc->membase, sc->memlimit);
208	device_printf(dev, "  prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
209	if (sc->flags & PCIB_SUBTRACTIVE)
210	    device_printf(dev, "  Subtractively decoded bridge.\n");
211    }
212
213    /*
214     * XXX If the secondary bus number is zero, we should assign a bus number
215     *     since the BIOS hasn't, then initialise the bridge.
216     */
217
218    /*
219     * XXX If the subordinate bus number is less than the secondary bus number,
220     *     we should pick a better value.  One sensible alternative would be to
221     *     pick 255; the only tradeoff here is that configuration transactions
222     *     would be more widely routed than absolutely necessary.
223     */
224}
225
226int
227pcib_attach(device_t dev)
228{
229    struct pcib_softc	*sc;
230    device_t		child;
231
232    pcib_attach_common(dev);
233    sc = device_get_softc(dev);
234    if (sc->secbus != 0) {
235	child = device_add_child(dev, "pci", sc->secbus);
236	if (child != NULL)
237	    return(bus_generic_attach(dev));
238    }
239
240    /* no secondary bus; we should have fixed this */
241    return(0);
242}
243
244int
245pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
246{
247    struct pcib_softc	*sc = device_get_softc(dev);
248
249    switch (which) {
250    case PCIB_IVAR_BUS:
251	*result = sc->secbus;
252	return(0);
253    }
254    return(ENOENT);
255}
256
257int
258pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
259{
260    struct pcib_softc	*sc = device_get_softc(dev);
261
262    switch (which) {
263    case PCIB_IVAR_BUS:
264	sc->secbus = value;
265	break;
266    }
267    return(ENOENT);
268}
269
270/*
271 * Is the prefetch window open (eg, can we allocate memory in it?)
272 */
273static int
274pcib_is_prefetch_open(struct pcib_softc *sc)
275{
276	return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
277}
278
279/*
280 * Is the nonprefetch window open (eg, can we allocate memory in it?)
281 */
282static int
283pcib_is_nonprefetch_open(struct pcib_softc *sc)
284{
285	return (sc->membase > 0 && sc->membase < sc->memlimit);
286}
287
288/*
289 * Is the io window open (eg, can we allocate ports in it?)
290 */
291static int
292pcib_is_io_open(struct pcib_softc *sc)
293{
294	return (sc->iobase > 0 && sc->iobase < sc->iolimit);
295}
296
297/*
298 * We have to trap resource allocation requests and ensure that the bridge
299 * is set up to, or capable of handling them.
300 */
301struct resource *
302pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
303    u_long start, u_long end, u_long count, u_int flags)
304{
305	struct pcib_softc	*sc = device_get_softc(dev);
306	int ok;
307
308	/*
309	 * Fail the allocation for this range if it's not supported.
310	 */
311	switch (type) {
312	case SYS_RES_IOPORT:
313		ok = 0;
314		if (!pcib_is_io_open(sc))
315			break;
316		ok = (start >= sc->iobase && end <= sc->iolimit);
317
318		/*
319		 * Make sure we allow access to VGA I/O addresses when the
320		 * bridge has the "VGA Enable" bit set.
321		 */
322		if (!ok && pci_is_vga_ioport_range(start, end))
323			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
324
325		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
326			if (!ok) {
327				if (start < sc->iobase)
328					start = sc->iobase;
329				if (end > sc->iolimit)
330					end = sc->iolimit;
331				if (start < end)
332					ok = 1;
333			}
334		} else {
335			ok = 1;
336#if 1
337			if (start < sc->iobase && end > sc->iolimit) {
338				start = sc->iobase;
339				end = sc->iolimit;
340			}
341#endif
342		}
343		if (end < start) {
344			device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
345			    end, start);
346			start = 0;
347			end = 0;
348			ok = 0;
349		}
350		if (!ok) {
351			device_printf(dev, "%s requested unsupported I/O "
352			    "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
353			    device_get_nameunit(child), start, end,
354			    sc->iobase, sc->iolimit);
355			return (NULL);
356		}
357		if (bootverbose)
358			device_printf(dev,
359			    "%s requested I/O range 0x%lx-0x%lx: in range\n",
360			    device_get_nameunit(child), start, end);
361		break;
362
363	case SYS_RES_MEMORY:
364		ok = 0;
365		if (pcib_is_nonprefetch_open(sc))
366			ok = ok || (start >= sc->membase && end <= sc->memlimit);
367		if (pcib_is_prefetch_open(sc))
368			ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
369
370		/*
371		 * Make sure we allow access to VGA memory addresses when the
372		 * bridge has the "VGA Enable" bit set.
373		 */
374		if (!ok && pci_is_vga_memory_range(start, end))
375			ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
376
377		if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
378			if (!ok) {
379				ok = 1;
380				if (flags & RF_PREFETCHABLE) {
381					if (pcib_is_prefetch_open(sc)) {
382						if (start < sc->pmembase)
383							start = sc->pmembase;
384						if (end > sc->pmemlimit)
385							end = sc->pmemlimit;
386					} else {
387						ok = 0;
388					}
389				} else {	/* non-prefetchable */
390					if (pcib_is_nonprefetch_open(sc)) {
391						if (start < sc->membase)
392							start = sc->membase;
393						if (end > sc->memlimit)
394							end = sc->memlimit;
395					} else {
396						ok = 0;
397					}
398				}
399			}
400		} else if (!ok) {
401			ok = 1;	/* subtractive bridge: always ok */
402#if 1
403			if (pcib_is_nonprefetch_open(sc)) {
404				if (start < sc->membase && end > sc->memlimit) {
405					start = sc->membase;
406					end = sc->memlimit;
407				}
408			}
409			if (pcib_is_prefetch_open(sc)) {
410				if (start < sc->pmembase && end > sc->pmemlimit) {
411					start = sc->pmembase;
412					end = sc->pmemlimit;
413				}
414			}
415#endif
416		}
417		if (end < start) {
418			device_printf(dev, "memory: end (%lx) < start (%lx)\n",
419			    end, start);
420			start = 0;
421			end = 0;
422			ok = 0;
423		}
424		if (!ok && bootverbose)
425			device_printf(dev,
426			    "%s requested unsupported memory range "
427			    "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
428			    device_get_nameunit(child), start, end,
429			    sc->membase, sc->memlimit, sc->pmembase,
430			    sc->pmemlimit);
431		if (!ok)
432			return (NULL);
433		if (bootverbose)
434			device_printf(dev,"%s requested memory range "
435			    "0x%lx-0x%lx: good\n",
436			    device_get_nameunit(child), start, end);
437		break;
438
439	default:
440		break;
441	}
442	/*
443	 * Bridge is OK decoding this resource, so pass it up.
444	 */
445	return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
446	    count, flags));
447}
448
449/*
450 * PCIB interface.
451 */
452int
453pcib_maxslots(device_t dev)
454{
455    return(PCI_SLOTMAX);
456}
457
458/*
459 * Since we are a child of a PCI bus, its parent must support the pcib interface.
460 */
461uint32_t
462pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
463{
464    return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
465}
466
467void
468pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
469{
470    PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
471}
472
473/*
474 * Route an interrupt across a PCI bridge.
475 */
476int
477pcib_route_interrupt(device_t pcib, device_t dev, int pin)
478{
479    device_t	bus;
480    int		parent_intpin;
481    int		intnum;
482
483    /*
484     *
485     * The PCI standard defines a swizzle of the child-side device/intpin to
486     * the parent-side intpin as follows.
487     *
488     * device = device on child bus
489     * child_intpin = intpin on child bus slot (0-3)
490     * parent_intpin = intpin on parent bus slot (0-3)
491     *
492     * parent_intpin = (device + child_intpin) % 4
493     */
494    parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
495
496    /*
497     * Our parent is a PCI bus.  Its parent must export the pcib interface
498     * which includes the ability to route interrupts.
499     */
500    bus = device_get_parent(pcib);
501    intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
502    if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
503	device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
504	    pci_get_slot(dev), 'A' + pin - 1, intnum);
505    }
506    return(intnum);
507}
508
509/*
510 * Try to read the bus number of a host-PCI bridge using appropriate config
511 * registers.
512 */
513int
514host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
515    uint8_t *busnum)
516{
517	uint32_t id;
518
519	id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
520	if (id == 0xffffffff)
521		return (0);
522
523	switch (id) {
524	case 0x12258086:
525		/* Intel 824?? */
526		/* XXX This is a guess */
527		/* *busnum = read_config(bus, slot, func, 0x41, 1); */
528		*busnum = bus;
529		break;
530	case 0x84c48086:
531		/* Intel 82454KX/GX (Orion) */
532		*busnum = read_config(bus, slot, func, 0x4a, 1);
533		break;
534	case 0x84ca8086:
535		/*
536		 * For the 450nx chipset, there is a whole bundle of
537		 * things pretending to be host bridges. The MIOC will
538		 * be seen first and isn't really a pci bridge (the
539		 * actual busses are attached to the PXB's). We need to
540		 * read the registers of the MIOC to figure out the
541		 * bus numbers for the PXB channels.
542		 *
543		 * Since the MIOC doesn't have a pci bus attached, we
544		 * pretend it wasn't there.
545		 */
546		return (0);
547	case 0x84cb8086:
548		switch (slot) {
549		case 0x12:
550			/* Intel 82454NX PXB#0, Bus#A */
551			*busnum = read_config(bus, 0x10, func, 0xd0, 1);
552			break;
553		case 0x13:
554			/* Intel 82454NX PXB#0, Bus#B */
555			*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
556			break;
557		case 0x14:
558			/* Intel 82454NX PXB#1, Bus#A */
559			*busnum = read_config(bus, 0x10, func, 0xd3, 1);
560			break;
561		case 0x15:
562			/* Intel 82454NX PXB#1, Bus#B */
563			*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
564			break;
565		}
566		break;
567
568		/* ServerWorks -- vendor 0x1166 */
569	case 0x00051166:
570	case 0x00061166:
571	case 0x00081166:
572	case 0x00091166:
573	case 0x00101166:
574	case 0x00111166:
575	case 0x00171166:
576	case 0x01011166:
577	case 0x010f1014:
578	case 0x02011166:
579	case 0x03021014:
580		*busnum = read_config(bus, slot, func, 0x44, 1);
581		break;
582
583		/* Compaq/HP -- vendor 0x0e11 */
584	case 0x60100e11:
585		*busnum = read_config(bus, slot, func, 0xc8, 1);
586		break;
587	default:
588		/* Don't know how to read bus number. */
589		return 0;
590	}
591
592	return 1;
593}
594