pci_subr.c revision 119418
169783Smsmith/*- 269783Smsmith * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 369783Smsmith * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 469783Smsmith * Copyright (c) 2000 BSDi 569783Smsmith * All rights reserved. 669783Smsmith * 769783Smsmith * Redistribution and use in source and binary forms, with or without 869783Smsmith * modification, are permitted provided that the following conditions 969783Smsmith * are met: 1069783Smsmith * 1. Redistributions of source code must retain the above copyright 1169783Smsmith * notice, this list of conditions and the following disclaimer. 1269783Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1369783Smsmith * notice, this list of conditions and the following disclaimer in the 1469783Smsmith * documentation and/or other materials provided with the distribution. 1569783Smsmith * 3. The name of the author may not be used to endorse or promote products 1669783Smsmith * derived from this software without specific prior written permission. 1769783Smsmith * 1869783Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1969783Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2069783Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2169783Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2269783Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2369783Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2469783Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2569783Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2669783Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2769783Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2869783Smsmith * SUCH DAMAGE. 2969783Smsmith */ 3069783Smsmith 31119418Sobrien#include <sys/cdefs.h> 32119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 119418 2003-08-24 17:55:58Z obrien $"); 33119418Sobrien 3469783Smsmith/* 3569783Smsmith * PCI:PCI bridge support. 3669783Smsmith */ 3769783Smsmith 3869783Smsmith#include <sys/param.h> 3969783Smsmith#include <sys/systm.h> 4069783Smsmith#include <sys/kernel.h> 4169783Smsmith#include <sys/bus.h> 42107546Simp#include <machine/bus.h> 43107546Simp#include <sys/rman.h> 44106844Smdodd#include <sys/sysctl.h> 4569783Smsmith 4669783Smsmith#include <machine/resource.h> 4769783Smsmith 48119285Simp#include <dev/pci/pcivar.h> 49119285Simp#include <dev/pci/pcireg.h> 50119285Simp#include <dev/pci/pcib_private.h> 5169783Smsmith 5269783Smsmith#include "pcib_if.h" 5369783Smsmith 5469783Smsmithstatic int pcib_probe(device_t dev); 5569783Smsmith 5669783Smsmithstatic device_method_t pcib_methods[] = { 5769783Smsmith /* Device interface */ 5869783Smsmith DEVMETHOD(device_probe, pcib_probe), 5969783Smsmith DEVMETHOD(device_attach, pcib_attach), 6069783Smsmith DEVMETHOD(device_shutdown, bus_generic_shutdown), 6169783Smsmith DEVMETHOD(device_suspend, bus_generic_suspend), 6269783Smsmith DEVMETHOD(device_resume, bus_generic_resume), 6369783Smsmith 6469783Smsmith /* Bus interface */ 6569783Smsmith DEVMETHOD(bus_print_child, bus_generic_print_child), 6669783Smsmith DEVMETHOD(bus_read_ivar, pcib_read_ivar), 6769783Smsmith DEVMETHOD(bus_write_ivar, pcib_write_ivar), 6869783Smsmith DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 6969783Smsmith DEVMETHOD(bus_release_resource, bus_generic_release_resource), 7069783Smsmith DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 7169783Smsmith DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 7269783Smsmith DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 7369783Smsmith DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 7469783Smsmith 7569783Smsmith /* pcib interface */ 7669783Smsmith DEVMETHOD(pcib_maxslots, pcib_maxslots), 7769783Smsmith DEVMETHOD(pcib_read_config, pcib_read_config), 7869783Smsmith DEVMETHOD(pcib_write_config, pcib_write_config), 7969783Smsmith DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 8069783Smsmith 8169783Smsmith { 0, 0 } 8269783Smsmith}; 8369783Smsmith 8469783Smsmithstatic driver_t pcib_driver = { 8569783Smsmith "pcib", 8669783Smsmith pcib_methods, 8769783Smsmith sizeof(struct pcib_softc), 8869783Smsmith}; 8969783Smsmith 90102441Sjhbdevclass_t pcib_devclass; 9169783Smsmith 9269783SmsmithDRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 9369783Smsmith 9469783Smsmith/* 95106844Smdodd * sysctl and tunable vars 96106844Smdodd */ 97106844Smdoddstatic int pci_allow_unsupported_io_range = 0; 98106844SmdoddTUNABLE_INT("hw.pci.allow_unsupported_io_range", 99106844Smdodd (int *)&pci_allow_unsupported_io_range); 100106844SmdoddSYSCTL_DECL(_hw_pci); 101106844SmdoddSYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD, 102106844Smdodd &pci_allow_unsupported_io_range, 0, 103106844Smdodd "Allows the PCI Bridge to pass through an unsupported memory range " 104106844Smdodd "assigned by the BIOS."); 105106844Smdodd 106106844Smdodd/* 10769783Smsmith * Generic device interface 10869783Smsmith */ 10969783Smsmithstatic int 11069783Smsmithpcib_probe(device_t dev) 11169783Smsmith{ 11269783Smsmith if ((pci_get_class(dev) == PCIC_BRIDGE) && 11369783Smsmith (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 11469783Smsmith device_set_desc(dev, "PCI-PCI bridge"); 11569783Smsmith return(-10000); 11669783Smsmith } 11769783Smsmith return(ENXIO); 11869783Smsmith} 11969783Smsmith 120102441Sjhbvoid 121102441Sjhbpcib_attach_common(device_t dev) 12269783Smsmith{ 12369783Smsmith struct pcib_softc *sc; 124119266Simp uint8_t iolow; 12569783Smsmith 12669783Smsmith sc = device_get_softc(dev); 12769783Smsmith sc->dev = dev; 12869783Smsmith 12969908Smsmith /* 13069908Smsmith * Get current bridge configuration. 13169908Smsmith */ 13269953Smsmith sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 13369908Smsmith sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 13469908Smsmith sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 13569908Smsmith sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 13669908Smsmith sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 13769908Smsmith sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 13869783Smsmith 13969908Smsmith /* 14069908Smsmith * Determine current I/O decode. 14169908Smsmith */ 14269953Smsmith if (sc->command & PCIM_CMD_PORTEN) { 14369953Smsmith iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 14469953Smsmith if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 14569953Smsmith sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 14669953Smsmith pci_read_config(dev, PCIR_IOBASEL_1, 1)); 14769953Smsmith } else { 14869953Smsmith sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 14969953Smsmith } 15069908Smsmith 15169953Smsmith iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 15269953Smsmith if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 15369953Smsmith sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 15469953Smsmith pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 15569953Smsmith } else { 15669953Smsmith sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 15769953Smsmith } 15869908Smsmith } 15969908Smsmith 16069908Smsmith /* 16169908Smsmith * Determine current memory decode. 16269908Smsmith */ 16369953Smsmith if (sc->command & PCIM_CMD_MEMEN) { 16469953Smsmith sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 16569953Smsmith sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 16669953Smsmith sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 16769953Smsmith pci_read_config(dev, PCIR_PMBASEL_1, 2)); 16869953Smsmith sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 16969953Smsmith pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 17069953Smsmith } 17169908Smsmith 17269908Smsmith /* 17369908Smsmith * Quirk handling. 17469908Smsmith */ 17569908Smsmith switch (pci_get_devid(dev)) { 17669908Smsmith case 0x12258086: /* Intel 82454KX/GX (Orion) */ 17769908Smsmith { 178119266Simp uint8_t supbus; 17969908Smsmith 18069908Smsmith supbus = pci_read_config(dev, 0x41, 1); 18169908Smsmith if (supbus != 0xff) { 18269908Smsmith sc->secbus = supbus + 1; 18369908Smsmith sc->subbus = supbus + 1; 18469908Smsmith } 18569908Smsmith } 18669908Smsmith break; 18769908Smsmith } 18869908Smsmith 18969783Smsmith if (bootverbose) { 19069783Smsmith device_printf(dev, " secondary bus %d\n", sc->secbus); 19169783Smsmith device_printf(dev, " subordinate bus %d\n", sc->subbus); 19269783Smsmith device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 19369783Smsmith device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 19469783Smsmith device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 19569783Smsmith } 19669783Smsmith 19769783Smsmith /* 19869783Smsmith * XXX If the secondary bus number is zero, we should assign a bus number 19969783Smsmith * since the BIOS hasn't, then initialise the bridge. 20069783Smsmith */ 20169783Smsmith 20269783Smsmith /* 20369783Smsmith * XXX If the subordinate bus number is less than the secondary bus number, 20469783Smsmith * we should pick a better value. One sensible alternative would be to 20569783Smsmith * pick 255; the only tradeoff here is that configuration transactions 20669783Smsmith * would be more widely routed than absolutely necessary. 20769783Smsmith */ 208102441Sjhb} 20969783Smsmith 210103042Sjhbint 211102441Sjhbpcib_attach(device_t dev) 212102441Sjhb{ 213102441Sjhb struct pcib_softc *sc; 214102441Sjhb device_t child; 215102441Sjhb 216102441Sjhb pcib_attach_common(dev); 217102441Sjhb sc = device_get_softc(dev); 21869783Smsmith if (sc->secbus != 0) { 219103016Sjhb child = device_add_child(dev, "pci", sc->secbus); 22069783Smsmith if (child != NULL) 22169783Smsmith return(bus_generic_attach(dev)); 22269783Smsmith } 22369783Smsmith 22469783Smsmith /* no secondary bus; we should have fixed this */ 22569783Smsmith return(0); 22669783Smsmith} 22769783Smsmith 228102441Sjhbint 22969783Smsmithpcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 23069783Smsmith{ 23169783Smsmith struct pcib_softc *sc = device_get_softc(dev); 23269783Smsmith 23369783Smsmith switch (which) { 23469783Smsmith case PCIB_IVAR_BUS: 23569783Smsmith *result = sc->secbus; 23669783Smsmith return(0); 23769783Smsmith } 23869783Smsmith return(ENOENT); 23969783Smsmith} 24069783Smsmith 241102441Sjhbint 24269783Smsmithpcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 24369783Smsmith{ 24469783Smsmith struct pcib_softc *sc = device_get_softc(dev); 24569783Smsmith 24669783Smsmith switch (which) { 24769783Smsmith case PCIB_IVAR_BUS: 24869783Smsmith sc->secbus = value; 24969783Smsmith break; 25069783Smsmith } 25169783Smsmith return(ENOENT); 25269783Smsmith} 25369783Smsmith 25469783Smsmith/* 25590388Simp * Is this a decoded ISA I/O port address? Note, we need to do the mask that 25690388Simp * we do below because of the ISA alias addresses. I'm not 100% sure that 257107546Simp * this is correct. Maybe the bridge needs to be subtractive decode for 258107546Simp * this to work? 25990388Simp */ 26090388Simpstatic int 26190388Simppcib_is_isa_io(u_long start) 26290388Simp{ 26390898Simp if ((start & 0xfffUL) > 0x3ffUL || start == 0) 26490388Simp return (0); 26590388Simp return (1); 26690388Simp} 26790388Simp 26890388Simp/* 26990388Simp * Is this a decoded ISA memory address? 27090388Simp */ 27190388Simpstatic int 27290388Simppcib_is_isa_mem(u_long start) 27390388Simp{ 27490898Simp if (start > 0xfffffUL || start == 0) 27590388Simp return (0); 27690388Simp return (1); 27790388Simp} 27890388Simp 27990388Simp/* 280107546Simp * Is the prefetch window open (eg, can we allocate memory in it?) 281107546Simp */ 282107546Simpstatic int 283107546Simppcib_is_prefetch_open(struct pcib_softc *sc) 284107546Simp{ 285107546Simp return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 286107546Simp} 287107546Simp 288107546Simp/* 289107546Simp * Is the nonprefetch window open (eg, can we allocate memory in it?) 290107546Simp */ 291107546Simpstatic int 292107546Simppcib_is_nonprefetch_open(struct pcib_softc *sc) 293107546Simp{ 294107546Simp return (sc->membase > 0 && sc->membase < sc->memlimit); 295107546Simp} 296107546Simp 297107546Simp/* 298107546Simp * Is the io window open (eg, can we allocate ports in it?) 299107546Simp */ 300107546Simpstatic int 301107546Simppcib_is_io_open(struct pcib_softc *sc) 302107546Simp{ 303107546Simp return (sc->iobase > 0 && sc->iobase < sc->iolimit); 304107546Simp} 305107546Simp 306107546Simp/* 30769783Smsmith * We have to trap resource allocation requests and ensure that the bridge 30869783Smsmith * is set up to, or capable of handling them. 30969783Smsmith */ 310102441Sjhbstruct resource * 31169783Smsmithpcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 31269783Smsmith u_long start, u_long end, u_long count, u_int flags) 31369783Smsmith{ 31469783Smsmith struct pcib_softc *sc = device_get_softc(dev); 315107546Simp int ok; 31669783Smsmith 31769783Smsmith /* 31869783Smsmith * If this is a "default" allocation against this rid, we can't work 31969783Smsmith * out where it's coming from (we should actually never see these) so we 32069783Smsmith * just have to punt. 32169783Smsmith */ 32269783Smsmith if ((start == 0) && (end == ~0)) { 32369783Smsmith device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 32469783Smsmith *rid, device_get_name(child), device_get_unit(child)); 32569783Smsmith } else { 32669783Smsmith /* 32769783Smsmith * Fail the allocation for this range if it's not supported. 32869783Smsmith */ 32969783Smsmith switch (type) { 33069783Smsmith case SYS_RES_IOPORT: 331107546Simp ok = 1; 33290898Simp if (!pcib_is_isa_io(start)) { 333107546Simp ok = 0; 334107546Simp if (pcib_is_io_open(sc)) 335107546Simp ok = (start >= sc->iobase && end <= sc->iolimit); 336106844Smdodd if (!pci_allow_unsupported_io_range) { 337107546Simp if (!ok) { 338107546Simp if (start < sc->iobase) 339107546Simp start = sc->iobase; 340107546Simp if (end > sc->iolimit) 341107546Simp end = sc->iolimit; 342107546Simp } 343106844Smdodd } else { 344106844Smdodd if (start < sc->iobase) 345106844Smdodd printf("start (%lx) < sc->iobase (%x)\n", start, 346106844Smdodd sc->iobase); 347106844Smdodd if (end > sc->iolimit) 348106844Smdodd printf("end (%lx) > sc->iolimit (%x)\n", 349106844Smdodd end, sc->iolimit); 350106844Smdodd if (end < start) 351106844Smdodd printf("end (%lx) < start (%lx)\n", end, start); 352106844Smdodd } 35390898Simp } 354107546Simp if (end < start) { 355107546Simp start = 0; 356107546Simp end = 0; 357107546Simp ok = 0; 358107546Simp } 359107546Simp if (!ok) { 360107546Simp device_printf(dev, "device %s%d requested unsupported I/O " 361107546Simp "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 362107546Simp device_get_name(child), device_get_unit(child), start, end, 363107546Simp sc->iobase, sc->iolimit); 36490388Simp return (NULL); 36569783Smsmith } 36669908Smsmith if (bootverbose) 36769908Smsmith device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 36869908Smsmith device_get_name(child), device_get_unit(child), start, end); 36969783Smsmith break; 37069783Smsmith 37169783Smsmith case SYS_RES_MEMORY: 372107546Simp ok = 1; 37390898Simp if (!pcib_is_isa_mem(start)) { 374107546Simp ok = 0; 375107546Simp if (pcib_is_nonprefetch_open(sc)) 376107546Simp ok = ok || (start >= sc->membase && end <= sc->memlimit); 377107546Simp if (pcib_is_prefetch_open(sc)) 378107546Simp ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 379106844Smdodd if (!pci_allow_unsupported_io_range) { 380107546Simp if (!ok) { 381107546Simp ok = 1; 382107546Simp if (flags & RF_PREFETCHABLE) { 383107546Simp if (pcib_is_prefetch_open(sc)) { 384107546Simp if (start < sc->pmembase) 385107546Simp start = sc->pmembase; 386107546Simp if (end > sc->pmemlimit) 387107546Simp end = sc->pmemlimit; 388107546Simp } else { 389107546Simp ok = 0; 390107546Simp } 391107546Simp } else { /* non-prefetchable */ 392107546Simp if (pcib_is_nonprefetch_open(sc)) { 393107546Simp if (start < sc->membase) 394107546Simp start = sc->membase; 395107546Simp if (end > sc->memlimit) 396107546Simp end = sc->memlimit; 397107546Simp } else { 398107546Simp ok = 0; 399107546Simp } 400107546Simp } 401107546Simp } 402107546Simp } else if (!ok) { 403107546Simp ok = 1; /* pci_allow_unsupported_ranges -> always ok */ 404107546Simp if (pcib_is_nonprefetch_open(sc)) { 405107546Simp if (start < sc->membase) 406107546Simp printf("start (%lx) < sc->membase (%x)\n", 407107546Simp start, sc->membase); 408107546Simp if (end > sc->memlimit) 409107546Simp printf("end (%lx) > sc->memlimit (%x)\n", 410107546Simp end, sc->memlimit); 411107546Simp } 412107546Simp if (pcib_is_prefetch_open(sc)) { 413107546Simp if (start < sc->pmembase) 414107546Simp printf("start (%lx) < sc->pmembase (%x)\n", 415107546Simp start, sc->pmembase); 416107546Simp if (end > sc->pmemlimit) 417107546Simp printf("end (%lx) > sc->pmemlimit (%x)\n", 418107546Simp end, sc->memlimit); 419107546Simp } 420106844Smdodd if (end < start) 421106844Smdodd printf("end (%lx) < start (%lx)\n", end, start); 422106844Smdodd } 42390898Simp } 424107546Simp if (end < start) { 425107546Simp start = 0; 426107546Simp end = 0; 427107546Simp ok = 0; 42869783Smsmith } 429107546Simp if (!ok && bootverbose) 430107546Simp device_printf(dev, 431107546Simp "device %s%d requested unsupported memory range " 432107546Simp "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 433107546Simp device_get_name(child), device_get_unit(child), start, 434107546Simp end, sc->membase, sc->memlimit, sc->pmembase, 435107546Simp sc->pmemlimit); 436107546Simp if (!ok) 437107546Simp return (NULL); 43869908Smsmith if (bootverbose) 43969908Smsmith device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 440107546Simp device_get_name(child), device_get_unit(child), start, end); 44169908Smsmith break; 44269908Smsmith 44369783Smsmith default: 44469908Smsmith break; 44569783Smsmith } 44669783Smsmith } 44769908Smsmith 44869783Smsmith /* 44969783Smsmith * Bridge is OK decoding this resource, so pass it up. 45069783Smsmith */ 45169783Smsmith return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 45269783Smsmith} 45369783Smsmith 45469783Smsmith/* 45569783Smsmith * PCIB interface. 45669783Smsmith */ 457102441Sjhbint 45869783Smsmithpcib_maxslots(device_t dev) 45969783Smsmith{ 46069908Smsmith return(PCI_SLOTMAX); 46169783Smsmith} 46269783Smsmith 46369783Smsmith/* 46469783Smsmith * Since we are a child of a PCI bus, its parent must support the pcib interface. 46569783Smsmith */ 466119266Simpuint32_t 46769783Smsmithpcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 46869783Smsmith{ 46969783Smsmith return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 47069783Smsmith} 47169783Smsmith 472102441Sjhbvoid 473119266Simppcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 47469783Smsmith{ 47569783Smsmith PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 47669783Smsmith} 47769783Smsmith 47869783Smsmith/* 47969783Smsmith * Route an interrupt across a PCI bridge. 48069783Smsmith */ 481109229Sbennoint 48269783Smsmithpcib_route_interrupt(device_t pcib, device_t dev, int pin) 48369783Smsmith{ 48469783Smsmith device_t bus; 48569783Smsmith int parent_intpin; 48669783Smsmith int intnum; 48769783Smsmith 48869783Smsmith /* 48969783Smsmith * 49069783Smsmith * The PCI standard defines a swizzle of the child-side device/intpin to 49169783Smsmith * the parent-side intpin as follows. 49269783Smsmith * 49369783Smsmith * device = device on child bus 49469783Smsmith * child_intpin = intpin on child bus slot (0-3) 49569783Smsmith * parent_intpin = intpin on parent bus slot (0-3) 49669783Smsmith * 49769783Smsmith * parent_intpin = (device + child_intpin) % 4 49869783Smsmith */ 499115234Sticso parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 50069783Smsmith 50169783Smsmith /* 50269783Smsmith * Our parent is a PCI bus. Its parent must export the pcib interface 50369783Smsmith * which includes the ability to route interrupts. 50469783Smsmith */ 50569783Smsmith bus = device_get_parent(pcib); 50669783Smsmith intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 50790554Smsmith if (PCI_INTERRUPT_VALID(intnum)) { 508102977Sjhb device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 509102977Sjhb pci_get_slot(dev), 'A' + pin - 1, intnum); 51090554Smsmith } 51169783Smsmith return(intnum); 51269783Smsmith} 513107172Sjhb 514107172Sjhb/* 515107172Sjhb * Try to read the bus number of a host-PCI bridge using appropriate config 516107172Sjhb * registers. 517107172Sjhb */ 518107172Sjhbint 519107172Sjhbhost_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 520119266Simp uint8_t *busnum) 521107172Sjhb{ 522119266Simp uint32_t id; 523107172Sjhb 524107172Sjhb id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 525107248Sjhb if (id == 0xffffffff) 526107172Sjhb return (0); 527107172Sjhb 528107172Sjhb switch (id) { 529107172Sjhb case 0x12258086: 530107172Sjhb /* Intel 824?? */ 531107172Sjhb /* XXX This is a guess */ 532107172Sjhb /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 533107172Sjhb *busnum = bus; 534107172Sjhb break; 535107172Sjhb case 0x84c48086: 536107172Sjhb /* Intel 82454KX/GX (Orion) */ 537107172Sjhb *busnum = read_config(bus, slot, func, 0x4a, 1); 538107172Sjhb break; 539107172Sjhb case 0x84ca8086: 540107172Sjhb /* 541107172Sjhb * For the 450nx chipset, there is a whole bundle of 542107172Sjhb * things pretending to be host bridges. The MIOC will 543107172Sjhb * be seen first and isn't really a pci bridge (the 544107172Sjhb * actual busses are attached to the PXB's). We need to 545107172Sjhb * read the registers of the MIOC to figure out the 546107172Sjhb * bus numbers for the PXB channels. 547107172Sjhb * 548107172Sjhb * Since the MIOC doesn't have a pci bus attached, we 549107172Sjhb * pretend it wasn't there. 550107172Sjhb */ 551107172Sjhb return (0); 552107172Sjhb case 0x84cb8086: 553107172Sjhb switch (slot) { 554107172Sjhb case 0x12: 555107172Sjhb /* Intel 82454NX PXB#0, Bus#A */ 556107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd0, 1); 557107172Sjhb break; 558107172Sjhb case 0x13: 559107172Sjhb /* Intel 82454NX PXB#0, Bus#B */ 560107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 561107172Sjhb break; 562107172Sjhb case 0x14: 563107172Sjhb /* Intel 82454NX PXB#1, Bus#A */ 564107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd3, 1); 565107172Sjhb break; 566107172Sjhb case 0x15: 567107172Sjhb /* Intel 82454NX PXB#1, Bus#B */ 568107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 569107172Sjhb break; 570107172Sjhb } 571107172Sjhb break; 572107172Sjhb 573107172Sjhb /* ServerWorks -- vendor 0x1166 */ 574107172Sjhb case 0x00051166: 575107172Sjhb case 0x00061166: 576107172Sjhb case 0x00081166: 577107172Sjhb case 0x00091166: 578107172Sjhb case 0x00101166: 579107172Sjhb case 0x00111166: 580107172Sjhb case 0x00171166: 581107172Sjhb case 0x01011166: 582107172Sjhb case 0x010f1014: 583107172Sjhb case 0x02011166: 584107172Sjhb case 0x03021014: 585107172Sjhb *busnum = read_config(bus, slot, func, 0x44, 1); 586107172Sjhb break; 587107172Sjhb default: 588107172Sjhb /* Don't know how to read bus number. */ 589107172Sjhb return 0; 590107172Sjhb } 591107172Sjhb 592107172Sjhb return 1; 593107172Sjhb} 594