pci_subr.c revision 107248
169783Smsmith/*- 269783Smsmith * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 369783Smsmith * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 469783Smsmith * Copyright (c) 2000 BSDi 569783Smsmith * All rights reserved. 669783Smsmith * 769783Smsmith * Redistribution and use in source and binary forms, with or without 869783Smsmith * modification, are permitted provided that the following conditions 969783Smsmith * are met: 1069783Smsmith * 1. Redistributions of source code must retain the above copyright 1169783Smsmith * notice, this list of conditions and the following disclaimer. 1269783Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1369783Smsmith * notice, this list of conditions and the following disclaimer in the 1469783Smsmith * documentation and/or other materials provided with the distribution. 1569783Smsmith * 3. The name of the author may not be used to endorse or promote products 1669783Smsmith * derived from this software without specific prior written permission. 1769783Smsmith * 1869783Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1969783Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2069783Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2169783Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2269783Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2369783Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2469783Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2569783Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2669783Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2769783Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2869783Smsmith * SUCH DAMAGE. 2969783Smsmith * 3069783Smsmith * $FreeBSD: head/sys/dev/pci/pci_pci.c 107248 2002-11-25 21:53:14Z jhb $ 3169783Smsmith */ 3269783Smsmith 3369783Smsmith/* 3469783Smsmith * PCI:PCI bridge support. 3569783Smsmith */ 3669783Smsmith 3769783Smsmith#include <sys/param.h> 3869783Smsmith#include <sys/systm.h> 3969783Smsmith#include <sys/kernel.h> 4069783Smsmith#include <sys/bus.h> 41106844Smdodd#include <sys/sysctl.h> 4269783Smsmith 4369783Smsmith#include <machine/resource.h> 4469783Smsmith 4569783Smsmith#include <pci/pcivar.h> 4669783Smsmith#include <pci/pcireg.h> 47102441Sjhb#include <pci/pcib_private.h> 4869783Smsmith 4969783Smsmith#include "pcib_if.h" 5069783Smsmith 5169783Smsmithstatic int pcib_probe(device_t dev); 5269783Smsmithstatic int pcib_route_interrupt(device_t pcib, device_t dev, int pin); 5369783Smsmith 5469783Smsmithstatic device_method_t pcib_methods[] = { 5569783Smsmith /* Device interface */ 5669783Smsmith DEVMETHOD(device_probe, pcib_probe), 5769783Smsmith DEVMETHOD(device_attach, pcib_attach), 5869783Smsmith DEVMETHOD(device_shutdown, bus_generic_shutdown), 5969783Smsmith DEVMETHOD(device_suspend, bus_generic_suspend), 6069783Smsmith DEVMETHOD(device_resume, bus_generic_resume), 6169783Smsmith 6269783Smsmith /* Bus interface */ 6369783Smsmith DEVMETHOD(bus_print_child, bus_generic_print_child), 6469783Smsmith DEVMETHOD(bus_read_ivar, pcib_read_ivar), 6569783Smsmith DEVMETHOD(bus_write_ivar, pcib_write_ivar), 6669783Smsmith DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 6769783Smsmith DEVMETHOD(bus_release_resource, bus_generic_release_resource), 6869783Smsmith DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 6969783Smsmith DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 7069783Smsmith DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 7169783Smsmith DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 7269783Smsmith 7369783Smsmith /* pcib interface */ 7469783Smsmith DEVMETHOD(pcib_maxslots, pcib_maxslots), 7569783Smsmith DEVMETHOD(pcib_read_config, pcib_read_config), 7669783Smsmith DEVMETHOD(pcib_write_config, pcib_write_config), 7769783Smsmith DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 7869783Smsmith 7969783Smsmith { 0, 0 } 8069783Smsmith}; 8169783Smsmith 8269783Smsmithstatic driver_t pcib_driver = { 8369783Smsmith "pcib", 8469783Smsmith pcib_methods, 8569783Smsmith sizeof(struct pcib_softc), 8669783Smsmith}; 8769783Smsmith 88102441Sjhbdevclass_t pcib_devclass; 8969783Smsmith 9069783SmsmithDRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 9169783Smsmith 9269783Smsmith/* 93106844Smdodd * sysctl and tunable vars 94106844Smdodd */ 95106844Smdoddstatic int pci_allow_unsupported_io_range = 0; 96106844SmdoddTUNABLE_INT("hw.pci.allow_unsupported_io_range", 97106844Smdodd (int *)&pci_allow_unsupported_io_range); 98106844SmdoddSYSCTL_DECL(_hw_pci); 99106844SmdoddSYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RD, 100106844Smdodd &pci_allow_unsupported_io_range, 0, 101106844Smdodd "Allows the PCI Bridge to pass through an unsupported memory range " 102106844Smdodd "assigned by the BIOS."); 103106844Smdodd 104106844Smdodd/* 10569783Smsmith * Generic device interface 10669783Smsmith */ 10769783Smsmithstatic int 10869783Smsmithpcib_probe(device_t dev) 10969783Smsmith{ 11069783Smsmith if ((pci_get_class(dev) == PCIC_BRIDGE) && 11169783Smsmith (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 11269783Smsmith device_set_desc(dev, "PCI-PCI bridge"); 11369783Smsmith return(-10000); 11469783Smsmith } 11569783Smsmith return(ENXIO); 11669783Smsmith} 11769783Smsmith 118102441Sjhbvoid 119102441Sjhbpcib_attach_common(device_t dev) 12069783Smsmith{ 12169783Smsmith struct pcib_softc *sc; 12269908Smsmith u_int8_t iolow; 12369783Smsmith 12469783Smsmith sc = device_get_softc(dev); 12569783Smsmith sc->dev = dev; 12669783Smsmith 12769908Smsmith /* 12869908Smsmith * Get current bridge configuration. 12969908Smsmith */ 13069953Smsmith sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 13169908Smsmith sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 13269908Smsmith sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 13369908Smsmith sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 13469908Smsmith sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 13569908Smsmith sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 13669783Smsmith 13769908Smsmith /* 13869908Smsmith * Determine current I/O decode. 13969908Smsmith */ 14069953Smsmith if (sc->command & PCIM_CMD_PORTEN) { 14169953Smsmith iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 14269953Smsmith if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 14369953Smsmith sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 14469953Smsmith pci_read_config(dev, PCIR_IOBASEL_1, 1)); 14569953Smsmith } else { 14669953Smsmith sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 14769953Smsmith } 14869908Smsmith 14969953Smsmith iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 15069953Smsmith if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 15169953Smsmith sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 15269953Smsmith pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 15369953Smsmith } else { 15469953Smsmith sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 15569953Smsmith } 15669908Smsmith } 15769908Smsmith 15869908Smsmith /* 15969908Smsmith * Determine current memory decode. 16069908Smsmith */ 16169953Smsmith if (sc->command & PCIM_CMD_MEMEN) { 16269953Smsmith sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 16369953Smsmith sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 16469953Smsmith sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4), 16569953Smsmith pci_read_config(dev, PCIR_PMBASEL_1, 2)); 16669953Smsmith sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4), 16769953Smsmith pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 16869953Smsmith } 16969908Smsmith 17069908Smsmith /* 17169908Smsmith * Quirk handling. 17269908Smsmith */ 17369908Smsmith switch (pci_get_devid(dev)) { 17469908Smsmith case 0x12258086: /* Intel 82454KX/GX (Orion) */ 17569908Smsmith { 17669908Smsmith u_int8_t supbus; 17769908Smsmith 17869908Smsmith supbus = pci_read_config(dev, 0x41, 1); 17969908Smsmith if (supbus != 0xff) { 18069908Smsmith sc->secbus = supbus + 1; 18169908Smsmith sc->subbus = supbus + 1; 18269908Smsmith } 18369908Smsmith } 18469908Smsmith break; 18569908Smsmith } 18669908Smsmith 18769783Smsmith if (bootverbose) { 18869783Smsmith device_printf(dev, " secondary bus %d\n", sc->secbus); 18969783Smsmith device_printf(dev, " subordinate bus %d\n", sc->subbus); 19069783Smsmith device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 19169783Smsmith device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit); 19269783Smsmith device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit); 19369783Smsmith } 19469783Smsmith 19569783Smsmith /* 19669783Smsmith * XXX If the secondary bus number is zero, we should assign a bus number 19769783Smsmith * since the BIOS hasn't, then initialise the bridge. 19869783Smsmith */ 19969783Smsmith 20069783Smsmith /* 20169783Smsmith * XXX If the subordinate bus number is less than the secondary bus number, 20269783Smsmith * we should pick a better value. One sensible alternative would be to 20369783Smsmith * pick 255; the only tradeoff here is that configuration transactions 20469783Smsmith * would be more widely routed than absolutely necessary. 20569783Smsmith */ 206102441Sjhb} 20769783Smsmith 208103042Sjhbint 209102441Sjhbpcib_attach(device_t dev) 210102441Sjhb{ 211102441Sjhb struct pcib_softc *sc; 212102441Sjhb device_t child; 213102441Sjhb 214102441Sjhb pcib_attach_common(dev); 215102441Sjhb sc = device_get_softc(dev); 21669783Smsmith if (sc->secbus != 0) { 217103016Sjhb child = device_add_child(dev, "pci", sc->secbus); 21869783Smsmith if (child != NULL) 21969783Smsmith return(bus_generic_attach(dev)); 22069783Smsmith } 22169783Smsmith 22269783Smsmith /* no secondary bus; we should have fixed this */ 22369783Smsmith return(0); 22469783Smsmith} 22569783Smsmith 226102441Sjhbint 22769783Smsmithpcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 22869783Smsmith{ 22969783Smsmith struct pcib_softc *sc = device_get_softc(dev); 23069783Smsmith 23169783Smsmith switch (which) { 23269783Smsmith case PCIB_IVAR_BUS: 23369783Smsmith *result = sc->secbus; 23469783Smsmith return(0); 23569783Smsmith } 23669783Smsmith return(ENOENT); 23769783Smsmith} 23869783Smsmith 239102441Sjhbint 24069783Smsmithpcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 24169783Smsmith{ 24269783Smsmith struct pcib_softc *sc = device_get_softc(dev); 24369783Smsmith 24469783Smsmith switch (which) { 24569783Smsmith case PCIB_IVAR_BUS: 24669783Smsmith sc->secbus = value; 24769783Smsmith break; 24869783Smsmith } 24969783Smsmith return(ENOENT); 25069783Smsmith} 25169783Smsmith 25269783Smsmith/* 25390388Simp * Is this a decoded ISA I/O port address? Note, we need to do the mask that 25490388Simp * we do below because of the ISA alias addresses. I'm not 100% sure that 25590388Simp * this is correct. 25690388Simp */ 25790388Simpstatic int 25890388Simppcib_is_isa_io(u_long start) 25990388Simp{ 26090898Simp if ((start & 0xfffUL) > 0x3ffUL || start == 0) 26190388Simp return (0); 26290388Simp return (1); 26390388Simp} 26490388Simp 26590388Simp/* 26690388Simp * Is this a decoded ISA memory address? 26790388Simp */ 26890388Simpstatic int 26990388Simppcib_is_isa_mem(u_long start) 27090388Simp{ 27190898Simp if (start > 0xfffffUL || start == 0) 27290388Simp return (0); 27390388Simp return (1); 27490388Simp} 27590388Simp 27690388Simp/* 27769783Smsmith * We have to trap resource allocation requests and ensure that the bridge 27869783Smsmith * is set up to, or capable of handling them. 27969783Smsmith */ 280102441Sjhbstruct resource * 28169783Smsmithpcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 28269783Smsmith u_long start, u_long end, u_long count, u_int flags) 28369783Smsmith{ 28469783Smsmith struct pcib_softc *sc = device_get_softc(dev); 28569783Smsmith 28669783Smsmith /* 28769783Smsmith * If this is a "default" allocation against this rid, we can't work 28869783Smsmith * out where it's coming from (we should actually never see these) so we 28969783Smsmith * just have to punt. 29069783Smsmith */ 29169783Smsmith if ((start == 0) && (end == ~0)) { 29269783Smsmith device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n", 29369783Smsmith *rid, device_get_name(child), device_get_unit(child)); 29469783Smsmith } else { 29569783Smsmith /* 29669783Smsmith * Fail the allocation for this range if it's not supported. 29769783Smsmith * 29869783Smsmith * XXX we should probably just fix up the bridge decode and soldier on. 29969783Smsmith */ 30069783Smsmith switch (type) { 30169783Smsmith case SYS_RES_IOPORT: 30290898Simp if (!pcib_is_isa_io(start)) { 303106844Smdodd if (!pci_allow_unsupported_io_range) { 304106844Smdodd if (start < sc->iobase) 305106844Smdodd start = sc->iobase; 306106844Smdodd if (end > sc->iolimit) 307106844Smdodd end = sc->iolimit; 308106844Smdodd if (end < start) 309106844Smdodd start = 0; 310106844Smdodd } else { 311106844Smdodd if (start < sc->iobase) 312106844Smdodd printf("start (%lx) < sc->iobase (%x)\n", start, 313106844Smdodd sc->iobase); 314106844Smdodd if (end > sc->iolimit) 315106844Smdodd printf("end (%lx) > sc->iolimit (%x)\n", 316106844Smdodd end, sc->iolimit); 317106844Smdodd if (end < start) 318106844Smdodd printf("end (%lx) < start (%lx)\n", end, start); 319106844Smdodd } 32090898Simp } 32190388Simp if (!pcib_is_isa_io(start) && 32290388Simp ((start < sc->iobase) || (end > sc->iolimit))) { 32369783Smsmith device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx" 32469783Smsmith " (decoding 0x%x-0x%x)\n", 32569783Smsmith device_get_name(child), device_get_unit(child), start, end, 32669783Smsmith sc->iobase, sc->iolimit); 32790388Simp return (NULL); 32869783Smsmith } 32969908Smsmith if (bootverbose) 33069908Smsmith device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n", 33169908Smsmith device_get_name(child), device_get_unit(child), start, end); 33269783Smsmith break; 33369783Smsmith 33469783Smsmith /* 33569783Smsmith * XXX will have to decide whether the device making the request is asking 33669783Smsmith * for prefetchable memory or not. If it's coming from another bridge 33769783Smsmith * down the line, do we assume not, or ask the bridge to pass in another 33869783Smsmith * flag as the request bubbles up? 33969783Smsmith */ 34069783Smsmith case SYS_RES_MEMORY: 34190898Simp if (!pcib_is_isa_mem(start)) { 342106844Smdodd if (!pci_allow_unsupported_io_range) { 343106844Smdodd if (start < sc->membase && end >= sc->membase) 344106844Smdodd start = sc->membase; 345106844Smdodd if (end > sc->memlimit) 346106844Smdodd end = sc->memlimit; 347106844Smdodd if (end < start) 348106844Smdodd start = 0; 349106844Smdodd } else { 350106844Smdodd if (start < sc->membase && end > sc->membase) 351106844Smdodd printf("start (%lx) < sc->membase (%x)\n", 352106844Smdodd start, sc->membase); 353106844Smdodd if (end > sc->memlimit) 354106844Smdodd printf("end (%lx) > sc->memlimit (%x)\n", 355106844Smdodd end, sc->memlimit); 356106844Smdodd if (end < start) 357106844Smdodd printf("end (%lx) < start (%lx)\n", end, start); 358106844Smdodd } 35990898Simp } 36090388Simp if (!pcib_is_isa_mem(start) && 36190388Simp (((start < sc->membase) || (end > sc->memlimit)) && 36290388Simp ((start < sc->pmembase) || (end > sc->pmemlimit)))) { 36390435Simp if (bootverbose) 36490435Simp device_printf(dev, 36590435Simp "device %s%d requested unsupported memory range " 36690435Simp "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n", 36790435Simp device_get_name(child), device_get_unit(child), start, 36890435Simp end, sc->membase, sc->memlimit, sc->pmembase, 36990435Simp sc->pmemlimit); 370106844Smdodd if (!pci_allow_unsupported_io_range) 371106844Smdodd return (NULL); 37269783Smsmith } 37369908Smsmith if (bootverbose) 37469908Smsmith device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n", 37569908Smsmith device_get_name(child), device_get_unit(child), start, end); 37669908Smsmith break; 37769908Smsmith 37869783Smsmith default: 37969908Smsmith break; 38069783Smsmith } 38169783Smsmith } 38269908Smsmith 38369783Smsmith /* 38469783Smsmith * Bridge is OK decoding this resource, so pass it up. 38569783Smsmith */ 38669783Smsmith return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); 38769783Smsmith} 38869783Smsmith 38969783Smsmith/* 39069783Smsmith * PCIB interface. 39169783Smsmith */ 392102441Sjhbint 39369783Smsmithpcib_maxslots(device_t dev) 39469783Smsmith{ 39569908Smsmith return(PCI_SLOTMAX); 39669783Smsmith} 39769783Smsmith 39869783Smsmith/* 39969783Smsmith * Since we are a child of a PCI bus, its parent must support the pcib interface. 40069783Smsmith */ 401102441Sjhbu_int32_t 40269783Smsmithpcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 40369783Smsmith{ 40469783Smsmith return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 40569783Smsmith} 40669783Smsmith 407102441Sjhbvoid 40869783Smsmithpcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width) 40969783Smsmith{ 41069783Smsmith PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 41169783Smsmith} 41269783Smsmith 41369783Smsmith/* 41469783Smsmith * Route an interrupt across a PCI bridge. 41569783Smsmith */ 41669783Smsmithstatic int 41769783Smsmithpcib_route_interrupt(device_t pcib, device_t dev, int pin) 41869783Smsmith{ 41969783Smsmith device_t bus; 42069783Smsmith int parent_intpin; 42169783Smsmith int intnum; 42269783Smsmith 42369783Smsmith /* 42469783Smsmith * 42569783Smsmith * The PCI standard defines a swizzle of the child-side device/intpin to 42669783Smsmith * the parent-side intpin as follows. 42769783Smsmith * 42869783Smsmith * device = device on child bus 42969783Smsmith * child_intpin = intpin on child bus slot (0-3) 43069783Smsmith * parent_intpin = intpin on parent bus slot (0-3) 43169783Smsmith * 43269783Smsmith * parent_intpin = (device + child_intpin) % 4 43369783Smsmith */ 43469783Smsmith parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4; 43569783Smsmith 43669783Smsmith /* 43769783Smsmith * Our parent is a PCI bus. Its parent must export the pcib interface 43869783Smsmith * which includes the ability to route interrupts. 43969783Smsmith */ 44069783Smsmith bus = device_get_parent(pcib); 44169783Smsmith intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 44290554Smsmith if (PCI_INTERRUPT_VALID(intnum)) { 443102977Sjhb device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 444102977Sjhb pci_get_slot(dev), 'A' + pin - 1, intnum); 44590554Smsmith } 44669783Smsmith return(intnum); 44769783Smsmith} 448107172Sjhb 449107172Sjhb/* 450107172Sjhb * Try to read the bus number of a host-PCI bridge using appropriate config 451107172Sjhb * registers. 452107172Sjhb */ 453107172Sjhbint 454107172Sjhbhost_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 455107172Sjhb u_int8_t *busnum) 456107172Sjhb{ 457107172Sjhb u_int32_t id; 458107172Sjhb 459107172Sjhb id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 460107248Sjhb if (id == 0xffffffff) 461107172Sjhb return (0); 462107172Sjhb 463107172Sjhb switch (id) { 464107172Sjhb case 0x12258086: 465107172Sjhb /* Intel 824?? */ 466107172Sjhb /* XXX This is a guess */ 467107172Sjhb /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 468107172Sjhb *busnum = bus; 469107172Sjhb break; 470107172Sjhb case 0x84c48086: 471107172Sjhb /* Intel 82454KX/GX (Orion) */ 472107172Sjhb *busnum = read_config(bus, slot, func, 0x4a, 1); 473107172Sjhb break; 474107172Sjhb case 0x84ca8086: 475107172Sjhb /* 476107172Sjhb * For the 450nx chipset, there is a whole bundle of 477107172Sjhb * things pretending to be host bridges. The MIOC will 478107172Sjhb * be seen first and isn't really a pci bridge (the 479107172Sjhb * actual busses are attached to the PXB's). We need to 480107172Sjhb * read the registers of the MIOC to figure out the 481107172Sjhb * bus numbers for the PXB channels. 482107172Sjhb * 483107172Sjhb * Since the MIOC doesn't have a pci bus attached, we 484107172Sjhb * pretend it wasn't there. 485107172Sjhb */ 486107172Sjhb return (0); 487107172Sjhb case 0x84cb8086: 488107172Sjhb switch (slot) { 489107172Sjhb case 0x12: 490107172Sjhb /* Intel 82454NX PXB#0, Bus#A */ 491107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd0, 1); 492107172Sjhb break; 493107172Sjhb case 0x13: 494107172Sjhb /* Intel 82454NX PXB#0, Bus#B */ 495107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 496107172Sjhb break; 497107172Sjhb case 0x14: 498107172Sjhb /* Intel 82454NX PXB#1, Bus#A */ 499107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd3, 1); 500107172Sjhb break; 501107172Sjhb case 0x15: 502107172Sjhb /* Intel 82454NX PXB#1, Bus#B */ 503107248Sjhb *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 504107172Sjhb break; 505107172Sjhb } 506107172Sjhb break; 507107172Sjhb 508107172Sjhb /* ServerWorks -- vendor 0x1166 */ 509107172Sjhb case 0x00051166: 510107172Sjhb case 0x00061166: 511107172Sjhb case 0x00081166: 512107172Sjhb case 0x00091166: 513107172Sjhb case 0x00101166: 514107172Sjhb case 0x00111166: 515107172Sjhb case 0x00171166: 516107172Sjhb case 0x01011166: 517107172Sjhb case 0x010f1014: 518107172Sjhb case 0x02011166: 519107172Sjhb case 0x03021014: 520107172Sjhb *busnum = read_config(bus, slot, func, 0x44, 1); 521107172Sjhb break; 522107172Sjhb default: 523107172Sjhb /* Don't know how to read bus number. */ 524107172Sjhb return 0; 525107172Sjhb } 526107172Sjhb 527107172Sjhb return 1; 528107172Sjhb} 529