pci_pci.c revision 313408
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/11/sys/dev/pci/pci_pci.c 313408 2017-02-07 22:40:38Z jhb $"); 33 34/* 35 * PCI:PCI bridge support. 36 */ 37 38#include "opt_pci.h" 39 40#include <sys/param.h> 41#include <sys/bus.h> 42#include <sys/kernel.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/sysctl.h> 47#include <sys/systm.h> 48#include <sys/taskqueue.h> 49 50#include <dev/pci/pcivar.h> 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pci_private.h> 53#include <dev/pci/pcib_private.h> 54 55#include "pcib_if.h" 56 57static int pcib_probe(device_t dev); 58static int pcib_suspend(device_t dev); 59static int pcib_resume(device_t dev); 60static int pcib_power_for_sleep(device_t pcib, device_t dev, 61 int *pstate); 62static int pcib_ari_get_id(device_t pcib, device_t dev, 63 enum pci_id_type type, uintptr_t *id); 64static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 65 u_int f, u_int reg, int width); 66static void pcib_write_config(device_t dev, u_int b, u_int s, 67 u_int f, u_int reg, uint32_t val, int width); 68static int pcib_ari_maxslots(device_t dev); 69static int pcib_ari_maxfuncs(device_t dev); 70static int pcib_try_enable_ari(device_t pcib, device_t dev); 71static int pcib_ari_enabled(device_t pcib); 72static void pcib_ari_decode_rid(device_t pcib, uint16_t rid, 73 int *bus, int *slot, int *func); 74#ifdef PCI_HP 75static void pcib_pcie_ab_timeout(void *arg); 76static void pcib_pcie_cc_timeout(void *arg); 77static void pcib_pcie_dll_timeout(void *arg); 78#endif 79 80static device_method_t pcib_methods[] = { 81 /* Device interface */ 82 DEVMETHOD(device_probe, pcib_probe), 83 DEVMETHOD(device_attach, pcib_attach), 84 DEVMETHOD(device_detach, pcib_detach), 85 DEVMETHOD(device_shutdown, bus_generic_shutdown), 86 DEVMETHOD(device_suspend, pcib_suspend), 87 DEVMETHOD(device_resume, pcib_resume), 88 89 /* Bus interface */ 90 DEVMETHOD(bus_child_present, pcib_child_present), 91 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 92 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 93 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 94#ifdef NEW_PCIB 95 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 96 DEVMETHOD(bus_release_resource, pcib_release_resource), 97#else 98 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 99 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 100#endif 101 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 102 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 /* pcib interface */ 107 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 108 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 109 DEVMETHOD(pcib_read_config, pcib_read_config), 110 DEVMETHOD(pcib_write_config, pcib_write_config), 111 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 112 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 113 DEVMETHOD(pcib_release_msi, pcib_release_msi), 114 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 115 DEVMETHOD(pcib_release_msix, pcib_release_msix), 116 DEVMETHOD(pcib_map_msi, pcib_map_msi), 117 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 118 DEVMETHOD(pcib_get_id, pcib_ari_get_id), 119 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 120 DEVMETHOD(pcib_ari_enabled, pcib_ari_enabled), 121 DEVMETHOD(pcib_decode_rid, pcib_ari_decode_rid), 122 123 DEVMETHOD_END 124}; 125 126static devclass_t pcib_devclass; 127 128DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 129DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 130 131#if defined(NEW_PCIB) || defined(PCI_HP) 132SYSCTL_DECL(_hw_pci); 133#endif 134 135#ifdef NEW_PCIB 136static int pci_clear_pcib; 137SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 138 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 139 140/* 141 * Is a resource from a child device sub-allocated from one of our 142 * resource managers? 143 */ 144static int 145pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 146{ 147 148 switch (type) { 149#ifdef PCI_RES_BUS 150 case PCI_RES_BUS: 151 return (rman_is_region_manager(r, &sc->bus.rman)); 152#endif 153 case SYS_RES_IOPORT: 154 return (rman_is_region_manager(r, &sc->io.rman)); 155 case SYS_RES_MEMORY: 156 /* Prefetchable resources may live in either memory rman. */ 157 if (rman_get_flags(r) & RF_PREFETCHABLE && 158 rman_is_region_manager(r, &sc->pmem.rman)) 159 return (1); 160 return (rman_is_region_manager(r, &sc->mem.rman)); 161 } 162 return (0); 163} 164 165static int 166pcib_is_window_open(struct pcib_window *pw) 167{ 168 169 return (pw->valid && pw->base < pw->limit); 170} 171 172/* 173 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 174 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 175 * when allocating the resource windows and rely on the PCI bus driver 176 * to do this for us. 177 */ 178static void 179pcib_activate_window(struct pcib_softc *sc, int type) 180{ 181 182 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 183} 184 185static void 186pcib_write_windows(struct pcib_softc *sc, int mask) 187{ 188 device_t dev; 189 uint32_t val; 190 191 dev = sc->dev; 192 if (sc->io.valid && mask & WIN_IO) { 193 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 194 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 195 pci_write_config(dev, PCIR_IOBASEH_1, 196 sc->io.base >> 16, 2); 197 pci_write_config(dev, PCIR_IOLIMITH_1, 198 sc->io.limit >> 16, 2); 199 } 200 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 201 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 202 } 203 204 if (mask & WIN_MEM) { 205 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 206 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 207 } 208 209 if (sc->pmem.valid && mask & WIN_PMEM) { 210 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 211 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 212 pci_write_config(dev, PCIR_PMBASEH_1, 213 sc->pmem.base >> 32, 4); 214 pci_write_config(dev, PCIR_PMLIMITH_1, 215 sc->pmem.limit >> 32, 4); 216 } 217 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 218 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 219 } 220} 221 222/* 223 * This is used to reject I/O port allocations that conflict with an 224 * ISA alias range. 225 */ 226static int 227pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end, 228 rman_res_t count) 229{ 230 rman_res_t next_alias; 231 232 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 233 return (0); 234 235 /* Only check fixed ranges for overlap. */ 236 if (start + count - 1 != end) 237 return (0); 238 239 /* ISA aliases are only in the lower 64KB of I/O space. */ 240 if (start >= 65536) 241 return (0); 242 243 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 244 if (start < 0x100) 245 goto alias; 246 247 /* 248 * If the start address is an alias, the range is an alias. 249 * Otherwise, compute the start of the next alias range and 250 * check if it is before the end of the candidate range. 251 */ 252 if ((start & 0x300) != 0) 253 goto alias; 254 next_alias = (start & ~0x3fful) | 0x100; 255 if (next_alias <= end) 256 goto alias; 257 return (0); 258 259alias: 260 if (bootverbose) 261 device_printf(sc->dev, 262 "I/O range %#jx-%#jx overlaps with an ISA alias\n", start, 263 end); 264 return (1); 265} 266 267static void 268pcib_add_window_resources(struct pcib_window *w, struct resource **res, 269 int count) 270{ 271 struct resource **newarray; 272 int error, i; 273 274 newarray = malloc(sizeof(struct resource *) * (w->count + count), 275 M_DEVBUF, M_WAITOK); 276 if (w->res != NULL) 277 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 278 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 279 free(w->res, M_DEVBUF); 280 w->res = newarray; 281 w->count += count; 282 283 for (i = 0; i < count; i++) { 284 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 285 rman_get_end(res[i])); 286 if (error) 287 panic("Failed to add resource to rman"); 288 } 289} 290 291typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg); 292 293static void 294pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb, 295 void *arg) 296{ 297 rman_res_t next_end; 298 299 /* 300 * If start is within an ISA alias range, move up to the start 301 * of the next non-alias range. As a special case, addresses 302 * in the range 0x000 - 0x0ff should also be skipped since 303 * those are used for various system I/O devices in ISA 304 * systems. 305 */ 306 if (start <= 65535) { 307 if (start < 0x100 || (start & 0x300) != 0) { 308 start &= ~0x3ff; 309 start += 0x400; 310 } 311 } 312 313 /* ISA aliases are only in the lower 64KB of I/O space. */ 314 while (start <= MIN(end, 65535)) { 315 next_end = MIN(start | 0xff, end); 316 cb(start, next_end, arg); 317 start += 0x400; 318 } 319 320 if (start <= end) 321 cb(start, end, arg); 322} 323 324static void 325count_ranges(rman_res_t start, rman_res_t end, void *arg) 326{ 327 int *countp; 328 329 countp = arg; 330 (*countp)++; 331} 332 333struct alloc_state { 334 struct resource **res; 335 struct pcib_softc *sc; 336 int count, error; 337}; 338 339static void 340alloc_ranges(rman_res_t start, rman_res_t end, void *arg) 341{ 342 struct alloc_state *as; 343 struct pcib_window *w; 344 int rid; 345 346 as = arg; 347 if (as->error != 0) 348 return; 349 350 w = &as->sc->io; 351 rid = w->reg; 352 if (bootverbose) 353 device_printf(as->sc->dev, 354 "allocating non-ISA range %#jx-%#jx\n", start, end); 355 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 356 &rid, start, end, end - start + 1, 0); 357 if (as->res[as->count] == NULL) 358 as->error = ENXIO; 359 else 360 as->count++; 361} 362 363static int 364pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end) 365{ 366 struct alloc_state as; 367 int i, new_count; 368 369 /* First, see how many ranges we need. */ 370 new_count = 0; 371 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 372 373 /* Second, allocate the ranges. */ 374 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 375 M_WAITOK); 376 as.sc = sc; 377 as.count = 0; 378 as.error = 0; 379 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 380 if (as.error != 0) { 381 for (i = 0; i < as.count; i++) 382 bus_release_resource(sc->dev, SYS_RES_IOPORT, 383 sc->io.reg, as.res[i]); 384 free(as.res, M_DEVBUF); 385 return (as.error); 386 } 387 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 388 389 /* Third, add the ranges to the window. */ 390 pcib_add_window_resources(&sc->io, as.res, as.count); 391 free(as.res, M_DEVBUF); 392 return (0); 393} 394 395static void 396pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 397 int flags, pci_addr_t max_address) 398{ 399 struct resource *res; 400 char buf[64]; 401 int error, rid; 402 403 if (max_address != (rman_res_t)max_address) 404 max_address = ~0; 405 w->rman.rm_start = 0; 406 w->rman.rm_end = max_address; 407 w->rman.rm_type = RMAN_ARRAY; 408 snprintf(buf, sizeof(buf), "%s %s window", 409 device_get_nameunit(sc->dev), w->name); 410 w->rman.rm_descr = strdup(buf, M_DEVBUF); 411 error = rman_init(&w->rman); 412 if (error) 413 panic("Failed to initialize %s %s rman", 414 device_get_nameunit(sc->dev), w->name); 415 416 if (!pcib_is_window_open(w)) 417 return; 418 419 if (w->base > max_address || w->limit > max_address) { 420 device_printf(sc->dev, 421 "initial %s window has too many bits, ignoring\n", w->name); 422 return; 423 } 424 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 425 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 426 else { 427 rid = w->reg; 428 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 429 w->limit - w->base + 1, flags); 430 if (res != NULL) 431 pcib_add_window_resources(w, &res, 1); 432 } 433 if (w->res == NULL) { 434 device_printf(sc->dev, 435 "failed to allocate initial %s window: %#jx-%#jx\n", 436 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 437 w->base = max_address; 438 w->limit = 0; 439 pcib_write_windows(sc, w->mask); 440 return; 441 } 442 pcib_activate_window(sc, type); 443} 444 445/* 446 * Initialize I/O windows. 447 */ 448static void 449pcib_probe_windows(struct pcib_softc *sc) 450{ 451 pci_addr_t max; 452 device_t dev; 453 uint32_t val; 454 455 dev = sc->dev; 456 457 if (pci_clear_pcib) { 458 pcib_bridge_init(dev); 459 } 460 461 /* Determine if the I/O port window is implemented. */ 462 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 463 if (val == 0) { 464 /* 465 * If 'val' is zero, then only 16-bits of I/O space 466 * are supported. 467 */ 468 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 469 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 470 sc->io.valid = 1; 471 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 472 } 473 } else 474 sc->io.valid = 1; 475 476 /* Read the existing I/O port window. */ 477 if (sc->io.valid) { 478 sc->io.reg = PCIR_IOBASEL_1; 479 sc->io.step = 12; 480 sc->io.mask = WIN_IO; 481 sc->io.name = "I/O port"; 482 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 483 sc->io.base = PCI_PPBIOBASE( 484 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 485 sc->io.limit = PCI_PPBIOLIMIT( 486 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 487 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 488 max = 0xffffffff; 489 } else { 490 sc->io.base = PCI_PPBIOBASE(0, val); 491 sc->io.limit = PCI_PPBIOLIMIT(0, 492 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 493 max = 0xffff; 494 } 495 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 496 } 497 498 /* Read the existing memory window. */ 499 sc->mem.valid = 1; 500 sc->mem.reg = PCIR_MEMBASE_1; 501 sc->mem.step = 20; 502 sc->mem.mask = WIN_MEM; 503 sc->mem.name = "memory"; 504 sc->mem.base = PCI_PPBMEMBASE(0, 505 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 506 sc->mem.limit = PCI_PPBMEMLIMIT(0, 507 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 508 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 509 510 /* Determine if the prefetchable memory window is implemented. */ 511 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 512 if (val == 0) { 513 /* 514 * If 'val' is zero, then only 32-bits of memory space 515 * are supported. 516 */ 517 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 518 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 519 sc->pmem.valid = 1; 520 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 521 } 522 } else 523 sc->pmem.valid = 1; 524 525 /* Read the existing prefetchable memory window. */ 526 if (sc->pmem.valid) { 527 sc->pmem.reg = PCIR_PMBASEL_1; 528 sc->pmem.step = 20; 529 sc->pmem.mask = WIN_PMEM; 530 sc->pmem.name = "prefetch"; 531 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 532 sc->pmem.base = PCI_PPBMEMBASE( 533 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 534 sc->pmem.limit = PCI_PPBMEMLIMIT( 535 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 536 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 537 max = 0xffffffffffffffff; 538 } else { 539 sc->pmem.base = PCI_PPBMEMBASE(0, val); 540 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 541 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 542 max = 0xffffffff; 543 } 544 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 545 RF_PREFETCHABLE, max); 546 } 547} 548 549static void 550pcib_release_window(struct pcib_softc *sc, struct pcib_window *w, int type) 551{ 552 device_t dev; 553 int error, i; 554 555 if (!w->valid) 556 return; 557 558 dev = sc->dev; 559 error = rman_fini(&w->rman); 560 if (error) { 561 device_printf(dev, "failed to release %s rman\n", w->name); 562 return; 563 } 564 free(__DECONST(char *, w->rman.rm_descr), M_DEVBUF); 565 566 for (i = 0; i < w->count; i++) { 567 error = bus_free_resource(dev, type, w->res[i]); 568 if (error) 569 device_printf(dev, 570 "failed to release %s resource: %d\n", w->name, 571 error); 572 } 573 free(w->res, M_DEVBUF); 574} 575 576static void 577pcib_free_windows(struct pcib_softc *sc) 578{ 579 580 pcib_release_window(sc, &sc->pmem, SYS_RES_MEMORY); 581 pcib_release_window(sc, &sc->mem, SYS_RES_MEMORY); 582 pcib_release_window(sc, &sc->io, SYS_RES_IOPORT); 583} 584 585#ifdef PCI_RES_BUS 586/* 587 * Allocate a suitable secondary bus for this bridge if needed and 588 * initialize the resource manager for the secondary bus range. Note 589 * that the minimum count is a desired value and this may allocate a 590 * smaller range. 591 */ 592void 593pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count) 594{ 595 char buf[64]; 596 int error, rid, sec_reg; 597 598 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) { 599 case PCIM_HDRTYPE_BRIDGE: 600 sec_reg = PCIR_SECBUS_1; 601 bus->sub_reg = PCIR_SUBBUS_1; 602 break; 603 case PCIM_HDRTYPE_CARDBUS: 604 sec_reg = PCIR_SECBUS_2; 605 bus->sub_reg = PCIR_SUBBUS_2; 606 break; 607 default: 608 panic("not a PCI bridge"); 609 } 610 bus->sec = pci_read_config(dev, sec_reg, 1); 611 bus->sub = pci_read_config(dev, bus->sub_reg, 1); 612 bus->dev = dev; 613 bus->rman.rm_start = 0; 614 bus->rman.rm_end = PCI_BUSMAX; 615 bus->rman.rm_type = RMAN_ARRAY; 616 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev)); 617 bus->rman.rm_descr = strdup(buf, M_DEVBUF); 618 error = rman_init(&bus->rman); 619 if (error) 620 panic("Failed to initialize %s bus number rman", 621 device_get_nameunit(dev)); 622 623 /* 624 * Allocate a bus range. This will return an existing bus range 625 * if one exists, or a new bus range if one does not. 626 */ 627 rid = 0; 628 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 629 min_count, 0); 630 if (bus->res == NULL) { 631 /* 632 * Fall back to just allocating a range of a single bus 633 * number. 634 */ 635 bus->res = bus_alloc_resource_anywhere(dev, PCI_RES_BUS, &rid, 636 1, 0); 637 } else if (rman_get_size(bus->res) < min_count) 638 /* 639 * Attempt to grow the existing range to satisfy the 640 * minimum desired count. 641 */ 642 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res, 643 rman_get_start(bus->res), rman_get_start(bus->res) + 644 min_count - 1); 645 646 /* 647 * Add the initial resource to the rman. 648 */ 649 if (bus->res != NULL) { 650 error = rman_manage_region(&bus->rman, rman_get_start(bus->res), 651 rman_get_end(bus->res)); 652 if (error) 653 panic("Failed to add resource to rman"); 654 bus->sec = rman_get_start(bus->res); 655 bus->sub = rman_get_end(bus->res); 656 } 657} 658 659void 660pcib_free_secbus(device_t dev, struct pcib_secbus *bus) 661{ 662 int error; 663 664 error = rman_fini(&bus->rman); 665 if (error) { 666 device_printf(dev, "failed to release bus number rman\n"); 667 return; 668 } 669 free(__DECONST(char *, bus->rman.rm_descr), M_DEVBUF); 670 671 error = bus_free_resource(dev, PCI_RES_BUS, bus->res); 672 if (error) 673 device_printf(dev, 674 "failed to release bus numbers resource: %d\n", error); 675} 676 677static struct resource * 678pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid, 679 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 680{ 681 struct resource *res; 682 683 res = rman_reserve_resource(&bus->rman, start, end, count, flags, 684 child); 685 if (res == NULL) 686 return (NULL); 687 688 if (bootverbose) 689 device_printf(bus->dev, 690 "allocated bus range (%ju-%ju) for rid %d of %s\n", 691 rman_get_start(res), rman_get_end(res), *rid, 692 pcib_child_name(child)); 693 rman_set_rid(res, *rid); 694 return (res); 695} 696 697/* 698 * Attempt to grow the secondary bus range. This is much simpler than 699 * for I/O windows as the range can only be grown by increasing 700 * subbus. 701 */ 702static int 703pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end) 704{ 705 rman_res_t old_end; 706 int error; 707 708 old_end = rman_get_end(bus->res); 709 KASSERT(new_end > old_end, ("attempt to shrink subbus")); 710 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res, 711 rman_get_start(bus->res), new_end); 712 if (error) 713 return (error); 714 if (bootverbose) 715 device_printf(bus->dev, "grew bus range to %ju-%ju\n", 716 rman_get_start(bus->res), rman_get_end(bus->res)); 717 error = rman_manage_region(&bus->rman, old_end + 1, 718 rman_get_end(bus->res)); 719 if (error) 720 panic("Failed to add resource to rman"); 721 bus->sub = rman_get_end(bus->res); 722 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1); 723 return (0); 724} 725 726struct resource * 727pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid, 728 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 729{ 730 struct resource *res; 731 rman_res_t start_free, end_free, new_end; 732 733 /* 734 * First, see if the request can be satisified by the existing 735 * bus range. 736 */ 737 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags); 738 if (res != NULL) 739 return (res); 740 741 /* 742 * Figure out a range to grow the bus range. First, find the 743 * first bus number after the last allocated bus in the rman and 744 * enforce that as a minimum starting point for the range. 745 */ 746 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 || 747 end_free != bus->sub) 748 start_free = bus->sub + 1; 749 if (start_free < start) 750 start_free = start; 751 new_end = start_free + count - 1; 752 753 /* 754 * See if this new range would satisfy the request if it 755 * succeeds. 756 */ 757 if (new_end > end) 758 return (NULL); 759 760 /* Finally, attempt to grow the existing resource. */ 761 if (bootverbose) { 762 device_printf(bus->dev, 763 "attempting to grow bus range for %ju buses\n", count); 764 printf("\tback candidate range: %ju-%ju\n", start_free, 765 new_end); 766 } 767 if (pcib_grow_subbus(bus, new_end) == 0) 768 return (pcib_suballoc_bus(bus, child, rid, start, end, count, 769 flags)); 770 return (NULL); 771} 772#endif 773 774#else 775 776/* 777 * Is the prefetch window open (eg, can we allocate memory in it?) 778 */ 779static int 780pcib_is_prefetch_open(struct pcib_softc *sc) 781{ 782 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 783} 784 785/* 786 * Is the nonprefetch window open (eg, can we allocate memory in it?) 787 */ 788static int 789pcib_is_nonprefetch_open(struct pcib_softc *sc) 790{ 791 return (sc->membase > 0 && sc->membase < sc->memlimit); 792} 793 794/* 795 * Is the io window open (eg, can we allocate ports in it?) 796 */ 797static int 798pcib_is_io_open(struct pcib_softc *sc) 799{ 800 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 801} 802 803/* 804 * Get current I/O decode. 805 */ 806static void 807pcib_get_io_decode(struct pcib_softc *sc) 808{ 809 device_t dev; 810 uint32_t iolow; 811 812 dev = sc->dev; 813 814 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 815 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 816 sc->iobase = PCI_PPBIOBASE( 817 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 818 else 819 sc->iobase = PCI_PPBIOBASE(0, iolow); 820 821 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 822 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 823 sc->iolimit = PCI_PPBIOLIMIT( 824 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 825 else 826 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 827} 828 829/* 830 * Get current memory decode. 831 */ 832static void 833pcib_get_mem_decode(struct pcib_softc *sc) 834{ 835 device_t dev; 836 pci_addr_t pmemlow; 837 838 dev = sc->dev; 839 840 sc->membase = PCI_PPBMEMBASE(0, 841 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 842 sc->memlimit = PCI_PPBMEMLIMIT(0, 843 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 844 845 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 846 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 847 sc->pmembase = PCI_PPBMEMBASE( 848 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 849 else 850 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 851 852 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 853 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 854 sc->pmemlimit = PCI_PPBMEMLIMIT( 855 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 856 else 857 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 858} 859 860/* 861 * Restore previous I/O decode. 862 */ 863static void 864pcib_set_io_decode(struct pcib_softc *sc) 865{ 866 device_t dev; 867 uint32_t iohi; 868 869 dev = sc->dev; 870 871 iohi = sc->iobase >> 16; 872 if (iohi > 0) 873 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 874 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 875 876 iohi = sc->iolimit >> 16; 877 if (iohi > 0) 878 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 879 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 880} 881 882/* 883 * Restore previous memory decode. 884 */ 885static void 886pcib_set_mem_decode(struct pcib_softc *sc) 887{ 888 device_t dev; 889 pci_addr_t pmemhi; 890 891 dev = sc->dev; 892 893 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 894 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 895 896 pmemhi = sc->pmembase >> 32; 897 if (pmemhi > 0) 898 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 899 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 900 901 pmemhi = sc->pmemlimit >> 32; 902 if (pmemhi > 0) 903 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 904 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 905} 906#endif 907 908#ifdef PCI_HP 909/* 910 * PCI-express HotPlug support. 911 */ 912static int pci_enable_pcie_hp = 1; 913SYSCTL_INT(_hw_pci, OID_AUTO, enable_pcie_hp, CTLFLAG_RDTUN, 914 &pci_enable_pcie_hp, 0, 915 "Enable support for native PCI-express HotPlug."); 916 917static void 918pcib_probe_hotplug(struct pcib_softc *sc) 919{ 920 device_t dev; 921 uint16_t link_sta, slot_sta; 922 923 if (!pci_enable_pcie_hp) 924 return; 925 926 dev = sc->dev; 927 if (pci_find_cap(dev, PCIY_EXPRESS, NULL) != 0) 928 return; 929 930 if (!(pcie_read_config(dev, PCIER_FLAGS, 2) & PCIEM_FLAGS_SLOT)) 931 return; 932 933 sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4); 934 sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4); 935 936 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0) 937 return; 938 if ((sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) == 0) 939 return; 940 941 /* 942 * Some devices report that they have an MRL when they actually 943 * do not. Since they always report that the MRL is open, child 944 * devices would be ignored. Try to detect these devices and 945 * ignore their claim of HotPlug support. 946 * 947 * If there is an open MRL but the Data Link Layer is active, 948 * the MRL is not real. 949 */ 950 if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) != 0 && 951 (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) != 0) { 952 link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 953 slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 954 if ((slot_sta & PCIEM_SLOT_STA_MRLSS) != 0 && 955 (link_sta & PCIEM_LINK_STA_DL_ACTIVE) != 0) { 956 return; 957 } 958 } 959 960 sc->flags |= PCIB_HOTPLUG; 961} 962 963/* 964 * Send a HotPlug command to the slot control register. If this slot 965 * uses command completion interrupts and a previous command is still 966 * in progress, then the command is dropped. Once the previous 967 * command completes or times out, pcib_pcie_hotplug_update() will be 968 * invoked to post a new command based on the slot's state at that 969 * time. 970 */ 971static void 972pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) 973{ 974 device_t dev; 975 uint16_t ctl, new; 976 977 dev = sc->dev; 978 979 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) 980 return; 981 982 ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2); 983 new = (ctl & ~mask) | val; 984 if (new == ctl) 985 return; 986 if (bootverbose) 987 device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new); 988 pcie_write_config(dev, PCIER_SLOT_CTL, new, 2); 989 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) && 990 (ctl & new) & PCIEM_SLOT_CTL_CCIE) { 991 sc->flags |= PCIB_HOTPLUG_CMD_PENDING; 992 if (!cold) 993 callout_reset(&sc->pcie_cc_timer, hz, 994 pcib_pcie_cc_timeout, sc); 995 } 996} 997 998static void 999pcib_pcie_hotplug_command_completed(struct pcib_softc *sc) 1000{ 1001 device_t dev; 1002 1003 dev = sc->dev; 1004 1005 if (bootverbose) 1006 device_printf(dev, "Command Completed\n"); 1007 if (!(sc->flags & PCIB_HOTPLUG_CMD_PENDING)) 1008 return; 1009 callout_stop(&sc->pcie_cc_timer); 1010 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1011 wakeup(sc); 1012} 1013 1014/* 1015 * Returns true if a card is fully inserted from the user's 1016 * perspective. It may not yet be ready for access, but the driver 1017 * can now start enabling access if necessary. 1018 */ 1019static bool 1020pcib_hotplug_inserted(struct pcib_softc *sc) 1021{ 1022 1023 /* Pretend the card isn't present if a detach is forced. */ 1024 if (sc->flags & PCIB_DETACHING) 1025 return (false); 1026 1027 /* Card must be present in the slot. */ 1028 if ((sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS) == 0) 1029 return (false); 1030 1031 /* A power fault implicitly turns off power to the slot. */ 1032 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1033 return (false); 1034 1035 /* If the MRL is disengaged, the slot is powered off. */ 1036 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP && 1037 (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS) != 0) 1038 return (false); 1039 1040 return (true); 1041} 1042 1043/* 1044 * Returns -1 if the card is fully inserted, powered, and ready for 1045 * access. Otherwise, returns 0. 1046 */ 1047static int 1048pcib_hotplug_present(struct pcib_softc *sc) 1049{ 1050 1051 /* Card must be inserted. */ 1052 if (!pcib_hotplug_inserted(sc)) 1053 return (0); 1054 1055 /* 1056 * Require the Electromechanical Interlock to be engaged if 1057 * present. 1058 */ 1059 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP && 1060 (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) == 0) 1061 return (0); 1062 1063 /* Require the Data Link Layer to be active. */ 1064 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1065 if (!(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE)) 1066 return (0); 1067 } 1068 1069 return (-1); 1070} 1071 1072static void 1073pcib_pcie_hotplug_update(struct pcib_softc *sc, uint16_t val, uint16_t mask, 1074 bool schedule_task) 1075{ 1076 bool card_inserted, ei_engaged; 1077 1078 /* Clear DETACHING if Presence Detect has cleared. */ 1079 if ((sc->pcie_slot_sta & (PCIEM_SLOT_STA_PDC | PCIEM_SLOT_STA_PDS)) == 1080 PCIEM_SLOT_STA_PDC) 1081 sc->flags &= ~PCIB_DETACHING; 1082 1083 card_inserted = pcib_hotplug_inserted(sc); 1084 1085 /* Turn the power indicator on if a card is inserted. */ 1086 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PIP) { 1087 mask |= PCIEM_SLOT_CTL_PIC; 1088 if (card_inserted) 1089 val |= PCIEM_SLOT_CTL_PI_ON; 1090 else if (sc->flags & PCIB_DETACH_PENDING) 1091 val |= PCIEM_SLOT_CTL_PI_BLINK; 1092 else 1093 val |= PCIEM_SLOT_CTL_PI_OFF; 1094 } 1095 1096 /* Turn the power on via the Power Controller if a card is inserted. */ 1097 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) { 1098 mask |= PCIEM_SLOT_CTL_PCC; 1099 if (card_inserted) 1100 val |= PCIEM_SLOT_CTL_PC_ON; 1101 else 1102 val |= PCIEM_SLOT_CTL_PC_OFF; 1103 } 1104 1105 /* 1106 * If a card is inserted, enable the Electromechanical 1107 * Interlock. If a card is not inserted (or we are in the 1108 * process of detaching), disable the Electromechanical 1109 * Interlock. 1110 */ 1111 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_EIP) { 1112 mask |= PCIEM_SLOT_CTL_EIC; 1113 ei_engaged = (sc->pcie_slot_sta & PCIEM_SLOT_STA_EIS) != 0; 1114 if (card_inserted != ei_engaged) 1115 val |= PCIEM_SLOT_CTL_EIC; 1116 } 1117 1118 /* 1119 * Start a timer to see if the Data Link Layer times out. 1120 * Note that we only start the timer if Presence Detect or MRL Sensor 1121 * changed on this interrupt. Stop any scheduled timer if 1122 * the Data Link Layer is active. 1123 */ 1124 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) { 1125 if (card_inserted && 1126 !(sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) && 1127 sc->pcie_slot_sta & 1128 (PCIEM_SLOT_STA_MRLSC | PCIEM_SLOT_STA_PDC)) { 1129 if (cold) 1130 device_printf(sc->dev, 1131 "Data Link Layer inactive\n"); 1132 else 1133 callout_reset(&sc->pcie_dll_timer, hz, 1134 pcib_pcie_dll_timeout, sc); 1135 } else if (sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE) 1136 callout_stop(&sc->pcie_dll_timer); 1137 } 1138 1139 pcib_pcie_hotplug_command(sc, val, mask); 1140 1141 /* 1142 * During attach the child "pci" device is added synchronously; 1143 * otherwise, the task is scheduled to manage the child 1144 * device. 1145 */ 1146 if (schedule_task && 1147 (pcib_hotplug_present(sc) != 0) != (sc->child != NULL)) 1148 taskqueue_enqueue(taskqueue_thread, &sc->pcie_hp_task); 1149} 1150 1151static void 1152pcib_pcie_intr(void *arg) 1153{ 1154 struct pcib_softc *sc; 1155 device_t dev; 1156 1157 sc = arg; 1158 dev = sc->dev; 1159 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1160 1161 /* Clear the events just reported. */ 1162 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1163 1164 if (bootverbose) 1165 device_printf(dev, "HotPlug interrupt: %#x\n", 1166 sc->pcie_slot_sta); 1167 1168 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_ABP) { 1169 if (sc->flags & PCIB_DETACH_PENDING) { 1170 device_printf(dev, 1171 "Attention Button Pressed: Detach Cancelled\n"); 1172 sc->flags &= ~PCIB_DETACH_PENDING; 1173 callout_stop(&sc->pcie_ab_timer); 1174 } else { 1175 device_printf(dev, 1176 "Attention Button Pressed: Detaching in 5 seconds\n"); 1177 sc->flags |= PCIB_DETACH_PENDING; 1178 callout_reset(&sc->pcie_ab_timer, 5 * hz, 1179 pcib_pcie_ab_timeout, sc); 1180 } 1181 } 1182 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_PFD) 1183 device_printf(dev, "Power Fault Detected\n"); 1184 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSC) 1185 device_printf(dev, "MRL Sensor Changed to %s\n", 1186 sc->pcie_slot_sta & PCIEM_SLOT_STA_MRLSS ? "open" : 1187 "closed"); 1188 if (bootverbose && sc->pcie_slot_sta & PCIEM_SLOT_STA_PDC) 1189 device_printf(dev, "Presence Detect Changed to %s\n", 1190 sc->pcie_slot_sta & PCIEM_SLOT_STA_PDS ? "card present" : 1191 "empty"); 1192 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_CC) 1193 pcib_pcie_hotplug_command_completed(sc); 1194 if (sc->pcie_slot_sta & PCIEM_SLOT_STA_DLLSC) { 1195 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1196 if (bootverbose) 1197 device_printf(dev, 1198 "Data Link Layer State Changed to %s\n", 1199 sc->pcie_link_sta & PCIEM_LINK_STA_DL_ACTIVE ? 1200 "active" : "inactive"); 1201 } 1202 1203 pcib_pcie_hotplug_update(sc, 0, 0, true); 1204} 1205 1206static void 1207pcib_pcie_hotplug_task(void *context, int pending) 1208{ 1209 struct pcib_softc *sc; 1210 device_t dev; 1211 1212 sc = context; 1213 mtx_lock(&Giant); 1214 dev = sc->dev; 1215 if (pcib_hotplug_present(sc) != 0) { 1216 if (sc->child == NULL) { 1217 sc->child = device_add_child(dev, "pci", -1); 1218 bus_generic_attach(dev); 1219 } 1220 } else { 1221 if (sc->child != NULL) { 1222 if (device_delete_child(dev, sc->child) == 0) 1223 sc->child = NULL; 1224 } 1225 } 1226 mtx_unlock(&Giant); 1227} 1228 1229static void 1230pcib_pcie_ab_timeout(void *arg) 1231{ 1232 struct pcib_softc *sc; 1233 device_t dev; 1234 1235 sc = arg; 1236 dev = sc->dev; 1237 mtx_assert(&Giant, MA_OWNED); 1238 if (sc->flags & PCIB_DETACH_PENDING) { 1239 sc->flags |= PCIB_DETACHING; 1240 sc->flags &= ~PCIB_DETACH_PENDING; 1241 pcib_pcie_hotplug_update(sc, 0, 0, true); 1242 } 1243} 1244 1245static void 1246pcib_pcie_cc_timeout(void *arg) 1247{ 1248 struct pcib_softc *sc; 1249 device_t dev; 1250 uint16_t sta; 1251 1252 sc = arg; 1253 dev = sc->dev; 1254 mtx_assert(&Giant, MA_OWNED); 1255 sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1256 if (!(sta & PCIEM_SLOT_STA_CC)) { 1257 device_printf(dev, 1258 "HotPlug Command Timed Out - forcing detach\n"); 1259 sc->flags &= ~(PCIB_HOTPLUG_CMD_PENDING | PCIB_DETACH_PENDING); 1260 sc->flags |= PCIB_DETACHING; 1261 pcib_pcie_hotplug_update(sc, 0, 0, true); 1262 } else { 1263 device_printf(dev, 1264 "Missed HotPlug interrupt waiting for Command Completion\n"); 1265 pcib_pcie_intr(sc); 1266 } 1267} 1268 1269static void 1270pcib_pcie_dll_timeout(void *arg) 1271{ 1272 struct pcib_softc *sc; 1273 device_t dev; 1274 uint16_t sta; 1275 1276 sc = arg; 1277 dev = sc->dev; 1278 mtx_assert(&Giant, MA_OWNED); 1279 sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1280 if (!(sta & PCIEM_LINK_STA_DL_ACTIVE)) { 1281 device_printf(dev, 1282 "Timed out waiting for Data Link Layer Active\n"); 1283 sc->flags |= PCIB_DETACHING; 1284 pcib_pcie_hotplug_update(sc, 0, 0, true); 1285 } else if (sta != sc->pcie_link_sta) { 1286 device_printf(dev, 1287 "Missed HotPlug interrupt waiting for DLL Active\n"); 1288 pcib_pcie_intr(sc); 1289 } 1290} 1291 1292static int 1293pcib_alloc_pcie_irq(struct pcib_softc *sc) 1294{ 1295 device_t dev; 1296 int count, error, rid; 1297 1298 rid = -1; 1299 dev = sc->dev; 1300 1301 /* 1302 * For simplicity, only use MSI-X if there is a single message. 1303 * To support a device with multiple messages we would have to 1304 * use remap intr if the MSI number is not 0. 1305 */ 1306 count = pci_msix_count(dev); 1307 if (count == 1) { 1308 error = pci_alloc_msix(dev, &count); 1309 if (error == 0) 1310 rid = 1; 1311 } 1312 1313 if (rid < 0 && pci_msi_count(dev) > 0) { 1314 count = 1; 1315 error = pci_alloc_msi(dev, &count); 1316 if (error == 0) 1317 rid = 1; 1318 } 1319 1320 if (rid < 0) 1321 rid = 0; 1322 1323 sc->pcie_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1324 RF_ACTIVE); 1325 if (sc->pcie_irq == NULL) { 1326 device_printf(dev, 1327 "Failed to allocate interrupt for PCI-e events\n"); 1328 if (rid > 0) 1329 pci_release_msi(dev); 1330 return (ENXIO); 1331 } 1332 1333 error = bus_setup_intr(dev, sc->pcie_irq, INTR_TYPE_MISC, 1334 NULL, pcib_pcie_intr, sc, &sc->pcie_ihand); 1335 if (error) { 1336 device_printf(dev, "Failed to setup PCI-e interrupt handler\n"); 1337 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->pcie_irq); 1338 if (rid > 0) 1339 pci_release_msi(dev); 1340 return (error); 1341 } 1342 return (0); 1343} 1344 1345static int 1346pcib_release_pcie_irq(struct pcib_softc *sc) 1347{ 1348 device_t dev; 1349 int error; 1350 1351 dev = sc->dev; 1352 error = bus_teardown_intr(dev, sc->pcie_irq, sc->pcie_ihand); 1353 if (error) 1354 return (error); 1355 error = bus_free_resource(dev, SYS_RES_IRQ, sc->pcie_irq); 1356 if (error) 1357 return (error); 1358 return (pci_release_msi(dev)); 1359} 1360 1361static void 1362pcib_setup_hotplug(struct pcib_softc *sc) 1363{ 1364 device_t dev; 1365 uint16_t mask, val; 1366 1367 dev = sc->dev; 1368 callout_init(&sc->pcie_ab_timer, 0); 1369 callout_init(&sc->pcie_cc_timer, 0); 1370 callout_init(&sc->pcie_dll_timer, 0); 1371 TASK_INIT(&sc->pcie_hp_task, 0, pcib_pcie_hotplug_task, sc); 1372 1373 /* Allocate IRQ. */ 1374 if (pcib_alloc_pcie_irq(sc) != 0) 1375 return; 1376 1377 sc->pcie_link_sta = pcie_read_config(dev, PCIER_LINK_STA, 2); 1378 sc->pcie_slot_sta = pcie_read_config(dev, PCIER_SLOT_STA, 2); 1379 1380 /* Clear any events previously pending. */ 1381 pcie_write_config(dev, PCIER_SLOT_STA, sc->pcie_slot_sta, 2); 1382 1383 /* Enable HotPlug events. */ 1384 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1385 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1386 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1387 val = PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_HPIE; 1388 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_APB) 1389 val |= PCIEM_SLOT_CTL_ABPE; 1390 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_PCP) 1391 val |= PCIEM_SLOT_CTL_PFDE; 1392 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_MRLSP) 1393 val |= PCIEM_SLOT_CTL_MRLSCE; 1394 if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS)) 1395 val |= PCIEM_SLOT_CTL_CCIE; 1396 if (sc->pcie_link_cap & PCIEM_LINK_CAP_DL_ACTIVE) 1397 val |= PCIEM_SLOT_CTL_DLLSCE; 1398 1399 /* Turn the attention indicator off. */ 1400 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1401 mask |= PCIEM_SLOT_CTL_AIC; 1402 val |= PCIEM_SLOT_CTL_AI_OFF; 1403 } 1404 1405 pcib_pcie_hotplug_update(sc, val, mask, false); 1406} 1407 1408static int 1409pcib_detach_hotplug(struct pcib_softc *sc) 1410{ 1411 uint16_t mask, val; 1412 int error; 1413 1414 /* Disable the card in the slot and force it to detach. */ 1415 if (sc->flags & PCIB_DETACH_PENDING) { 1416 sc->flags &= ~PCIB_DETACH_PENDING; 1417 callout_stop(&sc->pcie_ab_timer); 1418 } 1419 sc->flags |= PCIB_DETACHING; 1420 1421 if (sc->flags & PCIB_HOTPLUG_CMD_PENDING) { 1422 callout_stop(&sc->pcie_cc_timer); 1423 tsleep(sc, 0, "hpcmd", hz); 1424 sc->flags &= ~PCIB_HOTPLUG_CMD_PENDING; 1425 } 1426 1427 /* Disable HotPlug events. */ 1428 mask = PCIEM_SLOT_CTL_DLLSCE | PCIEM_SLOT_CTL_HPIE | 1429 PCIEM_SLOT_CTL_CCIE | PCIEM_SLOT_CTL_PDCE | PCIEM_SLOT_CTL_MRLSCE | 1430 PCIEM_SLOT_CTL_PFDE | PCIEM_SLOT_CTL_ABPE; 1431 val = 0; 1432 1433 /* Turn the attention indicator off. */ 1434 if (sc->pcie_slot_cap & PCIEM_SLOT_CAP_AIP) { 1435 mask |= PCIEM_SLOT_CTL_AIC; 1436 val |= PCIEM_SLOT_CTL_AI_OFF; 1437 } 1438 1439 pcib_pcie_hotplug_update(sc, val, mask, false); 1440 1441 error = pcib_release_pcie_irq(sc); 1442 if (error) 1443 return (error); 1444 taskqueue_drain(taskqueue_thread, &sc->pcie_hp_task); 1445 callout_drain(&sc->pcie_ab_timer); 1446 callout_drain(&sc->pcie_cc_timer); 1447 callout_drain(&sc->pcie_dll_timer); 1448 return (0); 1449} 1450#endif 1451 1452/* 1453 * Get current bridge configuration. 1454 */ 1455static void 1456pcib_cfg_save(struct pcib_softc *sc) 1457{ 1458#ifndef NEW_PCIB 1459 device_t dev; 1460 uint16_t command; 1461 1462 dev = sc->dev; 1463 1464 command = pci_read_config(dev, PCIR_COMMAND, 2); 1465 if (command & PCIM_CMD_PORTEN) 1466 pcib_get_io_decode(sc); 1467 if (command & PCIM_CMD_MEMEN) 1468 pcib_get_mem_decode(sc); 1469#endif 1470} 1471 1472/* 1473 * Restore previous bridge configuration. 1474 */ 1475static void 1476pcib_cfg_restore(struct pcib_softc *sc) 1477{ 1478 device_t dev; 1479#ifndef NEW_PCIB 1480 uint16_t command; 1481#endif 1482 dev = sc->dev; 1483 1484#ifdef NEW_PCIB 1485 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 1486#else 1487 command = pci_read_config(dev, PCIR_COMMAND, 2); 1488 if (command & PCIM_CMD_PORTEN) 1489 pcib_set_io_decode(sc); 1490 if (command & PCIM_CMD_MEMEN) 1491 pcib_set_mem_decode(sc); 1492#endif 1493} 1494 1495/* 1496 * Generic device interface 1497 */ 1498static int 1499pcib_probe(device_t dev) 1500{ 1501 if ((pci_get_class(dev) == PCIC_BRIDGE) && 1502 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 1503 device_set_desc(dev, "PCI-PCI bridge"); 1504 return(-10000); 1505 } 1506 return(ENXIO); 1507} 1508 1509void 1510pcib_attach_common(device_t dev) 1511{ 1512 struct pcib_softc *sc; 1513 struct sysctl_ctx_list *sctx; 1514 struct sysctl_oid *soid; 1515 int comma; 1516 1517 sc = device_get_softc(dev); 1518 sc->dev = dev; 1519 1520 /* 1521 * Get current bridge configuration. 1522 */ 1523 sc->domain = pci_get_domain(dev); 1524#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1525 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1); 1526 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1527#endif 1528 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 1529 pcib_cfg_save(sc); 1530 1531 /* 1532 * The primary bus register should always be the bus of the 1533 * parent. 1534 */ 1535 sc->pribus = pci_get_bus(dev); 1536 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 1537 1538 /* 1539 * Setup sysctl reporting nodes 1540 */ 1541 sctx = device_get_sysctl_ctx(dev); 1542 soid = device_get_sysctl_tree(dev); 1543 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 1544 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 1545 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 1546 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 1547 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 1548 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 1549 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 1550 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 1551 1552 /* 1553 * Quirk handling. 1554 */ 1555 switch (pci_get_devid(dev)) { 1556#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1557 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 1558 { 1559 uint8_t supbus; 1560 1561 supbus = pci_read_config(dev, 0x41, 1); 1562 if (supbus != 0xff) { 1563 sc->bus.sec = supbus + 1; 1564 sc->bus.sub = supbus + 1; 1565 } 1566 break; 1567 } 1568#endif 1569 1570 /* 1571 * The i82380FB mobile docking controller is a PCI-PCI bridge, 1572 * and it is a subtractive bridge. However, the ProgIf is wrong 1573 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 1574 * happen. There are also Toshiba and Cavium ThunderX bridges 1575 * that behave this way. 1576 */ 1577 case 0xa002177d: /* Cavium ThunderX */ 1578 case 0x124b8086: /* Intel 82380FB Mobile */ 1579 case 0x060513d7: /* Toshiba ???? */ 1580 sc->flags |= PCIB_SUBTRACTIVE; 1581 break; 1582 1583#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 1584 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 1585 case 0x00dd10de: 1586 { 1587 char *cp; 1588 1589 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 1590 break; 1591 if (strncmp(cp, "Compal", 6) != 0) { 1592 freeenv(cp); 1593 break; 1594 } 1595 freeenv(cp); 1596 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 1597 break; 1598 if (strncmp(cp, "08A0", 4) != 0) { 1599 freeenv(cp); 1600 break; 1601 } 1602 freeenv(cp); 1603 if (sc->bus.sub < 0xa) { 1604 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 1605 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1); 1606 } 1607 break; 1608 } 1609#endif 1610 } 1611 1612 if (pci_msi_device_blacklisted(dev)) 1613 sc->flags |= PCIB_DISABLE_MSI; 1614 1615 if (pci_msix_device_blacklisted(dev)) 1616 sc->flags |= PCIB_DISABLE_MSIX; 1617 1618 /* 1619 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 1620 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 1621 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 1622 * This means they act as if they were subtractively decoding 1623 * bridges and pass all transactions. Mark them and real ProgIf 1 1624 * parts as subtractive. 1625 */ 1626 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 1627 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 1628 sc->flags |= PCIB_SUBTRACTIVE; 1629 1630#ifdef PCI_HP 1631 pcib_probe_hotplug(sc); 1632#endif 1633#ifdef NEW_PCIB 1634#ifdef PCI_RES_BUS 1635 pcib_setup_secbus(dev, &sc->bus, 1); 1636#endif 1637 pcib_probe_windows(sc); 1638#endif 1639#ifdef PCI_HP 1640 if (sc->flags & PCIB_HOTPLUG) 1641 pcib_setup_hotplug(sc); 1642#endif 1643 if (bootverbose) { 1644 device_printf(dev, " domain %d\n", sc->domain); 1645 device_printf(dev, " secondary bus %d\n", sc->bus.sec); 1646 device_printf(dev, " subordinate bus %d\n", sc->bus.sub); 1647#ifdef NEW_PCIB 1648 if (pcib_is_window_open(&sc->io)) 1649 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 1650 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 1651 if (pcib_is_window_open(&sc->mem)) 1652 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1653 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 1654 if (pcib_is_window_open(&sc->pmem)) 1655 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1656 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 1657#else 1658 if (pcib_is_io_open(sc)) 1659 device_printf(dev, " I/O decode 0x%x-0x%x\n", 1660 sc->iobase, sc->iolimit); 1661 if (pcib_is_nonprefetch_open(sc)) 1662 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 1663 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 1664 if (pcib_is_prefetch_open(sc)) 1665 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 1666 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1667#endif 1668 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 1669 sc->flags & PCIB_SUBTRACTIVE) { 1670 device_printf(dev, " special decode "); 1671 comma = 0; 1672 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 1673 printf("ISA"); 1674 comma = 1; 1675 } 1676 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 1677 printf("%sVGA", comma ? ", " : ""); 1678 comma = 1; 1679 } 1680 if (sc->flags & PCIB_SUBTRACTIVE) 1681 printf("%ssubtractive", comma ? ", " : ""); 1682 printf("\n"); 1683 } 1684 } 1685 1686 /* 1687 * Always enable busmastering on bridges so that transactions 1688 * initiated on the secondary bus are passed through to the 1689 * primary bus. 1690 */ 1691 pci_enable_busmaster(dev); 1692} 1693 1694#ifdef PCI_HP 1695static int 1696pcib_present(struct pcib_softc *sc) 1697{ 1698 1699 if (sc->flags & PCIB_HOTPLUG) 1700 return (pcib_hotplug_present(sc) != 0); 1701 return (1); 1702} 1703#endif 1704 1705int 1706pcib_attach_child(device_t dev) 1707{ 1708 struct pcib_softc *sc; 1709 1710 sc = device_get_softc(dev); 1711 if (sc->bus.sec == 0) { 1712 /* no secondary bus; we should have fixed this */ 1713 return(0); 1714 } 1715 1716#ifdef PCI_HP 1717 if (!pcib_present(sc)) { 1718 /* An empty HotPlug slot, so don't add a PCI bus yet. */ 1719 return (0); 1720 } 1721#endif 1722 1723 sc->child = device_add_child(dev, "pci", -1); 1724 return (bus_generic_attach(dev)); 1725} 1726 1727int 1728pcib_attach(device_t dev) 1729{ 1730 1731 pcib_attach_common(dev); 1732 return (pcib_attach_child(dev)); 1733} 1734 1735int 1736pcib_detach(device_t dev) 1737{ 1738#if defined(PCI_HP) || defined(NEW_PCIB) 1739 struct pcib_softc *sc; 1740#endif 1741 int error; 1742 1743#if defined(PCI_HP) || defined(NEW_PCIB) 1744 sc = device_get_softc(dev); 1745#endif 1746 error = bus_generic_detach(dev); 1747 if (error) 1748 return (error); 1749#ifdef PCI_HP 1750 if (sc->flags & PCIB_HOTPLUG) { 1751 error = pcib_detach_hotplug(sc); 1752 if (error) 1753 return (error); 1754 } 1755#endif 1756 error = device_delete_children(dev); 1757 if (error) 1758 return (error); 1759#ifdef NEW_PCIB 1760 pcib_free_windows(sc); 1761#ifdef PCI_RES_BUS 1762 pcib_free_secbus(dev, &sc->bus); 1763#endif 1764#endif 1765 return (0); 1766} 1767 1768int 1769pcib_suspend(device_t dev) 1770{ 1771 1772 pcib_cfg_save(device_get_softc(dev)); 1773 return (bus_generic_suspend(dev)); 1774} 1775 1776int 1777pcib_resume(device_t dev) 1778{ 1779 1780 pcib_cfg_restore(device_get_softc(dev)); 1781 return (bus_generic_resume(dev)); 1782} 1783 1784void 1785pcib_bridge_init(device_t dev) 1786{ 1787 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 1788 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 1789 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 1790 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 1791 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 1792 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 1793 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 1794 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 1795 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 1796 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 1797} 1798 1799int 1800pcib_child_present(device_t dev, device_t child) 1801{ 1802#ifdef PCI_HP 1803 struct pcib_softc *sc = device_get_softc(dev); 1804 int retval; 1805 1806 retval = bus_child_present(dev); 1807 if (retval != 0 && sc->flags & PCIB_HOTPLUG) 1808 retval = pcib_hotplug_present(sc); 1809 return (retval); 1810#else 1811 return (bus_child_present(dev)); 1812#endif 1813} 1814 1815int 1816pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1817{ 1818 struct pcib_softc *sc = device_get_softc(dev); 1819 1820 switch (which) { 1821 case PCIB_IVAR_DOMAIN: 1822 *result = sc->domain; 1823 return(0); 1824 case PCIB_IVAR_BUS: 1825 *result = sc->bus.sec; 1826 return(0); 1827 } 1828 return(ENOENT); 1829} 1830 1831int 1832pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1833{ 1834 1835 switch (which) { 1836 case PCIB_IVAR_DOMAIN: 1837 return(EINVAL); 1838 case PCIB_IVAR_BUS: 1839 return(EINVAL); 1840 } 1841 return(ENOENT); 1842} 1843 1844#ifdef NEW_PCIB 1845/* 1846 * Attempt to allocate a resource from the existing resources assigned 1847 * to a window. 1848 */ 1849static struct resource * 1850pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 1851 device_t child, int type, int *rid, rman_res_t start, rman_res_t end, 1852 rman_res_t count, u_int flags) 1853{ 1854 struct resource *res; 1855 1856 if (!pcib_is_window_open(w)) 1857 return (NULL); 1858 1859 res = rman_reserve_resource(&w->rman, start, end, count, 1860 flags & ~RF_ACTIVE, child); 1861 if (res == NULL) 1862 return (NULL); 1863 1864 if (bootverbose) 1865 device_printf(sc->dev, 1866 "allocated %s range (%#jx-%#jx) for rid %x of %s\n", 1867 w->name, rman_get_start(res), rman_get_end(res), *rid, 1868 pcib_child_name(child)); 1869 rman_set_rid(res, *rid); 1870 1871 /* 1872 * If the resource should be active, pass that request up the 1873 * tree. This assumes the parent drivers can handle 1874 * activating sub-allocated resources. 1875 */ 1876 if (flags & RF_ACTIVE) { 1877 if (bus_activate_resource(child, type, *rid, res) != 0) { 1878 rman_release_resource(res); 1879 return (NULL); 1880 } 1881 } 1882 1883 return (res); 1884} 1885 1886/* Allocate a fresh resource range for an unconfigured window. */ 1887static int 1888pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1889 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1890{ 1891 struct resource *res; 1892 rman_res_t base, limit, wmask; 1893 int rid; 1894 1895 /* 1896 * If this is an I/O window on a bridge with ISA enable set 1897 * and the start address is below 64k, then try to allocate an 1898 * initial window of 0x1000 bytes long starting at address 1899 * 0xf000 and walking down. Note that if the original request 1900 * was larger than the non-aliased range size of 0x100 our 1901 * caller would have raised the start address up to 64k 1902 * already. 1903 */ 1904 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1905 start < 65536) { 1906 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1907 limit = base + 0xfff; 1908 1909 /* 1910 * Skip ranges that wouldn't work for the 1911 * original request. Note that the actual 1912 * window that overlaps are the non-alias 1913 * ranges within [base, limit], so this isn't 1914 * quite a simple comparison. 1915 */ 1916 if (start + count > limit - 0x400) 1917 continue; 1918 if (base == 0) { 1919 /* 1920 * The first open region for the window at 1921 * 0 is 0x400-0x4ff. 1922 */ 1923 if (end - count + 1 < 0x400) 1924 continue; 1925 } else { 1926 if (end - count + 1 < base) 1927 continue; 1928 } 1929 1930 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1931 w->base = base; 1932 w->limit = limit; 1933 return (0); 1934 } 1935 } 1936 return (ENOSPC); 1937 } 1938 1939 wmask = ((rman_res_t)1 << w->step) - 1; 1940 if (RF_ALIGNMENT(flags) < w->step) { 1941 flags &= ~RF_ALIGNMENT_MASK; 1942 flags |= RF_ALIGNMENT_LOG2(w->step); 1943 } 1944 start &= ~wmask; 1945 end |= wmask; 1946 count = roundup2(count, (rman_res_t)1 << w->step); 1947 rid = w->reg; 1948 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1949 flags & ~RF_ACTIVE); 1950 if (res == NULL) 1951 return (ENOSPC); 1952 pcib_add_window_resources(w, &res, 1); 1953 pcib_activate_window(sc, type); 1954 w->base = rman_get_start(res); 1955 w->limit = rman_get_end(res); 1956 return (0); 1957} 1958 1959/* Try to expand an existing window to the requested base and limit. */ 1960static int 1961pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1962 rman_res_t base, rman_res_t limit) 1963{ 1964 struct resource *res; 1965 int error, i, force_64k_base; 1966 1967 KASSERT(base <= w->base && limit >= w->limit, 1968 ("attempting to shrink window")); 1969 1970 /* 1971 * XXX: pcib_grow_window() doesn't try to do this anyway and 1972 * the error handling for all the edge cases would be tedious. 1973 */ 1974 KASSERT(limit == w->limit || base == w->base, 1975 ("attempting to grow both ends of a window")); 1976 1977 /* 1978 * Yet more special handling for requests to expand an I/O 1979 * window behind an ISA-enabled bridge. Since I/O windows 1980 * have to grow in 0x1000 increments and the end of the 0xffff 1981 * range is an alias, growing a window below 64k will always 1982 * result in allocating new resources and never adjusting an 1983 * existing resource. 1984 */ 1985 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1986 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1987 KASSERT(limit == w->limit || limit <= 65535, 1988 ("attempting to grow both ends across 64k ISA alias")); 1989 1990 if (base != w->base) 1991 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1992 else 1993 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1994 limit); 1995 if (error == 0) { 1996 w->base = base; 1997 w->limit = limit; 1998 } 1999 return (error); 2000 } 2001 2002 /* 2003 * Find the existing resource to adjust. Usually there is only one, 2004 * but for an ISA-enabled bridge we might be growing the I/O window 2005 * above 64k and need to find the existing resource that maps all 2006 * of the area above 64k. 2007 */ 2008 for (i = 0; i < w->count; i++) { 2009 if (rman_get_end(w->res[i]) == w->limit) 2010 break; 2011 } 2012 KASSERT(i != w->count, ("did not find existing resource")); 2013 res = w->res[i]; 2014 2015 /* 2016 * Usually the resource we found should match the window's 2017 * existing range. The one exception is the ISA-enabled case 2018 * mentioned above in which case the resource should start at 2019 * 64k. 2020 */ 2021 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 2022 w->base <= 65535) { 2023 KASSERT(rman_get_start(res) == 65536, 2024 ("existing resource mismatch")); 2025 force_64k_base = 1; 2026 } else { 2027 KASSERT(w->base == rman_get_start(res), 2028 ("existing resource mismatch")); 2029 force_64k_base = 0; 2030 } 2031 2032 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2033 rman_get_start(res) : base, limit); 2034 if (error) 2035 return (error); 2036 2037 /* Add the newly allocated region to the resource manager. */ 2038 if (w->base != base) { 2039 error = rman_manage_region(&w->rman, base, w->base - 1); 2040 w->base = base; 2041 } else { 2042 error = rman_manage_region(&w->rman, w->limit + 1, limit); 2043 w->limit = limit; 2044 } 2045 if (error) { 2046 if (bootverbose) 2047 device_printf(sc->dev, 2048 "failed to expand %s resource manager\n", w->name); 2049 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 2050 rman_get_start(res) : w->base, w->limit); 2051 } 2052 return (error); 2053} 2054 2055/* 2056 * Attempt to grow a window to make room for a given resource request. 2057 */ 2058static int 2059pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 2060 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2061{ 2062 rman_res_t align, start_free, end_free, front, back, wmask; 2063 int error; 2064 2065 /* 2066 * Clamp the desired resource range to the maximum address 2067 * this window supports. Reject impossible requests. 2068 * 2069 * For I/O port requests behind a bridge with the ISA enable 2070 * bit set, force large allocations to start above 64k. 2071 */ 2072 if (!w->valid) 2073 return (EINVAL); 2074 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 2075 start < 65536) 2076 start = 65536; 2077 if (end > w->rman.rm_end) 2078 end = w->rman.rm_end; 2079 if (start + count - 1 > end || start + count < start) 2080 return (EINVAL); 2081 wmask = ((rman_res_t)1 << w->step) - 1; 2082 2083 /* 2084 * If there is no resource at all, just try to allocate enough 2085 * aligned space for this resource. 2086 */ 2087 if (w->res == NULL) { 2088 error = pcib_alloc_new_window(sc, w, type, start, end, count, 2089 flags); 2090 if (error) { 2091 if (bootverbose) 2092 device_printf(sc->dev, 2093 "failed to allocate initial %s window (%#jx-%#jx,%#jx)\n", 2094 w->name, start, end, count); 2095 return (error); 2096 } 2097 if (bootverbose) 2098 device_printf(sc->dev, 2099 "allocated initial %s window of %#jx-%#jx\n", 2100 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2101 goto updatewin; 2102 } 2103 2104 /* 2105 * See if growing the window would help. Compute the minimum 2106 * amount of address space needed on both the front and back 2107 * ends of the existing window to satisfy the allocation. 2108 * 2109 * For each end, build a candidate region adjusting for the 2110 * required alignment, etc. If there is a free region at the 2111 * edge of the window, grow from the inner edge of the free 2112 * region. Otherwise grow from the window boundary. 2113 * 2114 * Growing an I/O window below 64k for a bridge with the ISA 2115 * enable bit doesn't require any special magic as the step 2116 * size of an I/O window (1k) always includes multiple 2117 * non-alias ranges when it is grown in either direction. 2118 * 2119 * XXX: Special case: if w->res is completely empty and the 2120 * request size is larger than w->res, we should find the 2121 * optimal aligned buffer containing w->res and allocate that. 2122 */ 2123 if (bootverbose) 2124 device_printf(sc->dev, 2125 "attempting to grow %s window for (%#jx-%#jx,%#jx)\n", 2126 w->name, start, end, count); 2127 align = (rman_res_t)1 << RF_ALIGNMENT(flags); 2128 if (start < w->base) { 2129 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 2130 0 || start_free != w->base) 2131 end_free = w->base; 2132 if (end_free > end) 2133 end_free = end + 1; 2134 2135 /* Move end_free down until it is properly aligned. */ 2136 end_free &= ~(align - 1); 2137 end_free--; 2138 front = end_free - (count - 1); 2139 2140 /* 2141 * The resource would now be allocated at (front, 2142 * end_free). Ensure that fits in the (start, end) 2143 * bounds. end_free is checked above. If 'front' is 2144 * ok, ensure it is properly aligned for this window. 2145 * Also check for underflow. 2146 */ 2147 if (front >= start && front <= end_free) { 2148 if (bootverbose) 2149 printf("\tfront candidate range: %#jx-%#jx\n", 2150 front, end_free); 2151 front &= ~wmask; 2152 front = w->base - front; 2153 } else 2154 front = 0; 2155 } else 2156 front = 0; 2157 if (end > w->limit) { 2158 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 2159 0 || end_free != w->limit) 2160 start_free = w->limit + 1; 2161 if (start_free < start) 2162 start_free = start; 2163 2164 /* Move start_free up until it is properly aligned. */ 2165 start_free = roundup2(start_free, align); 2166 back = start_free + count - 1; 2167 2168 /* 2169 * The resource would now be allocated at (start_free, 2170 * back). Ensure that fits in the (start, end) 2171 * bounds. start_free is checked above. If 'back' is 2172 * ok, ensure it is properly aligned for this window. 2173 * Also check for overflow. 2174 */ 2175 if (back <= end && start_free <= back) { 2176 if (bootverbose) 2177 printf("\tback candidate range: %#jx-%#jx\n", 2178 start_free, back); 2179 back |= wmask; 2180 back -= w->limit; 2181 } else 2182 back = 0; 2183 } else 2184 back = 0; 2185 2186 /* 2187 * Try to allocate the smallest needed region first. 2188 * If that fails, fall back to the other region. 2189 */ 2190 error = ENOSPC; 2191 while (front != 0 || back != 0) { 2192 if (front != 0 && (front <= back || back == 0)) { 2193 error = pcib_expand_window(sc, w, type, w->base - front, 2194 w->limit); 2195 if (error == 0) 2196 break; 2197 front = 0; 2198 } else { 2199 error = pcib_expand_window(sc, w, type, w->base, 2200 w->limit + back); 2201 if (error == 0) 2202 break; 2203 back = 0; 2204 } 2205 } 2206 2207 if (error) 2208 return (error); 2209 if (bootverbose) 2210 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 2211 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 2212 2213updatewin: 2214 /* Write the new window. */ 2215 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 2216 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 2217 pcib_write_windows(sc, w->mask); 2218 return (0); 2219} 2220 2221/* 2222 * We have to trap resource allocation requests and ensure that the bridge 2223 * is set up to, or capable of handling them. 2224 */ 2225struct resource * 2226pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2227 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2228{ 2229 struct pcib_softc *sc; 2230 struct resource *r; 2231 2232 sc = device_get_softc(dev); 2233 2234 /* 2235 * VGA resources are decoded iff the VGA enable bit is set in 2236 * the bridge control register. VGA resources do not fall into 2237 * the resource windows and are passed up to the parent. 2238 */ 2239 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 2240 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 2241 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 2242 return (bus_generic_alloc_resource(dev, child, type, 2243 rid, start, end, count, flags)); 2244 else 2245 return (NULL); 2246 } 2247 2248 switch (type) { 2249#ifdef PCI_RES_BUS 2250 case PCI_RES_BUS: 2251 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 2252 count, flags)); 2253#endif 2254 case SYS_RES_IOPORT: 2255 if (pcib_is_isa_range(sc, start, end, count)) 2256 return (NULL); 2257 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 2258 end, count, flags); 2259 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2260 break; 2261 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 2262 flags) == 0) 2263 r = pcib_suballoc_resource(sc, &sc->io, child, type, 2264 rid, start, end, count, flags); 2265 break; 2266 case SYS_RES_MEMORY: 2267 /* 2268 * For prefetchable resources, prefer the prefetchable 2269 * memory window, but fall back to the regular memory 2270 * window if that fails. Try both windows before 2271 * attempting to grow a window in case the firmware 2272 * has used a range in the regular memory window to 2273 * map a prefetchable BAR. 2274 */ 2275 if (flags & RF_PREFETCHABLE) { 2276 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 2277 rid, start, end, count, flags); 2278 if (r != NULL) 2279 break; 2280 } 2281 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 2282 start, end, count, flags); 2283 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 2284 break; 2285 if (flags & RF_PREFETCHABLE) { 2286 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 2287 count, flags) == 0) { 2288 r = pcib_suballoc_resource(sc, &sc->pmem, child, 2289 type, rid, start, end, count, flags); 2290 if (r != NULL) 2291 break; 2292 } 2293 } 2294 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 2295 flags & ~RF_PREFETCHABLE) == 0) 2296 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 2297 rid, start, end, count, flags); 2298 break; 2299 default: 2300 return (bus_generic_alloc_resource(dev, child, type, rid, 2301 start, end, count, flags)); 2302 } 2303 2304 /* 2305 * If attempts to suballocate from the window fail but this is a 2306 * subtractive bridge, pass the request up the tree. 2307 */ 2308 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 2309 return (bus_generic_alloc_resource(dev, child, type, rid, 2310 start, end, count, flags)); 2311 return (r); 2312} 2313 2314int 2315pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 2316 rman_res_t start, rman_res_t end) 2317{ 2318 struct pcib_softc *sc; 2319 2320 sc = device_get_softc(bus); 2321 if (pcib_is_resource_managed(sc, type, r)) 2322 return (rman_adjust_resource(r, start, end)); 2323 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 2324} 2325 2326int 2327pcib_release_resource(device_t dev, device_t child, int type, int rid, 2328 struct resource *r) 2329{ 2330 struct pcib_softc *sc; 2331 int error; 2332 2333 sc = device_get_softc(dev); 2334 if (pcib_is_resource_managed(sc, type, r)) { 2335 if (rman_get_flags(r) & RF_ACTIVE) { 2336 error = bus_deactivate_resource(child, type, rid, r); 2337 if (error) 2338 return (error); 2339 } 2340 return (rman_release_resource(r)); 2341 } 2342 return (bus_generic_release_resource(dev, child, type, rid, r)); 2343} 2344#else 2345/* 2346 * We have to trap resource allocation requests and ensure that the bridge 2347 * is set up to, or capable of handling them. 2348 */ 2349struct resource * 2350pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 2351 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 2352{ 2353 struct pcib_softc *sc = device_get_softc(dev); 2354 const char *name, *suffix; 2355 int ok; 2356 2357 /* 2358 * Fail the allocation for this range if it's not supported. 2359 */ 2360 name = device_get_nameunit(child); 2361 if (name == NULL) { 2362 name = ""; 2363 suffix = ""; 2364 } else 2365 suffix = " "; 2366 switch (type) { 2367 case SYS_RES_IOPORT: 2368 ok = 0; 2369 if (!pcib_is_io_open(sc)) 2370 break; 2371 ok = (start >= sc->iobase && end <= sc->iolimit); 2372 2373 /* 2374 * Make sure we allow access to VGA I/O addresses when the 2375 * bridge has the "VGA Enable" bit set. 2376 */ 2377 if (!ok && pci_is_vga_ioport_range(start, end)) 2378 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2379 2380 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2381 if (!ok) { 2382 if (start < sc->iobase) 2383 start = sc->iobase; 2384 if (end > sc->iolimit) 2385 end = sc->iolimit; 2386 if (start < end) 2387 ok = 1; 2388 } 2389 } else { 2390 ok = 1; 2391#if 0 2392 /* 2393 * If we overlap with the subtractive range, then 2394 * pick the upper range to use. 2395 */ 2396 if (start < sc->iolimit && end > sc->iobase) 2397 start = sc->iolimit + 1; 2398#endif 2399 } 2400 if (end < start) { 2401 device_printf(dev, "ioport: end (%jx) < start (%jx)\n", 2402 end, start); 2403 start = 0; 2404 end = 0; 2405 ok = 0; 2406 } 2407 if (!ok) { 2408 device_printf(dev, "%s%srequested unsupported I/O " 2409 "range 0x%jx-0x%jx (decoding 0x%x-0x%x)\n", 2410 name, suffix, start, end, sc->iobase, sc->iolimit); 2411 return (NULL); 2412 } 2413 if (bootverbose) 2414 device_printf(dev, 2415 "%s%srequested I/O range 0x%jx-0x%jx: in range\n", 2416 name, suffix, start, end); 2417 break; 2418 2419 case SYS_RES_MEMORY: 2420 ok = 0; 2421 if (pcib_is_nonprefetch_open(sc)) 2422 ok = ok || (start >= sc->membase && end <= sc->memlimit); 2423 if (pcib_is_prefetch_open(sc)) 2424 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 2425 2426 /* 2427 * Make sure we allow access to VGA memory addresses when the 2428 * bridge has the "VGA Enable" bit set. 2429 */ 2430 if (!ok && pci_is_vga_memory_range(start, end)) 2431 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 2432 2433 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 2434 if (!ok) { 2435 ok = 1; 2436 if (flags & RF_PREFETCHABLE) { 2437 if (pcib_is_prefetch_open(sc)) { 2438 if (start < sc->pmembase) 2439 start = sc->pmembase; 2440 if (end > sc->pmemlimit) 2441 end = sc->pmemlimit; 2442 } else { 2443 ok = 0; 2444 } 2445 } else { /* non-prefetchable */ 2446 if (pcib_is_nonprefetch_open(sc)) { 2447 if (start < sc->membase) 2448 start = sc->membase; 2449 if (end > sc->memlimit) 2450 end = sc->memlimit; 2451 } else { 2452 ok = 0; 2453 } 2454 } 2455 } 2456 } else if (!ok) { 2457 ok = 1; /* subtractive bridge: always ok */ 2458#if 0 2459 if (pcib_is_nonprefetch_open(sc)) { 2460 if (start < sc->memlimit && end > sc->membase) 2461 start = sc->memlimit + 1; 2462 } 2463 if (pcib_is_prefetch_open(sc)) { 2464 if (start < sc->pmemlimit && end > sc->pmembase) 2465 start = sc->pmemlimit + 1; 2466 } 2467#endif 2468 } 2469 if (end < start) { 2470 device_printf(dev, "memory: end (%jx) < start (%jx)\n", 2471 end, start); 2472 start = 0; 2473 end = 0; 2474 ok = 0; 2475 } 2476 if (!ok && bootverbose) 2477 device_printf(dev, 2478 "%s%srequested unsupported memory range %#jx-%#jx " 2479 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 2480 name, suffix, start, end, 2481 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 2482 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 2483 if (!ok) 2484 return (NULL); 2485 if (bootverbose) 2486 device_printf(dev,"%s%srequested memory range " 2487 "0x%jx-0x%jx: good\n", 2488 name, suffix, start, end); 2489 break; 2490 2491 default: 2492 break; 2493 } 2494 /* 2495 * Bridge is OK decoding this resource, so pass it up. 2496 */ 2497 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 2498 count, flags)); 2499} 2500#endif 2501 2502/* 2503 * If ARI is enabled on this downstream port, translate the function number 2504 * to the non-ARI slot/function. The downstream port will convert it back in 2505 * hardware. If ARI is not enabled slot and func are not modified. 2506 */ 2507static __inline void 2508pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 2509{ 2510 struct pcib_softc *sc; 2511 int ari_func; 2512 2513 sc = device_get_softc(pcib); 2514 ari_func = *func; 2515 2516 if (sc->flags & PCIB_ENABLE_ARI) { 2517 KASSERT(*slot == 0, 2518 ("Non-zero slot number with ARI enabled!")); 2519 *slot = PCIE_ARI_SLOT(ari_func); 2520 *func = PCIE_ARI_FUNC(ari_func); 2521 } 2522} 2523 2524 2525static void 2526pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 2527{ 2528 uint32_t ctl2; 2529 2530 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 2531 ctl2 |= PCIEM_CTL2_ARI; 2532 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 2533 2534 sc->flags |= PCIB_ENABLE_ARI; 2535} 2536 2537/* 2538 * PCIB interface. 2539 */ 2540int 2541pcib_maxslots(device_t dev) 2542{ 2543 return (PCI_SLOTMAX); 2544} 2545 2546static int 2547pcib_ari_maxslots(device_t dev) 2548{ 2549 struct pcib_softc *sc; 2550 2551 sc = device_get_softc(dev); 2552 2553 if (sc->flags & PCIB_ENABLE_ARI) 2554 return (PCIE_ARI_SLOTMAX); 2555 else 2556 return (PCI_SLOTMAX); 2557} 2558 2559static int 2560pcib_ari_maxfuncs(device_t dev) 2561{ 2562 struct pcib_softc *sc; 2563 2564 sc = device_get_softc(dev); 2565 2566 if (sc->flags & PCIB_ENABLE_ARI) 2567 return (PCIE_ARI_FUNCMAX); 2568 else 2569 return (PCI_FUNCMAX); 2570} 2571 2572static void 2573pcib_ari_decode_rid(device_t pcib, uint16_t rid, int *bus, int *slot, 2574 int *func) 2575{ 2576 struct pcib_softc *sc; 2577 2578 sc = device_get_softc(pcib); 2579 2580 *bus = PCI_RID2BUS(rid); 2581 if (sc->flags & PCIB_ENABLE_ARI) { 2582 *slot = PCIE_ARI_RID2SLOT(rid); 2583 *func = PCIE_ARI_RID2FUNC(rid); 2584 } else { 2585 *slot = PCI_RID2SLOT(rid); 2586 *func = PCI_RID2FUNC(rid); 2587 } 2588} 2589 2590/* 2591 * Since we are a child of a PCI bus, its parent must support the pcib interface. 2592 */ 2593static uint32_t 2594pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 2595{ 2596#ifdef PCI_HP 2597 struct pcib_softc *sc; 2598 2599 sc = device_get_softc(dev); 2600 if (!pcib_present(sc)) { 2601 switch (width) { 2602 case 2: 2603 return (0xffff); 2604 case 1: 2605 return (0xff); 2606 default: 2607 return (0xffffffff); 2608 } 2609 } 2610#endif 2611 pcib_xlate_ari(dev, b, &s, &f); 2612 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 2613 f, reg, width)); 2614} 2615 2616static void 2617pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 2618{ 2619#ifdef PCI_HP 2620 struct pcib_softc *sc; 2621 2622 sc = device_get_softc(dev); 2623 if (!pcib_present(sc)) 2624 return; 2625#endif 2626 pcib_xlate_ari(dev, b, &s, &f); 2627 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 2628 reg, val, width); 2629} 2630 2631/* 2632 * Route an interrupt across a PCI bridge. 2633 */ 2634int 2635pcib_route_interrupt(device_t pcib, device_t dev, int pin) 2636{ 2637 device_t bus; 2638 int parent_intpin; 2639 int intnum; 2640 2641 /* 2642 * 2643 * The PCI standard defines a swizzle of the child-side device/intpin to 2644 * the parent-side intpin as follows. 2645 * 2646 * device = device on child bus 2647 * child_intpin = intpin on child bus slot (0-3) 2648 * parent_intpin = intpin on parent bus slot (0-3) 2649 * 2650 * parent_intpin = (device + child_intpin) % 4 2651 */ 2652 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 2653 2654 /* 2655 * Our parent is a PCI bus. Its parent must export the pcib interface 2656 * which includes the ability to route interrupts. 2657 */ 2658 bus = device_get_parent(pcib); 2659 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 2660 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 2661 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 2662 pci_get_slot(dev), 'A' + pin - 1, intnum); 2663 } 2664 return(intnum); 2665} 2666 2667/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 2668int 2669pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 2670{ 2671 struct pcib_softc *sc = device_get_softc(pcib); 2672 device_t bus; 2673 2674 if (sc->flags & PCIB_DISABLE_MSI) 2675 return (ENXIO); 2676 bus = device_get_parent(pcib); 2677 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 2678 irqs)); 2679} 2680 2681/* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 2682int 2683pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 2684{ 2685 device_t bus; 2686 2687 bus = device_get_parent(pcib); 2688 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 2689} 2690 2691/* Pass request to alloc an MSI-X message up to the parent bridge. */ 2692int 2693pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 2694{ 2695 struct pcib_softc *sc = device_get_softc(pcib); 2696 device_t bus; 2697 2698 if (sc->flags & PCIB_DISABLE_MSIX) 2699 return (ENXIO); 2700 bus = device_get_parent(pcib); 2701 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 2702} 2703 2704/* Pass request to release an MSI-X message up to the parent bridge. */ 2705int 2706pcib_release_msix(device_t pcib, device_t dev, int irq) 2707{ 2708 device_t bus; 2709 2710 bus = device_get_parent(pcib); 2711 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 2712} 2713 2714/* Pass request to map MSI/MSI-X message up to parent bridge. */ 2715int 2716pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 2717 uint32_t *data) 2718{ 2719 device_t bus; 2720 int error; 2721 2722 bus = device_get_parent(pcib); 2723 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 2724 if (error) 2725 return (error); 2726 2727 pci_ht_map_msi(pcib, *addr); 2728 return (0); 2729} 2730 2731/* Pass request for device power state up to parent bridge. */ 2732int 2733pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 2734{ 2735 device_t bus; 2736 2737 bus = device_get_parent(pcib); 2738 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 2739} 2740 2741static int 2742pcib_ari_enabled(device_t pcib) 2743{ 2744 struct pcib_softc *sc; 2745 2746 sc = device_get_softc(pcib); 2747 2748 return ((sc->flags & PCIB_ENABLE_ARI) != 0); 2749} 2750 2751static int 2752pcib_ari_get_id(device_t pcib, device_t dev, enum pci_id_type type, 2753 uintptr_t *id) 2754{ 2755 struct pcib_softc *sc; 2756 device_t bus_dev; 2757 uint8_t bus, slot, func; 2758 2759 if (type != PCI_ID_RID) { 2760 bus_dev = device_get_parent(pcib); 2761 return (PCIB_GET_ID(device_get_parent(bus_dev), dev, type, id)); 2762 } 2763 2764 sc = device_get_softc(pcib); 2765 2766 if (sc->flags & PCIB_ENABLE_ARI) { 2767 bus = pci_get_bus(dev); 2768 func = pci_get_function(dev); 2769 2770 *id = (PCI_ARI_RID(bus, func)); 2771 } else { 2772 bus = pci_get_bus(dev); 2773 slot = pci_get_slot(dev); 2774 func = pci_get_function(dev); 2775 2776 *id = (PCI_RID(bus, slot, func)); 2777 } 2778 2779 return (0); 2780} 2781 2782/* 2783 * Check that the downstream port (pcib) and the endpoint device (dev) both 2784 * support ARI. If so, enable it and return 0, otherwise return an error. 2785 */ 2786static int 2787pcib_try_enable_ari(device_t pcib, device_t dev) 2788{ 2789 struct pcib_softc *sc; 2790 int error; 2791 uint32_t cap2; 2792 int ari_cap_off; 2793 uint32_t ari_ver; 2794 uint32_t pcie_pos; 2795 2796 sc = device_get_softc(pcib); 2797 2798 /* 2799 * ARI is controlled in a register in the PCIe capability structure. 2800 * If the downstream port does not have the PCIe capability structure 2801 * then it does not support ARI. 2802 */ 2803 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 2804 if (error != 0) 2805 return (ENODEV); 2806 2807 /* Check that the PCIe port advertises ARI support. */ 2808 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 2809 if (!(cap2 & PCIEM_CAP2_ARI)) 2810 return (ENODEV); 2811 2812 /* 2813 * Check that the endpoint device advertises ARI support via the ARI 2814 * extended capability structure. 2815 */ 2816 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 2817 if (error != 0) 2818 return (ENODEV); 2819 2820 /* 2821 * Finally, check that the endpoint device supports the same version 2822 * of ARI that we do. 2823 */ 2824 ari_ver = pci_read_config(dev, ari_cap_off, 4); 2825 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 2826 if (bootverbose) 2827 device_printf(pcib, 2828 "Unsupported version of ARI (%d) detected\n", 2829 PCI_EXTCAP_VER(ari_ver)); 2830 2831 return (ENXIO); 2832 } 2833 2834 pcib_enable_ari(sc, pcie_pos); 2835 2836 return (0); 2837} 2838