pci_iov.c revision 296865
1/*- 2 * Copyright (c) 2013-2015 Sandvine Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/pci/pci_iov.c 296865 2016-03-14 17:41:17Z rstone $"); 29 30#include "opt_bus.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/fcntl.h> 38#include <sys/ioccom.h> 39#include <sys/iov.h> 40#include <sys/linker.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/pciio.h> 44#include <sys/queue.h> 45#include <sys/rman.h> 46#include <sys/sysctl.h> 47 48#include <machine/bus.h> 49#include <machine/stdarg.h> 50 51#include <sys/nv.h> 52#include <sys/iov_schema.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pci_iov.h> 57#include <dev/pci/pci_private.h> 58#include <dev/pci/pci_iov_private.h> 59#include <dev/pci/schema_private.h> 60 61#include "pcib_if.h" 62 63static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations"); 64 65static d_ioctl_t pci_iov_ioctl; 66 67static struct cdevsw iov_cdevsw = { 68 .d_version = D_VERSION, 69 .d_name = "iov", 70 .d_ioctl = pci_iov_ioctl 71}; 72 73SYSCTL_DECL(_hw_pci); 74 75/* 76 * The maximum amount of memory we will allocate for user configuration of an 77 * SR-IOV device. 1MB ought to be enough for anyone, but leave this 78 * configurable just in case. 79 */ 80static u_long pci_iov_max_config = 1024 * 1024; 81SYSCTL_ULONG(_hw_pci, OID_AUTO, iov_max_config, CTLFLAG_RWTUN, 82 &pci_iov_max_config, 0, "Maximum allowed size of SR-IOV configuration."); 83 84 85#define IOV_READ(d, r, w) \ 86 pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w) 87 88#define IOV_WRITE(d, r, v, w) \ 89 pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w) 90 91static nvlist_t *pci_iov_build_schema(nvlist_t **pf_schema, 92 nvlist_t **vf_schema); 93static void pci_iov_build_pf_schema(nvlist_t *schema, 94 nvlist_t **driver_schema); 95static void pci_iov_build_vf_schema(nvlist_t *schema, 96 nvlist_t **driver_schema); 97static nvlist_t *pci_iov_get_pf_subsystem_schema(void); 98static nvlist_t *pci_iov_get_vf_subsystem_schema(void); 99 100int 101pci_iov_attach_method(device_t bus, device_t dev, nvlist_t *pf_schema, 102 nvlist_t *vf_schema) 103{ 104 device_t pcib; 105 struct pci_devinfo *dinfo; 106 struct pcicfg_iov *iov; 107 nvlist_t *schema; 108 uint32_t version; 109 int error; 110 int iov_pos; 111 112 dinfo = device_get_ivars(dev); 113 pcib = device_get_parent(bus); 114 schema = NULL; 115 116 error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 117 118 if (error != 0) 119 return (error); 120 121 version = pci_read_config(dev, iov_pos, 4); 122 if (PCI_EXTCAP_VER(version) != 1) { 123 if (bootverbose) 124 device_printf(dev, 125 "Unsupported version of SR-IOV (%d) detected\n", 126 PCI_EXTCAP_VER(version)); 127 128 return (ENXIO); 129 } 130 131 iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO); 132 133 mtx_lock(&Giant); 134 if (dinfo->cfg.iov != NULL) { 135 error = EBUSY; 136 goto cleanup; 137 } 138 iov->iov_pos = iov_pos; 139 140 schema = pci_iov_build_schema(&pf_schema, &vf_schema); 141 if (schema == NULL) { 142 error = ENOMEM; 143 goto cleanup; 144 } 145 146 error = pci_iov_validate_schema(schema); 147 if (error != 0) 148 goto cleanup; 149 iov->iov_schema = schema; 150 151 iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev), 152 UID_ROOT, GID_WHEEL, 0600, "iov/%s", device_get_nameunit(dev)); 153 154 if (iov->iov_cdev == NULL) { 155 error = ENOMEM; 156 goto cleanup; 157 } 158 159 dinfo->cfg.iov = iov; 160 iov->iov_cdev->si_drv1 = dinfo; 161 mtx_unlock(&Giant); 162 163 return (0); 164 165cleanup: 166 nvlist_destroy(schema); 167 nvlist_destroy(pf_schema); 168 nvlist_destroy(vf_schema); 169 free(iov, M_SRIOV); 170 mtx_unlock(&Giant); 171 return (error); 172} 173 174int 175pci_iov_detach_method(device_t bus, device_t dev) 176{ 177 struct pci_devinfo *dinfo; 178 struct pcicfg_iov *iov; 179 180 mtx_lock(&Giant); 181 dinfo = device_get_ivars(dev); 182 iov = dinfo->cfg.iov; 183 184 if (iov == NULL) { 185 mtx_unlock(&Giant); 186 return (0); 187 } 188 189 if (iov->iov_num_vfs != 0 || iov->iov_flags & IOV_BUSY) { 190 mtx_unlock(&Giant); 191 return (EBUSY); 192 } 193 194 dinfo->cfg.iov = NULL; 195 196 if (iov->iov_cdev) { 197 destroy_dev(iov->iov_cdev); 198 iov->iov_cdev = NULL; 199 } 200 nvlist_destroy(iov->iov_schema); 201 202 free(iov, M_SRIOV); 203 mtx_unlock(&Giant); 204 205 return (0); 206} 207 208static nvlist_t * 209pci_iov_build_schema(nvlist_t **pf, nvlist_t **vf) 210{ 211 nvlist_t *schema, *pf_driver, *vf_driver; 212 213 /* We always take ownership of the schemas. */ 214 pf_driver = *pf; 215 *pf = NULL; 216 vf_driver = *vf; 217 *vf = NULL; 218 219 schema = pci_iov_schema_alloc_node(); 220 if (schema == NULL) 221 goto cleanup; 222 223 pci_iov_build_pf_schema(schema, &pf_driver); 224 pci_iov_build_vf_schema(schema, &vf_driver); 225 226 if (nvlist_error(schema) != 0) 227 goto cleanup; 228 229 return (schema); 230 231cleanup: 232 nvlist_destroy(schema); 233 nvlist_destroy(pf_driver); 234 nvlist_destroy(vf_driver); 235 return (NULL); 236} 237 238static void 239pci_iov_build_pf_schema(nvlist_t *schema, nvlist_t **driver_schema) 240{ 241 nvlist_t *pf_schema, *iov_schema; 242 243 pf_schema = pci_iov_schema_alloc_node(); 244 if (pf_schema == NULL) { 245 nvlist_set_error(schema, ENOMEM); 246 return; 247 } 248 249 iov_schema = pci_iov_get_pf_subsystem_schema(); 250 251 /* 252 * Note that if either *driver_schema or iov_schema is NULL, then 253 * nvlist_move_nvlist will put the schema in the error state and 254 * SR-IOV will fail to initialize later, so we don't have to explicitly 255 * handle that case. 256 */ 257 nvlist_move_nvlist(pf_schema, DRIVER_CONFIG_NAME, *driver_schema); 258 nvlist_move_nvlist(pf_schema, IOV_CONFIG_NAME, iov_schema); 259 nvlist_move_nvlist(schema, PF_CONFIG_NAME, pf_schema); 260 *driver_schema = NULL; 261} 262 263static void 264pci_iov_build_vf_schema(nvlist_t *schema, nvlist_t **driver_schema) 265{ 266 nvlist_t *vf_schema, *iov_schema; 267 268 vf_schema = pci_iov_schema_alloc_node(); 269 if (vf_schema == NULL) { 270 nvlist_set_error(schema, ENOMEM); 271 return; 272 } 273 274 iov_schema = pci_iov_get_vf_subsystem_schema(); 275 276 /* 277 * Note that if either *driver_schema or iov_schema is NULL, then 278 * nvlist_move_nvlist will put the schema in the error state and 279 * SR-IOV will fail to initialize later, so we don't have to explicitly 280 * handle that case. 281 */ 282 nvlist_move_nvlist(vf_schema, DRIVER_CONFIG_NAME, *driver_schema); 283 nvlist_move_nvlist(vf_schema, IOV_CONFIG_NAME, iov_schema); 284 nvlist_move_nvlist(schema, VF_SCHEMA_NAME, vf_schema); 285 *driver_schema = NULL; 286} 287 288static nvlist_t * 289pci_iov_get_pf_subsystem_schema(void) 290{ 291 nvlist_t *pf; 292 293 pf = pci_iov_schema_alloc_node(); 294 if (pf == NULL) 295 return (NULL); 296 297 pci_iov_schema_add_uint16(pf, "num_vfs", IOV_SCHEMA_REQUIRED, -1); 298 pci_iov_schema_add_string(pf, "device", IOV_SCHEMA_REQUIRED, NULL); 299 300 return (pf); 301} 302 303static nvlist_t * 304pci_iov_get_vf_subsystem_schema(void) 305{ 306 nvlist_t *vf; 307 308 vf = pci_iov_schema_alloc_node(); 309 if (vf == NULL) 310 return (NULL); 311 312 pci_iov_schema_add_bool(vf, "passthrough", IOV_SCHEMA_HASDEFAULT, 0); 313 314 return (vf); 315} 316 317static int 318pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift) 319{ 320 struct resource *res; 321 struct pcicfg_iov *iov; 322 device_t dev, bus; 323 rman_res_t start, end; 324 pci_addr_t bar_size; 325 int rid; 326 327 iov = dinfo->cfg.iov; 328 dev = dinfo->cfg.dev; 329 bus = device_get_parent(dev); 330 rid = iov->iov_pos + PCIR_SRIOV_BAR(bar); 331 bar_size = 1 << bar_shift; 332 333 res = pci_alloc_multi_resource(bus, dev, SYS_RES_MEMORY, &rid, 0, 334 ~0, 1, iov->iov_num_vfs, RF_ACTIVE); 335 336 if (res == NULL) 337 return (ENXIO); 338 339 iov->iov_bar[bar].res = res; 340 iov->iov_bar[bar].bar_size = bar_size; 341 iov->iov_bar[bar].bar_shift = bar_shift; 342 343 start = rman_get_start(res); 344 end = rman_get_end(res); 345 return (rman_manage_region(&iov->rman, start, end)); 346} 347 348static void 349pci_iov_add_bars(struct pcicfg_iov *iov, struct pci_devinfo *dinfo) 350{ 351 struct pci_iov_bar *bar; 352 uint64_t bar_start; 353 int i; 354 355 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 356 bar = &iov->iov_bar[i]; 357 if (bar->res != NULL) { 358 bar_start = rman_get_start(bar->res) + 359 dinfo->cfg.vf.index * bar->bar_size; 360 361 pci_add_bar(dinfo->cfg.dev, PCIR_BAR(i), bar_start, 362 bar->bar_shift); 363 } 364 } 365} 366 367static int 368pci_iov_parse_config(struct pcicfg_iov *iov, struct pci_iov_arg *arg, 369 nvlist_t **ret) 370{ 371 void *packed_config; 372 nvlist_t *config; 373 int error; 374 375 config = NULL; 376 packed_config = NULL; 377 378 if (arg->len > pci_iov_max_config) { 379 error = EMSGSIZE; 380 goto out; 381 } 382 383 packed_config = malloc(arg->len, M_SRIOV, M_WAITOK); 384 385 error = copyin(arg->config, packed_config, arg->len); 386 if (error != 0) 387 goto out; 388 389 config = nvlist_unpack(packed_config, arg->len, NV_FLAG_IGNORE_CASE); 390 if (config == NULL) { 391 error = EINVAL; 392 goto out; 393 } 394 395 error = pci_iov_schema_validate_config(iov->iov_schema, config); 396 if (error != 0) 397 goto out; 398 399 error = nvlist_error(config); 400 if (error != 0) 401 goto out; 402 403 *ret = config; 404 config = NULL; 405 406out: 407 nvlist_destroy(config); 408 free(packed_config, M_SRIOV); 409 return (error); 410} 411 412/* 413 * Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV 414 * capability. This bit is only writeable on the lowest-numbered PF but 415 * affects all PFs on the device. 416 */ 417static int 418pci_iov_set_ari(device_t bus) 419{ 420 device_t lowest; 421 device_t *devlist; 422 int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func; 423 uint16_t iov_ctl; 424 425 /* If ARI is disabled on the downstream port there is nothing to do. */ 426 if (!PCIB_ARI_ENABLED(device_get_parent(bus))) 427 return (0); 428 429 error = device_get_children(bus, &devlist, &devcount); 430 431 if (error != 0) 432 return (error); 433 434 lowest = NULL; 435 for (i = 0; i < devcount; i++) { 436 if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) { 437 dev_func = pci_get_function(devlist[i]); 438 if (lowest == NULL || dev_func < lowest_func) { 439 lowest = devlist[i]; 440 lowest_func = dev_func; 441 lowest_pos = iov_pos; 442 } 443 } 444 } 445 446 /* 447 * If we called this function some device must have the SR-IOV 448 * capability. 449 */ 450 KASSERT(lowest != NULL, 451 ("Could not find child of %s with SR-IOV capability", 452 device_get_nameunit(bus))); 453 454 iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2); 455 iov_ctl |= PCIM_SRIOV_ARI_EN; 456 pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2); 457 free(devlist, M_TEMP); 458 return (0); 459} 460 461static int 462pci_iov_config_page_size(struct pci_devinfo *dinfo) 463{ 464 uint32_t page_cap, page_size; 465 466 page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4); 467 468 /* 469 * If the system page size is less than the smallest SR-IOV page size 470 * then round up to the smallest SR-IOV page size. 471 */ 472 if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT) 473 page_size = (1 << 0); 474 else 475 page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT)); 476 477 /* Check that the device supports the system page size. */ 478 if (!(page_size & page_cap)) 479 return (ENXIO); 480 481 IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4); 482 return (0); 483} 484 485static int 486pci_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *config) 487{ 488 const nvlist_t *device, *driver_config; 489 490 device = nvlist_get_nvlist(config, PF_CONFIG_NAME); 491 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 492 return (PCI_IOV_INIT(dev, num_vfs, driver_config)); 493} 494 495static int 496pci_iov_init_rman(device_t pf, struct pcicfg_iov *iov) 497{ 498 int error; 499 500 iov->rman.rm_start = 0; 501 iov->rman.rm_end = ~0; 502 iov->rman.rm_type = RMAN_ARRAY; 503 snprintf(iov->rman_name, sizeof(iov->rman_name), "%s VF I/O memory", 504 device_get_nameunit(pf)); 505 iov->rman.rm_descr = iov->rman_name; 506 507 error = rman_init(&iov->rman); 508 if (error != 0) 509 return (error); 510 511 iov->iov_flags |= IOV_RMAN_INITED; 512 return (0); 513} 514 515static int 516pci_iov_alloc_bar_ea(struct pci_devinfo *dinfo, int bar) 517{ 518 struct pcicfg_iov *iov; 519 rman_res_t start, end; 520 struct resource *res; 521 struct resource_list *rl; 522 struct resource_list_entry *rle; 523 524 rl = &dinfo->resources; 525 iov = dinfo->cfg.iov; 526 527 rle = resource_list_find(rl, SYS_RES_MEMORY, 528 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 529 if (rle == NULL) 530 rle = resource_list_find(rl, SYS_RES_IOPORT, 531 iov->iov_pos + PCIR_SRIOV_BAR(bar)); 532 if (rle == NULL) 533 return (ENXIO); 534 res = rle->res; 535 536 iov->iov_bar[bar].res = res; 537 iov->iov_bar[bar].bar_size = rman_get_size(res) / iov->iov_num_vfs; 538 iov->iov_bar[bar].bar_shift = pci_mapsize(iov->iov_bar[bar].bar_size); 539 540 start = rman_get_start(res); 541 end = rman_get_end(res); 542 543 return (rman_manage_region(&iov->rman, start, end)); 544} 545 546static int 547pci_iov_setup_bars(struct pci_devinfo *dinfo) 548{ 549 device_t dev; 550 struct pcicfg_iov *iov; 551 pci_addr_t bar_value, testval; 552 int i, last_64, error; 553 554 iov = dinfo->cfg.iov; 555 dev = dinfo->cfg.dev; 556 last_64 = 0; 557 558 pci_add_resources_ea(device_get_parent(dev), dev, 1); 559 560 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 561 /* First, try to use BARs allocated with EA */ 562 error = pci_iov_alloc_bar_ea(dinfo, i); 563 if (error == 0) 564 continue; 565 566 /* Allocate legacy-BAR only if EA is not enabled */ 567 if (pci_ea_is_enabled(dev, iov->iov_pos + PCIR_SRIOV_BAR(i))) 568 continue; 569 570 /* 571 * If a PCI BAR is a 64-bit wide BAR, then it spans two 572 * consecutive registers. Therefore if the last BAR that 573 * we looked at was a 64-bit BAR, we need to skip this 574 * register as it's the second half of the last BAR. 575 */ 576 if (!last_64) { 577 pci_read_bar(dev, 578 iov->iov_pos + PCIR_SRIOV_BAR(i), 579 &bar_value, &testval, &last_64); 580 581 if (testval != 0) { 582 error = pci_iov_alloc_bar(dinfo, i, 583 pci_mapsize(testval)); 584 if (error != 0) 585 return (error); 586 } 587 } else 588 last_64 = 0; 589 } 590 591 return (0); 592} 593 594static void 595pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const nvlist_t *config, 596 uint16_t first_rid, uint16_t rid_stride) 597{ 598 char device_name[VF_MAX_NAME]; 599 const nvlist_t *device, *driver_config, *iov_config; 600 device_t bus, dev, vf; 601 struct pcicfg_iov *iov; 602 struct pci_devinfo *vfinfo; 603 size_t size; 604 int i, error; 605 uint16_t vid, did, next_rid; 606 607 iov = dinfo->cfg.iov; 608 dev = dinfo->cfg.dev; 609 bus = device_get_parent(dev); 610 size = dinfo->cfg.devinfo_size; 611 next_rid = first_rid; 612 vid = pci_get_vendor(dev); 613 did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2); 614 615 for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) { 616 snprintf(device_name, sizeof(device_name), VF_PREFIX"%d", i); 617 device = nvlist_get_nvlist(config, device_name); 618 iov_config = nvlist_get_nvlist(device, IOV_CONFIG_NAME); 619 driver_config = nvlist_get_nvlist(device, DRIVER_CONFIG_NAME); 620 621 vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did); 622 if (vf == NULL) 623 break; 624 625 /* 626 * If we are creating passthrough devices then force the ppt 627 * driver to attach to prevent a VF driver from claiming the 628 * VFs. 629 */ 630 if (nvlist_get_bool(iov_config, "passthrough")) 631 device_set_devclass_fixed(vf, "ppt"); 632 633 vfinfo = device_get_ivars(vf); 634 635 vfinfo->cfg.iov = iov; 636 vfinfo->cfg.vf.index = i; 637 638 pci_iov_add_bars(iov, vfinfo); 639 640 error = PCI_IOV_ADD_VF(dev, i, driver_config); 641 if (error != 0) { 642 device_printf(dev, "Failed to add VF %d\n", i); 643 pci_delete_child(bus, vf); 644 } 645 } 646 647 bus_generic_attach(bus); 648} 649 650static int 651pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg) 652{ 653 device_t bus, dev; 654 struct pci_devinfo *dinfo; 655 struct pcicfg_iov *iov; 656 nvlist_t *config; 657 int i, error; 658 uint16_t rid_off, rid_stride; 659 uint16_t first_rid, last_rid; 660 uint16_t iov_ctl; 661 uint16_t num_vfs, total_vfs; 662 int iov_inited; 663 664 mtx_lock(&Giant); 665 dinfo = cdev->si_drv1; 666 iov = dinfo->cfg.iov; 667 dev = dinfo->cfg.dev; 668 bus = device_get_parent(dev); 669 iov_inited = 0; 670 config = NULL; 671 672 if ((iov->iov_flags & IOV_BUSY) || iov->iov_num_vfs != 0) { 673 mtx_unlock(&Giant); 674 return (EBUSY); 675 } 676 iov->iov_flags |= IOV_BUSY; 677 678 error = pci_iov_parse_config(iov, arg, &config); 679 if (error != 0) 680 goto out; 681 682 num_vfs = pci_iov_config_get_num_vfs(config); 683 total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2); 684 if (num_vfs > total_vfs) { 685 error = EINVAL; 686 goto out; 687 } 688 689 error = pci_iov_config_page_size(dinfo); 690 if (error != 0) 691 goto out; 692 693 error = pci_iov_set_ari(bus); 694 if (error != 0) 695 goto out; 696 697 error = pci_iov_init(dev, num_vfs, config); 698 if (error != 0) 699 goto out; 700 iov_inited = 1; 701 702 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, num_vfs, 2); 703 704 rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2); 705 rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2); 706 707 first_rid = pci_get_rid(dev) + rid_off; 708 last_rid = first_rid + (num_vfs - 1) * rid_stride; 709 710 /* We don't yet support allocating extra bus numbers for VFs. */ 711 if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) { 712 error = ENOSPC; 713 goto out; 714 } 715 716 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 717 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 718 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 719 720 error = pci_iov_init_rman(dev, iov); 721 if (error != 0) 722 goto out; 723 724 iov->iov_num_vfs = num_vfs; 725 726 error = pci_iov_setup_bars(dinfo); 727 if (error != 0) 728 goto out; 729 730 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 731 iov_ctl |= PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE; 732 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 733 734 /* Per specification, we must wait 100ms before accessing VFs. */ 735 pause("iov", roundup(hz, 10)); 736 pci_iov_enumerate_vfs(dinfo, config, first_rid, rid_stride); 737 738 nvlist_destroy(config); 739 iov->iov_flags &= ~IOV_BUSY; 740 mtx_unlock(&Giant); 741 742 return (0); 743out: 744 if (iov_inited) 745 PCI_IOV_UNINIT(dev); 746 747 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 748 if (iov->iov_bar[i].res != NULL) { 749 pci_release_resource(bus, dev, SYS_RES_MEMORY, 750 iov->iov_pos + PCIR_SRIOV_BAR(i), 751 iov->iov_bar[i].res); 752 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 753 iov->iov_pos + PCIR_SRIOV_BAR(i)); 754 iov->iov_bar[i].res = NULL; 755 } 756 } 757 758 if (iov->iov_flags & IOV_RMAN_INITED) { 759 rman_fini(&iov->rman); 760 iov->iov_flags &= ~IOV_RMAN_INITED; 761 } 762 763 nvlist_destroy(config); 764 iov->iov_num_vfs = 0; 765 iov->iov_flags &= ~IOV_BUSY; 766 mtx_unlock(&Giant); 767 return (error); 768} 769 770/* Return true if child is a VF of the given PF. */ 771static int 772pci_iov_is_child_vf(struct pcicfg_iov *pf, device_t child) 773{ 774 struct pci_devinfo *vfinfo; 775 776 vfinfo = device_get_ivars(child); 777 778 if (!(vfinfo->cfg.flags & PCICFG_VF)) 779 return (0); 780 781 return (pf == vfinfo->cfg.iov); 782} 783 784static int 785pci_iov_delete(struct cdev *cdev) 786{ 787 device_t bus, dev, vf, *devlist; 788 struct pci_devinfo *dinfo; 789 struct pcicfg_iov *iov; 790 int i, error, devcount; 791 uint32_t iov_ctl; 792 793 mtx_lock(&Giant); 794 dinfo = cdev->si_drv1; 795 iov = dinfo->cfg.iov; 796 dev = dinfo->cfg.dev; 797 bus = device_get_parent(dev); 798 devlist = NULL; 799 800 if (iov->iov_flags & IOV_BUSY) { 801 mtx_unlock(&Giant); 802 return (EBUSY); 803 } 804 805 if (iov->iov_num_vfs == 0) { 806 mtx_unlock(&Giant); 807 return (ECHILD); 808 } 809 810 iov->iov_flags |= IOV_BUSY; 811 812 error = device_get_children(bus, &devlist, &devcount); 813 814 if (error != 0) 815 goto out; 816 817 for (i = 0; i < devcount; i++) { 818 vf = devlist[i]; 819 820 if (!pci_iov_is_child_vf(iov, vf)) 821 continue; 822 823 error = device_detach(vf); 824 if (error != 0) { 825 device_printf(dev, 826 "Could not disable SR-IOV: failed to detach VF %s\n", 827 device_get_nameunit(vf)); 828 goto out; 829 } 830 } 831 832 for (i = 0; i < devcount; i++) { 833 vf = devlist[i]; 834 835 if (pci_iov_is_child_vf(iov, vf)) 836 pci_delete_child(bus, vf); 837 } 838 PCI_IOV_UNINIT(dev); 839 840 iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2); 841 iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE); 842 IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2); 843 IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, 0, 2); 844 845 iov->iov_num_vfs = 0; 846 847 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 848 if (iov->iov_bar[i].res != NULL) { 849 pci_release_resource(bus, dev, SYS_RES_MEMORY, 850 iov->iov_pos + PCIR_SRIOV_BAR(i), 851 iov->iov_bar[i].res); 852 pci_delete_resource(bus, dev, SYS_RES_MEMORY, 853 iov->iov_pos + PCIR_SRIOV_BAR(i)); 854 iov->iov_bar[i].res = NULL; 855 } 856 } 857 858 if (iov->iov_flags & IOV_RMAN_INITED) { 859 rman_fini(&iov->rman); 860 iov->iov_flags &= ~IOV_RMAN_INITED; 861 } 862 863 error = 0; 864out: 865 free(devlist, M_TEMP); 866 iov->iov_flags &= ~IOV_BUSY; 867 mtx_unlock(&Giant); 868 return (error); 869} 870 871static int 872pci_iov_get_schema_ioctl(struct cdev *cdev, struct pci_iov_schema *output) 873{ 874 struct pci_devinfo *dinfo; 875 void *packed; 876 size_t output_len, size; 877 int error; 878 879 packed = NULL; 880 881 mtx_lock(&Giant); 882 dinfo = cdev->si_drv1; 883 packed = nvlist_pack(dinfo->cfg.iov->iov_schema, &size); 884 mtx_unlock(&Giant); 885 886 if (packed == NULL) { 887 error = ENOMEM; 888 goto fail; 889 } 890 891 output_len = output->len; 892 output->len = size; 893 if (size <= output_len) { 894 error = copyout(packed, output->schema, size); 895 896 if (error != 0) 897 goto fail; 898 899 output->error = 0; 900 } else 901 /* 902 * If we return an error then the ioctl code won't copyout 903 * output back to userland, so we flag the error in the struct 904 * instead. 905 */ 906 output->error = EMSGSIZE; 907 908 error = 0; 909 910fail: 911 free(packed, M_NVLIST); 912 913 return (error); 914} 915 916static int 917pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 918 struct thread *td) 919{ 920 921 switch (cmd) { 922 case IOV_CONFIG: 923 return (pci_iov_config(dev, (struct pci_iov_arg *)data)); 924 case IOV_DELETE: 925 return (pci_iov_delete(dev)); 926 case IOV_GET_SCHEMA: 927 return (pci_iov_get_schema_ioctl(dev, 928 (struct pci_iov_schema *)data)); 929 default: 930 return (EINVAL); 931 } 932} 933 934struct resource * 935pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, 936 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 937{ 938 struct pci_devinfo *dinfo; 939 struct pcicfg_iov *iov; 940 struct pci_map *map; 941 struct resource *res; 942 struct resource_list_entry *rle; 943 rman_res_t bar_start, bar_end; 944 pci_addr_t bar_length; 945 int error; 946 947 dinfo = device_get_ivars(child); 948 iov = dinfo->cfg.iov; 949 950 map = pci_find_bar(child, *rid); 951 if (map == NULL) 952 return (NULL); 953 954 bar_length = 1 << map->pm_size; 955 bar_start = map->pm_value; 956 bar_end = bar_start + bar_length - 1; 957 958 /* Make sure that the resource fits the constraints. */ 959 if (bar_start >= end || bar_end <= bar_start || count != 1) 960 return (NULL); 961 962 /* Clamp the resource to the constraints if necessary. */ 963 if (bar_start < start) 964 bar_start = start; 965 if (bar_end > end) 966 bar_end = end; 967 bar_length = bar_end - bar_start + 1; 968 969 res = rman_reserve_resource(&iov->rman, bar_start, bar_end, 970 bar_length, flags, child); 971 if (res == NULL) 972 return (NULL); 973 974 rle = resource_list_add(&dinfo->resources, SYS_RES_MEMORY, *rid, 975 bar_start, bar_end, 1); 976 if (rle == NULL) { 977 rman_release_resource(res); 978 return (NULL); 979 } 980 981 rman_set_rid(res, *rid); 982 983 if (flags & RF_ACTIVE) { 984 error = bus_activate_resource(child, SYS_RES_MEMORY, *rid, res); 985 if (error != 0) { 986 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 987 *rid); 988 rman_release_resource(res); 989 return (NULL); 990 } 991 } 992 rle->res = res; 993 994 return (res); 995} 996 997int 998pci_vf_release_mem_resource(device_t dev, device_t child, int rid, 999 struct resource *r) 1000{ 1001 struct pci_devinfo *dinfo; 1002 struct resource_list_entry *rle; 1003 int error; 1004 1005 dinfo = device_get_ivars(child); 1006 1007 if (rman_get_flags(r) & RF_ACTIVE) { 1008 error = bus_deactivate_resource(child, SYS_RES_MEMORY, rid, r); 1009 if (error != 0) 1010 return (error); 1011 } 1012 1013 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, rid); 1014 if (rle != NULL) { 1015 rle->res = NULL; 1016 resource_list_delete(&dinfo->resources, SYS_RES_MEMORY, 1017 rid); 1018 } 1019 1020 return (rman_release_resource(r)); 1021} 1022 1023