if_patm.c revision 118158 
1/*
2 * Copyright (c) 2003
3 *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
4 * 	All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Author: Hartmut Brandt <harti@freebsd.org>
28 *
29 * Driver for IDT77252 based cards like ProSum's.
30 */
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/patm/if_patm.c 118158 2003-07-29 13:21:57Z harti $");
33
34#include "opt_inet.h"
35#include "opt_natm.h"
36
37#include <sys/types.h>
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/bus.h>
43#include <sys/errno.h>
44#include <sys/conf.h>
45#include <sys/module.h>
46#include <sys/lock.h>
47#include <sys/mutex.h>
48#include <sys/sysctl.h>
49#include <sys/queue.h>
50#include <sys/condvar.h>
51#include <sys/endian.h>
52#include <vm/uma.h>
53
54#include <sys/sockio.h>
55#include <sys/mbuf.h>
56#include <sys/socket.h>
57
58#include <net/if.h>
59#include <net/if_media.h>
60#include <net/if_atm.h>
61#include <net/route.h>
62#include <netinet/in.h>
63#include <netinet/if_atm.h>
64
65#include <machine/bus.h>
66#include <machine/resource.h>
67#include <sys/bus.h>
68#include <sys/rman.h>
69#include <sys/mbpool.h>
70
71#include <dev/utopia/utopia.h>
72#include <dev/patm/idt77252reg.h>
73#include <dev/patm/if_patmvar.h>
74
75static void patm_tst_init(struct patm_softc *sc);
76static void patm_scd_init(struct patm_softc *sc);
77
78/*
79 * Start the card. This assumes the mutex to be held
80 */
81void
82patm_initialize(struct patm_softc *sc)
83{
84	uint32_t cfg;
85	u_int i;
86
87	patm_debug(sc, ATTACH, "configuring...");
88
89	/* clear SRAM */
90	for (i = 0; i < sc->mmap->sram * 1024; i += 4)
91		patm_sram_write4(sc, i, 0, 0, 0, 0);
92	patm_scd_init(sc);
93
94	/* configuration register. Setting NOIDLE makes the timing wrong! */
95	cfg = IDT_CFG_TXFIFO9 | IDT_CFG_RXQ512 | PATM_CFG_VPI |
96	    /* IDT_CFG_NOIDLE | */ sc->mmap->rxtab;
97	if (!(sc->flags & PATM_UNASS))
98		cfg |= IDT_CFG_IDLECLP;
99	patm_nor_write(sc, IDT_NOR_CFG, cfg);
100
101	/* clean all the status queues and the Raw handle */
102	memset(sc->tsq, 0, sc->sq_size);
103
104	/* initialize RSQ */
105	patm_debug(sc, ATTACH, "RSQ %llx", (unsigned long long)sc->rsq_phy);
106	patm_nor_write(sc, IDT_NOR_RSQB, sc->rsq_phy);
107	patm_nor_write(sc, IDT_NOR_RSQT, sc->rsq_phy);
108	patm_nor_write(sc, IDT_NOR_RSQH, 0);
109	sc->rsq_last = PATM_RSQ_SIZE - 1;
110
111	/* initialize TSTB */
112	patm_nor_write(sc, IDT_NOR_TSTB, sc->mmap->tst1base << 2);
113	patm_tst_init(sc);
114
115	/* initialize TSQ */
116	for (i = 0; i < IDT_TSQ_SIZE; i++)
117		sc->tsq[i].stamp = htole32(IDT_TSQE_EMPTY);
118	patm_nor_write(sc, IDT_NOR_TSQB, sc->tsq_phy);
119	patm_nor_write(sc, IDT_NOR_TSQH, 0);
120	patm_nor_write(sc, IDT_NOR_TSQT, 0);
121	sc->tsq_next = sc->tsq;
122
123	/* GP */
124#if BYTE_ORDER == BIG_ENDIAN && 0
125	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_BIGE);
126#else
127	patm_nor_write(sc, IDT_NOR_GP, 0);
128#endif
129
130	/* VPM */
131	patm_nor_write(sc, IDT_NOR_VPM, 0);
132
133	/* RxFIFO */
134	patm_nor_write(sc, IDT_NOR_RXFD,
135	    IDT_RXFD(sc->mmap->rxfifo_addr, sc->mmap->rxfifo_code));
136	patm_nor_write(sc, IDT_NOR_RXFT, 0);
137	patm_nor_write(sc, IDT_NOR_RXFH, 0);
138
139	/* RAWHND */
140	patm_debug(sc, ATTACH, "RWH %llx",
141	    (unsigned long long)sc->rawhnd_phy);
142	patm_nor_write(sc, IDT_NOR_RAWHND, sc->rawhnd_phy);
143
144	/* ABRSTD */
145	patm_nor_write(sc, IDT_NOR_ABRSTD,
146	    IDT_ABRSTD(sc->mmap->abrstd_addr, sc->mmap->abrstd_code));
147	for (i = 0; i < sc->mmap->abrstd_size; i++)
148		patm_sram_write(sc, sc->mmap->abrstd_addr + i, 0);
149	patm_nor_write(sc, IDT_NOR_ABRRQ, 0);
150	patm_nor_write(sc, IDT_NOR_VBRRQ, 0);
151
152	/* rate tables */
153	if (sc->flags & PATM_25M) {
154		for (i = 0; i < patm_rtables_size; i++)
155			patm_sram_write(sc, sc->mmap->rtables + i,
156			    patm_rtables25[i]);
157	} else {
158		for (i = 0; i < patm_rtables_size; i++)
159			patm_sram_write(sc, sc->mmap->rtables + i,
160			    patm_rtables155[i]);
161	}
162	patm_nor_write(sc, IDT_NOR_RTBL, sc->mmap->rtables << 2);
163
164	/* Maximum deficit */
165	patm_nor_write(sc, IDT_NOR_MXDFCT, 32 | IDT_MDFCT_LCI | IDT_MDFCT_LNI);
166
167	/* Free buffer queues */
168	patm_nor_write(sc, IDT_NOR_FBQP0, 0);
169	patm_nor_write(sc, IDT_NOR_FBQP1, 0);
170	patm_nor_write(sc, IDT_NOR_FBQP2, 0);
171	patm_nor_write(sc, IDT_NOR_FBQP3, 0);
172
173	patm_nor_write(sc, IDT_NOR_FBQWP0, 0);
174	patm_nor_write(sc, IDT_NOR_FBQWP1, 0);
175	patm_nor_write(sc, IDT_NOR_FBQWP2, 0);
176	patm_nor_write(sc, IDT_NOR_FBQWP3, 0);
177
178	patm_nor_write(sc, IDT_NOR_FBQS0,
179	    (SMBUF_THRESHOLD << 28) |
180	    (SMBUF_NI_THRESH << 24) |
181	    (SMBUF_CI_THRESH << 20) |
182	    SMBUF_CELLS);
183	patm_nor_write(sc, IDT_NOR_FBQS1,
184	    (LMBUF_THRESHOLD << 28) |
185	    (LMBUF_NI_THRESH << 24) |
186	    (LMBUF_CI_THRESH << 20) |
187	    LMBUF_CELLS);
188	patm_nor_write(sc, IDT_NOR_FBQS2,
189	    (VMBUF_THRESHOLD << 28) | VMBUF_CELLS);
190	patm_nor_write(sc, IDT_NOR_FBQS3, 0);
191
192	/* make SCD0 for UBR0 */
193	if ((sc->scd0 = patm_scd_alloc(sc)) == NULL) {
194		patm_printf(sc, "cannot create UBR0 SCD\n");
195		patm_reset(sc);
196		return;
197	}
198	sc->scd0->q.ifq_maxlen = PATM_DLFT_MAXQ;
199
200	patm_scd_setup(sc, sc->scd0);
201	patm_tct_setup(sc, sc->scd0, NULL);
202
203	patm_debug(sc, ATTACH, "go...");
204
205	sc->utopia.flags &= ~UTP_FL_POLL_CARRIER;
206	sc->ifatm.ifnet.if_flags |= IFF_RUNNING;
207
208	/* enable interrupts, Tx and Rx paths */
209	cfg |= IDT_CFG_RXPTH | IDT_CFG_RXIIMM | IDT_CFG_RAWIE | IDT_CFG_RQFIE |
210	    IDT_CFG_TIMOIE | IDT_CFG_FBIE | IDT_CFG_TXENB | IDT_CFG_TXINT |
211	    IDT_CFG_TXUIE | IDT_CFG_TXSFI | IDT_CFG_PHYIE;
212	patm_nor_write(sc, IDT_NOR_CFG, cfg);
213
214	ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm,
215	    sc->utopia.carrier == UTP_CARR_OK);
216}
217
218/*
219 * External callable start function
220 */
221void
222patm_init(void *p)
223{
224	struct patm_softc *sc = p;
225
226	mtx_lock(&sc->mtx);
227	patm_stop(sc);
228	patm_initialize(sc);
229	mtx_unlock(&sc->mtx);
230}
231
232/*
233 * Stop the interface
234 */
235void
236patm_stop(struct patm_softc *sc)
237{
238	u_int i;
239	struct mbuf *m;
240	struct patm_txmap *map;
241	struct patm_scd *scd;
242
243	sc->ifatm.ifnet.if_flags &= ~IFF_RUNNING;
244	sc->utopia.flags |= UTP_FL_POLL_CARRIER;
245
246	patm_reset(sc);
247
248	mtx_lock(&sc->tst_lock);
249	i = sc->tst_state;
250	sc->tst_state = 0;
251	callout_stop(&sc->tst_callout);
252	mtx_unlock(&sc->tst_lock);
253
254	if (i != 0) {
255		/* this means we are just entering or leaving the timeout.
256		 * wait a little bit. Doing this correctly would be more
257		 * involved */
258		DELAY(1000);
259	}
260
261	/*
262	 * Give any waiters on closing a VCC a chance. They will stop
263	 * to wait if they see that IFF_RUNNING disappeared.
264	 */
265	while (!(cv_waitq_empty(&sc->vcc_cv))) {
266		cv_broadcast(&sc->vcc_cv);
267		DELAY(100);
268	}
269
270	/* free large buffers */
271	patm_debug(sc, ATTACH, "freeing large buffers...");
272	for (i = 0; i < sc->lbuf_max; i++)
273		if (sc->lbufs[i].m != NULL)
274			patm_lbuf_free(sc, &sc->lbufs[i]);
275
276	/* free small buffers that are on the card */
277	patm_debug(sc, ATTACH, "freeing small buffers...");
278	mbp_card_free(sc->sbuf_pool);
279
280	/* free aal0 buffers that are on the card */
281	patm_debug(sc, ATTACH, "freeing aal0 buffers...");
282	mbp_card_free(sc->vbuf_pool);
283
284	/* freeing partial receive chains and reset vcc state */
285	for (i = 0; i < sc->mmap->max_conn; i++) {
286		if (sc->vccs[i] != NULL) {
287			if (sc->vccs[i]->chain != NULL)
288				m_freem(sc->vccs[i]->chain);
289
290			if (sc->vccs[i]->vcc.flags & ATMIO_FLAG_NG) {
291				uma_zfree(sc->vcc_zone, sc->vccs[i]);
292				sc->vccs[i] = NULL;
293			} else {
294				/* keep HARP and NG */
295				sc->vccs[i]->chain = NULL;
296				sc->vccs[i]->last = NULL;
297				sc->vccs[i]->vflags = 0;
298			}
299		}
300	}
301
302	/* stop all active SCDs */
303	while ((scd = LIST_FIRST(&sc->scd_list)) != NULL) {
304		/* free queue packets */
305		for (;;) {
306			_IF_DEQUEUE(&scd->q, m);
307			if (m == NULL)
308				break;
309			m_freem(m);
310		}
311
312		/* free transmitting packets */
313		for (i = 0; i < IDT_TSQE_TAG_SPACE; i++) {
314			if ((m = scd->on_card[i]) != NULL) {
315				scd->on_card[i] = 0;
316				map = m->m_pkthdr.header;
317
318				bus_dmamap_unload(sc->tx_tag, map->map);
319				SLIST_INSERT_HEAD(&sc->tx_maps_free, map, link);
320				m_freem(m);
321			}
322		}
323		patm_scd_free(sc, scd);
324	}
325	sc->scd0 = NULL;
326
327	sc->flags &= ~PATM_CLR;
328
329	/* reset raw cell queue */
330	sc->rawh = NULL;
331
332	ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm,
333	    sc->utopia.carrier == UTP_CARR_OK);
334}
335
336/*
337 * Stop the card and reset it
338 */
339void
340patm_reset(struct patm_softc *sc)
341{
342
343	patm_debug(sc, ATTACH, "resetting...");
344
345	patm_nor_write(sc, IDT_NOR_CFG, IDT_CFG_SWRST);
346	DELAY(200);
347	patm_nor_write(sc, IDT_NOR_CFG, 0);
348	DELAY(200);
349
350	patm_nor_write(sc, IDT_NOR_RSQH, 0);
351	patm_nor_write(sc, IDT_NOR_TSQH, 0);
352
353	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_PHY_RST);
354	DELAY(50);
355	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_EEDO | IDT_GP_EECS);
356	DELAY(50);
357}
358
359/*
360 * Initialize the soft TST to contain only ABR scheduling and
361 * write it to SRAM
362 */
363static void
364patm_tst_init(struct patm_softc *sc)
365{
366	u_int i;
367	u_int base, idle;
368
369	base = sc->mmap->tst1base;
370	idle = sc->mmap->tst1base + sc->mmap->tst_size;
371
372	/* soft */
373	for (i = 0; i < sc->mmap->tst_size - 1; i++)
374		sc->tst_soft[i] = IDT_TST_VBR;
375
376	sc->tst_state = 0;
377	sc->tst_jump[0] = base + sc->mmap->tst_size - 1;
378	sc->tst_jump[1] = idle + sc->mmap->tst_size - 1;
379	sc->tst_base[0] = base;
380	sc->tst_base[1] = idle;
381
382	/* TST1 */
383	for (i = 0; i < sc->mmap->tst_size - 1; i++)
384		patm_sram_write(sc, base + i, IDT_TST_VBR);
385	patm_sram_write(sc, sc->tst_jump[0], IDT_TST_BR | (base << 2));
386
387	/* TST2 */
388	for (i = 0; i < sc->mmap->tst_size - 1; i++)
389		patm_sram_write(sc, idle + i, IDT_TST_VBR);
390	patm_sram_write(sc, sc->tst_jump[1], IDT_TST_BR | (idle << 2));
391
392	sc->tst_free = sc->mmap->tst_size - 1;
393	sc->tst_reserve = sc->tst_free * PATM_TST_RESERVE / 100;
394	sc->bwrem = sc->ifatm.mib.pcr;
395}
396
397/*
398 * Initialize the SCDs. This is done by building a list of all free
399 * SCDs in SRAM. The first word of each potential SCD is used as a
400 * link to the next free SCD. The list is rooted in softc.
401 */
402static void
403patm_scd_init(struct patm_softc *sc)
404{
405	u_int s;	/* SRAM address of current SCD */
406
407	sc->scd_free = 0;
408	for (s = sc->mmap->scd_base; s + 12 <= sc->mmap->tst1base; s += 12) {
409		patm_sram_write(sc, s, sc->scd_free);
410		sc->scd_free = s;
411	}
412}
413
414/*
415 * allocate an SCQ
416 */
417struct patm_scd *
418patm_scd_alloc(struct patm_softc *sc)
419{
420	u_int sram, next;	/* SRAM address of this and next SCD */
421	int error;
422	void *p;
423	struct patm_scd *scd;
424	bus_dmamap_t map;
425	bus_addr_t phy;
426
427	/* get an SCD from the free list */
428	if ((sram = sc->scd_free) == 0)
429		return (NULL);
430	next = patm_sram_read(sc, sram);
431
432	/* allocate memory for the queue and our host stuff */
433	error = bus_dmamem_alloc(sc->scd_tag, &p, BUS_DMA_NOWAIT, &map);
434	if (error != 0)
435		return (NULL);
436	phy = 0x3ff;
437	error = bus_dmamap_load(sc->scd_tag, map, p, sizeof(scd->scq),
438	    patm_load_callback, &phy, BUS_DMA_NOWAIT);
439	if (error != 0) {
440		bus_dmamem_free(sc->scd_tag, p, map);
441		return (NULL);
442	}
443	KASSERT((phy & 0x1ff) == 0, ("SCD not aligned %lx", (u_long)phy));
444
445	scd = p;
446	bzero(scd, sizeof(*scd));
447
448	scd->sram = sram;
449	scd->phy = phy;
450	scd->map = map;
451	scd->space = IDT_SCQ_SIZE;
452	scd->last_tag = IDT_TSQE_TAG_SPACE - 1;
453	scd->q.ifq_maxlen = PATM_TX_IFQLEN;
454
455	/* remove the scd from the free list */
456	sc->scd_free = next;
457	LIST_INSERT_HEAD(&sc->scd_list, scd, link);
458
459	return (scd);
460}
461
462/*
463 * Free an SCD
464 */
465void
466patm_scd_free(struct patm_softc *sc, struct patm_scd *scd)
467{
468
469	LIST_REMOVE(scd, link);
470
471	/* clear SCD and insert link word */
472	patm_sram_write4(sc, scd->sram, sc->scd_free, 0, 0, 0);
473	patm_sram_write4(sc, scd->sram, 0, 0, 0, 0);
474	patm_sram_write4(sc, scd->sram, 0, 0, 0, 0);
475
476	/* put on free list */
477	sc->scd_free = scd->sram;
478
479	/* free memory */
480	bus_dmamap_unload(sc->scd_tag, scd->map);
481	bus_dmamem_free(sc->scd_tag, scd, scd->map);
482}
483
484/*
485 * DMA loading helper function. This function handles the loading of
486 * all one segment DMA maps. The argument is a pointer to a bus_addr_t
487 * which must contain the desired alignment of the address as a bitmap.
488 */
489void
490patm_load_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
491{
492	bus_addr_t *phy = arg;
493
494	if (error)
495		return;
496
497	KASSERT(nsegs == 1,
498	    ("too many segments for DMA: %d", nsegs));
499	KASSERT(segs[0].ds_addr <= 0xffffffffUL,
500	    ("phys addr too large %lx", (u_long)segs[0].ds_addr));
501	KASSERT((segs[0].ds_addr & *phy) == 0,
502	    ("bad alignment %lx:%lx",  (u_long)segs[0].ds_addr, (u_long)*phy));
503
504	*phy = segs[0].ds_addr;
505}
506