if_patm.c revision 117632 
1/*
2 * Copyright (c) 2003
3 *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
4 * 	All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Author: Hartmut Brandt <harti@freebsd.org>
28 *
29 * Driver for IDT77252 based cards like ProSum's.
30 */
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/patm/if_patm.c 117632 2003-07-15 11:57:24Z harti $");
33
34#include "opt_inet.h"
35#include "opt_natm.h"
36
37#include <sys/types.h>
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/bus.h>
43#include <sys/errno.h>
44#include <sys/conf.h>
45#include <sys/module.h>
46#include <sys/lock.h>
47#include <sys/mutex.h>
48#include <sys/sysctl.h>
49#include <sys/queue.h>
50#include <sys/condvar.h>
51#include <sys/endian.h>
52#include <vm/uma.h>
53
54#include <sys/sockio.h>
55#include <sys/mbuf.h>
56#include <sys/socket.h>
57
58#include <net/if.h>
59#include <net/if_media.h>
60#include <net/if_atm.h>
61#include <net/route.h>
62#include <netinet/in.h>
63#include <netinet/if_atm.h>
64
65#include <machine/bus.h>
66#include <machine/resource.h>
67#include <sys/bus.h>
68#include <sys/rman.h>
69#include <sys/mbpool.h>
70
71#include <dev/utopia/utopia.h>
72#include <dev/patm/idt77252reg.h>
73#include <dev/patm/if_patmvar.h>
74
75static void patm_tst_init(struct patm_softc *sc);
76static void patm_scd_init(struct patm_softc *sc);
77
78/*
79 * Start the card. This assumes the mutex to be held
80 */
81void
82patm_initialize(struct patm_softc *sc)
83{
84	uint32_t cfg;
85	u_int i;
86
87	patm_debug(sc, ATTACH, "configuring...");
88
89	/* clear SRAM */
90	for (i = 0; i < sc->mmap->sram * 1024; i += 4)
91		patm_sram_write4(sc, i, 0, 0, 0, 0);
92	patm_scd_init(sc);
93
94	/* configuration register. Setting NOIDLE makes the timing wrong! */
95	cfg = IDT_CFG_TXFIFO9 | IDT_CFG_RXQ512 | PATM_CFG_VPI |
96	    /* IDT_CFG_NOIDLE | */ sc->mmap->rxtab;
97	if (!(sc->flags & PATM_UNASS))
98		cfg |= IDT_CFG_IDLECLP;
99	patm_nor_write(sc, IDT_NOR_CFG, cfg);
100
101	/* clean all the status queues and the Raw handle */
102	memset(sc->tsq, 0, sc->sq_size);
103
104	/* initialize RSQ */
105	patm_debug(sc, ATTACH, "RSQ %llx", (unsigned long long)sc->rsq_phy);
106	patm_nor_write(sc, IDT_NOR_RSQB, sc->rsq_phy);
107	patm_nor_write(sc, IDT_NOR_RSQT, sc->rsq_phy);
108	patm_nor_write(sc, IDT_NOR_RSQH, 0);
109	sc->rsq_last = PATM_RSQ_SIZE - 1;
110
111	/* initialize TSTB */
112	patm_nor_write(sc, IDT_NOR_TSTB, sc->mmap->tst1base << 2);
113	patm_tst_init(sc);
114
115	/* initialize TSQ */
116	for (i = 0; i < IDT_TSQ_SIZE; i++)
117		sc->tsq[i].stamp = htole32(IDT_TSQE_EMPTY);
118	patm_nor_write(sc, IDT_NOR_TSQB, sc->tsq_phy);
119	patm_nor_write(sc, IDT_NOR_TSQH, 0);
120	patm_nor_write(sc, IDT_NOR_TSQT, 0);
121	sc->tsq_next = sc->tsq;
122
123	/* GP */
124#if BYTE_ORDER == BIG_ENDIAN && 0
125	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_BIGE);
126#else
127	patm_nor_write(sc, IDT_NOR_GP, 0);
128#endif
129
130	/* VPM */
131	patm_nor_write(sc, IDT_NOR_VPM, 0);
132
133	/* RxFIFO */
134	patm_nor_write(sc, IDT_NOR_RXFD,
135	    IDT_RXFD(sc->mmap->rxfifo_addr, sc->mmap->rxfifo_code));
136	patm_nor_write(sc, IDT_NOR_RXFT, 0);
137	patm_nor_write(sc, IDT_NOR_RXFH, 0);
138
139	/* RAWHND */
140	patm_debug(sc, ATTACH, "RWH %llx",
141	    (unsigned long long)sc->rawhnd_phy);
142	patm_nor_write(sc, IDT_NOR_RAWHND, sc->rawhnd_phy);
143
144	/* ABRSTD */
145	patm_nor_write(sc, IDT_NOR_ABRSTD,
146	    IDT_ABRSTD(sc->mmap->abrstd_addr, sc->mmap->abrstd_code));
147	for (i = 0; i < sc->mmap->abrstd_size; i++)
148		patm_sram_write(sc, sc->mmap->abrstd_addr + i, 0);
149	patm_nor_write(sc, IDT_NOR_ABRRQ, 0);
150	patm_nor_write(sc, IDT_NOR_VBRRQ, 0);
151
152	/* rate tables */
153	if (sc->flags & PATM_25M) {
154		for (i = 0; i < patm_rtables_size; i++)
155			patm_sram_write(sc, sc->mmap->rtables + i,
156			    patm_rtables25[i]);
157	} else {
158		for (i = 0; i < patm_rtables_size; i++)
159			patm_sram_write(sc, sc->mmap->rtables + i,
160			    patm_rtables155[i]);
161	}
162	patm_nor_write(sc, IDT_NOR_RTBL, sc->mmap->rtables << 2);
163
164	/* Maximum deficit */
165	patm_nor_write(sc, IDT_NOR_MXDFCT, 32 | IDT_MDFCT_LCI | IDT_MDFCT_LNI);
166
167	/* Free buffer queues */
168	patm_nor_write(sc, IDT_NOR_FBQP0, 0);
169	patm_nor_write(sc, IDT_NOR_FBQP1, 0);
170	patm_nor_write(sc, IDT_NOR_FBQP2, 0);
171	patm_nor_write(sc, IDT_NOR_FBQP3, 0);
172
173	patm_nor_write(sc, IDT_NOR_FBQWP0, 0);
174	patm_nor_write(sc, IDT_NOR_FBQWP1, 0);
175	patm_nor_write(sc, IDT_NOR_FBQWP2, 0);
176	patm_nor_write(sc, IDT_NOR_FBQWP3, 0);
177
178	patm_nor_write(sc, IDT_NOR_FBQS0,
179	    (SMBUF_THRESHOLD << 28) |
180	    (SMBUF_NI_THRESH << 24) |
181	    (SMBUF_CI_THRESH << 20) |
182	    SMBUF_CELLS);
183	patm_nor_write(sc, IDT_NOR_FBQS1,
184	    (LMBUF_THRESHOLD << 28) |
185	    (LMBUF_NI_THRESH << 24) |
186	    (LMBUF_CI_THRESH << 20) |
187	    LMBUF_CELLS);
188	patm_nor_write(sc, IDT_NOR_FBQS2,
189	    (VMBUF_THRESHOLD << 28) | VMBUF_CELLS);
190	patm_nor_write(sc, IDT_NOR_FBQS3, 0);
191
192	/* make SCD0 for UBR0 */
193	if ((sc->scd0 = patm_scd_alloc(sc)) == NULL) {
194		patm_printf(sc, "cannot create UBR0 SCD\n");
195		patm_reset(sc);
196		return;
197	}
198	sc->scd0->q.ifq_maxlen = PATM_DLFT_MAXQ;
199
200	patm_scd_setup(sc, sc->scd0);
201	patm_tct_setup(sc, sc->scd0, NULL);
202
203	patm_debug(sc, ATTACH, "go...");
204
205	sc->utopia.flags &= ~UTP_FL_POLL_CARRIER;
206	sc->ifatm.ifnet.if_flags |= IFF_RUNNING;
207
208	/* enable interrupts, Tx and Rx paths */
209	cfg |= IDT_CFG_RXPTH | IDT_CFG_RXIIMM | IDT_CFG_RAWIE | IDT_CFG_RQFIE |
210	    IDT_CFG_TIMOIE | IDT_CFG_FBIE | IDT_CFG_TXENB | IDT_CFG_TXINT |
211	    IDT_CFG_TXUIE | IDT_CFG_TXSFI | IDT_CFG_PHYIE;
212	patm_nor_write(sc, IDT_NOR_CFG, cfg);
213}
214
215/*
216 * External callable start function
217 */
218void
219patm_init(void *p)
220{
221	struct patm_softc *sc = p;
222
223	mtx_lock(&sc->mtx);
224	patm_stop(sc);
225	patm_initialize(sc);
226	mtx_unlock(&sc->mtx);
227}
228
229/*
230 * Stop the interface
231 */
232void
233patm_stop(struct patm_softc *sc)
234{
235	u_int i;
236	struct mbuf *m;
237	struct patm_txmap *map;
238	struct patm_scd *scd;
239
240	sc->ifatm.ifnet.if_flags &= ~IFF_RUNNING;
241	sc->utopia.flags |= UTP_FL_POLL_CARRIER;
242
243	patm_reset(sc);
244
245	mtx_lock(&sc->tst_lock);
246	i = sc->tst_state;
247	sc->tst_state = 0;
248	callout_stop(&sc->tst_callout);
249	mtx_unlock(&sc->tst_lock);
250
251	if (i != 0) {
252		/* this means we are just entering or leaving the timeout.
253		 * wait a little bit. Doing this correctly would be more
254		 * involved */
255		DELAY(1000);
256	}
257
258	/*
259	 * Give any waiters on closing a VCC a chance. They will stop
260	 * to wait if they see that IFF_RUNNING disappeared.
261	 */
262	while (!(cv_waitq_empty(&sc->vcc_cv))) {
263		cv_broadcast(&sc->vcc_cv);
264		DELAY(100);
265	}
266
267	/* free large buffers */
268	patm_debug(sc, ATTACH, "freeing large buffers...");
269	for (i = 0; i < sc->lbuf_max; i++)
270		if (sc->lbufs[i].m != NULL)
271			patm_lbuf_free(sc, &sc->lbufs[i]);
272
273	/* free small buffers that are on the card */
274	patm_debug(sc, ATTACH, "freeing small buffers...");
275	mbp_card_free(sc->sbuf_pool);
276
277	/* free aal0 buffers that are on the card */
278	patm_debug(sc, ATTACH, "freeing aal0 buffers...");
279	mbp_card_free(sc->vbuf_pool);
280
281	/* freeing partial receive chains and reset vcc state */
282	for (i = 0; i < sc->mmap->max_conn; i++) {
283		if (sc->vccs[i] != NULL) {
284			if (sc->vccs[i]->chain != NULL)
285				m_freem(sc->vccs[i]->chain);
286
287			if (sc->vccs[i]->vcc.flags & ATMIO_FLAG_NG) {
288				uma_zfree(sc->vcc_zone, sc->vccs[i]);
289				sc->vccs[i] = NULL;
290			} else {
291				/* keep HARP and NG */
292				sc->vccs[i]->chain = NULL;
293				sc->vccs[i]->last = NULL;
294				sc->vccs[i]->vflags = 0;
295			}
296		}
297	}
298
299	/* stop all active SCDs */
300	while ((scd = LIST_FIRST(&sc->scd_list)) != NULL) {
301		/* free queue packets */
302		for (;;) {
303			_IF_DEQUEUE(&scd->q, m);
304			if (m == NULL)
305				break;
306			m_freem(m);
307		}
308
309		/* free transmitting packets */
310		for (i = 0; i < IDT_TSQE_TAG_SPACE; i++) {
311			if ((m = scd->on_card[i]) != NULL) {
312				scd->on_card[i] = 0;
313				map = m->m_pkthdr.header;
314
315				bus_dmamap_unload(sc->tx_tag, map->map);
316				SLIST_INSERT_HEAD(&sc->tx_maps_free, map, link);
317				m_freem(m);
318			}
319		}
320		patm_scd_free(sc, scd);
321	}
322	sc->scd0 = NULL;
323
324	sc->flags &= ~PATM_CLR;
325
326	/* reset raw cell queue */
327	sc->rawh = NULL;
328}
329
330/*
331 * Stop the card and reset it
332 */
333void
334patm_reset(struct patm_softc *sc)
335{
336
337	patm_debug(sc, ATTACH, "resetting...");
338
339	patm_nor_write(sc, IDT_NOR_CFG, IDT_CFG_SWRST);
340	DELAY(200);
341	patm_nor_write(sc, IDT_NOR_CFG, 0);
342	DELAY(200);
343
344	patm_nor_write(sc, IDT_NOR_RSQH, 0);
345	patm_nor_write(sc, IDT_NOR_TSQH, 0);
346
347	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_PHY_RST);
348	DELAY(50);
349	patm_nor_write(sc, IDT_NOR_GP, IDT_GP_EEDO | IDT_GP_EECS);
350	DELAY(50);
351}
352
353/*
354 * Initialize the soft TST to contain only ABR scheduling and
355 * write it to SRAM
356 */
357static void
358patm_tst_init(struct patm_softc *sc)
359{
360	u_int i;
361	u_int base, idle;
362
363	base = sc->mmap->tst1base;
364	idle = sc->mmap->tst1base + sc->mmap->tst_size;
365
366	/* soft */
367	for (i = 0; i < sc->mmap->tst_size - 1; i++)
368		sc->tst_soft[i] = IDT_TST_VBR;
369
370	sc->tst_state = 0;
371	sc->tst_jump[0] = base + sc->mmap->tst_size - 1;
372	sc->tst_jump[1] = idle + sc->mmap->tst_size - 1;
373	sc->tst_base[0] = base;
374	sc->tst_base[1] = idle;
375
376	/* TST1 */
377	for (i = 0; i < sc->mmap->tst_size - 1; i++)
378		patm_sram_write(sc, base + i, IDT_TST_VBR);
379	patm_sram_write(sc, sc->tst_jump[0], IDT_TST_BR | (base << 2));
380
381	/* TST2 */
382	for (i = 0; i < sc->mmap->tst_size - 1; i++)
383		patm_sram_write(sc, idle + i, IDT_TST_VBR);
384	patm_sram_write(sc, sc->tst_jump[1], IDT_TST_BR | (idle << 2));
385
386	sc->tst_free = sc->mmap->tst_size - 1;
387	sc->tst_reserve = sc->tst_free * PATM_TST_RESERVE / 100;
388	sc->bwrem = sc->ifatm.mib.pcr;
389}
390
391/*
392 * Initialize the SCDs. This is done by building a list of all free
393 * SCDs in SRAM. The first word of each potential SCD is used as a
394 * link to the next free SCD. The list is rooted in softc.
395 */
396static void
397patm_scd_init(struct patm_softc *sc)
398{
399	u_int s;	/* SRAM address of current SCD */
400
401	sc->scd_free = 0;
402	for (s = sc->mmap->scd_base; s + 12 <= sc->mmap->tst1base; s += 12) {
403		patm_sram_write(sc, s, sc->scd_free);
404		sc->scd_free = s;
405	}
406}
407
408/*
409 * allocate an SCQ
410 */
411struct patm_scd *
412patm_scd_alloc(struct patm_softc *sc)
413{
414	u_int sram, next;	/* SRAM address of this and next SCD */
415	int error;
416	void *p;
417	struct patm_scd *scd;
418	bus_dmamap_t map;
419	bus_addr_t phy;
420
421	/* get an SCD from the free list */
422	if ((sram = sc->scd_free) == 0)
423		return (NULL);
424	next = patm_sram_read(sc, sram);
425
426	/* allocate memory for the queue and our host stuff */
427	error = bus_dmamem_alloc(sc->scd_tag, &p, BUS_DMA_NOWAIT, &map);
428	if (error != 0)
429		return (NULL);
430	phy = 0x3ff;
431	error = bus_dmamap_load(sc->scd_tag, map, p, sizeof(scd->scq),
432	    patm_load_callback, &phy, BUS_DMA_NOWAIT);
433	if (error != 0) {
434		bus_dmamem_free(sc->scd_tag, p, map);
435		return (NULL);
436	}
437	KASSERT((phy & 0x1ff) == 0, ("SCD not aligned %lx", (u_long)phy));
438
439	scd = p;
440	bzero(scd, sizeof(*scd));
441
442	scd->sram = sram;
443	scd->phy = phy;
444	scd->map = map;
445	scd->space = IDT_SCQ_SIZE;
446	scd->last_tag = IDT_TSQE_TAG_SPACE - 1;
447	scd->q.ifq_maxlen = PATM_TX_IFQLEN;
448
449	/* remove the scd from the free list */
450	sc->scd_free = next;
451	LIST_INSERT_HEAD(&sc->scd_list, scd, link);
452
453	return (scd);
454}
455
456/*
457 * Free an SCD
458 */
459void
460patm_scd_free(struct patm_softc *sc, struct patm_scd *scd)
461{
462
463	LIST_REMOVE(scd, link);
464
465	/* clear SCD and insert link word */
466	patm_sram_write4(sc, scd->sram, sc->scd_free, 0, 0, 0);
467	patm_sram_write4(sc, scd->sram, 0, 0, 0, 0);
468	patm_sram_write4(sc, scd->sram, 0, 0, 0, 0);
469
470	/* put on free list */
471	sc->scd_free = scd->sram;
472
473	/* free memory */
474	bus_dmamap_unload(sc->scd_tag, scd->map);
475	bus_dmamem_free(sc->scd_tag, scd, scd->map);
476}
477
478/*
479 * DMA loading helper function. This function handles the loading of
480 * all one segment DMA maps. The argument is a pointer to a bus_addr_t
481 * which must contain the desired alignment of the address as a bitmap.
482 */
483void
484patm_load_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
485{
486	bus_addr_t *phy = arg;
487
488	if (error)
489		return;
490
491	KASSERT(nsegs == 1,
492	    ("too many segments for DMA: %d", nsegs));
493	KASSERT(segs[0].ds_addr <= 0xffffffffUL,
494	    ("phys addr too large %lx", (u_long)segs[0].ds_addr));
495	KASSERT((segs[0].ds_addr & *phy) == 0,
496	    ("bad alignment %lx:%lx",  (u_long)segs[0].ds_addr, (u_long)*phy));
497
498	*phy = segs[0].ds_addr;
499}
500