1231437Sluigi/*- 2252869Sdelphij * Copyright (C) 2013 Emulex 3231437Sluigi * All rights reserved. 4231437Sluigi * 5231437Sluigi * Redistribution and use in source and binary forms, with or without 6231437Sluigi * modification, are permitted provided that the following conditions are met: 7231437Sluigi * 8231437Sluigi * 1. Redistributions of source code must retain the above copyright notice, 9231437Sluigi * this list of conditions and the following disclaimer. 10231437Sluigi * 11231437Sluigi * 2. Redistributions in binary form must reproduce the above copyright 12231437Sluigi * notice, this list of conditions and the following disclaimer in the 13231437Sluigi * documentation and/or other materials provided with the distribution. 14231437Sluigi * 15231437Sluigi * 3. Neither the name of the Emulex Corporation nor the names of its 16231437Sluigi * contributors may be used to endorse or promote products derived from 17231437Sluigi * this software without specific prior written permission. 18231437Sluigi * 19231437Sluigi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20231437Sluigi * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21231437Sluigi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22231437Sluigi * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23231437Sluigi * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24231437Sluigi * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25231437Sluigi * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26231437Sluigi * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27231437Sluigi * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28231437Sluigi * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29231437Sluigi * POSSIBILITY OF SUCH DAMAGE. 30231437Sluigi * 31231437Sluigi * Contact Information: 32231437Sluigi * freebsd-drivers@emulex.com 33231437Sluigi * 34231437Sluigi * Emulex 35231437Sluigi * 3333 Susan Street 36231437Sluigi * Costa Mesa, CA 92626 37231437Sluigi */ 38231437Sluigi 39231437Sluigi/* $FreeBSD: stable/11/sys/dev/oce/oce_hw.h 338938 2018-09-25 23:48:43Z jpaetzel $ */ 40231437Sluigi 41231437Sluigi#include <sys/types.h> 42231437Sluigi 43231437Sluigi#undef _BIG_ENDIAN /* TODO */ 44231437Sluigi#pragma pack(1) 45231437Sluigi 46231437Sluigi#define OC_CNA_GEN2 0x2 47231437Sluigi#define OC_CNA_GEN3 0x3 48231437Sluigi#define DEVID_TIGERSHARK 0x700 49231437Sluigi#define DEVID_TOMCAT 0x710 50231437Sluigi 51231437Sluigi/* PCI CSR offsets */ 52231437Sluigi#define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 53231437Sluigi#define PCICFG_SEMAPHORE 0xbc 54231437Sluigi#define PCICFG_SOFT_RESET 0x5c 55231437Sluigi#define PCICFG_UE_STATUS_HI_MASK 0xac 56231437Sluigi#define PCICFG_UE_STATUS_LO_MASK 0xa8 57231437Sluigi#define PCICFG_ONLINE0 0xb0 58231437Sluigi#define PCICFG_ONLINE1 0xb4 59231437Sluigi#define INTR_EN 0x20000000 60231437Sluigi#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61231437Sluigi 62257007Sdelphij 63257007Sdelphij/********* UE Status and Mask Registers ***/ 64257007Sdelphij#define PCICFG_UE_STATUS_LOW 0xA0 65257007Sdelphij#define PCICFG_UE_STATUS_HIGH 0xA4 66257007Sdelphij#define PCICFG_UE_STATUS_LOW_MASK 0xA8 67257007Sdelphij 68257007Sdelphij/* Lancer SLIPORT registers */ 69257007Sdelphij#define SLIPORT_STATUS_OFFSET 0x404 70257007Sdelphij#define SLIPORT_CONTROL_OFFSET 0x408 71257007Sdelphij#define SLIPORT_ERROR1_OFFSET 0x40C 72257007Sdelphij#define SLIPORT_ERROR2_OFFSET 0x410 73257007Sdelphij#define PHYSDEV_CONTROL_OFFSET 0x414 74257007Sdelphij 75257007Sdelphij#define SLIPORT_STATUS_ERR_MASK 0x80000000 76257007Sdelphij#define SLIPORT_STATUS_DIP_MASK 0x02000000 77257007Sdelphij#define SLIPORT_STATUS_RN_MASK 0x01000000 78257007Sdelphij#define SLIPORT_STATUS_RDY_MASK 0x00800000 79257007Sdelphij#define SLI_PORT_CONTROL_IP_MASK 0x08000000 80257007Sdelphij#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 81257007Sdelphij#define PHYSDEV_CONTROL_DD_MASK 0x00000004 82257007Sdelphij#define PHYSDEV_CONTROL_INP_MASK 0x40000000 83257007Sdelphij 84257007Sdelphij#define SLIPORT_ERROR_NO_RESOURCE1 0x2 85257007Sdelphij#define SLIPORT_ERROR_NO_RESOURCE2 0x9 86231437Sluigi/* CSR register offsets */ 87231437Sluigi#define MPU_EP_CONTROL 0 88231437Sluigi#define MPU_EP_SEMAPHORE_BE3 0xac 89231437Sluigi#define MPU_EP_SEMAPHORE_XE201 0x400 90252869Sdelphij#define MPU_EP_SEMAPHORE_SH 0x94 91231437Sluigi#define PCICFG_INTR_CTRL 0xfc 92231437Sluigi#define HOSTINTR_MASK (1 << 29) 93231437Sluigi#define HOSTINTR_PFUNC_SHIFT 26 94231437Sluigi#define HOSTINTR_PFUNC_MASK 7 95231437Sluigi 96231437Sluigi/* POST status reg struct */ 97231437Sluigi#define POST_STAGE_POWER_ON_RESET 0x00 98231437Sluigi#define POST_STAGE_AWAITING_HOST_RDY 0x01 99231437Sluigi#define POST_STAGE_HOST_RDY 0x02 100231437Sluigi#define POST_STAGE_CHIP_RESET 0x03 101231437Sluigi#define POST_STAGE_ARMFW_READY 0xc000 102231437Sluigi#define POST_STAGE_ARMFW_UE 0xf000 103231437Sluigi 104231437Sluigi/* DOORBELL registers */ 105231437Sluigi#define PD_RXULP_DB 0x0100 106231437Sluigi#define PD_TXULP_DB 0x0060 107231437Sluigi#define DB_RQ_ID_MASK 0x3FF 108231437Sluigi 109231437Sluigi#define PD_CQ_DB 0x0120 110231437Sluigi#define PD_EQ_DB PD_CQ_DB 111231437Sluigi#define PD_MPU_MBOX_DB 0x0160 112231437Sluigi#define PD_MQ_DB 0x0140 113231437Sluigi 114338938Sjpaetzel#define DB_OFFSET 0xc0 115338938Sjpaetzel#define DB_LRO_RQ_ID_MASK 0x7FF 116338938Sjpaetzel 117231437Sluigi/* EQE completion types */ 118231437Sluigi#define EQ_MINOR_CODE_COMPLETION 0x00 119231437Sluigi#define EQ_MINOR_CODE_OTHER 0x01 120231437Sluigi#define EQ_MAJOR_CODE_COMPLETION 0x00 121231437Sluigi 122231437Sluigi/* Link Status field values */ 123231437Sluigi#define PHY_LINK_FAULT_NONE 0x0 124231437Sluigi#define PHY_LINK_FAULT_LOCAL 0x01 125231437Sluigi#define PHY_LINK_FAULT_REMOTE 0x02 126231437Sluigi 127231437Sluigi#define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 128231437Sluigi#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 129231437Sluigi#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 130231437Sluigi#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 131231437Sluigi#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 132231437Sluigi 133231437Sluigi#define PHY_LINK_DUPLEX_NONE 0x0 134231437Sluigi#define PHY_LINK_DUPLEX_HALF 0x1 135231437Sluigi#define PHY_LINK_DUPLEX_FULL 0x2 136231437Sluigi 137231437Sluigi#define NTWK_PORT_A 0x0 /* (Port A) */ 138231437Sluigi#define NTWK_PORT_B 0x1 /* (Port B) */ 139231437Sluigi 140231437Sluigi#define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 141231437Sluigi#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 142231437Sluigi#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 143231437Sluigi#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 144231437Sluigi#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 145231437Sluigi 146231437Sluigi/* Hardware Address types */ 147231437Sluigi#define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 148231437Sluigi#define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 149231437Sluigi#define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 150231437Sluigi#define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 151231437Sluigi#define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 152231437Sluigi 153231437Sluigi/* CREATE_IFACE capability and cap_en flags */ 154231437Sluigi#define MBX_RX_IFACE_FLAGS_RSS 0x4 155231437Sluigi#define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 156231437Sluigi#define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 157231437Sluigi#define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 158231437Sluigi#define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 159231437Sluigi#define MBX_RX_IFACE_FLAGS_VLAN 0x100 160231437Sluigi#define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 161231437Sluigi#define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 162231437Sluigi#define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 163231437Sluigi#define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 164231437Sluigi#define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 165231437Sluigi#define MBX_RX_IFACE_FLAGS_HDS 0x4000 166231437Sluigi#define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 167231437Sluigi#define MBX_RX_IFACE_FLAGS_VMQ 0x10000 168231437Sluigi#define MBX_RX_IFACE_FLAGS_NETQ 0x20000 169231437Sluigi#define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 170231437Sluigi#define MBX_RX_IFACE_FLAGS_LSO 0x80000 171231437Sluigi#define MBX_RX_IFACE_FLAGS_LRO 0x100000 172231437Sluigi 173231437Sluigi#define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 174231437Sluigi#define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 175231437Sluigi#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 176231437Sluigi#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 177231437Sluigi 178231437Sluigi#define MBX_DB_READY_BIT 0x1 179231437Sluigi#define MBX_DB_HI_BIT 0x2 180231437Sluigi#define ASYNC_EVENT_CODE_LINK_STATE 0x1 181231437Sluigi#define ASYNC_EVENT_LINK_UP 0x1 182231437Sluigi#define ASYNC_EVENT_LINK_DOWN 0x0 183231879Sluigi#define ASYNC_EVENT_GRP5 0x5 184247880Sdelphij#define ASYNC_EVENT_CODE_DEBUG 0x6 185231879Sluigi#define ASYNC_EVENT_PVID_STATE 0x3 186338938Sjpaetzel#define ASYNC_EVENT_OS2BMC 0x5 187247880Sdelphij#define ASYNC_EVENT_DEBUG_QNQ 0x1 188247880Sdelphij#define ASYNC_EVENT_CODE_SLIPORT 0x11 189231879Sluigi#define VLAN_VID_MASK 0x0FFF 190231437Sluigi 191231437Sluigi/* port link_status */ 192231437Sluigi#define ASYNC_EVENT_LOGICAL 0x02 193231437Sluigi 194231437Sluigi/* Logical Link Status */ 195231437Sluigi#define NTWK_LOGICAL_LINK_DOWN 0 196231437Sluigi#define NTWK_LOGICAL_LINK_UP 1 197231437Sluigi 198231437Sluigi/* Rx filter bits */ 199231437Sluigi#define NTWK_RX_FILTER_IP_CKSUM 0x1 200231437Sluigi#define NTWK_RX_FILTER_TCP_CKSUM 0x2 201231437Sluigi#define NTWK_RX_FILTER_UDP_CKSUM 0x4 202231437Sluigi#define NTWK_RX_FILTER_STRIP_CRC 0x8 203231437Sluigi 204231437Sluigi/* max SGE per mbx */ 205231437Sluigi#define MAX_MBX_SGE 19 206231437Sluigi 207231437Sluigi/* Max multicast filter size*/ 208231437Sluigi#define OCE_MAX_MC_FILTER_SIZE 64 209231437Sluigi 210231437Sluigi/* PCI SLI (Service Level Interface) capabilities register */ 211231437Sluigi#define OCE_INTF_REG_OFFSET 0x58 212231437Sluigi#define OCE_INTF_VALID_SIG 6 /* register's signature */ 213231437Sluigi#define OCE_INTF_FUNC_RESET_REQD 1 214231437Sluigi#define OCE_INTF_HINT1_NOHINT 0 215231437Sluigi#define OCE_INTF_HINT1_SEMAINIT 1 216231437Sluigi#define OCE_INTF_HINT1_STATCTRL 2 217231437Sluigi#define OCE_INTF_IF_TYPE_0 0 218231437Sluigi#define OCE_INTF_IF_TYPE_1 1 219231437Sluigi#define OCE_INTF_IF_TYPE_2 2 220231437Sluigi#define OCE_INTF_IF_TYPE_3 3 221231437Sluigi#define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 222231437Sluigi#define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 223231437Sluigi#define OCE_INTF_PHYS_FUNC 0 224231437Sluigi#define OCE_INTF_VIRT_FUNC 1 225231437Sluigi#define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 226231437Sluigi#define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 227231437Sluigi#define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 228231437Sluigi#define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 229231437Sluigi 230231437Sluigi#define NIC_WQE_SIZE 16 231231437Sluigi#define NIC_UNICAST 0x00 232231437Sluigi#define NIC_MULTICAST 0x01 233231437Sluigi#define NIC_BROADCAST 0x02 234231437Sluigi 235231437Sluigi#define NIC_HDS_NO_SPLIT 0x00 236231437Sluigi#define NIC_HDS_SPLIT_L3PL 0x01 237231437Sluigi#define NIC_HDS_SPLIT_L4PL 0x02 238231437Sluigi 239231437Sluigi#define NIC_WQ_TYPE_FORWARDING 0x01 240231437Sluigi#define NIC_WQ_TYPE_STANDARD 0x02 241231437Sluigi#define NIC_WQ_TYPE_LOW_LATENCY 0x04 242231437Sluigi 243231437Sluigi#define OCE_RESET_STATS 1 244231437Sluigi#define OCE_RETAIN_STATS 0 245231437Sluigi#define OCE_TXP_SW_SZ 48 246231437Sluigi 247231437Sluigitypedef union pci_sli_intf_u { 248231437Sluigi uint32_t dw0; 249231437Sluigi struct { 250231437Sluigi#ifdef _BIG_ENDIAN 251231437Sluigi uint32_t sli_valid:3; 252231437Sluigi uint32_t sli_hint2:5; 253231437Sluigi uint32_t sli_hint1:8; 254231437Sluigi uint32_t sli_if_type:4; 255231437Sluigi uint32_t sli_family:4; 256231437Sluigi uint32_t sli_rev:4; 257231437Sluigi uint32_t rsv0:3; 258231437Sluigi uint32_t sli_func_type:1; 259231437Sluigi#else 260231437Sluigi uint32_t sli_func_type:1; 261231437Sluigi uint32_t rsv0:3; 262231437Sluigi uint32_t sli_rev:4; 263231437Sluigi uint32_t sli_family:4; 264231437Sluigi uint32_t sli_if_type:4; 265231437Sluigi uint32_t sli_hint1:8; 266231437Sluigi uint32_t sli_hint2:5; 267231437Sluigi uint32_t sli_valid:3; 268231437Sluigi#endif 269231437Sluigi } bits; 270231437Sluigi} pci_sli_intf_t; 271231437Sluigi 272231437Sluigi 273231437Sluigi 274231437Sluigi/* physical address structure to be used in MBX */ 275231437Sluigistruct phys_addr { 276231437Sluigi /* dw0 */ 277231437Sluigi uint32_t lo; 278231437Sluigi /* dw1 */ 279231437Sluigi uint32_t hi; 280231437Sluigi}; 281231437Sluigi 282231437Sluigi 283231437Sluigi 284231437Sluigitypedef union pcicfg_intr_ctl_u { 285231437Sluigi uint32_t dw0; 286231437Sluigi struct { 287231437Sluigi#ifdef _BIG_ENDIAN 288231437Sluigi uint32_t winselect:2; 289231437Sluigi uint32_t hostintr:1; 290231437Sluigi uint32_t pfnum:3; 291231437Sluigi uint32_t vf_cev_int_line_en:1; 292231437Sluigi uint32_t winaddr:23; 293231437Sluigi uint32_t membarwinen:1; 294231437Sluigi#else 295231437Sluigi uint32_t membarwinen:1; 296231437Sluigi uint32_t winaddr:23; 297231437Sluigi uint32_t vf_cev_int_line_en:1; 298231437Sluigi uint32_t pfnum:3; 299231437Sluigi uint32_t hostintr:1; 300231437Sluigi uint32_t winselect:2; 301231437Sluigi#endif 302231437Sluigi } bits; 303231437Sluigi} pcicfg_intr_ctl_t; 304231437Sluigi 305231437Sluigi 306231437Sluigi 307231437Sluigi 308231437Sluigitypedef union pcicfg_semaphore_u { 309231437Sluigi uint32_t dw0; 310231437Sluigi struct { 311231437Sluigi#ifdef _BIG_ENDIAN 312231437Sluigi uint32_t rsvd:31; 313231437Sluigi uint32_t lock:1; 314231437Sluigi#else 315231437Sluigi uint32_t lock:1; 316231437Sluigi uint32_t rsvd:31; 317231437Sluigi#endif 318231437Sluigi } bits; 319231437Sluigi} pcicfg_semaphore_t; 320231437Sluigi 321231437Sluigi 322231437Sluigi 323231437Sluigi 324231437Sluigitypedef union pcicfg_soft_reset_u { 325231437Sluigi uint32_t dw0; 326231437Sluigi struct { 327231437Sluigi#ifdef _BIG_ENDIAN 328231437Sluigi uint32_t nec_ll_rcvdetect:8; 329231437Sluigi uint32_t dbg_all_reqs_62_49:14; 330231437Sluigi uint32_t scratchpad0:1; 331231437Sluigi uint32_t exception_oe:1; 332231437Sluigi uint32_t soft_reset:1; 333231437Sluigi uint32_t rsvd0:7; 334231437Sluigi#else 335231437Sluigi uint32_t rsvd0:7; 336231437Sluigi uint32_t soft_reset:1; 337231437Sluigi uint32_t exception_oe:1; 338231437Sluigi uint32_t scratchpad0:1; 339231437Sluigi uint32_t dbg_all_reqs_62_49:14; 340231437Sluigi uint32_t nec_ll_rcvdetect:8; 341231437Sluigi#endif 342231437Sluigi } bits; 343231437Sluigi} pcicfg_soft_reset_t; 344231437Sluigi 345231437Sluigi 346231437Sluigi 347231437Sluigi 348231437Sluigitypedef union pcicfg_online1_u { 349231437Sluigi uint32_t dw0; 350231437Sluigi struct { 351231437Sluigi#ifdef _BIG_ENDIAN 352231437Sluigi uint32_t host8_online:1; 353231437Sluigi uint32_t host7_online:1; 354231437Sluigi uint32_t host6_online:1; 355231437Sluigi uint32_t host5_online:1; 356231437Sluigi uint32_t host4_online:1; 357231437Sluigi uint32_t host3_online:1; 358231437Sluigi uint32_t host2_online:1; 359231437Sluigi uint32_t ipc_online:1; 360231437Sluigi uint32_t arm_online:1; 361231437Sluigi uint32_t txp_online:1; 362231437Sluigi uint32_t xaui_online:1; 363231437Sluigi uint32_t rxpp_online:1; 364231437Sluigi uint32_t txpb_online:1; 365231437Sluigi uint32_t rr_online:1; 366231437Sluigi uint32_t pmem_online:1; 367231437Sluigi uint32_t pctl1_online:1; 368231437Sluigi uint32_t pctl0_online:1; 369231437Sluigi uint32_t pcs1online_online:1; 370231437Sluigi uint32_t mpu_iram_online:1; 371231437Sluigi uint32_t pcs0online_online:1; 372231437Sluigi uint32_t mgmt_mac_online:1; 373231437Sluigi uint32_t lpcmemhost_online:1; 374231437Sluigi#else 375231437Sluigi uint32_t lpcmemhost_online:1; 376231437Sluigi uint32_t mgmt_mac_online:1; 377231437Sluigi uint32_t pcs0online_online:1; 378231437Sluigi uint32_t mpu_iram_online:1; 379231437Sluigi uint32_t pcs1online_online:1; 380231437Sluigi uint32_t pctl0_online:1; 381231437Sluigi uint32_t pctl1_online:1; 382231437Sluigi uint32_t pmem_online:1; 383231437Sluigi uint32_t rr_online:1; 384231437Sluigi uint32_t txpb_online:1; 385231437Sluigi uint32_t rxpp_online:1; 386231437Sluigi uint32_t xaui_online:1; 387231437Sluigi uint32_t txp_online:1; 388231437Sluigi uint32_t arm_online:1; 389231437Sluigi uint32_t ipc_online:1; 390231437Sluigi uint32_t host2_online:1; 391231437Sluigi uint32_t host3_online:1; 392231437Sluigi uint32_t host4_online:1; 393231437Sluigi uint32_t host5_online:1; 394231437Sluigi uint32_t host6_online:1; 395231437Sluigi uint32_t host7_online:1; 396231437Sluigi uint32_t host8_online:1; 397231437Sluigi#endif 398231437Sluigi } bits; 399231437Sluigi} pcicfg_online1_t; 400231437Sluigi 401231437Sluigi 402231437Sluigi 403231437Sluigitypedef union mpu_ep_semaphore_u { 404231437Sluigi uint32_t dw0; 405231437Sluigi struct { 406231437Sluigi#ifdef _BIG_ENDIAN 407231437Sluigi uint32_t error:1; 408231437Sluigi uint32_t backup_fw:1; 409231437Sluigi uint32_t iscsi_no_ip:1; 410231437Sluigi uint32_t iscsi_ip_conflict:1; 411231437Sluigi uint32_t option_rom_installed:1; 412231437Sluigi uint32_t iscsi_drv_loaded:1; 413231437Sluigi uint32_t rsvd0:10; 414231437Sluigi uint32_t stage:16; 415231437Sluigi#else 416231437Sluigi uint32_t stage:16; 417231437Sluigi uint32_t rsvd0:10; 418231437Sluigi uint32_t iscsi_drv_loaded:1; 419231437Sluigi uint32_t option_rom_installed:1; 420231437Sluigi uint32_t iscsi_ip_conflict:1; 421231437Sluigi uint32_t iscsi_no_ip:1; 422231437Sluigi uint32_t backup_fw:1; 423231437Sluigi uint32_t error:1; 424231437Sluigi#endif 425231437Sluigi } bits; 426231437Sluigi} mpu_ep_semaphore_t; 427231437Sluigi 428231437Sluigi 429231437Sluigi 430231437Sluigi 431231437Sluigitypedef union mpu_ep_control_u { 432231437Sluigi uint32_t dw0; 433231437Sluigi struct { 434231437Sluigi#ifdef _BIG_ENDIAN 435231437Sluigi uint32_t cpu_reset:1; 436231437Sluigi uint32_t rsvd1:15; 437231437Sluigi uint32_t ep_ram_init_status:1; 438231437Sluigi uint32_t rsvd0:12; 439231437Sluigi uint32_t m2_rxpbuf:1; 440231437Sluigi uint32_t m1_rxpbuf:1; 441231437Sluigi uint32_t m0_rxpbuf:1; 442231437Sluigi#else 443231437Sluigi uint32_t m0_rxpbuf:1; 444231437Sluigi uint32_t m1_rxpbuf:1; 445231437Sluigi uint32_t m2_rxpbuf:1; 446231437Sluigi uint32_t rsvd0:12; 447231437Sluigi uint32_t ep_ram_init_status:1; 448231437Sluigi uint32_t rsvd1:15; 449231437Sluigi uint32_t cpu_reset:1; 450231437Sluigi#endif 451231437Sluigi } bits; 452231437Sluigi} mpu_ep_control_t; 453231437Sluigi 454231437Sluigi 455231437Sluigi 456231437Sluigi 457231437Sluigi/* RX doorbell */ 458231437Sluigitypedef union pd_rxulp_db_u { 459231437Sluigi uint32_t dw0; 460231437Sluigi struct { 461231437Sluigi#ifdef _BIG_ENDIAN 462231437Sluigi uint32_t num_posted:8; 463231437Sluigi uint32_t invalidate:1; 464231437Sluigi uint32_t rsvd1:13; 465231437Sluigi uint32_t qid:10; 466231437Sluigi#else 467231437Sluigi uint32_t qid:10; 468231437Sluigi uint32_t rsvd1:13; 469231437Sluigi uint32_t invalidate:1; 470231437Sluigi uint32_t num_posted:8; 471231437Sluigi#endif 472231437Sluigi } bits; 473231437Sluigi} pd_rxulp_db_t; 474231437Sluigi 475231437Sluigi 476231437Sluigi/* TX doorbell */ 477231437Sluigitypedef union pd_txulp_db_u { 478231437Sluigi uint32_t dw0; 479231437Sluigi struct { 480231437Sluigi#ifdef _BIG_ENDIAN 481231437Sluigi uint32_t rsvd1:2; 482231437Sluigi uint32_t num_posted:14; 483231437Sluigi uint32_t rsvd0:6; 484231437Sluigi uint32_t qid:10; 485231437Sluigi#else 486231437Sluigi uint32_t qid:10; 487231437Sluigi uint32_t rsvd0:6; 488231437Sluigi uint32_t num_posted:14; 489231437Sluigi uint32_t rsvd1:2; 490231437Sluigi#endif 491231437Sluigi } bits; 492231437Sluigi} pd_txulp_db_t; 493231437Sluigi 494231437Sluigi/* CQ doorbell */ 495231437Sluigitypedef union cq_db_u { 496231437Sluigi uint32_t dw0; 497231437Sluigi struct { 498231437Sluigi#ifdef _BIG_ENDIAN 499231437Sluigi uint32_t rsvd1:2; 500231437Sluigi uint32_t rearm:1; 501231437Sluigi uint32_t num_popped:13; 502231437Sluigi uint32_t rsvd0:5; 503231437Sluigi uint32_t event:1; 504231437Sluigi uint32_t qid:10; 505231437Sluigi#else 506231437Sluigi uint32_t qid:10; 507231437Sluigi uint32_t event:1; 508231437Sluigi uint32_t rsvd0:5; 509231437Sluigi uint32_t num_popped:13; 510231437Sluigi uint32_t rearm:1; 511231437Sluigi uint32_t rsvd1:2; 512231437Sluigi#endif 513231437Sluigi } bits; 514231437Sluigi} cq_db_t; 515231437Sluigi 516231437Sluigi/* EQ doorbell */ 517231437Sluigitypedef union eq_db_u { 518231437Sluigi uint32_t dw0; 519231437Sluigi struct { 520231437Sluigi#ifdef _BIG_ENDIAN 521231437Sluigi uint32_t rsvd1:2; 522231437Sluigi uint32_t rearm:1; 523231437Sluigi uint32_t num_popped:13; 524231437Sluigi uint32_t rsvd0:5; 525231437Sluigi uint32_t event:1; 526231437Sluigi uint32_t clrint:1; 527231437Sluigi uint32_t qid:9; 528231437Sluigi#else 529231437Sluigi uint32_t qid:9; 530231437Sluigi uint32_t clrint:1; 531231437Sluigi uint32_t event:1; 532231437Sluigi uint32_t rsvd0:5; 533231437Sluigi uint32_t num_popped:13; 534231437Sluigi uint32_t rearm:1; 535231437Sluigi uint32_t rsvd1:2; 536231437Sluigi#endif 537231437Sluigi } bits; 538231437Sluigi} eq_db_t; 539231437Sluigi 540231437Sluigi/* bootstrap mbox doorbell */ 541231437Sluigitypedef union pd_mpu_mbox_db_u { 542231437Sluigi uint32_t dw0; 543231437Sluigi struct { 544231437Sluigi#ifdef _BIG_ENDIAN 545231437Sluigi uint32_t address:30; 546231437Sluigi uint32_t hi:1; 547231437Sluigi uint32_t ready:1; 548231437Sluigi#else 549231437Sluigi uint32_t ready:1; 550231437Sluigi uint32_t hi:1; 551231437Sluigi uint32_t address:30; 552231437Sluigi#endif 553231437Sluigi } bits; 554231437Sluigi} pd_mpu_mbox_db_t; 555231437Sluigi 556231437Sluigi/* MQ ring doorbell */ 557231437Sluigitypedef union pd_mq_db_u { 558231437Sluigi uint32_t dw0; 559231437Sluigi struct { 560231437Sluigi#ifdef _BIG_ENDIAN 561231437Sluigi uint32_t rsvd1:2; 562231437Sluigi uint32_t num_posted:14; 563231437Sluigi uint32_t rsvd0:5; 564231437Sluigi uint32_t mq_id:11; 565231437Sluigi#else 566231437Sluigi uint32_t mq_id:11; 567231437Sluigi uint32_t rsvd0:5; 568231437Sluigi uint32_t num_posted:14; 569231437Sluigi uint32_t rsvd1:2; 570231437Sluigi#endif 571231437Sluigi } bits; 572231437Sluigi} pd_mq_db_t; 573231437Sluigi 574231437Sluigi/* 575231437Sluigi * Event Queue Entry 576231437Sluigi */ 577231437Sluigistruct oce_eqe { 578231437Sluigi uint32_t evnt; 579231437Sluigi}; 580231437Sluigi 581231437Sluigi/* MQ scatter gather entry. Array of these make an SGL */ 582231437Sluigistruct oce_mq_sge { 583231437Sluigi uint32_t pa_lo; 584231437Sluigi uint32_t pa_hi; 585231437Sluigi uint32_t length; 586231437Sluigi}; 587231437Sluigi 588231437Sluigi/* 589231437Sluigi * payload can contain an SGL or an embedded array of upto 59 dwords 590231437Sluigi */ 591231437Sluigistruct oce_mbx_payload { 592231437Sluigi union { 593231437Sluigi union { 594231437Sluigi struct oce_mq_sge sgl[MAX_MBX_SGE]; 595231437Sluigi uint32_t embedded[59]; 596231437Sluigi } u1; 597231437Sluigi uint32_t dw[59]; 598231437Sluigi } u0; 599231437Sluigi}; 600231437Sluigi 601231437Sluigi/* 602231437Sluigi * MQ MBX structure 603231437Sluigi */ 604231437Sluigistruct oce_mbx { 605231437Sluigi union { 606231437Sluigi struct { 607231437Sluigi#ifdef _BIG_ENDIAN 608231437Sluigi uint32_t special:8; 609231437Sluigi uint32_t rsvd1:16; 610231437Sluigi uint32_t sge_count:5; 611231437Sluigi uint32_t rsvd0:2; 612231437Sluigi uint32_t embedded:1; 613231437Sluigi#else 614231437Sluigi uint32_t embedded:1; 615231437Sluigi uint32_t rsvd0:2; 616231437Sluigi uint32_t sge_count:5; 617231437Sluigi uint32_t rsvd1:16; 618231437Sluigi uint32_t special:8; 619231437Sluigi#endif 620231437Sluigi } s; 621231437Sluigi uint32_t dw0; 622231437Sluigi } u0; 623231437Sluigi 624231437Sluigi uint32_t payload_length; 625231437Sluigi uint32_t tag[2]; 626231437Sluigi uint32_t rsvd2[1]; 627231437Sluigi struct oce_mbx_payload payload; 628231437Sluigi}; 629231437Sluigi 630231437Sluigi/* completion queue entry for MQ */ 631231437Sluigistruct oce_mq_cqe { 632231437Sluigi union { 633231437Sluigi struct { 634231437Sluigi#ifdef _BIG_ENDIAN 635231437Sluigi /* dw0 */ 636231437Sluigi uint32_t extended_status:16; 637231437Sluigi uint32_t completion_status:16; 638231437Sluigi /* dw1 dw2 */ 639231437Sluigi uint32_t mq_tag[2]; 640231437Sluigi /* dw3 */ 641231437Sluigi uint32_t valid:1; 642231437Sluigi uint32_t async_event:1; 643231437Sluigi uint32_t hpi_buffer_cmpl:1; 644231437Sluigi uint32_t completed:1; 645231437Sluigi uint32_t consumed:1; 646231879Sluigi uint32_t rsvd0:3; 647231879Sluigi uint32_t async_type:8; 648231879Sluigi uint32_t event_type:8; 649231879Sluigi uint32_t rsvd1:8; 650231437Sluigi#else 651231437Sluigi /* dw0 */ 652231437Sluigi uint32_t completion_status:16; 653231437Sluigi uint32_t extended_status:16; 654231437Sluigi /* dw1 dw2 */ 655231437Sluigi uint32_t mq_tag[2]; 656231437Sluigi /* dw3 */ 657231879Sluigi uint32_t rsvd1:8; 658231879Sluigi uint32_t event_type:8; 659231879Sluigi uint32_t async_type:8; 660231879Sluigi uint32_t rsvd0:3; 661231437Sluigi uint32_t consumed:1; 662231437Sluigi uint32_t completed:1; 663231437Sluigi uint32_t hpi_buffer_cmpl:1; 664231437Sluigi uint32_t async_event:1; 665231437Sluigi uint32_t valid:1; 666231437Sluigi#endif 667231437Sluigi } s; 668231437Sluigi uint32_t dw[4]; 669231437Sluigi } u0; 670231437Sluigi}; 671231437Sluigi 672231437Sluigi/* Mailbox Completion Status Codes */ 673231437Sluigienum MBX_COMPLETION_STATUS { 674231437Sluigi MBX_CQE_STATUS_SUCCESS = 0x00, 675231437Sluigi MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 676231437Sluigi MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 677231437Sluigi MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 678231437Sluigi MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 679231437Sluigi MBX_CQE_STATUS_DMA_FAILED = 0x05 680231437Sluigi}; 681231437Sluigi 682231437Sluigistruct oce_async_cqe_link_state { 683231437Sluigi union { 684231437Sluigi struct { 685231437Sluigi#ifdef _BIG_ENDIAN 686231437Sluigi /* dw0 */ 687231437Sluigi uint8_t speed; 688231437Sluigi uint8_t duplex; 689231437Sluigi uint8_t link_status; 690231437Sluigi uint8_t phy_port; 691231437Sluigi /* dw1 */ 692231437Sluigi uint16_t qos_link_speed; 693231437Sluigi uint8_t rsvd0; 694231437Sluigi uint8_t fault; 695231437Sluigi /* dw2 */ 696231437Sluigi uint32_t event_tag; 697231437Sluigi /* dw3 */ 698231437Sluigi uint32_t valid:1; 699231437Sluigi uint32_t async_event:1; 700231437Sluigi uint32_t rsvd2:6; 701231437Sluigi uint32_t event_type:8; 702231437Sluigi uint32_t event_code:8; 703231437Sluigi uint32_t rsvd1:8; 704231437Sluigi#else 705231437Sluigi /* dw0 */ 706231437Sluigi uint8_t phy_port; 707231437Sluigi uint8_t link_status; 708231437Sluigi uint8_t duplex; 709231437Sluigi uint8_t speed; 710231437Sluigi /* dw1 */ 711231437Sluigi uint8_t fault; 712231437Sluigi uint8_t rsvd0; 713231437Sluigi uint16_t qos_link_speed; 714231437Sluigi /* dw2 */ 715231437Sluigi uint32_t event_tag; 716231437Sluigi /* dw3 */ 717231437Sluigi uint32_t rsvd1:8; 718231437Sluigi uint32_t event_code:8; 719231437Sluigi uint32_t event_type:8; 720231437Sluigi uint32_t rsvd2:6; 721231437Sluigi uint32_t async_event:1; 722231437Sluigi uint32_t valid:1; 723231437Sluigi#endif 724231437Sluigi } s; 725231437Sluigi uint32_t dw[4]; 726231437Sluigi } u0; 727231437Sluigi}; 728231437Sluigi 729338938Sjpaetzel/* OS2BMC async event */ 730338938Sjpaetzelstruct oce_async_evt_grp5_os2bmc { 731338938Sjpaetzel union { 732338938Sjpaetzel struct { 733338938Sjpaetzel uint32_t lrn_enable:1; 734338938Sjpaetzel uint32_t lrn_disable:1; 735338938Sjpaetzel uint32_t mgmt_enable:1; 736338938Sjpaetzel uint32_t mgmt_disable:1; 737338938Sjpaetzel uint32_t rsvd0:12; 738338938Sjpaetzel uint32_t vlan_tag:16; 739338938Sjpaetzel uint32_t arp_filter:1; 740338938Sjpaetzel uint32_t dhcp_client_filt:1; 741338938Sjpaetzel uint32_t dhcp_server_filt:1; 742338938Sjpaetzel uint32_t net_bios_filt:1; 743338938Sjpaetzel uint32_t rsvd1:3; 744338938Sjpaetzel uint32_t bcast_filt:1; 745338938Sjpaetzel uint32_t ipv6_nbr_filt:1; 746338938Sjpaetzel uint32_t ipv6_ra_filt:1; 747338938Sjpaetzel uint32_t ipv6_ras_filt:1; 748338938Sjpaetzel uint32_t rsvd2[4]; 749338938Sjpaetzel uint32_t mcast_filt:1; 750338938Sjpaetzel uint32_t rsvd3:16; 751338938Sjpaetzel uint32_t evt_tag; 752338938Sjpaetzel uint32_t dword3; 753338938Sjpaetzel } s; 754338938Sjpaetzel uint32_t dword[4]; 755338938Sjpaetzel } u; 756338938Sjpaetzel}; 757231879Sluigi 758231879Sluigi/* PVID aync event */ 759231879Sluigistruct oce_async_event_grp5_pvid_state { 760231879Sluigi uint8_t enabled; 761231879Sluigi uint8_t rsvd0; 762231879Sluigi uint16_t tag; 763231879Sluigi uint32_t event_tag; 764231879Sluigi uint32_t rsvd1; 765231879Sluigi uint32_t code; 766231879Sluigi}; 767231879Sluigi 768247880Sdelphij/* async event indicating outer VLAN tag in QnQ */ 769247880Sdelphijstruct oce_async_event_qnq { 770247880Sdelphij uint8_t valid; /* Indicates if outer VLAN is valid */ 771247880Sdelphij uint8_t rsvd0; 772247880Sdelphij uint16_t vlan_tag; 773247880Sdelphij uint32_t event_tag; 774247880Sdelphij uint8_t rsvd1[4]; 775247880Sdelphij uint32_t code; 776247880Sdelphij} ; 777247880Sdelphij 778247880Sdelphij 779231879Sluigitypedef union oce_mq_ext_ctx_u { 780231879Sluigi uint32_t dw[6]; 781231879Sluigi struct { 782231879Sluigi #ifdef _BIG_ENDIAN 783231879Sluigi /* dw0 */ 784231879Sluigi uint32_t dw4rsvd1:16; 785231879Sluigi uint32_t num_pages:16; 786231879Sluigi /* dw1 */ 787231879Sluigi uint32_t async_evt_bitmap; 788231879Sluigi /* dw2 */ 789231879Sluigi uint32_t cq_id:10; 790231879Sluigi uint32_t dw5rsvd2:2; 791231879Sluigi uint32_t ring_size:4; 792231879Sluigi uint32_t dw5rsvd1:16; 793231879Sluigi /* dw3 */ 794231879Sluigi uint32_t valid:1; 795231879Sluigi uint32_t dw6rsvd1:31; 796231879Sluigi /* dw4 */ 797231879Sluigi uint32_t dw7rsvd1:21; 798231879Sluigi uint32_t async_cq_id:10; 799231879Sluigi uint32_t async_cq_valid:1; 800231879Sluigi #else 801231879Sluigi /* dw0 */ 802231879Sluigi uint32_t num_pages:16; 803231879Sluigi uint32_t dw4rsvd1:16; 804231879Sluigi /* dw1 */ 805231879Sluigi uint32_t async_evt_bitmap; 806231879Sluigi /* dw2 */ 807231879Sluigi uint32_t dw5rsvd1:16; 808231879Sluigi uint32_t ring_size:4; 809231879Sluigi uint32_t dw5rsvd2:2; 810231879Sluigi uint32_t cq_id:10; 811231879Sluigi /* dw3 */ 812231879Sluigi uint32_t dw6rsvd1:31; 813231879Sluigi uint32_t valid:1; 814231879Sluigi /* dw4 */ 815231879Sluigi uint32_t async_cq_valid:1; 816231879Sluigi uint32_t async_cq_id:10; 817231879Sluigi uint32_t dw7rsvd1:21; 818231879Sluigi #endif 819231879Sluigi /* dw5 */ 820231879Sluigi uint32_t dw8rsvd1; 821231879Sluigi } v0; 822247880Sdelphij struct { 823247880Sdelphij #ifdef _BIG_ENDIAN 824247880Sdelphij /* dw0 */ 825247880Sdelphij uint32_t cq_id:16; 826247880Sdelphij uint32_t num_pages:16; 827247880Sdelphij /* dw1 */ 828247880Sdelphij uint32_t async_evt_bitmap; 829247880Sdelphij /* dw2 */ 830247880Sdelphij uint32_t dw5rsvd2:12; 831247880Sdelphij uint32_t ring_size:4; 832247880Sdelphij uint32_t async_cq_id:16; 833247880Sdelphij /* dw3 */ 834247880Sdelphij uint32_t valid:1; 835247880Sdelphij uint32_t dw6rsvd1:31; 836247880Sdelphij /* dw4 */ 837247880Sdelphij uint32_t dw7rsvd1:31; 838247880Sdelphij uint32_t async_cq_valid:1; 839247880Sdelphij #else 840247880Sdelphij /* dw0 */ 841247880Sdelphij uint32_t num_pages:16; 842247880Sdelphij uint32_t cq_id:16; 843247880Sdelphij /* dw1 */ 844247880Sdelphij uint32_t async_evt_bitmap; 845247880Sdelphij /* dw2 */ 846247880Sdelphij uint32_t async_cq_id:16; 847247880Sdelphij uint32_t ring_size:4; 848247880Sdelphij uint32_t dw5rsvd2:12; 849247880Sdelphij /* dw3 */ 850247880Sdelphij uint32_t dw6rsvd1:31; 851247880Sdelphij uint32_t valid:1; 852247880Sdelphij /* dw4 */ 853247880Sdelphij uint32_t async_cq_valid:1; 854247880Sdelphij uint32_t dw7rsvd1:31; 855247880Sdelphij #endif 856247880Sdelphij /* dw5 */ 857247880Sdelphij uint32_t dw8rsvd1; 858247880Sdelphij } v1; 859247880Sdelphij 860231879Sluigi} oce_mq_ext_ctx_t; 861231879Sluigi 862231879Sluigi 863231437Sluigi/* MQ mailbox structure */ 864231437Sluigistruct oce_bmbx { 865231437Sluigi struct oce_mbx mbx; 866231437Sluigi struct oce_mq_cqe cqe; 867231437Sluigi}; 868231437Sluigi 869231437Sluigi/* ---[ MBXs start here ]---------------------------------------------- */ 870231437Sluigi/* MBXs sub system codes */ 871231437Sluigienum MBX_SUBSYSTEM_CODES { 872231437Sluigi MBX_SUBSYSTEM_RSVD = 0, 873231437Sluigi MBX_SUBSYSTEM_COMMON = 1, 874231437Sluigi MBX_SUBSYSTEM_COMMON_ISCSI = 2, 875231437Sluigi MBX_SUBSYSTEM_NIC = 3, 876231437Sluigi MBX_SUBSYSTEM_TOE = 4, 877231437Sluigi MBX_SUBSYSTEM_PXE_UNDI = 5, 878231437Sluigi MBX_SUBSYSTEM_ISCSI_INI = 6, 879231437Sluigi MBX_SUBSYSTEM_ISCSI_TGT = 7, 880231437Sluigi MBX_SUBSYSTEM_MILI_PTL = 8, 881231437Sluigi MBX_SUBSYSTEM_MILI_TMD = 9, 882231437Sluigi MBX_SUBSYSTEM_RDMA = 10, 883231437Sluigi MBX_SUBSYSTEM_LOWLEVEL = 11, 884231437Sluigi MBX_SUBSYSTEM_LRO = 13, 885231437Sluigi IOCBMBX_SUBSYSTEM_DCBX = 15, 886231437Sluigi IOCBMBX_SUBSYSTEM_DIAG = 16, 887231437Sluigi IOCBMBX_SUBSYSTEM_VENDOR = 17 888231437Sluigi}; 889231437Sluigi 890231437Sluigi/* common ioctl opcodes */ 891231437Sluigienum COMMON_SUBSYSTEM_OPCODES { 892231437Sluigi/* These opcodes are common to both networking and storage PCI functions 893231437Sluigi * They are used to reserve resources and configure CNA. These opcodes 894231437Sluigi * all use the MBX_SUBSYSTEM_COMMON subsystem code. 895231437Sluigi */ 896231437Sluigi OPCODE_COMMON_QUERY_IFACE_MAC = 1, 897231437Sluigi OPCODE_COMMON_SET_IFACE_MAC = 2, 898231437Sluigi OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 899231437Sluigi OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 900231437Sluigi OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 901231437Sluigi OPCODE_COMMON_READ_FLASHROM = 6, 902231437Sluigi OPCODE_COMMON_WRITE_FLASHROM = 7, 903231437Sluigi OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 904231437Sluigi OPCODE_COMMON_CREATE_CQ = 12, 905231437Sluigi OPCODE_COMMON_CREATE_EQ = 13, 906231437Sluigi OPCODE_COMMON_CREATE_MQ = 21, 907231437Sluigi OPCODE_COMMON_GET_QOS = 27, 908231437Sluigi OPCODE_COMMON_SET_QOS = 28, 909231437Sluigi OPCODE_COMMON_READ_EPROM = 30, 910231437Sluigi OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 911231437Sluigi OPCODE_COMMON_NOP = 33, 912231437Sluigi OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 913231437Sluigi OPCODE_COMMON_GET_FW_VERSION = 35, 914231437Sluigi OPCODE_COMMON_SET_FLOW_CONTROL = 36, 915231437Sluigi OPCODE_COMMON_GET_FLOW_CONTROL = 37, 916231437Sluigi OPCODE_COMMON_SET_FRAME_SIZE = 39, 917231437Sluigi OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 918231437Sluigi OPCODE_COMMON_CREATE_IFACE = 50, 919231437Sluigi OPCODE_COMMON_DESTROY_IFACE = 51, 920231437Sluigi OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 921231437Sluigi OPCODE_COMMON_DESTROY_MQ = 53, 922231437Sluigi OPCODE_COMMON_DESTROY_CQ = 54, 923231437Sluigi OPCODE_COMMON_DESTROY_EQ = 55, 924231437Sluigi OPCODE_COMMON_UPLOAD_TCP = 56, 925231437Sluigi OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 926231437Sluigi OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 927231437Sluigi OPCODE_COMMON_ADD_IFACE_MAC = 59, 928231437Sluigi OPCODE_COMMON_DEL_IFACE_MAC = 60, 929231437Sluigi OPCODE_COMMON_FUNCTION_RESET = 61, 930231437Sluigi OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 931231437Sluigi OPCODE_COMMON_GET_BOOT_CONFIG = 66, 932231437Sluigi OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 933231437Sluigi OPCODE_COMMON_SET_BEACON_CONFIG = 69, 934231437Sluigi OPCODE_COMMON_GET_BEACON_CONFIG = 70, 935231437Sluigi OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 936247880Sdelphij OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 937231437Sluigi OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 938231437Sluigi OPCODE_COMMON_GET_PORT_NAME = 77, 939231437Sluigi OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 940231437Sluigi OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 941231437Sluigi OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 942231437Sluigi OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 943231437Sluigi OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 944231437Sluigi OPCODE_COMMON_GET_RESET_NEEDED = 84, 945231437Sluigi OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 946231437Sluigi OPCODE_COMMON_GET_NCSI_CONFIG = 86, 947231437Sluigi OPCODE_COMMON_SET_NCSI_CONFIG = 87, 948231437Sluigi OPCODE_COMMON_CREATE_MQ_EXT = 90, 949231437Sluigi OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 950231437Sluigi OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 951231437Sluigi OPCODE_COMMON_GET_PHY_CONFIG = 102, 952231437Sluigi OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 953231437Sluigi OPCODE_COMMON_GET_ADAPTER_ID = 110, 954231437Sluigi OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 955231437Sluigi OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 956231437Sluigi OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 957231437Sluigi OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 958231437Sluigi OPCODE_COMMON_SEND_ACTIVATION = 115, 959231437Sluigi OPCODE_COMMON_RESET_LICENSES = 116, 960231437Sluigi OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 961231437Sluigi OPCODE_COMMON_QUERY_TCB = 144, 962231437Sluigi OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 963231437Sluigi OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 964231437Sluigi OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 965231437Sluigi OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 966231437Sluigi OPCODE_COMMON_MODIFY_CQ = 149, 967231437Sluigi OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 968231437Sluigi OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 969231437Sluigi OPCODE_COMMON_GET_HSW_CONFIG = 152, 970231437Sluigi OPCODE_COMMON_SET_HSW_CONFIG = 153, 971231437Sluigi OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 972231437Sluigi OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 973231437Sluigi OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 974231437Sluigi OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 975231437Sluigi OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 976231437Sluigi OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 977231437Sluigi OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 978231437Sluigi OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 979231437Sluigi OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 980231437Sluigi OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 981231437Sluigi OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 982231437Sluigi OPCODE_COMMON_GET_PROFILE_LIST = 166, 983231437Sluigi OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 984231437Sluigi OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 985231437Sluigi OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 986231437Sluigi OPCODE_COMMON_READ_OBJECT = 171, 987231437Sluigi OPCODE_COMMON_WRITE_OBJECT = 172 988231437Sluigi}; 989231437Sluigi 990231437Sluigi/* common ioctl header */ 991231437Sluigi#define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 992231437Sluigi#define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 993231437Sluigi#define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 994231437Sluigistruct mbx_hdr { 995231437Sluigi union { 996231437Sluigi uint32_t dw[4]; 997231437Sluigi struct { 998231437Sluigi #ifdef _BIG_ENDIAN 999231437Sluigi /* dw 0 */ 1000231437Sluigi uint32_t domain:8; 1001231437Sluigi uint32_t port_number:8; 1002231437Sluigi uint32_t subsystem:8; 1003231437Sluigi uint32_t opcode:8; 1004231437Sluigi /* dw 1 */ 1005231437Sluigi uint32_t timeout; 1006231437Sluigi /* dw 2 */ 1007231437Sluigi uint32_t request_length; 1008231437Sluigi /* dw 3 */ 1009231437Sluigi uint32_t rsvd0:24; 1010231437Sluigi uint32_t version:8; 1011231437Sluigi #else 1012231437Sluigi /* dw 0 */ 1013231437Sluigi uint32_t opcode:8; 1014231437Sluigi uint32_t subsystem:8; 1015231437Sluigi uint32_t port_number:8; 1016231437Sluigi uint32_t domain:8; 1017231437Sluigi /* dw 1 */ 1018231437Sluigi uint32_t timeout; 1019231437Sluigi /* dw 2 */ 1020231437Sluigi uint32_t request_length; 1021231437Sluigi /* dw 3 */ 1022231437Sluigi uint32_t version:8; 1023231437Sluigi uint32_t rsvd0:24; 1024231437Sluigi #endif 1025231437Sluigi } req; 1026231437Sluigi struct { 1027231437Sluigi #ifdef _BIG_ENDIAN 1028231437Sluigi /* dw 0 */ 1029231437Sluigi uint32_t domain:8; 1030231437Sluigi uint32_t rsvd0:8; 1031231437Sluigi uint32_t subsystem:8; 1032231437Sluigi uint32_t opcode:8; 1033231437Sluigi /* dw 1 */ 1034231437Sluigi uint32_t rsvd1:16; 1035231437Sluigi uint32_t additional_status:8; 1036231437Sluigi uint32_t status:8; 1037231437Sluigi #else 1038231437Sluigi /* dw 0 */ 1039231437Sluigi uint32_t opcode:8; 1040231437Sluigi uint32_t subsystem:8; 1041231437Sluigi uint32_t rsvd0:8; 1042231437Sluigi uint32_t domain:8; 1043231437Sluigi /* dw 1 */ 1044231437Sluigi uint32_t status:8; 1045231437Sluigi uint32_t additional_status:8; 1046231437Sluigi uint32_t rsvd1:16; 1047231437Sluigi #endif 1048231437Sluigi uint32_t rsp_length; 1049231437Sluigi uint32_t actual_rsp_length; 1050231437Sluigi } rsp; 1051231437Sluigi } u0; 1052231437Sluigi}; 1053231437Sluigi#define OCE_BMBX_RHDR_SZ 20 1054231437Sluigi#define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1055231437Sluigi#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1056231437Sluigi#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1057231437Sluigi 1058267839Sdelphij/* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */ 1059231437Sluigistruct mbx_query_common_link_config { 1060231437Sluigi struct mbx_hdr hdr; 1061231437Sluigi union { 1062231437Sluigi struct { 1063231437Sluigi uint32_t rsvd0; 1064231437Sluigi } req; 1065231437Sluigi 1066231437Sluigi struct { 1067267839Sdelphij #ifdef _BIG_ENDIAN 1068267839Sdelphij uint32_t physical_port_fault:8; 1069267839Sdelphij uint32_t physical_port_speed:8; 1070267839Sdelphij uint32_t link_duplex:8; 1071267839Sdelphij uint32_t pt:2; 1072267839Sdelphij uint32_t port_number:6; 1073267839Sdelphij 1074231437Sluigi uint16_t qos_link_speed; 1075267839Sdelphij uint16_t rsvd0; 1076267839Sdelphij 1077267839Sdelphij uint32_t rsvd1:21; 1078267839Sdelphij uint32_t phys_fcv:1; 1079267839Sdelphij uint32_t phys_rxf:1; 1080267839Sdelphij uint32_t phys_txf:1; 1081267839Sdelphij uint32_t logical_link_status:8; 1082267839Sdelphij #else 1083267839Sdelphij uint32_t port_number:6; 1084267839Sdelphij uint32_t pt:2; 1085267839Sdelphij uint32_t link_duplex:8; 1086267839Sdelphij uint32_t physical_port_speed:8; 1087267839Sdelphij uint32_t physical_port_fault:8; 1088267839Sdelphij 1089267839Sdelphij uint16_t rsvd0; 1090267839Sdelphij uint16_t qos_link_speed; 1091267839Sdelphij 1092267839Sdelphij uint32_t logical_link_status:8; 1093267839Sdelphij uint32_t phys_txf:1; 1094267839Sdelphij uint32_t phys_rxf:1; 1095267839Sdelphij uint32_t phys_fcv:1; 1096267839Sdelphij uint32_t rsvd1:21; 1097267839Sdelphij #endif 1098231437Sluigi } rsp; 1099231437Sluigi } params; 1100231437Sluigi}; 1101231437Sluigi 1102231437Sluigi/* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1103231437Sluigistruct mbx_set_common_link_speed { 1104231437Sluigi struct mbx_hdr hdr; 1105231437Sluigi union { 1106231437Sluigi struct { 1107231437Sluigi#ifdef _BIG_ENDIAN 1108231437Sluigi uint8_t rsvd0; 1109231437Sluigi uint8_t mac_speed; 1110231437Sluigi uint8_t virtual_port; 1111231437Sluigi uint8_t physical_port; 1112231437Sluigi#else 1113231437Sluigi uint8_t physical_port; 1114231437Sluigi uint8_t virtual_port; 1115231437Sluigi uint8_t mac_speed; 1116231437Sluigi uint8_t rsvd0; 1117231437Sluigi#endif 1118231437Sluigi } req; 1119231437Sluigi 1120231437Sluigi struct { 1121231437Sluigi uint32_t rsvd0; 1122231437Sluigi } rsp; 1123231437Sluigi 1124231437Sluigi uint32_t dw; 1125231437Sluigi } params; 1126231437Sluigi}; 1127231437Sluigi 1128231437Sluigistruct mac_address_format { 1129231437Sluigi uint16_t size_of_struct; 1130231437Sluigi uint8_t mac_addr[6]; 1131231437Sluigi}; 1132231437Sluigi 1133231437Sluigi/* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1134231437Sluigistruct mbx_query_common_iface_mac { 1135231437Sluigi struct mbx_hdr hdr; 1136231437Sluigi union { 1137231437Sluigi struct { 1138231437Sluigi#ifdef _BIG_ENDIAN 1139231437Sluigi uint16_t if_id; 1140231437Sluigi uint8_t permanent; 1141231437Sluigi uint8_t type; 1142231437Sluigi#else 1143231437Sluigi uint8_t type; 1144231437Sluigi uint8_t permanent; 1145231437Sluigi uint16_t if_id; 1146231437Sluigi#endif 1147231437Sluigi 1148231437Sluigi } req; 1149231437Sluigi 1150231437Sluigi struct { 1151231437Sluigi struct mac_address_format mac; 1152231437Sluigi } rsp; 1153231437Sluigi } params; 1154231437Sluigi}; 1155231437Sluigi 1156231437Sluigi/* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1157231437Sluigistruct mbx_set_common_iface_mac { 1158231437Sluigi struct mbx_hdr hdr; 1159231437Sluigi union { 1160231437Sluigi struct { 1161231437Sluigi#ifdef _BIG_ENDIAN 1162231437Sluigi /* dw 0 */ 1163231437Sluigi uint16_t if_id; 1164231437Sluigi uint8_t invalidate; 1165231437Sluigi uint8_t type; 1166231437Sluigi#else 1167231437Sluigi /* dw 0 */ 1168231437Sluigi uint8_t type; 1169231437Sluigi uint8_t invalidate; 1170231437Sluigi uint16_t if_id; 1171231437Sluigi#endif 1172231437Sluigi /* dw 1 */ 1173231437Sluigi struct mac_address_format mac; 1174231437Sluigi } req; 1175231437Sluigi 1176231437Sluigi struct { 1177231437Sluigi uint32_t rsvd0; 1178231437Sluigi } rsp; 1179231437Sluigi 1180231437Sluigi uint32_t dw[2]; 1181231437Sluigi } params; 1182231437Sluigi}; 1183231437Sluigi 1184231437Sluigi/* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1185231437Sluigistruct mbx_set_common_iface_multicast { 1186231437Sluigi struct mbx_hdr hdr; 1187231437Sluigi union { 1188231437Sluigi struct { 1189231437Sluigi /* dw 0 */ 1190231437Sluigi uint16_t num_mac; 1191231437Sluigi uint8_t promiscuous; 1192231437Sluigi uint8_t if_id; 1193231437Sluigi /* dw 1-48 */ 1194231437Sluigi struct { 1195231437Sluigi uint8_t byte[6]; 1196231437Sluigi } mac[32]; 1197231437Sluigi 1198231437Sluigi } req; 1199231437Sluigi 1200231437Sluigi struct { 1201231437Sluigi uint32_t rsvd0; 1202231437Sluigi } rsp; 1203231437Sluigi 1204231437Sluigi uint32_t dw[49]; 1205231437Sluigi } params; 1206231437Sluigi}; 1207231437Sluigi 1208231437Sluigistruct qinq_vlan { 1209231437Sluigi#ifdef _BIG_ENDIAN 1210231437Sluigi uint16_t inner; 1211231437Sluigi uint16_t outer; 1212231437Sluigi#else 1213231437Sluigi uint16_t outer; 1214231437Sluigi uint16_t inner; 1215231437Sluigi#endif 1216231437Sluigi}; 1217231437Sluigi 1218231437Sluigistruct normal_vlan { 1219231437Sluigi uint16_t vtag; 1220231437Sluigi}; 1221231437Sluigi 1222231437Sluigistruct ntwk_if_vlan_tag { 1223231437Sluigi union { 1224231437Sluigi struct normal_vlan normal; 1225231437Sluigi struct qinq_vlan qinq; 1226231437Sluigi } u0; 1227231437Sluigi}; 1228231437Sluigi 1229231437Sluigi/* [50] OPCODE_COMMON_CREATE_IFACE */ 1230231437Sluigistruct mbx_create_common_iface { 1231231437Sluigi struct mbx_hdr hdr; 1232231437Sluigi union { 1233231437Sluigi struct { 1234231437Sluigi uint32_t version; 1235231437Sluigi uint32_t cap_flags; 1236231437Sluigi uint32_t enable_flags; 1237231437Sluigi uint8_t mac_addr[6]; 1238231437Sluigi uint8_t rsvd0; 1239231437Sluigi uint8_t mac_invalid; 1240231437Sluigi struct ntwk_if_vlan_tag vlan_tag; 1241231437Sluigi } req; 1242231437Sluigi 1243231437Sluigi struct { 1244231437Sluigi uint32_t if_id; 1245231437Sluigi uint32_t pmac_id; 1246231437Sluigi } rsp; 1247231437Sluigi uint32_t dw[4]; 1248231437Sluigi } params; 1249231437Sluigi}; 1250231437Sluigi 1251231437Sluigi/* [51] OPCODE_COMMON_DESTROY_IFACE */ 1252231437Sluigistruct mbx_destroy_common_iface { 1253231437Sluigi struct mbx_hdr hdr; 1254231437Sluigi union { 1255231437Sluigi struct { 1256231437Sluigi uint32_t if_id; 1257231437Sluigi } req; 1258231437Sluigi 1259231437Sluigi struct { 1260231437Sluigi uint32_t rsvd0; 1261231437Sluigi } rsp; 1262231437Sluigi 1263231437Sluigi uint32_t dw; 1264231437Sluigi } params; 1265231437Sluigi}; 1266231437Sluigi 1267231437Sluigi/* event queue context structure */ 1268231437Sluigistruct oce_eq_ctx { 1269231437Sluigi#ifdef _BIG_ENDIAN 1270231437Sluigi uint32_t dw4rsvd1:16; 1271231437Sluigi uint32_t num_pages:16; 1272231437Sluigi 1273231437Sluigi uint32_t size:1; 1274231437Sluigi uint32_t dw5rsvd2:1; 1275231437Sluigi uint32_t valid:1; 1276231437Sluigi uint32_t dw5rsvd1:29; 1277231437Sluigi 1278231437Sluigi uint32_t armed:1; 1279231437Sluigi uint32_t dw6rsvd2:2; 1280231437Sluigi uint32_t count:3; 1281231437Sluigi uint32_t dw6rsvd1:26; 1282231437Sluigi 1283231437Sluigi uint32_t dw7rsvd2:9; 1284231437Sluigi uint32_t delay_mult:10; 1285231437Sluigi uint32_t dw7rsvd1:13; 1286231437Sluigi 1287231437Sluigi uint32_t dw8rsvd1; 1288231437Sluigi#else 1289231437Sluigi uint32_t num_pages:16; 1290231437Sluigi uint32_t dw4rsvd1:16; 1291231437Sluigi 1292231437Sluigi uint32_t dw5rsvd1:29; 1293231437Sluigi uint32_t valid:1; 1294231437Sluigi uint32_t dw5rsvd2:1; 1295231437Sluigi uint32_t size:1; 1296231437Sluigi 1297231437Sluigi uint32_t dw6rsvd1:26; 1298231437Sluigi uint32_t count:3; 1299231437Sluigi uint32_t dw6rsvd2:2; 1300231437Sluigi uint32_t armed:1; 1301231437Sluigi 1302231437Sluigi uint32_t dw7rsvd1:13; 1303231437Sluigi uint32_t delay_mult:10; 1304231437Sluigi uint32_t dw7rsvd2:9; 1305231437Sluigi 1306231437Sluigi uint32_t dw8rsvd1; 1307231437Sluigi#endif 1308231437Sluigi}; 1309231437Sluigi 1310231437Sluigi/* [13] OPCODE_COMMON_CREATE_EQ */ 1311231437Sluigistruct mbx_create_common_eq { 1312231437Sluigi struct mbx_hdr hdr; 1313231437Sluigi union { 1314231437Sluigi struct { 1315231437Sluigi struct oce_eq_ctx ctx; 1316231437Sluigi struct phys_addr pages[8]; 1317231437Sluigi } req; 1318231437Sluigi 1319231437Sluigi struct { 1320231437Sluigi uint16_t eq_id; 1321231437Sluigi uint16_t rsvd0; 1322231437Sluigi } rsp; 1323231437Sluigi } params; 1324231437Sluigi}; 1325231437Sluigi 1326231437Sluigi/* [55] OPCODE_COMMON_DESTROY_EQ */ 1327231437Sluigistruct mbx_destroy_common_eq { 1328231437Sluigi struct mbx_hdr hdr; 1329231437Sluigi union { 1330231437Sluigi struct { 1331231437Sluigi#ifdef _BIG_ENDIAN 1332231437Sluigi uint16_t rsvd0; 1333231437Sluigi uint16_t id; 1334231437Sluigi#else 1335231437Sluigi uint16_t id; 1336231437Sluigi uint16_t rsvd0; 1337231437Sluigi#endif 1338231437Sluigi } req; 1339231437Sluigi 1340231437Sluigi struct { 1341231437Sluigi uint32_t rsvd0; 1342231437Sluigi } rsp; 1343231437Sluigi } params; 1344231437Sluigi}; 1345231437Sluigi 1346231437Sluigi/* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1347231437Sluigitypedef union oce_cq_ctx_u { 1348231437Sluigi uint32_t dw[5]; 1349231437Sluigi struct { 1350231437Sluigi #ifdef _BIG_ENDIAN 1351231437Sluigi /* dw4 */ 1352231437Sluigi uint32_t dw4rsvd1:16; 1353231437Sluigi uint32_t num_pages:16; 1354231437Sluigi /* dw5 */ 1355231437Sluigi uint32_t eventable:1; 1356231437Sluigi uint32_t dw5rsvd3:1; 1357231437Sluigi uint32_t valid:1; 1358231437Sluigi uint32_t count:2; 1359231437Sluigi uint32_t dw5rsvd2:12; 1360231437Sluigi uint32_t nodelay:1; 1361231437Sluigi uint32_t coalesce_wm:2; 1362231437Sluigi uint32_t dw5rsvd1:12; 1363231437Sluigi /* dw6 */ 1364231437Sluigi uint32_t armed:1; 1365231437Sluigi uint32_t dw6rsvd2:1; 1366231437Sluigi uint32_t eq_id:8; 1367231437Sluigi uint32_t dw6rsvd1:22; 1368231437Sluigi #else 1369231437Sluigi /* dw4 */ 1370231437Sluigi uint32_t num_pages:16; 1371231437Sluigi uint32_t dw4rsvd1:16; 1372231437Sluigi /* dw5 */ 1373231437Sluigi uint32_t dw5rsvd1:12; 1374231437Sluigi uint32_t coalesce_wm:2; 1375231437Sluigi uint32_t nodelay:1; 1376231437Sluigi uint32_t dw5rsvd2:12; 1377231437Sluigi uint32_t count:2; 1378231437Sluigi uint32_t valid:1; 1379231437Sluigi uint32_t dw5rsvd3:1; 1380231437Sluigi uint32_t eventable:1; 1381231437Sluigi /* dw6 */ 1382231437Sluigi uint32_t dw6rsvd1:22; 1383231437Sluigi uint32_t eq_id:8; 1384231437Sluigi uint32_t dw6rsvd2:1; 1385231437Sluigi uint32_t armed:1; 1386231437Sluigi #endif 1387231437Sluigi /* dw7 */ 1388231437Sluigi uint32_t dw7rsvd1; 1389231437Sluigi /* dw8 */ 1390231437Sluigi uint32_t dw8rsvd1; 1391231437Sluigi } v0; 1392231437Sluigi struct { 1393231437Sluigi #ifdef _BIG_ENDIAN 1394231437Sluigi /* dw4 */ 1395231437Sluigi uint32_t dw4rsvd1:8; 1396231437Sluigi uint32_t page_size:8; 1397231437Sluigi uint32_t num_pages:16; 1398231437Sluigi /* dw5 */ 1399231437Sluigi uint32_t eventable:1; 1400231437Sluigi uint32_t dw5rsvd3:1; 1401231437Sluigi uint32_t valid:1; 1402231437Sluigi uint32_t count:2; 1403231437Sluigi uint32_t dw5rsvd2:11; 1404231437Sluigi uint32_t autovalid:1; 1405231437Sluigi uint32_t nodelay:1; 1406231437Sluigi uint32_t coalesce_wm:2; 1407231437Sluigi uint32_t dw5rsvd1:12; 1408231437Sluigi /* dw6 */ 1409231437Sluigi uint32_t armed:1; 1410231437Sluigi uint32_t dw6rsvd1:15; 1411231437Sluigi uint32_t eq_id:16; 1412231437Sluigi /* dw7 */ 1413231437Sluigi uint32_t dw7rsvd1:16; 1414231437Sluigi uint32_t cqe_count:16; 1415231437Sluigi #else 1416231437Sluigi /* dw4 */ 1417231437Sluigi uint32_t num_pages:16; 1418231437Sluigi uint32_t page_size:8; 1419231437Sluigi uint32_t dw4rsvd1:8; 1420231437Sluigi /* dw5 */ 1421231437Sluigi uint32_t dw5rsvd1:12; 1422231437Sluigi uint32_t coalesce_wm:2; 1423231437Sluigi uint32_t nodelay:1; 1424231437Sluigi uint32_t autovalid:1; 1425231437Sluigi uint32_t dw5rsvd2:11; 1426231437Sluigi uint32_t count:2; 1427231437Sluigi uint32_t valid:1; 1428231437Sluigi uint32_t dw5rsvd3:1; 1429231437Sluigi uint32_t eventable:1; 1430231437Sluigi /* dw6 */ 1431338938Sjpaetzel uint32_t eq_id:16; 1432231437Sluigi uint32_t dw6rsvd1:15; 1433231437Sluigi uint32_t armed:1; 1434231437Sluigi /* dw7 */ 1435231437Sluigi uint32_t cqe_count:16; 1436231437Sluigi uint32_t dw7rsvd1:16; 1437231437Sluigi #endif 1438231437Sluigi /* dw8 */ 1439231437Sluigi uint32_t dw8rsvd1; 1440231437Sluigi } v2; 1441231437Sluigi} oce_cq_ctx_t; 1442231437Sluigi 1443231437Sluigi/* [12] OPCODE_COMMON_CREATE_CQ */ 1444231437Sluigistruct mbx_create_common_cq { 1445231437Sluigi struct mbx_hdr hdr; 1446231437Sluigi union { 1447231437Sluigi struct { 1448231437Sluigi oce_cq_ctx_t cq_ctx; 1449231437Sluigi struct phys_addr pages[4]; 1450231437Sluigi } req; 1451231437Sluigi 1452231437Sluigi struct { 1453231437Sluigi uint16_t cq_id; 1454231437Sluigi uint16_t rsvd0; 1455231437Sluigi } rsp; 1456231437Sluigi } params; 1457231437Sluigi}; 1458231437Sluigi 1459231437Sluigi/* [54] OPCODE_COMMON_DESTROY_CQ */ 1460231437Sluigistruct mbx_destroy_common_cq { 1461231437Sluigi struct mbx_hdr hdr; 1462231437Sluigi union { 1463231437Sluigi struct { 1464231437Sluigi#ifdef _BIG_ENDIAN 1465231437Sluigi uint16_t rsvd0; 1466231437Sluigi uint16_t id; 1467231437Sluigi#else 1468231437Sluigi uint16_t id; 1469231437Sluigi uint16_t rsvd0; 1470231437Sluigi#endif 1471231437Sluigi } req; 1472231437Sluigi 1473231437Sluigi struct { 1474231437Sluigi uint32_t rsvd0; 1475231437Sluigi } rsp; 1476231437Sluigi } params; 1477231437Sluigi}; 1478231437Sluigi 1479231437Sluigitypedef union oce_mq_ctx_u { 1480231437Sluigi uint32_t dw[5]; 1481231437Sluigi struct { 1482231437Sluigi #ifdef _BIG_ENDIAN 1483231437Sluigi /* dw4 */ 1484231437Sluigi uint32_t dw4rsvd1:16; 1485231437Sluigi uint32_t num_pages:16; 1486231437Sluigi /* dw5 */ 1487231437Sluigi uint32_t cq_id:10; 1488231437Sluigi uint32_t dw5rsvd2:2; 1489231437Sluigi uint32_t ring_size:4; 1490231437Sluigi uint32_t dw5rsvd1:16; 1491231437Sluigi /* dw6 */ 1492231437Sluigi uint32_t valid:1; 1493231437Sluigi uint32_t dw6rsvd1:31; 1494231437Sluigi /* dw7 */ 1495231437Sluigi uint32_t dw7rsvd1:21; 1496231437Sluigi uint32_t async_cq_id:10; 1497231437Sluigi uint32_t async_cq_valid:1; 1498231437Sluigi #else 1499231437Sluigi /* dw4 */ 1500231437Sluigi uint32_t num_pages:16; 1501231437Sluigi uint32_t dw4rsvd1:16; 1502231437Sluigi /* dw5 */ 1503231437Sluigi uint32_t dw5rsvd1:16; 1504231437Sluigi uint32_t ring_size:4; 1505231437Sluigi uint32_t dw5rsvd2:2; 1506231437Sluigi uint32_t cq_id:10; 1507231437Sluigi /* dw6 */ 1508231437Sluigi uint32_t dw6rsvd1:31; 1509231437Sluigi uint32_t valid:1; 1510231437Sluigi /* dw7 */ 1511231437Sluigi uint32_t async_cq_valid:1; 1512231437Sluigi uint32_t async_cq_id:10; 1513231437Sluigi uint32_t dw7rsvd1:21; 1514231437Sluigi #endif 1515231437Sluigi /* dw8 */ 1516231437Sluigi uint32_t dw8rsvd1; 1517231437Sluigi } v0; 1518231437Sluigi} oce_mq_ctx_t; 1519231437Sluigi 1520231437Sluigi/** 1521231437Sluigi * @brief [21] OPCODE_COMMON_CREATE_MQ 1522231437Sluigi * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1523231437Sluigi * at most 128 entries deep (corresponding to 8 pages). 1524231437Sluigi */ 1525231437Sluigistruct mbx_create_common_mq { 1526231437Sluigi struct mbx_hdr hdr; 1527231437Sluigi union { 1528231437Sluigi struct { 1529231437Sluigi oce_mq_ctx_t context; 1530231437Sluigi struct phys_addr pages[8]; 1531231437Sluigi } req; 1532231437Sluigi 1533231437Sluigi struct { 1534231437Sluigi uint32_t mq_id:16; 1535231437Sluigi uint32_t rsvd0:16; 1536231437Sluigi } rsp; 1537231437Sluigi } params; 1538231437Sluigi}; 1539231437Sluigi 1540231879Sluigistruct mbx_create_common_mq_ex { 1541231879Sluigi struct mbx_hdr hdr; 1542231879Sluigi union { 1543231879Sluigi struct { 1544231879Sluigi oce_mq_ext_ctx_t context; 1545231879Sluigi struct phys_addr pages[8]; 1546231879Sluigi } req; 1547231879Sluigi 1548231879Sluigi struct { 1549231879Sluigi uint32_t mq_id:16; 1550231879Sluigi uint32_t rsvd0:16; 1551231879Sluigi } rsp; 1552231879Sluigi } params; 1553231879Sluigi}; 1554231879Sluigi 1555231879Sluigi 1556231879Sluigi 1557231437Sluigi/* [53] OPCODE_COMMON_DESTROY_MQ */ 1558231437Sluigistruct mbx_destroy_common_mq { 1559231437Sluigi struct mbx_hdr hdr; 1560231437Sluigi union { 1561231437Sluigi struct { 1562231437Sluigi#ifdef _BIG_ENDIAN 1563231437Sluigi uint16_t rsvd0; 1564231437Sluigi uint16_t id; 1565231437Sluigi#else 1566231437Sluigi uint16_t id; 1567231437Sluigi uint16_t rsvd0; 1568231437Sluigi#endif 1569231437Sluigi } req; 1570231437Sluigi 1571231437Sluigi struct { 1572231437Sluigi uint32_t rsvd0; 1573231437Sluigi } rsp; 1574231437Sluigi } params; 1575231437Sluigi}; 1576231437Sluigi 1577231437Sluigi/* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1578231437Sluigistruct mbx_get_common_fw_version { 1579231437Sluigi struct mbx_hdr hdr; 1580231437Sluigi union { 1581231437Sluigi struct { 1582231437Sluigi uint32_t rsvd0; 1583231437Sluigi } req; 1584231437Sluigi 1585231437Sluigi struct { 1586231437Sluigi uint8_t fw_ver_str[32]; 1587231437Sluigi uint8_t fw_on_flash_ver_str[32]; 1588231437Sluigi } rsp; 1589231437Sluigi } params; 1590231437Sluigi}; 1591231437Sluigi 1592231437Sluigi/* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1593231437Sluigistruct mbx_common_cev_modify_msi_messages { 1594231437Sluigi struct mbx_hdr hdr; 1595231437Sluigi union { 1596231437Sluigi struct { 1597231437Sluigi uint32_t num_msi_msgs; 1598231437Sluigi } req; 1599231437Sluigi 1600231437Sluigi struct { 1601231437Sluigi uint32_t rsvd0; 1602231437Sluigi } rsp; 1603231437Sluigi } params; 1604231437Sluigi}; 1605231437Sluigi 1606231437Sluigi/* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1607231437Sluigi/* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1608231437Sluigistruct mbx_common_get_set_flow_control { 1609231437Sluigi struct mbx_hdr hdr; 1610231437Sluigi#ifdef _BIG_ENDIAN 1611231437Sluigi uint16_t tx_flow_control; 1612231437Sluigi uint16_t rx_flow_control; 1613231437Sluigi#else 1614231437Sluigi uint16_t rx_flow_control; 1615231437Sluigi uint16_t tx_flow_control; 1616231437Sluigi#endif 1617231437Sluigi}; 1618231437Sluigi 1619231437Sluigienum e_flash_opcode { 1620231437Sluigi MGMT_FLASHROM_OPCODE_FLASH = 1, 1621231437Sluigi MGMT_FLASHROM_OPCODE_SAVE = 2 1622231437Sluigi}; 1623231437Sluigi 1624231437Sluigi/* [06] OPCODE_READ_COMMON_FLASHROM */ 1625231437Sluigi/* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1626231437Sluigi 1627231437Sluigistruct mbx_common_read_write_flashrom { 1628231437Sluigi struct mbx_hdr hdr; 1629231437Sluigi uint32_t flash_op_code; 1630231437Sluigi uint32_t flash_op_type; 1631231437Sluigi uint32_t data_buffer_size; 1632231437Sluigi uint32_t data_offset; 1633258140Sdelphij uint8_t data_buffer[32768]; /* + IMAGE_TRANSFER_SIZE */ 1634258140Sdelphij uint8_t rsvd[4]; 1635231437Sluigi}; 1636231437Sluigi 1637231437Sluigistruct oce_phy_info { 1638231437Sluigi uint16_t phy_type; 1639231437Sluigi uint16_t interface_type; 1640231437Sluigi uint32_t misc_params; 1641231437Sluigi uint16_t ext_phy_details; 1642231437Sluigi uint16_t rsvd; 1643231437Sluigi uint16_t auto_speeds_supported; 1644231437Sluigi uint16_t fixed_speeds_supported; 1645231437Sluigi uint32_t future_use[2]; 1646231437Sluigi}; 1647231437Sluigi 1648231437Sluigistruct mbx_common_phy_info { 1649231437Sluigi struct mbx_hdr hdr; 1650231437Sluigi union { 1651231437Sluigi struct { 1652231437Sluigi uint32_t rsvd0[4]; 1653231437Sluigi } req; 1654231437Sluigi struct { 1655231437Sluigi struct oce_phy_info phy_info; 1656231437Sluigi } rsp; 1657231437Sluigi } params; 1658231437Sluigi}; 1659231437Sluigi 1660231437Sluigi/*Lancer firmware*/ 1661231437Sluigi 1662231437Sluigistruct mbx_lancer_common_write_object { 1663231437Sluigi union { 1664231437Sluigi struct { 1665231437Sluigi struct mbx_hdr hdr; 1666231437Sluigi uint32_t write_length: 24; 1667231437Sluigi uint32_t rsvd: 7; 1668231437Sluigi uint32_t eof: 1; 1669231437Sluigi uint32_t write_offset; 1670231437Sluigi uint8_t object_name[104]; 1671231437Sluigi uint32_t descriptor_count; 1672231437Sluigi uint32_t buffer_length; 1673231437Sluigi uint32_t address_lower; 1674231437Sluigi uint32_t address_upper; 1675231437Sluigi } req; 1676231437Sluigi struct { 1677231437Sluigi uint8_t opcode; 1678231437Sluigi uint8_t subsystem; 1679231437Sluigi uint8_t rsvd1[2]; 1680231437Sluigi uint8_t status; 1681231437Sluigi uint8_t additional_status; 1682231437Sluigi uint8_t rsvd2[2]; 1683231437Sluigi uint32_t response_length; 1684231437Sluigi uint32_t actual_response_length; 1685231437Sluigi uint32_t actual_write_length; 1686231437Sluigi } rsp; 1687231437Sluigi } params; 1688231437Sluigi}; 1689231437Sluigi 1690231437Sluigi/** 1691231437Sluigi * @brief MBX Common Quiery Firmaware Config 1692231437Sluigi * This command retrieves firmware configuration parameters and adapter 1693231437Sluigi * resources available to the driver originating the request. The firmware 1694231437Sluigi * configuration defines supported protocols by the installed adapter firmware. 1695231437Sluigi * This includes which ULP processors support the specified protocols and 1696231437Sluigi * the number of TCP connections allowed for that protocol. 1697231437Sluigi */ 1698231437Sluigistruct mbx_common_query_fw_config { 1699231437Sluigi struct mbx_hdr hdr; 1700231437Sluigi union { 1701231437Sluigi struct { 1702231437Sluigi uint32_t rsvd0[30]; 1703231437Sluigi } req; 1704231437Sluigi 1705231437Sluigi struct { 1706231437Sluigi uint32_t config_number; 1707231437Sluigi uint32_t asic_revision; 1708231437Sluigi uint32_t port_id; /* used for stats retrieval */ 1709231437Sluigi uint32_t function_mode; 1710231437Sluigi struct { 1711231437Sluigi 1712231437Sluigi uint32_t ulp_mode; 1713231437Sluigi uint32_t nic_wqid_base; 1714231437Sluigi uint32_t nic_wq_tot; 1715231437Sluigi uint32_t toe_wqid_base; 1716231437Sluigi uint32_t toe_wq_tot; 1717231437Sluigi uint32_t toe_rqid_base; 1718231437Sluigi uint32_t toe_rqid_tot; 1719231437Sluigi uint32_t toe_defrqid_base; 1720231437Sluigi uint32_t toe_defrqid_count; 1721231437Sluigi uint32_t lro_rqid_base; 1722231437Sluigi uint32_t lro_rqid_tot; 1723231437Sluigi uint32_t iscsi_icd_base; 1724231437Sluigi uint32_t iscsi_icd_count; 1725231437Sluigi } ulp[2]; 1726231437Sluigi uint32_t function_caps; 1727231437Sluigi uint32_t cqid_base; 1728231437Sluigi uint32_t cqid_tot; 1729231437Sluigi uint32_t eqid_base; 1730231437Sluigi uint32_t eqid_tot; 1731231437Sluigi } rsp; 1732231437Sluigi } params; 1733231437Sluigi}; 1734231437Sluigi 1735231437Sluigienum CQFW_CONFIG_NUMBER { 1736231437Sluigi FCN_NIC_ISCSI_Initiator = 0x0, 1737231437Sluigi FCN_ISCSI_Target = 0x3, 1738231437Sluigi FCN_FCoE = 0x7, 1739231437Sluigi FCN_ISCSI_Initiator_Target = 0x9, 1740231437Sluigi FCN_NIC_RDMA_TOE = 0xA, 1741231437Sluigi FCN_NIC_RDMA_FCoE = 0xB, 1742231437Sluigi FCN_NIC_RDMA_iSCSI = 0xC, 1743231437Sluigi FCN_NIC_iSCSI_FCoE = 0xD 1744231437Sluigi}; 1745231437Sluigi 1746231437Sluigi/** 1747231437Sluigi * @brief Function Capabilites 1748231437Sluigi * This field contains the flags indicating the capabilities of 1749231437Sluigi * the SLI Host���s PCI function. 1750231437Sluigi */ 1751231437Sluigienum CQFW_FUNCTION_CAPABILITIES { 1752231437Sluigi FNC_UNCLASSIFIED_STATS = 0x1, 1753231437Sluigi FNC_RSS = 0x2, 1754231437Sluigi FNC_PROMISCUOUS = 0x4, 1755231437Sluigi FNC_LEGACY_MODE = 0x8, 1756231437Sluigi FNC_HDS = 0x4000, 1757231437Sluigi FNC_VMQ = 0x10000, 1758231437Sluigi FNC_NETQ = 0x20000, 1759231437Sluigi FNC_QGROUPS = 0x40000, 1760231437Sluigi FNC_LRO = 0x100000, 1761231437Sluigi FNC_VLAN_OFFLOAD = 0x800000 1762231437Sluigi}; 1763231437Sluigi 1764231437Sluigienum CQFW_ULP_MODES_SUPPORTED { 1765231437Sluigi ULP_TOE_MODE = 0x1, 1766231437Sluigi ULP_NIC_MODE = 0x2, 1767231437Sluigi ULP_RDMA_MODE = 0x4, 1768231437Sluigi ULP_ISCSI_INI_MODE = 0x10, 1769231437Sluigi ULP_ISCSI_TGT_MODE = 0x20, 1770231437Sluigi ULP_FCOE_INI_MODE = 0x40, 1771231437Sluigi ULP_FCOE_TGT_MODE = 0x80, 1772231437Sluigi ULP_DAL_MODE = 0x100, 1773231437Sluigi ULP_LRO_MODE = 0x200 1774231437Sluigi}; 1775231437Sluigi 1776231437Sluigi/** 1777231437Sluigi * @brief Function Modes Supported 1778231437Sluigi * Valid function modes (or protocol-types) supported on the SLI-Host���s 1779231437Sluigi * PCIe function. This field is a logical OR of the following values: 1780231437Sluigi */ 1781231437Sluigienum CQFW_FUNCTION_MODES_SUPPORTED { 1782231437Sluigi FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1783231437Sluigi FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1784231437Sluigi FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1785231437Sluigi FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1786231437Sluigi FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1787231437Sluigi FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1788231437Sluigi FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1789231437Sluigi FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1790231437Sluigi FNM_DAL_MODE = 0x100, /* DAL supported */ 1791231437Sluigi FNM_LRO_MODE = 0x200, /* LRO supported */ 1792231437Sluigi FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1793231437Sluigi FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1794231437Sluigi FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1795231437Sluigi FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1796231437Sluigi FNM_INVALID_MODE = 0x8000, /* Invalid */ 1797231437Sluigi FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1798231437Sluigi FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1799231437Sluigi FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1800231879Sluigi FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1801231437Sluigi FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1802231437Sluigi FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1803231437Sluigi FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1804231437Sluigi FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1805231437Sluigi}; 1806231437Sluigi 1807231437Sluigi 1808231437Sluigistruct mbx_common_config_vlan { 1809231437Sluigi struct mbx_hdr hdr; 1810231437Sluigi union { 1811231437Sluigi struct { 1812231437Sluigi#ifdef _BIG_ENDIAN 1813231437Sluigi uint8_t num_vlans; 1814231437Sluigi uint8_t untagged; 1815231437Sluigi uint8_t promisc; 1816231437Sluigi uint8_t if_id; 1817231437Sluigi#else 1818231437Sluigi uint8_t if_id; 1819231437Sluigi uint8_t promisc; 1820231437Sluigi uint8_t untagged; 1821231437Sluigi uint8_t num_vlans; 1822231437Sluigi#endif 1823231437Sluigi union { 1824231437Sluigi struct normal_vlan normal_vlans[64]; 1825231437Sluigi struct qinq_vlan qinq_vlans[32]; 1826231437Sluigi } tags; 1827231437Sluigi } req; 1828231437Sluigi 1829231437Sluigi struct { 1830231437Sluigi uint32_t rsvd; 1831231437Sluigi } rsp; 1832231437Sluigi } params; 1833231437Sluigi}; 1834231437Sluigi 1835231437Sluigitypedef struct iface_rx_filter_ctx { 1836231437Sluigi uint32_t global_flags_mask; 1837231437Sluigi uint32_t global_flags; 1838231437Sluigi uint32_t iface_flags_mask; 1839231437Sluigi uint32_t iface_flags; 1840231437Sluigi uint32_t if_id; 1841231437Sluigi #define IFACE_RX_NUM_MCAST_MAX 64 1842231437Sluigi uint32_t num_mcast; 1843231437Sluigi struct mbx_mcast_addr { 1844231437Sluigi uint8_t byte[6]; 1845231437Sluigi } mac[IFACE_RX_NUM_MCAST_MAX]; 1846231437Sluigi} iface_rx_filter_ctx_t; 1847231437Sluigi 1848231437Sluigi/* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1849231437Sluigistruct mbx_set_common_iface_rx_filter { 1850231437Sluigi struct mbx_hdr hdr; 1851231437Sluigi union { 1852231437Sluigi iface_rx_filter_ctx_t req; 1853231437Sluigi iface_rx_filter_ctx_t rsp; 1854231437Sluigi } params; 1855231437Sluigi}; 1856231437Sluigi 1857247880Sdelphijstruct be_set_eqd { 1858247880Sdelphij uint32_t eq_id; 1859247880Sdelphij uint32_t phase; 1860247880Sdelphij uint32_t dm; 1861247880Sdelphij}; 1862247880Sdelphij 1863231437Sluigi/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1864231437Sluigistruct mbx_modify_common_eq_delay { 1865231437Sluigi struct mbx_hdr hdr; 1866231437Sluigi union { 1867231437Sluigi struct { 1868231437Sluigi uint32_t num_eq; 1869231437Sluigi struct { 1870231437Sluigi uint32_t eq_id; 1871231437Sluigi uint32_t phase; 1872231437Sluigi uint32_t dm; 1873231437Sluigi } delay[8]; 1874231437Sluigi } req; 1875231437Sluigi 1876231437Sluigi struct { 1877231437Sluigi uint32_t rsvd0; 1878231437Sluigi } rsp; 1879231437Sluigi } params; 1880231437Sluigi}; 1881231437Sluigi 1882247880Sdelphij/* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1883247880Sdelphij 1884247880Sdelphijstruct mgmt_hba_attr { 1885247880Sdelphij int8_t flashrom_ver_str[32]; 1886247880Sdelphij int8_t manufac_name[32]; 1887247880Sdelphij uint32_t supp_modes; 1888247880Sdelphij int8_t seeprom_ver_lo; 1889247880Sdelphij int8_t seeprom_ver_hi; 1890247880Sdelphij int8_t rsvd0[2]; 1891247880Sdelphij uint32_t ioctl_data_struct_ver; 1892247880Sdelphij uint32_t ep_fw_data_struct_ver; 1893247880Sdelphij uint8_t ncsi_ver_str[12]; 1894247880Sdelphij uint32_t def_ext_to; 1895247880Sdelphij int8_t cntl_mod_num[32]; 1896247880Sdelphij int8_t cntl_desc[64]; 1897247880Sdelphij int8_t cntl_ser_num[32]; 1898247880Sdelphij int8_t ip_ver_str[32]; 1899247880Sdelphij int8_t fw_ver_str[32]; 1900247880Sdelphij int8_t bios_ver_str[32]; 1901247880Sdelphij int8_t redboot_ver_str[32]; 1902247880Sdelphij int8_t drv_ver_str[32]; 1903247880Sdelphij int8_t fw_on_flash_ver_str[32]; 1904247880Sdelphij uint32_t funcs_supp; 1905247880Sdelphij uint16_t max_cdblen; 1906247880Sdelphij uint8_t asic_rev; 1907247880Sdelphij uint8_t gen_guid[16]; 1908247880Sdelphij uint8_t hba_port_count; 1909247880Sdelphij uint16_t default_link_down_timeout; 1910247880Sdelphij uint8_t iscsi_ver_min_max; 1911247880Sdelphij uint8_t multifunc_dev; 1912247880Sdelphij uint8_t cache_valid; 1913247880Sdelphij uint8_t hba_status; 1914247880Sdelphij uint8_t max_domains_supp; 1915247880Sdelphij uint8_t phy_port; 1916247880Sdelphij uint32_t fw_post_status; 1917247880Sdelphij uint32_t hba_mtu[8]; 1918247880Sdelphij uint8_t iSCSI_feat; 1919247880Sdelphij uint8_t asic_gen; 1920247880Sdelphij uint8_t future_u8[2]; 1921247880Sdelphij uint32_t future_u32[3]; 1922247880Sdelphij}; 1923247880Sdelphij 1924247880Sdelphijstruct mgmt_cntl_attr { 1925247880Sdelphij struct mgmt_hba_attr hba_attr; 1926247880Sdelphij uint16_t pci_vendor_id; 1927247880Sdelphij uint16_t pci_device_id; 1928247880Sdelphij uint16_t pci_sub_vendor_id; 1929247880Sdelphij uint16_t pci_sub_system_id; 1930247880Sdelphij uint8_t pci_bus_num; 1931247880Sdelphij uint8_t pci_dev_num; 1932247880Sdelphij uint8_t pci_func_num; 1933247880Sdelphij uint8_t interface_type; 1934247880Sdelphij uint64_t unique_id; 1935247880Sdelphij uint8_t netfilters; 1936247880Sdelphij uint8_t rsvd0[3]; 1937247880Sdelphij uint32_t future_u32[4]; 1938247880Sdelphij}; 1939247880Sdelphij 1940247880Sdelphijstruct mbx_common_get_cntl_attr { 1941247880Sdelphij struct mbx_hdr hdr; 1942247880Sdelphij union { 1943247880Sdelphij struct { 1944247880Sdelphij uint32_t rsvd0; 1945247880Sdelphij } req; 1946247880Sdelphij struct { 1947247880Sdelphij struct mgmt_cntl_attr cntl_attr_info; 1948247880Sdelphij } rsp; 1949247880Sdelphij } params; 1950247880Sdelphij}; 1951247880Sdelphij 1952231437Sluigi/* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1953231437Sluigistruct mbx_add_common_iface_mac { 1954231437Sluigi struct mbx_hdr hdr; 1955231437Sluigi union { 1956231437Sluigi struct { 1957231437Sluigi uint32_t if_id; 1958231437Sluigi uint8_t mac_address[6]; 1959231437Sluigi uint8_t rsvd0[2]; 1960231437Sluigi } req; 1961231437Sluigi struct { 1962231437Sluigi uint32_t pmac_id; 1963231437Sluigi } rsp; 1964231437Sluigi } params; 1965231437Sluigi}; 1966231437Sluigi 1967231437Sluigi/* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1968231437Sluigistruct mbx_del_common_iface_mac { 1969231437Sluigi struct mbx_hdr hdr; 1970231437Sluigi union { 1971231437Sluigi struct { 1972231437Sluigi uint32_t if_id; 1973231437Sluigi uint32_t pmac_id; 1974231437Sluigi } req; 1975231437Sluigi struct { 1976231437Sluigi uint32_t rsvd0; 1977231437Sluigi } rsp; 1978231437Sluigi } params; 1979231437Sluigi}; 1980231437Sluigi 1981231437Sluigi/* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1982231437Sluigistruct mbx_query_common_max_mbx_buffer_size { 1983231437Sluigi struct mbx_hdr hdr; 1984231437Sluigi struct { 1985231437Sluigi uint32_t max_ioctl_bufsz; 1986231437Sluigi } rsp; 1987231437Sluigi}; 1988231437Sluigi 1989231437Sluigi/* [61] OPCODE_COMMON_FUNCTION_RESET */ 1990231437Sluigistruct ioctl_common_function_reset { 1991231437Sluigi struct mbx_hdr hdr; 1992231437Sluigi}; 1993231437Sluigi 1994247880Sdelphij/* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1995247880Sdelphijstruct mbx_read_common_transrecv_data { 1996247880Sdelphij struct mbx_hdr hdr; 1997247880Sdelphij union { 1998247880Sdelphij struct { 1999247880Sdelphij uint32_t page_num; 2000247880Sdelphij uint32_t port; 2001247880Sdelphij } req; 2002247880Sdelphij struct { 2003247880Sdelphij uint32_t page_num; 2004247880Sdelphij uint32_t port; 2005247880Sdelphij uint32_t page_data[32]; 2006247880Sdelphij } rsp; 2007247880Sdelphij } params; 2008247880Sdelphij 2009247880Sdelphij}; 2010247880Sdelphij 2011231437Sluigi/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 2012231437Sluigistruct mbx_common_func_link_cfg { 2013231437Sluigi struct mbx_hdr hdr; 2014231437Sluigi union { 2015231437Sluigi struct { 2016231437Sluigi uint32_t enable; 2017231437Sluigi } req; 2018231437Sluigi struct { 2019231437Sluigi uint32_t rsvd0; 2020231437Sluigi } rsp; 2021231437Sluigi } params; 2022231437Sluigi}; 2023231437Sluigi 2024231437Sluigi/* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 2025231437Sluigi#define CAP_SW_TIMESTAMPS 2 2026231437Sluigi#define CAP_BE3_NATIVE_ERX_API 4 2027231437Sluigi 2028231437Sluigistruct mbx_common_set_function_cap { 2029231437Sluigi struct mbx_hdr hdr; 2030231437Sluigi union { 2031231437Sluigi struct { 2032231437Sluigi uint32_t valid_capability_flags; 2033231437Sluigi uint32_t capability_flags; 2034231437Sluigi uint8_t sbz[212]; 2035231437Sluigi } req; 2036231437Sluigi struct { 2037231437Sluigi uint32_t valid_capability_flags; 2038231437Sluigi uint32_t capability_flags; 2039231437Sluigi uint8_t sbz[212]; 2040231437Sluigi } rsp; 2041231437Sluigi } params; 2042231437Sluigi}; 2043231437Sluigistruct mbx_lowlevel_test_loopback_mode { 2044231437Sluigi struct mbx_hdr hdr; 2045231437Sluigi union { 2046231437Sluigi struct { 2047231437Sluigi uint32_t loopback_type; 2048231437Sluigi uint32_t num_pkts; 2049231437Sluigi uint64_t pattern; 2050231437Sluigi uint32_t src_port; 2051231437Sluigi uint32_t dest_port; 2052231437Sluigi uint32_t pkt_size; 2053231437Sluigi }req; 2054231437Sluigi struct { 2055231437Sluigi uint32_t status; 2056231437Sluigi uint32_t num_txfer; 2057231437Sluigi uint32_t num_rx; 2058231437Sluigi uint32_t miscomp_off; 2059231437Sluigi uint32_t ticks_compl; 2060231437Sluigi }rsp; 2061231437Sluigi } params; 2062231437Sluigi}; 2063231437Sluigi 2064231437Sluigistruct mbx_lowlevel_set_loopback_mode { 2065231437Sluigi struct mbx_hdr hdr; 2066231437Sluigi union { 2067231437Sluigi struct { 2068231437Sluigi uint8_t src_port; 2069231437Sluigi uint8_t dest_port; 2070231437Sluigi uint8_t loopback_type; 2071231437Sluigi uint8_t loopback_state; 2072231437Sluigi } req; 2073231437Sluigi struct { 2074231437Sluigi uint8_t rsvd0[4]; 2075231437Sluigi } rsp; 2076231437Sluigi } params; 2077231437Sluigi}; 2078252869Sdelphij#define MAX_RESC_DESC 256 2079252869Sdelphij#define RESC_DESC_SIZE 88 2080252869Sdelphij#define ACTIVE_PROFILE 2 2081252869Sdelphij#define NIC_RESC_DESC_TYPE_V0 0x41 2082252869Sdelphij#define NIC_RESC_DESC_TYPE_V1 0x51 2083252869Sdelphij/* OPCODE_COMMON_GET_FUNCTION_CONFIG */ 2084252869Sdelphijstruct mbx_common_get_func_config { 2085252869Sdelphij struct mbx_hdr hdr; 2086252869Sdelphij union { 2087252869Sdelphij struct { 2088252869Sdelphij uint8_t rsvd; 2089252869Sdelphij uint8_t type; 2090252869Sdelphij uint16_t rsvd1; 2091252869Sdelphij } req; 2092252869Sdelphij struct { 2093252869Sdelphij uint32_t desc_count; 2094252869Sdelphij uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2095252869Sdelphij } rsp; 2096252869Sdelphij } params; 2097252869Sdelphij}; 2098231437Sluigi 2099252869Sdelphij 2100252869Sdelphij/* OPCODE_COMMON_GET_PROFILE_CONFIG */ 2101252869Sdelphij 2102252869Sdelphijstruct mbx_common_get_profile_config { 2103252869Sdelphij struct mbx_hdr hdr; 2104252869Sdelphij union { 2105252869Sdelphij struct { 2106252869Sdelphij uint8_t rsvd; 2107252869Sdelphij uint8_t type; 2108252869Sdelphij uint16_t rsvd1; 2109252869Sdelphij } req; 2110252869Sdelphij struct { 2111252869Sdelphij uint32_t desc_count; 2112252869Sdelphij uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2113252869Sdelphij } rsp; 2114252869Sdelphij } params; 2115252869Sdelphij}; 2116252869Sdelphij 2117252869Sdelphijstruct oce_nic_resc_desc { 2118252869Sdelphij uint8_t desc_type; 2119252869Sdelphij uint8_t desc_len; 2120252869Sdelphij uint8_t rsvd1; 2121252869Sdelphij uint8_t flags; 2122252869Sdelphij uint8_t vf_num; 2123252869Sdelphij uint8_t rsvd2; 2124252869Sdelphij uint8_t pf_num; 2125252869Sdelphij uint8_t rsvd3; 2126252869Sdelphij uint16_t unicast_mac_count; 2127252869Sdelphij uint8_t rsvd4[6]; 2128252869Sdelphij uint16_t mcc_count; 2129252869Sdelphij uint16_t vlan_count; 2130252869Sdelphij uint16_t mcast_mac_count; 2131252869Sdelphij uint16_t txq_count; 2132252869Sdelphij uint16_t rq_count; 2133252869Sdelphij uint16_t rssq_count; 2134252869Sdelphij uint16_t lro_count; 2135252869Sdelphij uint16_t cq_count; 2136252869Sdelphij uint16_t toe_conn_count; 2137252869Sdelphij uint16_t eq_count; 2138252869Sdelphij uint32_t rsvd5; 2139252869Sdelphij uint32_t cap_flags; 2140252869Sdelphij uint8_t link_param; 2141252869Sdelphij uint8_t rsvd6[3]; 2142252869Sdelphij uint32_t bw_min; 2143252869Sdelphij uint32_t bw_max; 2144252869Sdelphij uint8_t acpi_params; 2145252869Sdelphij uint8_t wol_param; 2146252869Sdelphij uint16_t rsvd7; 2147252869Sdelphij uint32_t rsvd8[7]; 2148252869Sdelphij 2149252869Sdelphij}; 2150252869Sdelphij 2151252869Sdelphij 2152231437Sluigistruct flash_file_hdr { 2153231437Sluigi uint8_t sign[52]; 2154231437Sluigi uint8_t ufi_version[4]; 2155231437Sluigi uint32_t file_len; 2156231437Sluigi uint32_t cksum; 2157231437Sluigi uint32_t antidote; 2158231437Sluigi uint32_t num_imgs; 2159231437Sluigi uint8_t build[24]; 2160257007Sdelphij uint8_t asic_type_rev; 2161257007Sdelphij uint8_t rsvd[31]; 2162231437Sluigi}; 2163231437Sluigi 2164231437Sluigistruct image_hdr { 2165231437Sluigi uint32_t imageid; 2166231437Sluigi uint32_t imageoffset; 2167231437Sluigi uint32_t imagelength; 2168231437Sluigi uint32_t image_checksum; 2169231437Sluigi uint8_t image_version[32]; 2170231437Sluigi}; 2171231437Sluigi 2172231437Sluigistruct flash_section_hdr { 2173231437Sluigi uint32_t format_rev; 2174231437Sluigi uint32_t cksum; 2175231437Sluigi uint32_t antidote; 2176231437Sluigi uint32_t num_images; 2177231437Sluigi uint8_t id_string[128]; 2178231437Sluigi uint32_t rsvd[4]; 2179231437Sluigi}; 2180231437Sluigi 2181231437Sluigistruct flash_section_entry { 2182231437Sluigi uint32_t type; 2183231437Sluigi uint32_t offset; 2184231437Sluigi uint32_t pad_size; 2185231437Sluigi uint32_t image_size; 2186231437Sluigi uint32_t cksum; 2187231437Sluigi uint32_t entry_point; 2188231437Sluigi uint32_t rsvd0; 2189231437Sluigi uint32_t rsvd1; 2190231437Sluigi uint8_t ver_data[32]; 2191231437Sluigi}; 2192231437Sluigi 2193231437Sluigistruct flash_sec_info { 2194231437Sluigi uint8_t cookie[32]; 2195231437Sluigi struct flash_section_hdr fsec_hdr; 2196231437Sluigi struct flash_section_entry fsec_entry[32]; 2197231437Sluigi}; 2198231437Sluigi 2199231437Sluigi 2200231437Sluigienum LOWLEVEL_SUBSYSTEM_OPCODES { 2201231437Sluigi/* Opcodes used for lowlevel functions common to many subystems. 2202231437Sluigi * Some of these opcodes are used for diagnostic functions only. 2203231437Sluigi * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2204231437Sluigi */ 2205231437Sluigi OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2206231437Sluigi OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2207231437Sluigi OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2208231437Sluigi}; 2209231437Sluigi 2210231437Sluigienum LLDP_SUBSYSTEM_OPCODES { 2211231437Sluigi/* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2212231437Sluigi OPCODE_LLDP_GET_CFG = 1, 2213231437Sluigi OPCODE_LLDP_SET_CFG = 2, 2214231437Sluigi OPCODE_LLDP_GET_STATS = 3 2215231437Sluigi}; 2216231437Sluigi 2217231437Sluigienum DCBX_SUBSYSTEM_OPCODES { 2218231437Sluigi/* Opcodes used for DCBX. */ 2219231437Sluigi OPCODE_DCBX_GET_CFG = 1, 2220231437Sluigi OPCODE_DCBX_SET_CFG = 2, 2221231437Sluigi OPCODE_DCBX_GET_MIB_INFO = 3, 2222231437Sluigi OPCODE_DCBX_GET_DCBX_MODE = 4, 2223231437Sluigi OPCODE_DCBX_SET_MODE = 5 2224231437Sluigi}; 2225231437Sluigi 2226231437Sluigienum DMTF_SUBSYSTEM_OPCODES { 2227231437Sluigi/* Opcodes used for DCBX subsystem. */ 2228231437Sluigi OPCODE_DMTF_EXEC_CLP_CMD = 1 2229231437Sluigi}; 2230231437Sluigi 2231231437Sluigienum DIAG_SUBSYSTEM_OPCODES { 2232231437Sluigi/* Opcodes used for diag functions common to many subsystems. */ 2233231437Sluigi OPCODE_DIAG_RUN_DMA_TEST = 1, 2234231437Sluigi OPCODE_DIAG_RUN_MDIO_TEST = 2, 2235231437Sluigi OPCODE_DIAG_RUN_NLB_TEST = 3, 2236231437Sluigi OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2237231437Sluigi OPCODE_DIAG_GET_MAC = 5 2238231437Sluigi}; 2239231437Sluigi 2240231437Sluigienum VENDOR_SUBSYSTEM_OPCODES { 2241231437Sluigi/* Opcodes used for Vendor subsystem. */ 2242231437Sluigi OPCODE_VENDOR_SLI = 1 2243231437Sluigi}; 2244231437Sluigi 2245231437Sluigi/* Management Status Codes */ 2246231437Sluigienum MGMT_STATUS_SUCCESS { 2247231437Sluigi MGMT_SUCCESS = 0, 2248231437Sluigi MGMT_FAILED = 1, 2249231437Sluigi MGMT_ILLEGAL_REQUEST = 2, 2250231437Sluigi MGMT_ILLEGAL_FIELD = 3, 2251231437Sluigi MGMT_INSUFFICIENT_BUFFER = 4, 2252231437Sluigi MGMT_UNAUTHORIZED_REQUEST = 5, 2253231437Sluigi MGMT_INVALID_ISNS_ADDRESS = 10, 2254231437Sluigi MGMT_INVALID_IPADDR = 11, 2255231437Sluigi MGMT_INVALID_GATEWAY = 12, 2256231437Sluigi MGMT_INVALID_SUBNETMASK = 13, 2257231437Sluigi MGMT_INVALID_TARGET_IPADDR = 16, 2258231437Sluigi MGMT_TGTTBL_FULL = 20, 2259231437Sluigi MGMT_FLASHROM_SAVE_FAILED = 23, 2260231437Sluigi MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2261231437Sluigi MGMT_INVALID_SESSION = 31, 2262231437Sluigi MGMT_INVALID_CONNECTION = 32, 2263231437Sluigi MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2264231437Sluigi MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2265231437Sluigi MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2266231437Sluigi MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2267231437Sluigi MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2268231437Sluigi MGMT_POLL_IOCTL_TIMEOUT = 40, 2269231437Sluigi MGMT_ERROR_ACITISCSI = 41, 2270231437Sluigi MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2271231437Sluigi MGMT_REBOOT_REQUIRED = 44, 2272231437Sluigi MGMT_INSUFFICIENT_TIMEOUT = 45, 2273231437Sluigi MGMT_IPADDR_NOT_SET = 46, 2274231437Sluigi MGMT_IPADDR_DUP_DETECTED = 47, 2275231437Sluigi MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2276231437Sluigi MGMT_TARGET_BUSY = 49, 2277231437Sluigi MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2278231437Sluigi MGMT_TGT_ERR_BIND_SOCKET = 51, 2279231437Sluigi MGMT_TGT_ERR_NO_SOCKET = 52, 2280231437Sluigi MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2281231437Sluigi MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2282231437Sluigi MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2283231437Sluigi MGMT_FCF_IN_USE = 58 , 2284231437Sluigi MGMT_NO_CQE = 59, 2285231437Sluigi MGMT_TARGET_NOT_FOUND = 65, 2286231437Sluigi MGMT_NOT_SUPPORTED = 66, 2287231437Sluigi MGMT_NO_FCF_RECORDS = 67, 2288231437Sluigi MGMT_FEATURE_NOT_SUPPORTED = 68, 2289231437Sluigi MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2290231437Sluigi MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2291231437Sluigi MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2292231437Sluigi MGMT_OOR = 100, 2293231437Sluigi MGMT_INVALID_PD = 101, 2294231437Sluigi MGMT_STATUS_PD_INUSE = 102, 2295231437Sluigi MGMT_INVALID_CQ = 103, 2296231437Sluigi MGMT_INVALID_QP = 104, 2297231437Sluigi MGMT_INVALID_STAG = 105, 2298231437Sluigi MGMT_ORD_EXCEEDS = 106, 2299231437Sluigi MGMT_IRD_EXCEEDS = 107, 2300231437Sluigi MGMT_SENDQ_WQE_EXCEEDS = 108, 2301231437Sluigi MGMT_RECVQ_RQE_EXCEEDS = 109, 2302231437Sluigi MGMT_SGE_SEND_EXCEEDS = 110, 2303231437Sluigi MGMT_SGE_WRITE_EXCEEDS = 111, 2304231437Sluigi MGMT_SGE_RECV_EXCEEDS = 112, 2305231437Sluigi MGMT_INVALID_STATE_CHANGE = 113, 2306231437Sluigi MGMT_MW_BOUND = 114, 2307231437Sluigi MGMT_INVALID_VA = 115, 2308231437Sluigi MGMT_INVALID_LENGTH = 116, 2309231437Sluigi MGMT_INVALID_FBO = 117, 2310231437Sluigi MGMT_INVALID_ACC_RIGHTS = 118, 2311231437Sluigi MGMT_INVALID_PBE_SIZE = 119, 2312231437Sluigi MGMT_INVALID_PBL_ENTRY = 120, 2313231437Sluigi MGMT_INVALID_PBL_OFFSET = 121, 2314231437Sluigi MGMT_ADDR_NON_EXIST = 122, 2315231437Sluigi MGMT_INVALID_VLANID = 123, 2316231437Sluigi MGMT_INVALID_MTU = 124, 2317231437Sluigi MGMT_INVALID_BACKLOG = 125, 2318231437Sluigi MGMT_CONNECTION_INPROGRESS = 126, 2319231437Sluigi MGMT_INVALID_RQE_SIZE = 127, 2320231437Sluigi MGMT_INVALID_RQE_ENTRY = 128 2321231437Sluigi}; 2322231437Sluigi 2323231437Sluigi/* Additional Management Status Codes */ 2324231437Sluigienum MGMT_ADDI_STATUS { 2325231437Sluigi MGMT_ADDI_NO_STATUS = 0, 2326231437Sluigi MGMT_ADDI_INVALID_IPTYPE = 1, 2327231437Sluigi MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2328231437Sluigi MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2329231437Sluigi MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2330231437Sluigi MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2331231437Sluigi MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2332231437Sluigi MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2333231437Sluigi MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2334231437Sluigi MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2335231437Sluigi MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2336231437Sluigi MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2337231437Sluigi MGMT_ADDI_LINK_DOWN = 23, 2338231437Sluigi MGMT_ADDI_DHCP_ERROR = 24, 2339231437Sluigi MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2340231437Sluigi MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2341231437Sluigi MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2342231437Sluigi MGMT_ADDI_REQUEST_REJECTED = 28, 2343231437Sluigi MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2344231437Sluigi MGMT_ADDI_INVALID_OPCODE = 30, 2345231437Sluigi MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2346231437Sluigi MGMT_ADDI_INVALID_KEY = 32, 2347231437Sluigi MGMT_ADDI_INVALID_DOMAIN = 35, 2348231437Sluigi MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2349231437Sluigi MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2350231437Sluigi MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2351231437Sluigi MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2352231437Sluigi MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2353231437Sluigi MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2354231437Sluigi MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2355231437Sluigi MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2356231437Sluigi MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2357231437Sluigi MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2358231437Sluigi MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2359231437Sluigi MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2360231437Sluigi MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2361231437Sluigi MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2362231437Sluigi MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2363231437Sluigi MGMT_ADDI_SAME_CHAP_SECRET = 58, 2364231437Sluigi MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2365231437Sluigi MGMT_ADDI_DUPLICATE_ENTRY = 60, 2366231437Sluigi MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2367231437Sluigi MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2368231437Sluigi MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2369231437Sluigi MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2370231437Sluigi MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2371231437Sluigi MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2372231437Sluigi MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2373231437Sluigi MGMT_ADDI_ERR_SET_VLAN = 70, 2374231437Sluigi MGMT_ADDI_ERR_DEL_VLAN = 71, 2375231437Sluigi MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2376231437Sluigi MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2377231437Sluigi MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2378231437Sluigi MGMT_ADDI_INVALID_REQUEST = 75 2379231437Sluigi}; 2380231437Sluigi 2381231437Sluigienum NIC_SUBSYSTEM_OPCODES { 2382231437Sluigi/** 2383231437Sluigi * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2384231437Sluigi * These opcodes are used for configuring the Ethernet interfaces. 2385231437Sluigi * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2386231437Sluigi */ 2387231437Sluigi NIC_CONFIG_RSS = 1, 2388231437Sluigi NIC_CONFIG_ACPI = 2, 2389231437Sluigi NIC_CONFIG_PROMISCUOUS = 3, 2390231437Sluigi NIC_GET_STATS = 4, 2391231437Sluigi NIC_CREATE_WQ = 7, 2392231437Sluigi NIC_CREATE_RQ = 8, 2393231437Sluigi NIC_DELETE_WQ = 9, 2394231437Sluigi NIC_DELETE_RQ = 10, 2395231437Sluigi NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2396231437Sluigi NIC_GET_NETWORK_STATS = 13, 2397231437Sluigi NIC_CREATE_HDS_RQ = 16, 2398231437Sluigi NIC_DELETE_HDS_RQ = 17, 2399231437Sluigi NIC_GET_PPORT_STATS = 18, 2400231437Sluigi NIC_GET_VPORT_STATS = 19, 2401231437Sluigi NIC_GET_QUEUE_STATS = 20 2402231437Sluigi}; 2403231437Sluigi 2404231437Sluigi/* Hash option flags for RSS enable */ 2405231437Sluigienum RSS_ENABLE_FLAGS { 2406231437Sluigi RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2407231437Sluigi RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2408231437Sluigi RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2409231437Sluigi RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2410247880Sdelphij RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2411247880Sdelphij RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2412247880Sdelphij RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2413231437Sluigi}; 2414231437Sluigi#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2415231437Sluigi#define RSS_DISABLE RSS_ENABLE_NONE 2416231437Sluigi 2417231437Sluigi/* NIC header WQE */ 2418231437Sluigistruct oce_nic_hdr_wqe { 2419231437Sluigi union { 2420231437Sluigi struct { 2421231437Sluigi#ifdef _BIG_ENDIAN 2422231437Sluigi /* dw0 */ 2423231437Sluigi uint32_t rsvd0; 2424231437Sluigi 2425231437Sluigi /* dw1 */ 2426231437Sluigi uint32_t last_seg_udp_len:14; 2427231437Sluigi uint32_t rsvd1:18; 2428231437Sluigi 2429231437Sluigi /* dw2 */ 2430231437Sluigi uint32_t lso_mss:14; 2431231437Sluigi uint32_t num_wqe:5; 2432231437Sluigi uint32_t rsvd4:2; 2433231437Sluigi uint32_t vlan:1; 2434231437Sluigi uint32_t lso:1; 2435231437Sluigi uint32_t tcpcs:1; 2436231437Sluigi uint32_t udpcs:1; 2437231437Sluigi uint32_t ipcs:1; 2438338938Sjpaetzel uint32_t mgmt:1; 2439338938Sjpaetzel uint32_t lso6:1; 2440231437Sluigi uint32_t forward:1; 2441231437Sluigi uint32_t crc:1; 2442231437Sluigi uint32_t event:1; 2443231437Sluigi uint32_t complete:1; 2444231437Sluigi 2445231437Sluigi /* dw3 */ 2446231437Sluigi uint32_t vlan_tag:16; 2447231437Sluigi uint32_t total_length:16; 2448231437Sluigi#else 2449231437Sluigi /* dw0 */ 2450231437Sluigi uint32_t rsvd0; 2451231437Sluigi 2452231437Sluigi /* dw1 */ 2453231437Sluigi uint32_t rsvd1:18; 2454231437Sluigi uint32_t last_seg_udp_len:14; 2455231437Sluigi 2456231437Sluigi /* dw2 */ 2457231437Sluigi uint32_t complete:1; 2458231437Sluigi uint32_t event:1; 2459231437Sluigi uint32_t crc:1; 2460231437Sluigi uint32_t forward:1; 2461338938Sjpaetzel uint32_t lso6:1; 2462338938Sjpaetzel uint32_t mgmt:1; 2463231437Sluigi uint32_t ipcs:1; 2464231437Sluigi uint32_t udpcs:1; 2465231437Sluigi uint32_t tcpcs:1; 2466231437Sluigi uint32_t lso:1; 2467231437Sluigi uint32_t vlan:1; 2468231437Sluigi uint32_t rsvd4:2; 2469231437Sluigi uint32_t num_wqe:5; 2470231437Sluigi uint32_t lso_mss:14; 2471231437Sluigi 2472231437Sluigi /* dw3 */ 2473231437Sluigi uint32_t total_length:16; 2474231437Sluigi uint32_t vlan_tag:16; 2475231437Sluigi#endif 2476231437Sluigi } s; 2477231437Sluigi uint32_t dw[4]; 2478231437Sluigi } u0; 2479231437Sluigi}; 2480231437Sluigi 2481231437Sluigi/* NIC fragment WQE */ 2482231437Sluigistruct oce_nic_frag_wqe { 2483231437Sluigi union { 2484231437Sluigi struct { 2485231437Sluigi /* dw0 */ 2486231437Sluigi uint32_t frag_pa_hi; 2487231437Sluigi /* dw1 */ 2488231437Sluigi uint32_t frag_pa_lo; 2489231437Sluigi /* dw2 */ 2490231437Sluigi uint32_t rsvd0; 2491231437Sluigi uint32_t frag_len; 2492231437Sluigi } s; 2493231437Sluigi uint32_t dw[4]; 2494231437Sluigi } u0; 2495231437Sluigi}; 2496231437Sluigi 2497231437Sluigi/* Ethernet Tx Completion Descriptor */ 2498231437Sluigistruct oce_nic_tx_cqe { 2499231437Sluigi union { 2500231437Sluigi struct { 2501231437Sluigi#ifdef _BIG_ENDIAN 2502231437Sluigi /* dw 0 */ 2503231437Sluigi uint32_t status:4; 2504231437Sluigi uint32_t rsvd0:8; 2505231437Sluigi uint32_t port:2; 2506231437Sluigi uint32_t ct:2; 2507231437Sluigi uint32_t wqe_index:16; 2508231437Sluigi 2509231437Sluigi /* dw 1 */ 2510231437Sluigi uint32_t rsvd1:5; 2511231437Sluigi uint32_t cast_enc:2; 2512231437Sluigi uint32_t lso:1; 2513231437Sluigi uint32_t nwh_bytes:8; 2514231437Sluigi uint32_t user_bytes:16; 2515231437Sluigi 2516231437Sluigi /* dw 2 */ 2517231437Sluigi uint32_t rsvd2; 2518231437Sluigi 2519231437Sluigi /* dw 3 */ 2520231437Sluigi uint32_t valid:1; 2521231437Sluigi uint32_t rsvd3:4; 2522231437Sluigi uint32_t wq_id:11; 2523231437Sluigi uint32_t num_pkts:16; 2524231437Sluigi#else 2525231437Sluigi /* dw 0 */ 2526231437Sluigi uint32_t wqe_index:16; 2527231437Sluigi uint32_t ct:2; 2528231437Sluigi uint32_t port:2; 2529231437Sluigi uint32_t rsvd0:8; 2530231437Sluigi uint32_t status:4; 2531231437Sluigi 2532231437Sluigi /* dw 1 */ 2533231437Sluigi uint32_t user_bytes:16; 2534231437Sluigi uint32_t nwh_bytes:8; 2535231437Sluigi uint32_t lso:1; 2536231437Sluigi uint32_t cast_enc:2; 2537231437Sluigi uint32_t rsvd1:5; 2538231437Sluigi /* dw 2 */ 2539231437Sluigi uint32_t rsvd2; 2540231437Sluigi 2541231437Sluigi /* dw 3 */ 2542231437Sluigi uint32_t num_pkts:16; 2543231437Sluigi uint32_t wq_id:11; 2544231437Sluigi uint32_t rsvd3:4; 2545231437Sluigi uint32_t valid:1; 2546231437Sluigi#endif 2547231437Sluigi } s; 2548231437Sluigi uint32_t dw[4]; 2549231437Sluigi } u0; 2550231437Sluigi}; 2551231437Sluigi#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2552231437Sluigi#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2553231437Sluigi 2554231437Sluigi/* Receive Queue Entry (RQE) */ 2555231437Sluigistruct oce_nic_rqe { 2556231437Sluigi union { 2557231437Sluigi struct { 2558231437Sluigi uint32_t frag_pa_hi; 2559231437Sluigi uint32_t frag_pa_lo; 2560231437Sluigi } s; 2561231437Sluigi uint32_t dw[2]; 2562231437Sluigi } u0; 2563231437Sluigi}; 2564231437Sluigi 2565231437Sluigi/* NIC Receive CQE */ 2566231437Sluigistruct oce_nic_rx_cqe { 2567231437Sluigi union { 2568231437Sluigi struct { 2569231437Sluigi#ifdef _BIG_ENDIAN 2570231437Sluigi /* dw 0 */ 2571231437Sluigi uint32_t ip_options:1; 2572231437Sluigi uint32_t port:1; 2573231437Sluigi uint32_t pkt_size:14; 2574231437Sluigi uint32_t vlan_tag:16; 2575231437Sluigi 2576231437Sluigi /* dw 1 */ 2577231437Sluigi uint32_t num_fragments:3; 2578231437Sluigi uint32_t switched:1; 2579231437Sluigi uint32_t ct:2; 2580231437Sluigi uint32_t frag_index:10; 2581231437Sluigi uint32_t rsvd0:1; 2582231437Sluigi uint32_t vlan_tag_present:1; 2583231437Sluigi uint32_t mac_dst:6; 2584231437Sluigi uint32_t ip_ver:1; 2585231437Sluigi uint32_t l4_cksum_pass:1; 2586231437Sluigi uint32_t ip_cksum_pass:1; 2587231437Sluigi uint32_t udpframe:1; 2588231437Sluigi uint32_t tcpframe:1; 2589231437Sluigi uint32_t ipframe:1; 2590231437Sluigi uint32_t rss_hp:1; 2591231437Sluigi uint32_t error:1; 2592231437Sluigi 2593231437Sluigi /* dw 2 */ 2594231437Sluigi uint32_t valid:1; 2595231437Sluigi uint32_t hds_type:2; 2596231437Sluigi uint32_t lro_pkt:1; 2597231437Sluigi uint32_t rsvd4:1; 2598231437Sluigi uint32_t hds_hdr_size:12; 2599231437Sluigi uint32_t hds_hdr_frag_index:10; 2600231437Sluigi uint32_t rss_bank:1; 2601231437Sluigi uint32_t qnq:1; 2602231437Sluigi uint32_t pkt_type:2; 2603231437Sluigi uint32_t rss_flush:1; 2604231437Sluigi 2605231437Sluigi /* dw 3 */ 2606231437Sluigi uint32_t rss_hash_value; 2607231437Sluigi#else 2608231437Sluigi /* dw 0 */ 2609231437Sluigi uint32_t vlan_tag:16; 2610231437Sluigi uint32_t pkt_size:14; 2611231437Sluigi uint32_t port:1; 2612231437Sluigi uint32_t ip_options:1; 2613231437Sluigi /* dw 1 */ 2614231437Sluigi uint32_t error:1; 2615231437Sluigi uint32_t rss_hp:1; 2616231437Sluigi uint32_t ipframe:1; 2617231437Sluigi uint32_t tcpframe:1; 2618231437Sluigi uint32_t udpframe:1; 2619231437Sluigi uint32_t ip_cksum_pass:1; 2620231437Sluigi uint32_t l4_cksum_pass:1; 2621231437Sluigi uint32_t ip_ver:1; 2622231437Sluigi uint32_t mac_dst:6; 2623231437Sluigi uint32_t vlan_tag_present:1; 2624231437Sluigi uint32_t rsvd0:1; 2625231437Sluigi uint32_t frag_index:10; 2626231437Sluigi uint32_t ct:2; 2627231437Sluigi uint32_t switched:1; 2628231437Sluigi uint32_t num_fragments:3; 2629231437Sluigi 2630231437Sluigi /* dw 2 */ 2631231437Sluigi uint32_t rss_flush:1; 2632231437Sluigi uint32_t pkt_type:2; 2633231437Sluigi uint32_t qnq:1; 2634231437Sluigi uint32_t rss_bank:1; 2635231437Sluigi uint32_t hds_hdr_frag_index:10; 2636231437Sluigi uint32_t hds_hdr_size:12; 2637231437Sluigi uint32_t rsvd4:1; 2638231437Sluigi uint32_t lro_pkt:1; 2639231437Sluigi uint32_t hds_type:2; 2640231437Sluigi uint32_t valid:1; 2641231437Sluigi /* dw 3 */ 2642231437Sluigi uint32_t rss_hash_value; 2643231437Sluigi#endif 2644231437Sluigi } s; 2645231437Sluigi uint32_t dw[4]; 2646231437Sluigi } u0; 2647231437Sluigi}; 2648231437Sluigi/* NIC Receive CQE_v1 */ 2649231437Sluigistruct oce_nic_rx_cqe_v1 { 2650231437Sluigi union { 2651231437Sluigi struct { 2652231437Sluigi#ifdef _BIG_ENDIAN 2653231437Sluigi /* dw 0 */ 2654231437Sluigi uint32_t ip_options:1; 2655231437Sluigi uint32_t vlan_tag_present:1; 2656231437Sluigi uint32_t pkt_size:14; 2657231437Sluigi uint32_t vlan_tag:16; 2658231437Sluigi 2659231437Sluigi /* dw 1 */ 2660231437Sluigi uint32_t num_fragments:3; 2661231437Sluigi uint32_t switched:1; 2662231437Sluigi uint32_t ct:2; 2663231437Sluigi uint32_t frag_index:10; 2664231437Sluigi uint32_t rsvd0:1; 2665231437Sluigi uint32_t mac_dst:7; 2666231437Sluigi uint32_t ip_ver:1; 2667231437Sluigi uint32_t l4_cksum_pass:1; 2668231437Sluigi uint32_t ip_cksum_pass:1; 2669231437Sluigi uint32_t udpframe:1; 2670231437Sluigi uint32_t tcpframe:1; 2671231437Sluigi uint32_t ipframe:1; 2672231437Sluigi uint32_t rss_hp:1; 2673231437Sluigi uint32_t error:1; 2674231437Sluigi 2675231437Sluigi /* dw 2 */ 2676231437Sluigi uint32_t valid:1; 2677231437Sluigi uint32_t rsvd4:13; 2678231437Sluigi uint32_t hds_hdr_size: 2679231437Sluigi uint32_t hds_hdr_frag_index:8; 2680231437Sluigi uint32_t vlantag:1; 2681231437Sluigi uint32_t port:2; 2682231437Sluigi uint32_t rss_bank:1; 2683231437Sluigi uint32_t qnq:1; 2684231437Sluigi uint32_t pkt_type:2; 2685231437Sluigi uint32_t rss_flush:1; 2686231437Sluigi 2687231437Sluigi /* dw 3 */ 2688231437Sluigi uint32_t rss_hash_value; 2689231437Sluigi #else 2690231437Sluigi /* dw 0 */ 2691231437Sluigi uint32_t vlan_tag:16; 2692231437Sluigi uint32_t pkt_size:14; 2693231437Sluigi uint32_t vlan_tag_present:1; 2694231437Sluigi uint32_t ip_options:1; 2695231437Sluigi /* dw 1 */ 2696231437Sluigi uint32_t error:1; 2697231437Sluigi uint32_t rss_hp:1; 2698231437Sluigi uint32_t ipframe:1; 2699231437Sluigi uint32_t tcpframe:1; 2700231437Sluigi uint32_t udpframe:1; 2701231437Sluigi uint32_t ip_cksum_pass:1; 2702231437Sluigi uint32_t l4_cksum_pass:1; 2703231437Sluigi uint32_t ip_ver:1; 2704231437Sluigi uint32_t mac_dst:7; 2705231437Sluigi uint32_t rsvd0:1; 2706231437Sluigi uint32_t frag_index:10; 2707231437Sluigi uint32_t ct:2; 2708231437Sluigi uint32_t switched:1; 2709231437Sluigi uint32_t num_fragments:3; 2710231437Sluigi 2711231437Sluigi /* dw 2 */ 2712231437Sluigi uint32_t rss_flush:1; 2713231437Sluigi uint32_t pkt_type:2; 2714231437Sluigi uint32_t qnq:1; 2715231437Sluigi uint32_t rss_bank:1; 2716231437Sluigi uint32_t port:2; 2717231437Sluigi uint32_t vlantag:1; 2718231437Sluigi uint32_t hds_hdr_frag_index:8; 2719231437Sluigi uint32_t hds_hdr_size:2; 2720231437Sluigi uint32_t rsvd4:13; 2721231437Sluigi uint32_t valid:1; 2722231437Sluigi /* dw 3 */ 2723231437Sluigi uint32_t rss_hash_value; 2724231437Sluigi#endif 2725231437Sluigi } s; 2726231437Sluigi uint32_t dw[4]; 2727231437Sluigi } u0; 2728231437Sluigi}; 2729231437Sluigi 2730231437Sluigi#define RQ_CQE_VALID_MASK 0x80 2731231437Sluigi#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2732231437Sluigi#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2733231437Sluigi 2734231437Sluigistruct mbx_config_nic_promiscuous { 2735231437Sluigi struct mbx_hdr hdr; 2736231437Sluigi union { 2737231437Sluigi struct { 2738231437Sluigi#ifdef _BIG_ENDIAN 2739231437Sluigi uint16_t rsvd0; 2740231437Sluigi uint8_t port1_promisc; 2741231437Sluigi uint8_t port0_promisc; 2742231437Sluigi#else 2743231437Sluigi uint8_t port0_promisc; 2744231437Sluigi uint8_t port1_promisc; 2745231437Sluigi uint16_t rsvd0; 2746231437Sluigi#endif 2747231437Sluigi } req; 2748231437Sluigi 2749231437Sluigi struct { 2750231437Sluigi uint32_t rsvd0; 2751231437Sluigi } rsp; 2752231437Sluigi } params; 2753231437Sluigi}; 2754231437Sluigi 2755231437Sluigitypedef union oce_wq_ctx_u { 2756231437Sluigi uint32_t dw[17]; 2757231437Sluigi struct { 2758231437Sluigi#ifdef _BIG_ENDIAN 2759231437Sluigi /* dw4 */ 2760231437Sluigi uint32_t dw4rsvd2:8; 2761231437Sluigi uint32_t nic_wq_type:8; 2762231437Sluigi uint32_t dw4rsvd1:8; 2763231437Sluigi uint32_t num_pages:8; 2764231437Sluigi /* dw5 */ 2765231437Sluigi uint32_t dw5rsvd2:12; 2766231437Sluigi uint32_t wq_size:4; 2767231437Sluigi uint32_t dw5rsvd1:16; 2768231437Sluigi /* dw6 */ 2769231437Sluigi uint32_t valid:1; 2770231437Sluigi uint32_t dw6rsvd1:31; 2771231437Sluigi /* dw7 */ 2772231437Sluigi uint32_t dw7rsvd1:16; 2773231437Sluigi uint32_t cq_id:16; 2774231437Sluigi#else 2775231437Sluigi /* dw4 */ 2776231437Sluigi uint32_t num_pages:8; 2777231437Sluigi#if 0 2778231437Sluigi uint32_t dw4rsvd1:8; 2779231437Sluigi#else 2780231437Sluigi/* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2781231437Sluigi uint32_t ulp_mask:8; 2782231437Sluigi#endif 2783231437Sluigi uint32_t nic_wq_type:8; 2784231437Sluigi uint32_t dw4rsvd2:8; 2785231437Sluigi /* dw5 */ 2786231437Sluigi uint32_t dw5rsvd1:16; 2787231437Sluigi uint32_t wq_size:4; 2788231437Sluigi uint32_t dw5rsvd2:12; 2789231437Sluigi /* dw6 */ 2790231437Sluigi uint32_t dw6rsvd1:31; 2791231437Sluigi uint32_t valid:1; 2792231437Sluigi /* dw7 */ 2793231437Sluigi uint32_t cq_id:16; 2794231437Sluigi uint32_t dw7rsvd1:16; 2795231437Sluigi#endif 2796231437Sluigi /* dw8 - dw20 */ 2797231437Sluigi uint32_t dw8_20rsvd1[13]; 2798231437Sluigi } v0; 2799231437Sluigi struct { 2800231437Sluigi#ifdef _BIG_ENDIAN 2801231437Sluigi /* dw4 */ 2802231437Sluigi uint32_t dw4rsvd2:8; 2803231437Sluigi uint32_t nic_wq_type:8; 2804231437Sluigi uint32_t dw4rsvd1:8; 2805231437Sluigi uint32_t num_pages:8; 2806231437Sluigi /* dw5 */ 2807231437Sluigi uint32_t dw5rsvd2:12; 2808231437Sluigi uint32_t wq_size:4; 2809231437Sluigi uint32_t iface_id:16; 2810231437Sluigi /* dw6 */ 2811231437Sluigi uint32_t valid:1; 2812231437Sluigi uint32_t dw6rsvd1:31; 2813231437Sluigi /* dw7 */ 2814231437Sluigi uint32_t dw7rsvd1:16; 2815231437Sluigi uint32_t cq_id:16; 2816231437Sluigi#else 2817231437Sluigi /* dw4 */ 2818231437Sluigi uint32_t num_pages:8; 2819231437Sluigi uint32_t dw4rsvd1:8; 2820231437Sluigi uint32_t nic_wq_type:8; 2821231437Sluigi uint32_t dw4rsvd2:8; 2822231437Sluigi /* dw5 */ 2823231437Sluigi uint32_t iface_id:16; 2824231437Sluigi uint32_t wq_size:4; 2825231437Sluigi uint32_t dw5rsvd2:12; 2826231437Sluigi /* dw6 */ 2827231437Sluigi uint32_t dw6rsvd1:31; 2828231437Sluigi uint32_t valid:1; 2829231437Sluigi /* dw7 */ 2830231437Sluigi uint32_t cq_id:16; 2831231437Sluigi uint32_t dw7rsvd1:16; 2832231437Sluigi#endif 2833231437Sluigi /* dw8 - dw20 */ 2834231437Sluigi uint32_t dw8_20rsvd1[13]; 2835231437Sluigi } v1; 2836231437Sluigi} oce_wq_ctx_t; 2837231437Sluigi 2838231437Sluigi/** 2839231437Sluigi * @brief [07] NIC_CREATE_WQ 2840231437Sluigi * @note 2841231437Sluigi * Lancer requires an InterfaceID to be specified with every WQ. This 2842231437Sluigi * is the basis for NIC IOV where the Interface maps to a vPort and maps 2843231437Sluigi * to both Tx and Rx sides. 2844231437Sluigi */ 2845231437Sluigi#define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2846231437Sluigi#define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2847231437Sluigistruct mbx_create_nic_wq { 2848231437Sluigi struct mbx_hdr hdr; 2849231437Sluigi union { 2850231437Sluigi struct { 2851231437Sluigi uint8_t num_pages; 2852231437Sluigi uint8_t ulp_num; 2853231437Sluigi uint16_t nic_wq_type; 2854231437Sluigi uint16_t if_id; 2855231437Sluigi uint8_t wq_size; 2856231437Sluigi uint8_t rsvd1; 2857231437Sluigi uint32_t rsvd2; 2858231437Sluigi uint16_t cq_id; 2859231437Sluigi uint16_t rsvd3; 2860231437Sluigi uint32_t rsvd4[13]; 2861231437Sluigi struct phys_addr pages[8]; 2862231437Sluigi 2863231437Sluigi } req; 2864231437Sluigi 2865231437Sluigi struct { 2866231437Sluigi uint16_t wq_id; 2867231437Sluigi uint16_t rid; 2868231437Sluigi uint32_t db_offset; 2869231437Sluigi uint8_t tc_id; 2870231437Sluigi uint8_t rsvd0[3]; 2871231437Sluigi } rsp; 2872231437Sluigi } params; 2873231437Sluigi}; 2874231437Sluigi 2875231437Sluigi/* [09] NIC_DELETE_WQ */ 2876231437Sluigistruct mbx_delete_nic_wq { 2877231437Sluigi /* dw0 - dw3 */ 2878231437Sluigi struct mbx_hdr hdr; 2879231437Sluigi union { 2880231437Sluigi struct { 2881231437Sluigi#ifdef _BIG_ENDIAN 2882231437Sluigi /* dw4 */ 2883231437Sluigi uint16_t rsvd0; 2884231437Sluigi uint16_t wq_id; 2885231437Sluigi#else 2886231437Sluigi /* dw4 */ 2887231437Sluigi uint16_t wq_id; 2888231437Sluigi uint16_t rsvd0; 2889231437Sluigi#endif 2890231437Sluigi } req; 2891231437Sluigi struct { 2892231437Sluigi uint32_t rsvd0; 2893231437Sluigi } rsp; 2894231437Sluigi } params; 2895231437Sluigi}; 2896231437Sluigi 2897231437Sluigi 2898231437Sluigi 2899231437Sluigistruct mbx_create_nic_rq { 2900231437Sluigi struct mbx_hdr hdr; 2901231437Sluigi union { 2902231437Sluigi struct { 2903231437Sluigi uint16_t cq_id; 2904231437Sluigi uint8_t frag_size; 2905231437Sluigi uint8_t num_pages; 2906231437Sluigi struct phys_addr pages[2]; 2907231437Sluigi uint32_t if_id; 2908231437Sluigi uint16_t max_frame_size; 2909231437Sluigi uint16_t page_size; 2910231437Sluigi uint32_t is_rss_queue; 2911231437Sluigi } req; 2912231437Sluigi 2913231437Sluigi struct { 2914231437Sluigi uint16_t rq_id; 2915231437Sluigi uint8_t rss_cpuid; 2916231437Sluigi uint8_t rsvd0; 2917231437Sluigi } rsp; 2918231437Sluigi 2919231437Sluigi } params; 2920231437Sluigi}; 2921231437Sluigi 2922231437Sluigi 2923231437Sluigi 2924231437Sluigi/* [10] NIC_DELETE_RQ */ 2925231437Sluigistruct mbx_delete_nic_rq { 2926231437Sluigi /* dw0 - dw3 */ 2927231437Sluigi struct mbx_hdr hdr; 2928231437Sluigi union { 2929231437Sluigi struct { 2930231437Sluigi#ifdef _BIG_ENDIAN 2931231437Sluigi /* dw4 */ 2932231437Sluigi uint16_t bypass_flush; 2933231437Sluigi uint16_t rq_id; 2934231437Sluigi#else 2935231437Sluigi /* dw4 */ 2936231437Sluigi uint16_t rq_id; 2937231437Sluigi uint16_t bypass_flush; 2938231437Sluigi#endif 2939231437Sluigi } req; 2940231437Sluigi 2941231437Sluigi struct { 2942231437Sluigi /* dw4 */ 2943231437Sluigi uint32_t rsvd0; 2944231437Sluigi } rsp; 2945231437Sluigi } params; 2946231437Sluigi}; 2947231437Sluigi 2948231437Sluigi 2949231437Sluigi 2950231437Sluigi 2951231437Sluigistruct oce_port_rxf_stats_v0 { 2952231437Sluigi uint32_t rx_bytes_lsd; /* dword 0*/ 2953231437Sluigi uint32_t rx_bytes_msd; /* dword 1*/ 2954231437Sluigi uint32_t rx_total_frames; /* dword 2*/ 2955231437Sluigi uint32_t rx_unicast_frames; /* dword 3*/ 2956231437Sluigi uint32_t rx_multicast_frames; /* dword 4*/ 2957231437Sluigi uint32_t rx_broadcast_frames; /* dword 5*/ 2958231437Sluigi uint32_t rx_crc_errors; /* dword 6*/ 2959231437Sluigi uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2960231437Sluigi uint32_t rx_pause_frames; /* dword 8*/ 2961231437Sluigi uint32_t rx_control_frames; /* dword 9*/ 2962231437Sluigi uint32_t rx_in_range_errors; /* dword 10*/ 2963231437Sluigi uint32_t rx_out_range_errors; /* dword 11*/ 2964231437Sluigi uint32_t rx_frame_too_long; /* dword 12*/ 2965231437Sluigi uint32_t rx_address_match_errors; /* dword 13*/ 2966231437Sluigi uint32_t rx_vlan_mismatch; /* dword 14*/ 2967231437Sluigi uint32_t rx_dropped_too_small; /* dword 15*/ 2968231437Sluigi uint32_t rx_dropped_too_short; /* dword 16*/ 2969231437Sluigi uint32_t rx_dropped_header_too_small; /* dword 17*/ 2970231437Sluigi uint32_t rx_dropped_tcp_length; /* dword 18*/ 2971231437Sluigi uint32_t rx_dropped_runt; /* dword 19*/ 2972231437Sluigi uint32_t rx_64_byte_packets; /* dword 20*/ 2973231437Sluigi uint32_t rx_65_127_byte_packets; /* dword 21*/ 2974231437Sluigi uint32_t rx_128_256_byte_packets; /* dword 22*/ 2975231437Sluigi uint32_t rx_256_511_byte_packets; /* dword 23*/ 2976231437Sluigi uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2977231437Sluigi uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2978231437Sluigi uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2979231437Sluigi uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2980231437Sluigi uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2981231437Sluigi uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2982231437Sluigi uint32_t rx_ip_checksum_errs; /* dword 30*/ 2983231437Sluigi uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2984231437Sluigi uint32_t rx_udp_checksum_errs; /* dword 32*/ 2985231437Sluigi uint32_t rx_non_rss_packets; /* dword 33*/ 2986231437Sluigi uint32_t rx_ipv4_packets; /* dword 34*/ 2987231437Sluigi uint32_t rx_ipv6_packets; /* dword 35*/ 2988231437Sluigi uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2989231437Sluigi uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2990231437Sluigi uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2991231437Sluigi uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2992231437Sluigi uint32_t rx_chute1_packets; /* dword 40*/ 2993231437Sluigi uint32_t rx_chute2_packets; /* dword 41*/ 2994231437Sluigi uint32_t rx_chute3_packets; /* dword 42*/ 2995231437Sluigi uint32_t rx_management_packets; /* dword 43*/ 2996231437Sluigi uint32_t rx_switched_unicast_packets; /* dword 44*/ 2997231437Sluigi uint32_t rx_switched_multicast_packets; /* dword 45*/ 2998231437Sluigi uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2999231437Sluigi uint32_t tx_bytes_lsd; /* dword 47*/ 3000231437Sluigi uint32_t tx_bytes_msd; /* dword 48*/ 3001231437Sluigi uint32_t tx_unicastframes; /* dword 49*/ 3002231437Sluigi uint32_t tx_multicastframes; /* dword 50*/ 3003231437Sluigi uint32_t tx_broadcastframes; /* dword 51*/ 3004231437Sluigi uint32_t tx_pauseframes; /* dword 52*/ 3005231437Sluigi uint32_t tx_controlframes; /* dword 53*/ 3006231437Sluigi uint32_t tx_64_byte_packets; /* dword 54*/ 3007231437Sluigi uint32_t tx_65_127_byte_packets; /* dword 55*/ 3008231437Sluigi uint32_t tx_128_256_byte_packets; /* dword 56*/ 3009231437Sluigi uint32_t tx_256_511_byte_packets; /* dword 57*/ 3010231437Sluigi uint32_t tx_512_1023_byte_packets; /* dword 58*/ 3011231437Sluigi uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 3012231437Sluigi uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 3013231437Sluigi uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 3014231437Sluigi uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 3015231437Sluigi uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 3016231437Sluigi uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 3017231437Sluigi uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 3018231437Sluigi}; 3019231437Sluigi 3020231437Sluigi 3021231437Sluigistruct oce_rxf_stats_v0 { 3022231437Sluigi struct oce_port_rxf_stats_v0 port[2]; 3023231437Sluigi uint32_t rx_drops_no_pbuf; /* dword 132*/ 3024231437Sluigi uint32_t rx_drops_no_txpb; /* dword 133*/ 3025231437Sluigi uint32_t rx_drops_no_erx_descr; /* dword 134*/ 3026231437Sluigi uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 3027231437Sluigi uint32_t management_rx_port_packets; /* dword 136*/ 3028231437Sluigi uint32_t management_rx_port_bytes; /* dword 137*/ 3029231437Sluigi uint32_t management_rx_port_pause_frames;/* dword 138*/ 3030231437Sluigi uint32_t management_rx_port_errors; /* dword 139*/ 3031231437Sluigi uint32_t management_tx_port_packets; /* dword 140*/ 3032231437Sluigi uint32_t management_tx_port_bytes; /* dword 141*/ 3033231437Sluigi uint32_t management_tx_port_pause; /* dword 142*/ 3034231437Sluigi uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 3035231437Sluigi uint32_t rx_drops_too_many_frags; /* dword 144*/ 3036231437Sluigi uint32_t rx_drops_invalid_ring; /* dword 145*/ 3037231437Sluigi uint32_t forwarded_packets; /* dword 146*/ 3038231437Sluigi uint32_t rx_drops_mtu; /* dword 147*/ 3039231437Sluigi uint32_t rsvd0[7]; 3040231437Sluigi uint32_t port0_jabber_events; 3041231437Sluigi uint32_t port1_jabber_events; 3042231437Sluigi uint32_t rsvd1[6]; 3043231437Sluigi}; 3044231437Sluigi 3045338938Sjpaetzelstruct oce_port_rxf_stats_v2 { 3046338938Sjpaetzel uint32_t rsvd0[10]; 3047338938Sjpaetzel uint32_t roce_bytes_received_lsd; 3048338938Sjpaetzel uint32_t roce_bytes_received_msd; 3049338938Sjpaetzel uint32_t rsvd1[5]; 3050338938Sjpaetzel uint32_t roce_frames_received; 3051338938Sjpaetzel uint32_t rx_crc_errors; 3052338938Sjpaetzel uint32_t rx_alignment_symbol_errors; 3053338938Sjpaetzel uint32_t rx_pause_frames; 3054338938Sjpaetzel uint32_t rx_priority_pause_frames; 3055338938Sjpaetzel uint32_t rx_control_frames; 3056338938Sjpaetzel uint32_t rx_in_range_errors; 3057338938Sjpaetzel uint32_t rx_out_range_errors; 3058338938Sjpaetzel uint32_t rx_frame_too_long; 3059338938Sjpaetzel uint32_t rx_address_match_errors; 3060338938Sjpaetzel uint32_t rx_dropped_too_small; 3061338938Sjpaetzel uint32_t rx_dropped_too_short; 3062338938Sjpaetzel uint32_t rx_dropped_header_too_small; 3063338938Sjpaetzel uint32_t rx_dropped_tcp_length; 3064338938Sjpaetzel uint32_t rx_dropped_runt; 3065338938Sjpaetzel uint32_t rsvd2[10]; 3066338938Sjpaetzel uint32_t rx_ip_checksum_errs; 3067338938Sjpaetzel uint32_t rx_tcp_checksum_errs; 3068338938Sjpaetzel uint32_t rx_udp_checksum_errs; 3069338938Sjpaetzel uint32_t rsvd3[7]; 3070338938Sjpaetzel uint32_t rx_switched_unicast_packets; 3071338938Sjpaetzel uint32_t rx_switched_multicast_packets; 3072338938Sjpaetzel uint32_t rx_switched_broadcast_packets; 3073338938Sjpaetzel uint32_t rsvd4[3]; 3074338938Sjpaetzel uint32_t tx_pauseframes; 3075338938Sjpaetzel uint32_t tx_priority_pauseframes; 3076338938Sjpaetzel uint32_t tx_controlframes; 3077338938Sjpaetzel uint32_t rsvd5[10]; 3078338938Sjpaetzel uint32_t rxpp_fifo_overflow_drop; 3079338938Sjpaetzel uint32_t rx_input_fifo_overflow_drop; 3080338938Sjpaetzel uint32_t pmem_fifo_overflow_drop; 3081338938Sjpaetzel uint32_t jabber_events; 3082338938Sjpaetzel uint32_t rsvd6[3]; 3083338938Sjpaetzel uint32_t rx_drops_payload_size; 3084338938Sjpaetzel uint32_t rx_drops_clipped_header; 3085338938Sjpaetzel uint32_t rx_drops_crc; 3086338938Sjpaetzel uint32_t roce_drops_payload_len; 3087338938Sjpaetzel uint32_t roce_drops_crc; 3088338938Sjpaetzel uint32_t rsvd7[19]; 3089338938Sjpaetzel}; 3090338938Sjpaetzel 3091338938Sjpaetzel 3092231437Sluigistruct oce_port_rxf_stats_v1 { 3093231437Sluigi uint32_t rsvd0[12]; 3094231437Sluigi uint32_t rx_crc_errors; 3095231437Sluigi uint32_t rx_alignment_symbol_errors; 3096231437Sluigi uint32_t rx_pause_frames; 3097231437Sluigi uint32_t rx_priority_pause_frames; 3098231437Sluigi uint32_t rx_control_frames; 3099231437Sluigi uint32_t rx_in_range_errors; 3100231437Sluigi uint32_t rx_out_range_errors; 3101231437Sluigi uint32_t rx_frame_too_long; 3102231437Sluigi uint32_t rx_address_match_errors; 3103231437Sluigi uint32_t rx_dropped_too_small; 3104231437Sluigi uint32_t rx_dropped_too_short; 3105231437Sluigi uint32_t rx_dropped_header_too_small; 3106231437Sluigi uint32_t rx_dropped_tcp_length; 3107231437Sluigi uint32_t rx_dropped_runt; 3108231437Sluigi uint32_t rsvd1[10]; 3109231437Sluigi uint32_t rx_ip_checksum_errs; 3110231437Sluigi uint32_t rx_tcp_checksum_errs; 3111231437Sluigi uint32_t rx_udp_checksum_errs; 3112231437Sluigi uint32_t rsvd2[7]; 3113231437Sluigi uint32_t rx_switched_unicast_packets; 3114231437Sluigi uint32_t rx_switched_multicast_packets; 3115231437Sluigi uint32_t rx_switched_broadcast_packets; 3116231437Sluigi uint32_t rsvd3[3]; 3117231437Sluigi uint32_t tx_pauseframes; 3118231437Sluigi uint32_t tx_priority_pauseframes; 3119231437Sluigi uint32_t tx_controlframes; 3120231437Sluigi uint32_t rsvd4[10]; 3121231437Sluigi uint32_t rxpp_fifo_overflow_drop; 3122231437Sluigi uint32_t rx_input_fifo_overflow_drop; 3123231437Sluigi uint32_t pmem_fifo_overflow_drop; 3124231437Sluigi uint32_t jabber_events; 3125231437Sluigi uint32_t rsvd5[3]; 3126231437Sluigi}; 3127231437Sluigi 3128338938Sjpaetzelstruct oce_rxf_stats_v2 { 3129338938Sjpaetzel struct oce_port_rxf_stats_v2 port[4]; 3130338938Sjpaetzel uint32_t rsvd0[2]; 3131338938Sjpaetzel uint32_t rx_drops_no_pbuf; 3132338938Sjpaetzel uint32_t rx_drops_no_txpb; 3133338938Sjpaetzel uint32_t rx_drops_no_erx_descr; 3134338938Sjpaetzel uint32_t rx_drops_no_tpre_descr; 3135338938Sjpaetzel uint32_t rsvd1[6]; 3136338938Sjpaetzel uint32_t rx_drops_too_many_frags; 3137338938Sjpaetzel uint32_t rx_drops_invalid_ring; 3138338938Sjpaetzel uint32_t forwarded_packets; 3139338938Sjpaetzel uint32_t rx_drops_mtu; 3140338938Sjpaetzel uint32_t rsvd2[35]; 3141338938Sjpaetzel}; 3142231437Sluigi 3143231437Sluigistruct oce_rxf_stats_v1 { 3144231437Sluigi struct oce_port_rxf_stats_v1 port[4]; 3145231437Sluigi uint32_t rsvd0[2]; 3146231437Sluigi uint32_t rx_drops_no_pbuf; 3147231437Sluigi uint32_t rx_drops_no_txpb; 3148231437Sluigi uint32_t rx_drops_no_erx_descr; 3149231437Sluigi uint32_t rx_drops_no_tpre_descr; 3150231437Sluigi uint32_t rsvd1[6]; 3151231437Sluigi uint32_t rx_drops_too_many_frags; 3152231437Sluigi uint32_t rx_drops_invalid_ring; 3153231437Sluigi uint32_t forwarded_packets; 3154231437Sluigi uint32_t rx_drops_mtu; 3155231437Sluigi uint32_t rsvd2[14]; 3156231437Sluigi}; 3157231437Sluigi 3158338938Sjpaetzelstruct oce_erx_stats_v2 { 3159338938Sjpaetzel uint32_t rx_drops_no_fragments[136]; 3160338938Sjpaetzel uint32_t rsvd[3]; 3161338938Sjpaetzel}; 3162338938Sjpaetzel 3163231437Sluigistruct oce_erx_stats_v1 { 3164231437Sluigi uint32_t rx_drops_no_fragments[68]; 3165231437Sluigi uint32_t rsvd[4]; 3166231437Sluigi}; 3167231437Sluigi 3168231437Sluigi 3169231437Sluigistruct oce_erx_stats_v0 { 3170231437Sluigi uint32_t rx_drops_no_fragments[44]; 3171231437Sluigi uint32_t rsvd[4]; 3172231437Sluigi}; 3173231437Sluigi 3174231437Sluigistruct oce_pmem_stats { 3175231437Sluigi uint32_t eth_red_drops; 3176231437Sluigi uint32_t rsvd[5]; 3177231437Sluigi}; 3178231437Sluigi 3179338938Sjpaetzelstruct oce_hw_stats_v2 { 3180338938Sjpaetzel struct oce_rxf_stats_v2 rxf; 3181338938Sjpaetzel uint32_t rsvd0[OCE_TXP_SW_SZ]; 3182338938Sjpaetzel struct oce_erx_stats_v2 erx; 3183338938Sjpaetzel struct oce_pmem_stats pmem; 3184338938Sjpaetzel uint32_t rsvd1[18]; 3185338938Sjpaetzel}; 3186338938Sjpaetzel 3187338938Sjpaetzel 3188231437Sluigistruct oce_hw_stats_v1 { 3189231437Sluigi struct oce_rxf_stats_v1 rxf; 3190231437Sluigi uint32_t rsvd0[OCE_TXP_SW_SZ]; 3191231437Sluigi struct oce_erx_stats_v1 erx; 3192231437Sluigi struct oce_pmem_stats pmem; 3193231437Sluigi uint32_t rsvd1[18]; 3194231437Sluigi}; 3195231437Sluigi 3196231437Sluigistruct oce_hw_stats_v0 { 3197231437Sluigi struct oce_rxf_stats_v0 rxf; 3198231437Sluigi uint32_t rsvd[48]; 3199231437Sluigi struct oce_erx_stats_v0 erx; 3200231437Sluigi struct oce_pmem_stats pmem; 3201231437Sluigi}; 3202231437Sluigi 3203338938Sjpaetzel#define MBX_GET_NIC_STATS(version) \ 3204338938Sjpaetzel struct mbx_get_nic_stats_v##version { \ 3205338938Sjpaetzel struct mbx_hdr hdr; \ 3206338938Sjpaetzel union { \ 3207338938Sjpaetzel struct { \ 3208338938Sjpaetzel uint32_t rsvd0; \ 3209338938Sjpaetzel } req; \ 3210338938Sjpaetzel union { \ 3211338938Sjpaetzel struct oce_hw_stats_v##version stats; \ 3212338938Sjpaetzel } rsp; \ 3213338938Sjpaetzel } params; \ 3214338938Sjpaetzel} 3215231437Sluigi 3216338938SjpaetzelMBX_GET_NIC_STATS(0); 3217338938SjpaetzelMBX_GET_NIC_STATS(1); 3218338938SjpaetzelMBX_GET_NIC_STATS(2); 3219231437Sluigi 3220231437Sluigi/* [18(0x12)] NIC_GET_PPORT_STATS */ 3221231437Sluigistruct pport_stats { 3222231437Sluigi uint64_t tx_pkts; 3223231437Sluigi uint64_t tx_unicast_pkts; 3224231437Sluigi uint64_t tx_multicast_pkts; 3225231437Sluigi uint64_t tx_broadcast_pkts; 3226231437Sluigi uint64_t tx_bytes; 3227231437Sluigi uint64_t tx_unicast_bytes; 3228231437Sluigi uint64_t tx_multicast_bytes; 3229231437Sluigi uint64_t tx_broadcast_bytes; 3230231437Sluigi uint64_t tx_discards; 3231231437Sluigi uint64_t tx_errors; 3232231437Sluigi uint64_t tx_pause_frames; 3233231437Sluigi uint64_t tx_pause_on_frames; 3234231437Sluigi uint64_t tx_pause_off_frames; 3235231437Sluigi uint64_t tx_internal_mac_errors; 3236231437Sluigi uint64_t tx_control_frames; 3237231437Sluigi uint64_t tx_pkts_64_bytes; 3238231437Sluigi uint64_t tx_pkts_65_to_127_bytes; 3239231437Sluigi uint64_t tx_pkts_128_to_255_bytes; 3240231437Sluigi uint64_t tx_pkts_256_to_511_bytes; 3241231437Sluigi uint64_t tx_pkts_512_to_1023_bytes; 3242231437Sluigi uint64_t tx_pkts_1024_to_1518_bytes; 3243231437Sluigi uint64_t tx_pkts_1519_to_2047_bytes; 3244231437Sluigi uint64_t tx_pkts_2048_to_4095_bytes; 3245231437Sluigi uint64_t tx_pkts_4096_to_8191_bytes; 3246231437Sluigi uint64_t tx_pkts_8192_to_9216_bytes; 3247231437Sluigi uint64_t tx_lso_pkts; 3248231437Sluigi uint64_t rx_pkts; 3249231437Sluigi uint64_t rx_unicast_pkts; 3250231437Sluigi uint64_t rx_multicast_pkts; 3251231437Sluigi uint64_t rx_broadcast_pkts; 3252231437Sluigi uint64_t rx_bytes; 3253231437Sluigi uint64_t rx_unicast_bytes; 3254231437Sluigi uint64_t rx_multicast_bytes; 3255231437Sluigi uint64_t rx_broadcast_bytes; 3256231437Sluigi uint32_t rx_unknown_protos; 3257231437Sluigi uint32_t reserved_word69; 3258231437Sluigi uint64_t rx_discards; 3259231437Sluigi uint64_t rx_errors; 3260231437Sluigi uint64_t rx_crc_errors; 3261231437Sluigi uint64_t rx_alignment_errors; 3262231437Sluigi uint64_t rx_symbol_errors; 3263231437Sluigi uint64_t rx_pause_frames; 3264231437Sluigi uint64_t rx_pause_on_frames; 3265231437Sluigi uint64_t rx_pause_off_frames; 3266231437Sluigi uint64_t rx_frames_too_long; 3267231437Sluigi uint64_t rx_internal_mac_errors; 3268231437Sluigi uint32_t rx_undersize_pkts; 3269231437Sluigi uint32_t rx_oversize_pkts; 3270231437Sluigi uint32_t rx_fragment_pkts; 3271231437Sluigi uint32_t rx_jabbers; 3272231437Sluigi uint64_t rx_control_frames; 3273231437Sluigi uint64_t rx_control_frames_unknown_opcode; 3274231437Sluigi uint32_t rx_in_range_errors; 3275231437Sluigi uint32_t rx_out_of_range_errors; 3276231437Sluigi uint32_t rx_address_match_errors; 3277231437Sluigi uint32_t rx_vlan_mismatch_errors; 3278231437Sluigi uint32_t rx_dropped_too_small; 3279231437Sluigi uint32_t rx_dropped_too_short; 3280231437Sluigi uint32_t rx_dropped_header_too_small; 3281231437Sluigi uint32_t rx_dropped_invalid_tcp_length; 3282231437Sluigi uint32_t rx_dropped_runt; 3283231437Sluigi uint32_t rx_ip_checksum_errors; 3284231437Sluigi uint32_t rx_tcp_checksum_errors; 3285231437Sluigi uint32_t rx_udp_checksum_errors; 3286231437Sluigi uint32_t rx_non_rss_pkts; 3287231437Sluigi uint64_t reserved_word111; 3288231437Sluigi uint64_t rx_ipv4_pkts; 3289231437Sluigi uint64_t rx_ipv6_pkts; 3290231437Sluigi uint64_t rx_ipv4_bytes; 3291231437Sluigi uint64_t rx_ipv6_bytes; 3292231437Sluigi uint64_t rx_nic_pkts; 3293231437Sluigi uint64_t rx_tcp_pkts; 3294231437Sluigi uint64_t rx_iscsi_pkts; 3295231437Sluigi uint64_t rx_management_pkts; 3296231437Sluigi uint64_t rx_switched_unicast_pkts; 3297231437Sluigi uint64_t rx_switched_multicast_pkts; 3298231437Sluigi uint64_t rx_switched_broadcast_pkts; 3299231437Sluigi uint64_t num_forwards; 3300231437Sluigi uint32_t rx_fifo_overflow; 3301231437Sluigi uint32_t rx_input_fifo_overflow; 3302231437Sluigi uint64_t rx_drops_too_many_frags; 3303231437Sluigi uint32_t rx_drops_invalid_queue; 3304231437Sluigi uint32_t reserved_word141; 3305231437Sluigi uint64_t rx_drops_mtu; 3306231437Sluigi uint64_t rx_pkts_64_bytes; 3307231437Sluigi uint64_t rx_pkts_65_to_127_bytes; 3308231437Sluigi uint64_t rx_pkts_128_to_255_bytes; 3309231437Sluigi uint64_t rx_pkts_256_to_511_bytes; 3310231437Sluigi uint64_t rx_pkts_512_to_1023_bytes; 3311231437Sluigi uint64_t rx_pkts_1024_to_1518_bytes; 3312231437Sluigi uint64_t rx_pkts_1519_to_2047_bytes; 3313231437Sluigi uint64_t rx_pkts_2048_to_4095_bytes; 3314231437Sluigi uint64_t rx_pkts_4096_to_8191_bytes; 3315231437Sluigi uint64_t rx_pkts_8192_to_9216_bytes; 3316231437Sluigi}; 3317231437Sluigi 3318231437Sluigistruct mbx_get_pport_stats { 3319231437Sluigi /* dw0 - dw3 */ 3320231437Sluigi struct mbx_hdr hdr; 3321231437Sluigi union { 3322231437Sluigi struct { 3323231437Sluigi /* dw4 */ 3324231437Sluigi#ifdef _BIG_ENDIAN 3325231437Sluigi uint32_t reset_stats:8; 3326231437Sluigi uint32_t rsvd0:8; 3327231437Sluigi uint32_t port_number:16; 3328231437Sluigi#else 3329231437Sluigi uint32_t port_number:16; 3330231437Sluigi uint32_t rsvd0:8; 3331231437Sluigi uint32_t reset_stats:8; 3332231437Sluigi#endif 3333231437Sluigi } req; 3334231437Sluigi 3335231437Sluigi union { 3336231437Sluigi struct pport_stats pps; 3337231437Sluigi uint32_t pport_stats[164 - 4 + 1]; 3338231437Sluigi } rsp; 3339231437Sluigi } params; 3340231437Sluigi}; 3341231437Sluigi 3342231437Sluigi/* [19(0x13)] NIC_GET_VPORT_STATS */ 3343231437Sluigistruct vport_stats { 3344231437Sluigi uint64_t tx_pkts; 3345231437Sluigi uint64_t tx_unicast_pkts; 3346231437Sluigi uint64_t tx_multicast_pkts; 3347231437Sluigi uint64_t tx_broadcast_pkts; 3348231437Sluigi uint64_t tx_bytes; 3349231437Sluigi uint64_t tx_unicast_bytes; 3350231437Sluigi uint64_t tx_multicast_bytes; 3351231437Sluigi uint64_t tx_broadcast_bytes; 3352231437Sluigi uint64_t tx_discards; 3353231437Sluigi uint64_t tx_errors; 3354231437Sluigi uint64_t tx_pkts_64_bytes; 3355231437Sluigi uint64_t tx_pkts_65_to_127_bytes; 3356231437Sluigi uint64_t tx_pkts_128_to_255_bytes; 3357231437Sluigi uint64_t tx_pkts_256_to_511_bytes; 3358231437Sluigi uint64_t tx_pkts_512_to_1023_bytes; 3359231437Sluigi uint64_t tx_pkts_1024_to_1518_bytes; 3360231437Sluigi uint64_t tx_pkts_1519_to_9699_bytes; 3361231437Sluigi uint64_t tx_pkts_over_9699_bytes; 3362231437Sluigi uint64_t rx_pkts; 3363231437Sluigi uint64_t rx_unicast_pkts; 3364231437Sluigi uint64_t rx_multicast_pkts; 3365231437Sluigi uint64_t rx_broadcast_pkts; 3366231437Sluigi uint64_t rx_bytes; 3367231437Sluigi uint64_t rx_unicast_bytes; 3368231437Sluigi uint64_t rx_multicast_bytes; 3369231437Sluigi uint64_t rx_broadcast_bytes; 3370231437Sluigi uint64_t rx_discards; 3371231437Sluigi uint64_t rx_errors; 3372231437Sluigi uint64_t rx_pkts_64_bytes; 3373231437Sluigi uint64_t rx_pkts_65_to_127_bytes; 3374231437Sluigi uint64_t rx_pkts_128_to_255_bytes; 3375231437Sluigi uint64_t rx_pkts_256_to_511_bytes; 3376231437Sluigi uint64_t rx_pkts_512_to_1023_bytes; 3377231437Sluigi uint64_t rx_pkts_1024_to_1518_bytes; 3378231437Sluigi uint64_t rx_pkts_1519_to_9699_bytes; 3379231437Sluigi uint64_t rx_pkts_gt_9699_bytes; 3380231437Sluigi}; 3381231437Sluigistruct mbx_get_vport_stats { 3382231437Sluigi /* dw0 - dw3 */ 3383231437Sluigi struct mbx_hdr hdr; 3384231437Sluigi union { 3385231437Sluigi struct { 3386231437Sluigi /* dw4 */ 3387231437Sluigi#ifdef _BIG_ENDIAN 3388231437Sluigi uint32_t reset_stats:8; 3389231437Sluigi uint32_t rsvd0:8; 3390231437Sluigi uint32_t vport_number:16; 3391231437Sluigi#else 3392231437Sluigi uint32_t vport_number:16; 3393231437Sluigi uint32_t rsvd0:8; 3394231437Sluigi uint32_t reset_stats:8; 3395231437Sluigi#endif 3396231437Sluigi } req; 3397231437Sluigi 3398231437Sluigi union { 3399231437Sluigi struct vport_stats vps; 3400231437Sluigi uint32_t vport_stats[75 - 4 + 1]; 3401231437Sluigi } rsp; 3402231437Sluigi } params; 3403231437Sluigi}; 3404231437Sluigi 3405231437Sluigi/** 3406231437Sluigi * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3407231437Sluigi * The significant difference between vPort and Queue statistics is 3408231437Sluigi * the packet byte counters. 3409231437Sluigi */ 3410231437Sluigistruct queue_stats { 3411231437Sluigi uint64_t packets; 3412231437Sluigi uint64_t bytes; 3413231437Sluigi uint64_t errors; 3414231437Sluigi uint64_t drops; 3415231437Sluigi uint64_t buffer_errors; /* rsvd when tx */ 3416231437Sluigi}; 3417231437Sluigi 3418231437Sluigi#define QUEUE_TYPE_WQ 0 3419231437Sluigi#define QUEUE_TYPE_RQ 1 3420231437Sluigi#define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3421231437Sluigi 3422231437Sluigistruct mbx_get_queue_stats { 3423231437Sluigi /* dw0 - dw3 */ 3424231437Sluigi struct mbx_hdr hdr; 3425231437Sluigi union { 3426231437Sluigi struct { 3427231437Sluigi /* dw4 */ 3428231437Sluigi#ifdef _BIG_ENDIAN 3429231437Sluigi uint32_t reset_stats:8; 3430231437Sluigi uint32_t queue_type:8; 3431231437Sluigi uint32_t queue_id:16; 3432231437Sluigi#else 3433231437Sluigi uint32_t queue_id:16; 3434231437Sluigi uint32_t queue_type:8; 3435231437Sluigi uint32_t reset_stats:8; 3436231437Sluigi#endif 3437231437Sluigi } req; 3438231437Sluigi 3439231437Sluigi union { 3440231437Sluigi struct queue_stats qs; 3441231437Sluigi uint32_t queue_stats[13 - 4 + 1]; 3442231437Sluigi } rsp; 3443231437Sluigi } params; 3444231437Sluigi}; 3445231437Sluigi 3446231437Sluigi 3447231437Sluigi/* [01] NIC_CONFIG_RSS */ 3448231437Sluigi#define OCE_HASH_TBL_SZ 10 3449231437Sluigi#define OCE_CPU_TBL_SZ 128 3450231437Sluigi#define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3451231437Sluigistruct mbx_config_nic_rss { 3452231437Sluigi struct mbx_hdr hdr; 3453231437Sluigi union { 3454231437Sluigi struct { 3455231437Sluigi#ifdef _BIG_ENDIAN 3456231437Sluigi uint32_t if_id; 3457231437Sluigi uint16_t cpu_tbl_sz_log2; 3458231437Sluigi uint16_t enable_rss; 3459231437Sluigi uint32_t hash[OCE_HASH_TBL_SZ]; 3460231437Sluigi uint8_t cputable[OCE_CPU_TBL_SZ]; 3461231437Sluigi uint8_t rsvd[3]; 3462231437Sluigi uint8_t flush; 3463231437Sluigi#else 3464231437Sluigi uint32_t if_id; 3465231437Sluigi uint16_t enable_rss; 3466231437Sluigi uint16_t cpu_tbl_sz_log2; 3467231437Sluigi uint32_t hash[OCE_HASH_TBL_SZ]; 3468231437Sluigi uint8_t cputable[OCE_CPU_TBL_SZ]; 3469231437Sluigi uint8_t flush; 3470231437Sluigi uint8_t rsvd[3]; 3471231437Sluigi#endif 3472231437Sluigi } req; 3473231437Sluigi struct { 3474231437Sluigi uint8_t rsvd[3]; 3475231437Sluigi uint8_t rss_bank; 3476231437Sluigi } rsp; 3477231437Sluigi } params; 3478231437Sluigi}; 3479231437Sluigi 3480231437Sluigi 3481231437Sluigi#pragma pack() 3482231437Sluigi 3483231437Sluigi 3484231437Sluigitypedef uint32_t oce_stat_t; /* statistic counter */ 3485231437Sluigi 3486231437Sluigienum OCE_RXF_PORT_STATS { 3487231437Sluigi RXF_RX_BYTES_LSD, 3488231437Sluigi RXF_RX_BYTES_MSD, 3489231437Sluigi RXF_RX_TOTAL_FRAMES, 3490231437Sluigi RXF_RX_UNICAST_FRAMES, 3491231437Sluigi RXF_RX_MULTICAST_FRAMES, 3492231437Sluigi RXF_RX_BROADCAST_FRAMES, 3493231437Sluigi RXF_RX_CRC_ERRORS, 3494231437Sluigi RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3495231437Sluigi RXF_RX_PAUSE_FRAMES, 3496231437Sluigi RXF_RX_CONTROL_FRAMES, 3497231437Sluigi RXF_RX_IN_RANGE_ERRORS, 3498231437Sluigi RXF_RX_OUT_RANGE_ERRORS, 3499231437Sluigi RXF_RX_FRAME_TOO_LONG, 3500231437Sluigi RXF_RX_ADDRESS_MATCH_ERRORS, 3501231437Sluigi RXF_RX_VLAN_MISMATCH, 3502231437Sluigi RXF_RX_DROPPED_TOO_SMALL, 3503231437Sluigi RXF_RX_DROPPED_TOO_SHORT, 3504231437Sluigi RXF_RX_DROPPED_HEADER_TOO_SMALL, 3505231437Sluigi RXF_RX_DROPPED_TCP_LENGTH, 3506231437Sluigi RXF_RX_DROPPED_RUNT, 3507231437Sluigi RXF_RX_64_BYTE_PACKETS, 3508231437Sluigi RXF_RX_65_127_BYTE_PACKETS, 3509231437Sluigi RXF_RX_128_256_BYTE_PACKETS, 3510231437Sluigi RXF_RX_256_511_BYTE_PACKETS, 3511231437Sluigi RXF_RX_512_1023_BYTE_PACKETS, 3512231437Sluigi RXF_RX_1024_1518_BYTE_PACKETS, 3513231437Sluigi RXF_RX_1519_2047_BYTE_PACKETS, 3514231437Sluigi RXF_RX_2048_4095_BYTE_PACKETS, 3515231437Sluigi RXF_RX_4096_8191_BYTE_PACKETS, 3516231437Sluigi RXF_RX_8192_9216_BYTE_PACKETS, 3517231437Sluigi RXF_RX_IP_CHECKSUM_ERRS, 3518231437Sluigi RXF_RX_TCP_CHECKSUM_ERRS, 3519231437Sluigi RXF_RX_UDP_CHECKSUM_ERRS, 3520231437Sluigi RXF_RX_NON_RSS_PACKETS, 3521231437Sluigi RXF_RX_IPV4_PACKETS, 3522231437Sluigi RXF_RX_IPV6_PACKETS, 3523231437Sluigi RXF_RX_IPV4_BYTES_LSD, 3524231437Sluigi RXF_RX_IPV4_BYTES_MSD, 3525231437Sluigi RXF_RX_IPV6_BYTES_LSD, 3526231437Sluigi RXF_RX_IPV6_BYTES_MSD, 3527231437Sluigi RXF_RX_CHUTE1_PACKETS, 3528231437Sluigi RXF_RX_CHUTE2_PACKETS, 3529231437Sluigi RXF_RX_CHUTE3_PACKETS, 3530231437Sluigi RXF_RX_MANAGEMENT_PACKETS, 3531231437Sluigi RXF_RX_SWITCHED_UNICAST_PACKETS, 3532231437Sluigi RXF_RX_SWITCHED_MULTICAST_PACKETS, 3533231437Sluigi RXF_RX_SWITCHED_BROADCAST_PACKETS, 3534231437Sluigi RXF_TX_BYTES_LSD, 3535231437Sluigi RXF_TX_BYTES_MSD, 3536231437Sluigi RXF_TX_UNICAST_FRAMES, 3537231437Sluigi RXF_TX_MULTICAST_FRAMES, 3538231437Sluigi RXF_TX_BROADCAST_FRAMES, 3539231437Sluigi RXF_TX_PAUSE_FRAMES, 3540231437Sluigi RXF_TX_CONTROL_FRAMES, 3541231437Sluigi RXF_TX_64_BYTE_PACKETS, 3542231437Sluigi RXF_TX_65_127_BYTE_PACKETS, 3543231437Sluigi RXF_TX_128_256_BYTE_PACKETS, 3544231437Sluigi RXF_TX_256_511_BYTE_PACKETS, 3545231437Sluigi RXF_TX_512_1023_BYTE_PACKETS, 3546231437Sluigi RXF_TX_1024_1518_BYTE_PACKETS, 3547231437Sluigi RXF_TX_1519_2047_BYTE_PACKETS, 3548231437Sluigi RXF_TX_2048_4095_BYTE_PACKETS, 3549231437Sluigi RXF_TX_4096_8191_BYTE_PACKETS, 3550231437Sluigi RXF_TX_8192_9216_BYTE_PACKETS, 3551231437Sluigi RXF_RX_FIFO_OVERFLOW, 3552231437Sluigi RXF_RX_INPUT_FIFO_OVERFLOW, 3553231437Sluigi RXF_PORT_STATS_N_WORDS 3554231437Sluigi}; 3555231437Sluigi 3556231437Sluigienum OCE_RXF_ADDL_STATS { 3557231437Sluigi RXF_RX_DROPS_NO_PBUF, 3558231437Sluigi RXF_RX_DROPS_NO_TXPB, 3559231437Sluigi RXF_RX_DROPS_NO_ERX_DESCR, 3560231437Sluigi RXF_RX_DROPS_NO_TPRE_DESCR, 3561231437Sluigi RXF_MANAGEMENT_RX_PORT_PACKETS, 3562231437Sluigi RXF_MANAGEMENT_RX_PORT_BYTES, 3563231437Sluigi RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3564231437Sluigi RXF_MANAGEMENT_RX_PORT_ERRORS, 3565231437Sluigi RXF_MANAGEMENT_TX_PORT_PACKETS, 3566231437Sluigi RXF_MANAGEMENT_TX_PORT_BYTES, 3567231437Sluigi RXF_MANAGEMENT_TX_PORT_PAUSE, 3568231437Sluigi RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3569231437Sluigi RXF_RX_DROPS_TOO_MANY_FRAGS, 3570231437Sluigi RXF_RX_DROPS_INVALID_RING, 3571231437Sluigi RXF_FORWARDED_PACKETS, 3572231437Sluigi RXF_RX_DROPS_MTU, 3573231437Sluigi RXF_ADDL_STATS_N_WORDS 3574231437Sluigi}; 3575231437Sluigi 3576231437Sluigienum OCE_TX_CHUTE_PORT_STATS { 3577231437Sluigi CTPT_XMT_IPV4_PKTS, 3578231437Sluigi CTPT_XMT_IPV4_LSD, 3579231437Sluigi CTPT_XMT_IPV4_MSD, 3580231437Sluigi CTPT_XMT_IPV6_PKTS, 3581231437Sluigi CTPT_XMT_IPV6_LSD, 3582231437Sluigi CTPT_XMT_IPV6_MSD, 3583231437Sluigi CTPT_REXMT_IPV4_PKTs, 3584231437Sluigi CTPT_REXMT_IPV4_LSD, 3585231437Sluigi CTPT_REXMT_IPV4_MSD, 3586231437Sluigi CTPT_REXMT_IPV6_PKTs, 3587231437Sluigi CTPT_REXMT_IPV6_LSD, 3588231437Sluigi CTPT_REXMT_IPV6_MSD, 3589231437Sluigi CTPT_N_WORDS, 3590231437Sluigi}; 3591231437Sluigi 3592231437Sluigienum OCE_RX_ERR_STATS { 3593231437Sluigi RX_DROPS_NO_FRAGMENTS_0, 3594231437Sluigi RX_DROPS_NO_FRAGMENTS_1, 3595231437Sluigi RX_DROPS_NO_FRAGMENTS_2, 3596231437Sluigi RX_DROPS_NO_FRAGMENTS_3, 3597231437Sluigi RX_DROPS_NO_FRAGMENTS_4, 3598231437Sluigi RX_DROPS_NO_FRAGMENTS_5, 3599231437Sluigi RX_DROPS_NO_FRAGMENTS_6, 3600231437Sluigi RX_DROPS_NO_FRAGMENTS_7, 3601231437Sluigi RX_DROPS_NO_FRAGMENTS_8, 3602231437Sluigi RX_DROPS_NO_FRAGMENTS_9, 3603231437Sluigi RX_DROPS_NO_FRAGMENTS_10, 3604231437Sluigi RX_DROPS_NO_FRAGMENTS_11, 3605231437Sluigi RX_DROPS_NO_FRAGMENTS_12, 3606231437Sluigi RX_DROPS_NO_FRAGMENTS_13, 3607231437Sluigi RX_DROPS_NO_FRAGMENTS_14, 3608231437Sluigi RX_DROPS_NO_FRAGMENTS_15, 3609231437Sluigi RX_DROPS_NO_FRAGMENTS_16, 3610231437Sluigi RX_DROPS_NO_FRAGMENTS_17, 3611231437Sluigi RX_DROPS_NO_FRAGMENTS_18, 3612231437Sluigi RX_DROPS_NO_FRAGMENTS_19, 3613231437Sluigi RX_DROPS_NO_FRAGMENTS_20, 3614231437Sluigi RX_DROPS_NO_FRAGMENTS_21, 3615231437Sluigi RX_DROPS_NO_FRAGMENTS_22, 3616231437Sluigi RX_DROPS_NO_FRAGMENTS_23, 3617231437Sluigi RX_DROPS_NO_FRAGMENTS_24, 3618231437Sluigi RX_DROPS_NO_FRAGMENTS_25, 3619231437Sluigi RX_DROPS_NO_FRAGMENTS_26, 3620231437Sluigi RX_DROPS_NO_FRAGMENTS_27, 3621231437Sluigi RX_DROPS_NO_FRAGMENTS_28, 3622231437Sluigi RX_DROPS_NO_FRAGMENTS_29, 3623231437Sluigi RX_DROPS_NO_FRAGMENTS_30, 3624231437Sluigi RX_DROPS_NO_FRAGMENTS_31, 3625231437Sluigi RX_DROPS_NO_FRAGMENTS_32, 3626231437Sluigi RX_DROPS_NO_FRAGMENTS_33, 3627231437Sluigi RX_DROPS_NO_FRAGMENTS_34, 3628231437Sluigi RX_DROPS_NO_FRAGMENTS_35, 3629231437Sluigi RX_DROPS_NO_FRAGMENTS_36, 3630231437Sluigi RX_DROPS_NO_FRAGMENTS_37, 3631231437Sluigi RX_DROPS_NO_FRAGMENTS_38, 3632231437Sluigi RX_DROPS_NO_FRAGMENTS_39, 3633231437Sluigi RX_DROPS_NO_FRAGMENTS_40, 3634231437Sluigi RX_DROPS_NO_FRAGMENTS_41, 3635231437Sluigi RX_DROPS_NO_FRAGMENTS_42, 3636231437Sluigi RX_DROPS_NO_FRAGMENTS_43, 3637231437Sluigi RX_DEBUG_WDMA_SENT_HOLD, 3638231437Sluigi RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3639231437Sluigi RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3640231437Sluigi RX_DEBUG_PMEM_PBUF_DEALLOC, 3641231437Sluigi RX_ERRORS_N_WORDS 3642231437Sluigi}; 3643231437Sluigi 3644231437Sluigienum OCE_PMEM_ERR_STATS { 3645231437Sluigi PMEM_ETH_RED_DROPS, 3646231437Sluigi PMEM_LRO_RED_DROPS, 3647231437Sluigi PMEM_ULP0_RED_DROPS, 3648231437Sluigi PMEM_ULP1_RED_DROPS, 3649231437Sluigi PMEM_GLOBAL_RED_DROPS, 3650231437Sluigi PMEM_ERRORS_N_WORDS 3651231437Sluigi}; 3652231437Sluigi 3653231437Sluigi/** 3654231437Sluigi * @brief Statistics for a given Physical Port 3655231437Sluigi * These satisfy all the required BE2 statistics and also the 3656231437Sluigi * following MIB objects: 3657231437Sluigi * 3658231437Sluigi * RFC 2863 - The Interfaces Group MIB 3659231437Sluigi * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3660231437Sluigi * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3661231437Sluigi * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3662231437Sluigi * 3663231437Sluigi */ 3664231437Sluigienum OCE_PPORT_STATS { 3665231437Sluigi PPORT_TX_PKTS = 0, 3666231437Sluigi PPORT_TX_UNICAST_PKTS = 2, 3667231437Sluigi PPORT_TX_MULTICAST_PKTS = 4, 3668231437Sluigi PPORT_TX_BROADCAST_PKTS = 6, 3669231437Sluigi PPORT_TX_BYTES = 8, 3670231437Sluigi PPORT_TX_UNICAST_BYTES = 10, 3671231437Sluigi PPORT_TX_MULTICAST_BYTES = 12, 3672231437Sluigi PPORT_TX_BROADCAST_BYTES = 14, 3673231437Sluigi PPORT_TX_DISCARDS = 16, 3674231437Sluigi PPORT_TX_ERRORS = 18, 3675231437Sluigi PPORT_TX_PAUSE_FRAMES = 20, 3676231437Sluigi PPORT_TX_PAUSE_ON_FRAMES = 22, 3677231437Sluigi PPORT_TX_PAUSE_OFF_FRAMES = 24, 3678231437Sluigi PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3679231437Sluigi PPORT_TX_CONTROL_FRAMES = 28, 3680231437Sluigi PPORT_TX_PKTS_64_BYTES = 30, 3681231437Sluigi PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3682231437Sluigi PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3683231437Sluigi PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3684231437Sluigi PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3685231437Sluigi PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3686231437Sluigi PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3687231437Sluigi PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3688231437Sluigi PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3689231437Sluigi PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3690231437Sluigi PPORT_TX_LSO_PKTS = 50, 3691231437Sluigi PPORT_RX_PKTS = 52, 3692231437Sluigi PPORT_RX_UNICAST_PKTS = 54, 3693231437Sluigi PPORT_RX_MULTICAST_PKTS = 56, 3694231437Sluigi PPORT_RX_BROADCAST_PKTS = 58, 3695231437Sluigi PPORT_RX_BYTES = 60, 3696231437Sluigi PPORT_RX_UNICAST_BYTES = 62, 3697231437Sluigi PPORT_RX_MULTICAST_BYTES = 64, 3698231437Sluigi PPORT_RX_BROADCAST_BYTES = 66, 3699231437Sluigi PPORT_RX_UNKNOWN_PROTOS = 68, 3700231437Sluigi PPORT_RESERVED_WORD69 = 69, 3701231437Sluigi PPORT_RX_DISCARDS = 70, 3702231437Sluigi PPORT_RX_ERRORS = 72, 3703231437Sluigi PPORT_RX_CRC_ERRORS = 74, 3704231437Sluigi PPORT_RX_ALIGNMENT_ERRORS = 76, 3705231437Sluigi PPORT_RX_SYMBOL_ERRORS = 78, 3706231437Sluigi PPORT_RX_PAUSE_FRAMES = 80, 3707231437Sluigi PPORT_RX_PAUSE_ON_FRAMES = 82, 3708231437Sluigi PPORT_RX_PAUSE_OFF_FRAMES = 84, 3709231437Sluigi PPORT_RX_FRAMES_TOO_LONG = 86, 3710231437Sluigi PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3711231437Sluigi PPORT_RX_UNDERSIZE_PKTS = 90, 3712231437Sluigi PPORT_RX_OVERSIZE_PKTS = 91, 3713231437Sluigi PPORT_RX_FRAGMENT_PKTS = 92, 3714231437Sluigi PPORT_RX_JABBERS = 93, 3715231437Sluigi PPORT_RX_CONTROL_FRAMES = 94, 3716231437Sluigi PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3717231437Sluigi PPORT_RX_IN_RANGE_ERRORS = 98, 3718231437Sluigi PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3719231437Sluigi PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3720231437Sluigi PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3721231437Sluigi PPORT_RX_DROPPED_TOO_SMALL = 102, 3722231437Sluigi PPORT_RX_DROPPED_TOO_SHORT = 103, 3723231437Sluigi PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3724231437Sluigi PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3725231437Sluigi PPORT_RX_DROPPED_RUNT = 106, 3726231437Sluigi PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3727231437Sluigi PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3728231437Sluigi PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3729231437Sluigi PPORT_RX_NON_RSS_PKTS = 110, 3730231437Sluigi PPORT_RESERVED_WORD111 = 111, 3731231437Sluigi PPORT_RX_IPV4_PKTS = 112, 3732231437Sluigi PPORT_RX_IPV6_PKTS = 114, 3733231437Sluigi PPORT_RX_IPV4_BYTES = 116, 3734231437Sluigi PPORT_RX_IPV6_BYTES = 118, 3735231437Sluigi PPORT_RX_NIC_PKTS = 120, 3736231437Sluigi PPORT_RX_TCP_PKTS = 122, 3737231437Sluigi PPORT_RX_ISCSI_PKTS = 124, 3738231437Sluigi PPORT_RX_MANAGEMENT_PKTS = 126, 3739231437Sluigi PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3740231437Sluigi PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3741231437Sluigi PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3742231437Sluigi PPORT_NUM_FORWARDS = 134, 3743231437Sluigi PPORT_RX_FIFO_OVERFLOW = 136, 3744231437Sluigi PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3745231437Sluigi PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3746231437Sluigi PPORT_RX_DROPS_INVALID_QUEUE = 140, 3747231437Sluigi PPORT_RESERVED_WORD141 = 141, 3748231437Sluigi PPORT_RX_DROPS_MTU = 142, 3749231437Sluigi PPORT_RX_PKTS_64_BYTES = 144, 3750231437Sluigi PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3751231437Sluigi PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3752231437Sluigi PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3753231437Sluigi PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3754231437Sluigi PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3755231437Sluigi PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3756231437Sluigi PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3757231437Sluigi PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3758231437Sluigi PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3759231437Sluigi PPORT_N_WORDS = 164 3760231437Sluigi}; 3761231437Sluigi 3762231437Sluigi/** 3763231437Sluigi * @brief Statistics for a given Virtual Port (vPort) 3764231437Sluigi * The following describes the vPort statistics satisfying 3765231437Sluigi * requirements of Linux/VMWare netdev statistics and 3766231437Sluigi * Microsoft Windows Statistics along with other Operating Systems. 3767231437Sluigi */ 3768231437Sluigienum OCE_VPORT_STATS { 3769231437Sluigi VPORT_TX_PKTS = 0, 3770231437Sluigi VPORT_TX_UNICAST_PKTS = 2, 3771231437Sluigi VPORT_TX_MULTICAST_PKTS = 4, 3772231437Sluigi VPORT_TX_BROADCAST_PKTS = 6, 3773231437Sluigi VPORT_TX_BYTES = 8, 3774231437Sluigi VPORT_TX_UNICAST_BYTES = 10, 3775231437Sluigi VPORT_TX_MULTICAST_BYTES = 12, 3776231437Sluigi VPORT_TX_BROADCAST_BYTES = 14, 3777231437Sluigi VPORT_TX_DISCARDS = 16, 3778231437Sluigi VPORT_TX_ERRORS = 18, 3779231437Sluigi VPORT_TX_PKTS_64_BYTES = 20, 3780231437Sluigi VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3781231437Sluigi VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3782231437Sluigi VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3783231437Sluigi VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3784231437Sluigi VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3785231437Sluigi VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3786231437Sluigi VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3787231437Sluigi VPORT_RX_PKTS = 36, 3788231437Sluigi VPORT_RX_UNICAST_PKTS = 38, 3789231437Sluigi VPORT_RX_MULTICAST_PKTS = 40, 3790231437Sluigi VPORT_RX_BROADCAST_PKTS = 42, 3791231437Sluigi VPORT_RX_BYTES = 44, 3792231437Sluigi VPORT_RX_UNICAST_BYTES = 46, 3793231437Sluigi VPORT_RX_MULTICAST_BYTES = 48, 3794231437Sluigi VPORT_RX_BROADCAST_BYTES = 50, 3795231437Sluigi VPORT_RX_DISCARDS = 52, 3796231437Sluigi VPORT_RX_ERRORS = 54, 3797231437Sluigi VPORT_RX_PKTS_64_BYTES = 56, 3798231437Sluigi VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3799231437Sluigi VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3800231437Sluigi VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3801231437Sluigi VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3802231437Sluigi VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3803231437Sluigi VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3804231437Sluigi VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3805231437Sluigi VPORT_N_WORDS = 72 3806231437Sluigi}; 3807231437Sluigi 3808231437Sluigi/** 3809231437Sluigi * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3810231437Sluigi * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3811231437Sluigi */ 3812231437Sluigienum OCE_QUEUE_TX_STATS { 3813231437Sluigi QUEUE_TX_PKTS = 0, 3814231437Sluigi QUEUE_TX_BYTES = 2, 3815231437Sluigi QUEUE_TX_ERRORS = 4, 3816231437Sluigi QUEUE_TX_DROPS = 6, 3817231437Sluigi QUEUE_TX_N_WORDS = 8 3818231437Sluigi}; 3819231437Sluigi 3820231437Sluigienum OCE_QUEUE_RX_STATS { 3821231437Sluigi QUEUE_RX_PKTS = 0, 3822231437Sluigi QUEUE_RX_BYTES = 2, 3823231437Sluigi QUEUE_RX_ERRORS = 4, 3824231437Sluigi QUEUE_RX_DROPS = 6, 3825231437Sluigi QUEUE_RX_BUFFER_ERRORS = 8, 3826231437Sluigi QUEUE_RX_N_WORDS = 10 3827231437Sluigi}; 3828338938Sjpaetzel 3829338938Sjpaetzel/* HW LRO structures */ 3830338938Sjpaetzelstruct mbx_nic_query_lro_capabilities { 3831338938Sjpaetzel struct mbx_hdr hdr; 3832338938Sjpaetzel union { 3833338938Sjpaetzel struct { 3834338938Sjpaetzel uint32_t rsvd[6]; 3835338938Sjpaetzel } req; 3836338938Sjpaetzel struct { 3837338938Sjpaetzel#ifdef _BIG_ENDIAN 3838338938Sjpaetzel uint32_t lro_flags; 3839338938Sjpaetzel uint16_t lro_rq_cnt; 3840338938Sjpaetzel uint16_t plro_max_offload; 3841338938Sjpaetzel uint32_t rsvd[4]; 3842338938Sjpaetzel#else 3843338938Sjpaetzel uint32_t lro_flags; 3844338938Sjpaetzel uint16_t plro_max_offload; 3845338938Sjpaetzel uint16_t lro_rq_cnt; 3846338938Sjpaetzel uint32_t rsvd[4]; 3847338938Sjpaetzel#endif 3848338938Sjpaetzel } rsp; 3849338938Sjpaetzel } params; 3850338938Sjpaetzel}; 3851338938Sjpaetzel 3852338938Sjpaetzelstruct mbx_nic_set_iface_lro_config { 3853338938Sjpaetzel struct mbx_hdr hdr; 3854338938Sjpaetzel union { 3855338938Sjpaetzel struct { 3856338938Sjpaetzel#ifdef _BIG_ENDIAN 3857338938Sjpaetzel uint32_t lro_flags; 3858338938Sjpaetzel uint32_t iface_id; 3859338938Sjpaetzel uint32_t max_clsc_byte_cnt; 3860338938Sjpaetzel uint32_t max_clsc_seg_cnt; 3861338938Sjpaetzel uint32_t max_clsc_usec_delay; 3862338938Sjpaetzel uint32_t min_clsc_frame_byte_cnt; 3863338938Sjpaetzel uint32_t rsvd[2]; 3864338938Sjpaetzel#else 3865338938Sjpaetzel uint32_t lro_flags; 3866338938Sjpaetzel uint32_t iface_id; 3867338938Sjpaetzel uint32_t max_clsc_byte_cnt; 3868338938Sjpaetzel uint32_t max_clsc_seg_cnt; 3869338938Sjpaetzel uint32_t max_clsc_usec_delay; 3870338938Sjpaetzel uint32_t min_clsc_frame_byte_cnt; 3871338938Sjpaetzel uint32_t rsvd[2]; 3872338938Sjpaetzel#endif 3873338938Sjpaetzel } req; 3874338938Sjpaetzel struct { 3875338938Sjpaetzel#ifdef _BIG_ENDIAN 3876338938Sjpaetzel uint32_t lro_flags; 3877338938Sjpaetzel uint32_t rsvd[7]; 3878338938Sjpaetzel#else 3879338938Sjpaetzel uint32_t lro_flags; 3880338938Sjpaetzel uint32_t rsvd[7]; 3881338938Sjpaetzel#endif 3882338938Sjpaetzel } rsp; 3883338938Sjpaetzel } params; 3884338938Sjpaetzel}; 3885338938Sjpaetzel 3886338938Sjpaetzel 3887338938Sjpaetzelstruct mbx_create_nic_rq_v2 { 3888338938Sjpaetzel struct mbx_hdr hdr; 3889338938Sjpaetzel union { 3890338938Sjpaetzel struct { 3891338938Sjpaetzel#ifdef _BIG_ENDIAN 3892338938Sjpaetzel uint8_t num_pages; 3893338938Sjpaetzel uint8_t frag_size; 3894338938Sjpaetzel uint16_t cq_id; 3895338938Sjpaetzel 3896338938Sjpaetzel uint32_t if_id; 3897338938Sjpaetzel 3898338938Sjpaetzel uint16_t page_size; 3899338938Sjpaetzel uint16_t max_frame_size; 3900338938Sjpaetzel 3901338938Sjpaetzel uint16_t rsvd; 3902338938Sjpaetzel uint16_t pd_id; 3903338938Sjpaetzel 3904338938Sjpaetzel uint16_t rsvd1; 3905338938Sjpaetzel uint16_t rq_flags; 3906338938Sjpaetzel 3907338938Sjpaetzel uint16_t hds_fixed_offset; 3908338938Sjpaetzel uint8_t hds_start; 3909338938Sjpaetzel uint8_t hds_frag; 3910338938Sjpaetzel 3911338938Sjpaetzel uint16_t hds_backfill_size; 3912338938Sjpaetzel uint16_t hds_frag_size; 3913338938Sjpaetzel 3914338938Sjpaetzel uint32_t rbq_id; 3915338938Sjpaetzel 3916338938Sjpaetzel uint32_t rsvd2[8]; 3917338938Sjpaetzel 3918338938Sjpaetzel struct phys_addr pages[2]; 3919338938Sjpaetzel#else 3920338938Sjpaetzel uint16_t cq_id; 3921338938Sjpaetzel uint8_t frag_size; 3922338938Sjpaetzel uint8_t num_pages; 3923338938Sjpaetzel 3924338938Sjpaetzel uint32_t if_id; 3925338938Sjpaetzel 3926338938Sjpaetzel uint16_t max_frame_size; 3927338938Sjpaetzel uint16_t page_size; 3928338938Sjpaetzel 3929338938Sjpaetzel uint16_t pd_id; 3930338938Sjpaetzel uint16_t rsvd; 3931338938Sjpaetzel 3932338938Sjpaetzel uint16_t rq_flags; 3933338938Sjpaetzel uint16_t rsvd1; 3934338938Sjpaetzel 3935338938Sjpaetzel uint8_t hds_frag; 3936338938Sjpaetzel uint8_t hds_start; 3937338938Sjpaetzel uint16_t hds_fixed_offset; 3938338938Sjpaetzel 3939338938Sjpaetzel uint16_t hds_frag_size; 3940338938Sjpaetzel uint16_t hds_backfill_size; 3941338938Sjpaetzel 3942338938Sjpaetzel uint32_t rbq_id; 3943338938Sjpaetzel 3944338938Sjpaetzel uint32_t rsvd2[8]; 3945338938Sjpaetzel 3946338938Sjpaetzel struct phys_addr pages[2]; 3947338938Sjpaetzel#endif 3948338938Sjpaetzel } req; 3949338938Sjpaetzel struct { 3950338938Sjpaetzel#ifdef _BIG_ENDIAN 3951338938Sjpaetzel uint8_t rsvd0; 3952338938Sjpaetzel uint8_t rss_cpuid; 3953338938Sjpaetzel uint16_t rq_id; 3954338938Sjpaetzel 3955338938Sjpaetzel uint8_t db_format; 3956338938Sjpaetzel uint8_t db_reg_set; 3957338938Sjpaetzel uint16_t rsvd1; 3958338938Sjpaetzel 3959338938Sjpaetzel uint32_t db_offset; 3960338938Sjpaetzel 3961338938Sjpaetzel uint32_t rsvd2; 3962338938Sjpaetzel 3963338938Sjpaetzel uint16_t rsvd3; 3964338938Sjpaetzel uint16_t rq_flags; 3965338938Sjpaetzel 3966338938Sjpaetzel#else 3967338938Sjpaetzel uint16_t rq_id; 3968338938Sjpaetzel uint8_t rss_cpuid; 3969338938Sjpaetzel uint8_t rsvd0; 3970338938Sjpaetzel 3971338938Sjpaetzel uint16_t rsvd1; 3972338938Sjpaetzel uint8_t db_reg_set; 3973338938Sjpaetzel uint8_t db_format; 3974338938Sjpaetzel 3975338938Sjpaetzel uint32_t db_offset; 3976338938Sjpaetzel 3977338938Sjpaetzel uint32_t rsvd2; 3978338938Sjpaetzel 3979338938Sjpaetzel uint16_t rq_flags; 3980338938Sjpaetzel uint16_t rsvd3; 3981338938Sjpaetzel#endif 3982338938Sjpaetzel } rsp; 3983338938Sjpaetzel 3984338938Sjpaetzel } params; 3985338938Sjpaetzel}; 3986338938Sjpaetzel 3987338938Sjpaetzelstruct mbx_delete_nic_rq_v1 { 3988338938Sjpaetzel struct mbx_hdr hdr; 3989338938Sjpaetzel union { 3990338938Sjpaetzel struct { 3991338938Sjpaetzel#ifdef _BIG_ENDIAN 3992338938Sjpaetzel uint16_t bypass_flush; 3993338938Sjpaetzel uint16_t rq_id; 3994338938Sjpaetzel uint16_t rsvd; 3995338938Sjpaetzel uint16_t rq_flags; 3996338938Sjpaetzel#else 3997338938Sjpaetzel uint16_t rq_id; 3998338938Sjpaetzel uint16_t bypass_flush; 3999338938Sjpaetzel uint16_t rq_flags; 4000338938Sjpaetzel uint16_t rsvd; 4001338938Sjpaetzel#endif 4002338938Sjpaetzel } req; 4003338938Sjpaetzel struct { 4004338938Sjpaetzel uint32_t rsvd[2]; 4005338938Sjpaetzel } rsp; 4006338938Sjpaetzel } params; 4007338938Sjpaetzel}; 4008338938Sjpaetzel 4009338938Sjpaetzelstruct nic_hwlro_singleton_cqe { 4010338938Sjpaetzel#ifdef _BIG_ENDIAN 4011338938Sjpaetzel /* dw 0 */ 4012338938Sjpaetzel uint32_t ip_opt:1; 4013338938Sjpaetzel uint32_t vtp:1; 4014338938Sjpaetzel uint32_t pkt_size:14; 4015338938Sjpaetzel uint32_t vlan_tag:16; 4016338938Sjpaetzel 4017338938Sjpaetzel /* dw 1 */ 4018338938Sjpaetzel uint32_t num_frags:3; 4019338938Sjpaetzel uint32_t rsvd1:3; 4020338938Sjpaetzel uint32_t frag_index:10; 4021338938Sjpaetzel uint32_t rsvd:8; 4022338938Sjpaetzel uint32_t ipv6_frame:1; 4023338938Sjpaetzel uint32_t l4_cksum_pass:1; 4024338938Sjpaetzel uint32_t ip_cksum_pass:1; 4025338938Sjpaetzel uint32_t udpframe:1; 4026338938Sjpaetzel uint32_t tcpframe:1; 4027338938Sjpaetzel uint32_t ipframe:1; 4028338938Sjpaetzel uint32_t rss_hp:1; 4029338938Sjpaetzel uint32_t error:1; 4030338938Sjpaetzel 4031338938Sjpaetzel /* dw 2 */ 4032338938Sjpaetzel uint32_t valid:1; 4033338938Sjpaetzel uint32_t cqe_type:2; 4034338938Sjpaetzel uint32_t debug:7; 4035338938Sjpaetzel uint32_t rsvd4:6; 4036338938Sjpaetzel uint32_t data_offset:8; 4037338938Sjpaetzel uint32_t rsvd3:3; 4038338938Sjpaetzel uint32_t rss_bank:1; 4039338938Sjpaetzel uint32_t qnq:1; 4040338938Sjpaetzel uint32_t rsvd2:3; 4041338938Sjpaetzel 4042338938Sjpaetzel /* dw 3 */ 4043338938Sjpaetzel uint32_t rss_hash_value; 4044338938Sjpaetzel#else 4045338938Sjpaetzel /* dw 0 */ 4046338938Sjpaetzel uint32_t vlan_tag:16; 4047338938Sjpaetzel uint32_t pkt_size:14; 4048338938Sjpaetzel uint32_t vtp:1; 4049338938Sjpaetzel uint32_t ip_opt:1; 4050338938Sjpaetzel 4051338938Sjpaetzel /* dw 1 */ 4052338938Sjpaetzel uint32_t error:1; 4053338938Sjpaetzel uint32_t rss_hp:1; 4054338938Sjpaetzel uint32_t ipframe:1; 4055338938Sjpaetzel uint32_t tcpframe:1; 4056338938Sjpaetzel uint32_t udpframe:1; 4057338938Sjpaetzel uint32_t ip_cksum_pass:1; 4058338938Sjpaetzel uint32_t l4_cksum_pass:1; 4059338938Sjpaetzel uint32_t ipv6_frame:1; 4060338938Sjpaetzel uint32_t rsvd:8; 4061338938Sjpaetzel uint32_t frag_index:10; 4062338938Sjpaetzel uint32_t rsvd1:3; 4063338938Sjpaetzel uint32_t num_frags:3; 4064338938Sjpaetzel 4065338938Sjpaetzel /* dw 2 */ 4066338938Sjpaetzel uint32_t rsvd2:3; 4067338938Sjpaetzel uint32_t qnq:1; 4068338938Sjpaetzel uint32_t rss_bank:1; 4069338938Sjpaetzel uint32_t rsvd3:3; 4070338938Sjpaetzel uint32_t data_offset:8; 4071338938Sjpaetzel uint32_t rsvd4:6; 4072338938Sjpaetzel uint32_t debug:7; 4073338938Sjpaetzel uint32_t cqe_type:2; 4074338938Sjpaetzel uint32_t valid:1; 4075338938Sjpaetzel 4076338938Sjpaetzel /* dw 3 */ 4077338938Sjpaetzel uint32_t rss_hash_value; 4078338938Sjpaetzel#endif 4079338938Sjpaetzel}; 4080338938Sjpaetzel 4081338938Sjpaetzelstruct nic_hwlro_cqe_part1 { 4082338938Sjpaetzel#ifdef _BIG_ENDIAN 4083338938Sjpaetzel /* dw 0 */ 4084338938Sjpaetzel uint32_t tcp_timestamp_val; 4085338938Sjpaetzel 4086338938Sjpaetzel /* dw 1 */ 4087338938Sjpaetzel uint32_t tcp_timestamp_ecr; 4088338938Sjpaetzel 4089338938Sjpaetzel /* dw 2 */ 4090338938Sjpaetzel uint32_t valid:1; 4091338938Sjpaetzel uint32_t cqe_type:2; 4092338938Sjpaetzel uint32_t rsvd3:7; 4093338938Sjpaetzel uint32_t rss_policy:4; 4094338938Sjpaetzel uint32_t rsvd2:2; 4095338938Sjpaetzel uint32_t data_offset:8; 4096338938Sjpaetzel uint32_t rsvd1:1; 4097338938Sjpaetzel uint32_t lro_desc:1; 4098338938Sjpaetzel uint32_t lro_timer_pop:1; 4099338938Sjpaetzel uint32_t rss_bank:1; 4100338938Sjpaetzel uint32_t qnq:1; 4101338938Sjpaetzel uint32_t rsvd:2; 4102338938Sjpaetzel uint32_t rss_flush:1; 4103338938Sjpaetzel 4104338938Sjpaetzel /* dw 3 */ 4105338938Sjpaetzel uint32_t rss_hash_value; 4106338938Sjpaetzel#else 4107338938Sjpaetzel /* dw 0 */ 4108338938Sjpaetzel uint32_t tcp_timestamp_val; 4109338938Sjpaetzel 4110338938Sjpaetzel /* dw 1 */ 4111338938Sjpaetzel uint32_t tcp_timestamp_ecr; 4112338938Sjpaetzel 4113338938Sjpaetzel /* dw 2 */ 4114338938Sjpaetzel uint32_t rss_flush:1; 4115338938Sjpaetzel uint32_t rsvd:2; 4116338938Sjpaetzel uint32_t qnq:1; 4117338938Sjpaetzel uint32_t rss_bank:1; 4118338938Sjpaetzel uint32_t lro_timer_pop:1; 4119338938Sjpaetzel uint32_t lro_desc:1; 4120338938Sjpaetzel uint32_t rsvd1:1; 4121338938Sjpaetzel uint32_t data_offset:8; 4122338938Sjpaetzel uint32_t rsvd2:2; 4123338938Sjpaetzel uint32_t rss_policy:4; 4124338938Sjpaetzel uint32_t rsvd3:7; 4125338938Sjpaetzel uint32_t cqe_type:2; 4126338938Sjpaetzel uint32_t valid:1; 4127338938Sjpaetzel 4128338938Sjpaetzel /* dw 3 */ 4129338938Sjpaetzel uint32_t rss_hash_value; 4130338938Sjpaetzel#endif 4131338938Sjpaetzel}; 4132338938Sjpaetzel 4133338938Sjpaetzelstruct nic_hwlro_cqe_part2 { 4134338938Sjpaetzel#ifdef _BIG_ENDIAN 4135338938Sjpaetzel /* dw 0 */ 4136338938Sjpaetzel uint32_t ip_opt:1; 4137338938Sjpaetzel uint32_t vtp:1; 4138338938Sjpaetzel uint32_t pkt_size:14; 4139338938Sjpaetzel uint32_t vlan_tag:16; 4140338938Sjpaetzel 4141338938Sjpaetzel /* dw 1 */ 4142338938Sjpaetzel uint32_t tcp_window:16; 4143338938Sjpaetzel uint32_t coalesced_size:16; 4144338938Sjpaetzel 4145338938Sjpaetzel /* dw 2 */ 4146338938Sjpaetzel uint32_t valid:1; 4147338938Sjpaetzel uint32_t cqe_type:2; 4148338938Sjpaetzel uint32_t rsvd:2; 4149338938Sjpaetzel uint32_t push:1; 4150338938Sjpaetzel uint32_t ts_opt:1; 4151338938Sjpaetzel uint32_t threshold:1; 4152338938Sjpaetzel uint32_t seg_cnt:8; 4153338938Sjpaetzel uint32_t frame_lifespan:8; 4154338938Sjpaetzel uint32_t ipv6_frame:1; 4155338938Sjpaetzel uint32_t l4_cksum_pass:1; 4156338938Sjpaetzel uint32_t ip_cksum_pass:1; 4157338938Sjpaetzel uint32_t udpframe:1; 4158338938Sjpaetzel uint32_t tcpframe:1; 4159338938Sjpaetzel uint32_t ipframe:1; 4160338938Sjpaetzel uint32_t rss_hp:1; 4161338938Sjpaetzel uint32_t error:1; 4162338938Sjpaetzel 4163338938Sjpaetzel /* dw 3 */ 4164338938Sjpaetzel uint32_t tcp_ack_num; 4165338938Sjpaetzel#else 4166338938Sjpaetzel /* dw 0 */ 4167338938Sjpaetzel uint32_t vlan_tag:16; 4168338938Sjpaetzel uint32_t pkt_size:14; 4169338938Sjpaetzel uint32_t vtp:1; 4170338938Sjpaetzel uint32_t ip_opt:1; 4171338938Sjpaetzel 4172338938Sjpaetzel /* dw 1 */ 4173338938Sjpaetzel uint32_t coalesced_size:16; 4174338938Sjpaetzel uint32_t tcp_window:16; 4175338938Sjpaetzel 4176338938Sjpaetzel /* dw 2 */ 4177338938Sjpaetzel uint32_t error:1; 4178338938Sjpaetzel uint32_t rss_hp:1; 4179338938Sjpaetzel uint32_t ipframe:1; 4180338938Sjpaetzel uint32_t tcpframe:1; 4181338938Sjpaetzel uint32_t udpframe:1; 4182338938Sjpaetzel uint32_t ip_cksum_pass:1; 4183338938Sjpaetzel uint32_t l4_cksum_pass:1; 4184338938Sjpaetzel uint32_t ipv6_frame:1; 4185338938Sjpaetzel uint32_t frame_lifespan:8; 4186338938Sjpaetzel uint32_t seg_cnt:8; 4187338938Sjpaetzel uint32_t threshold:1; 4188338938Sjpaetzel uint32_t ts_opt:1; 4189338938Sjpaetzel uint32_t push:1; 4190338938Sjpaetzel uint32_t rsvd:2; 4191338938Sjpaetzel uint32_t cqe_type:2; 4192338938Sjpaetzel uint32_t valid:1; 4193338938Sjpaetzel 4194338938Sjpaetzel /* dw 3 */ 4195338938Sjpaetzel uint32_t tcp_ack_num; 4196338938Sjpaetzel#endif 4197338938Sjpaetzel}; 4198