1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_TYPES_H 30171095Ssam#define XGE_HAL_TYPES_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xge-os-pal.h> 33171095Ssam 34171095Ssam__EXTERN_BEGIN_DECLS 35171095Ssam 36171095Ssam/* 37171095Ssam * BIT(loc) - set bit at offset 38171095Ssam */ 39173139Srwatson#define BIT(loc) (0x8000000000000000ULL >> (loc)) 40171095Ssam 41171095Ssam/* 42171095Ssam * vBIT(val, loc, sz) - set bits at offset 43171095Ssam */ 44173139Srwatson#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 45173139Srwatson#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 46171095Ssam 47171095Ssam/* 48171095Ssam * bVALx(bits, loc) - Get the value of x bits at location 49171095Ssam */ 50173139Srwatson#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) 51173139Srwatson#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) 52173139Srwatson#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) 53173139Srwatson#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) 54173139Srwatson#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) 55173139Srwatson#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) 56173139Srwatson#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) 57173139Srwatson#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) 58173139Srwatson#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) 59173139Srwatson#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) 60173139Srwatson#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) 61173139Srwatson#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) 62173139Srwatson#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) 63173139Srwatson#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) 64173139Srwatson#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) 65173139Srwatson#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) 66173139Srwatson#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) 67173139Srwatson#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) 68173139Srwatson#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) 69173139Srwatson#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) 70173139Srwatson#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) 71173139Srwatson#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) 72173139Srwatson#define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) 73171095Ssam 74173139Srwatson#define XGE_HAL_BASE_INF 100 75173139Srwatson#define XGE_HAL_BASE_ERR 200 76173139Srwatson#define XGE_HAL_BASE_BADCFG 300 77171095Ssam 78171095Ssam#define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 79171095Ssam 80171095Ssam/** 81171095Ssam * enum xge_hal_status_e - HAL return codes. 82171095Ssam * @XGE_HAL_OK: Success. 83171095Ssam * @XGE_HAL_FAIL: Failure. 84171095Ssam * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 85171095Ssam * (specific to polling mode completion processing). 86171095Ssam * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 87171095Ssam * descriptors. See xge_hal_fifo_dtr_next_completed(). 88171095Ssam * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 89171095Ssam * descriptors 90171095Ssam * are reserved (via xge_hal_fifo_dtr_reserve(), 91171095Ssam * xge_hal_fifo_dtr_reserve()) 92171095Ssam * and not yet freed (via xge_hal_fifo_dtr_free(), 93171095Ssam * xge_hal_ring_dtr_free()). 94171095Ssam * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 95171095Ssam * operation. 96171095Ssam * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 97171095Ssam * poll until PIO is executed. 98171095Ssam * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 99171095Ssam * HAL and/or device is not yet initialized. 100171095Ssam * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 101171095Ssam * reserve. Internal use only. 102171095Ssam * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 103171095Ssam * callback when instructed to exit descriptor processing loop 104171095Ssam * prematurely. Typical usage: polling mode of processing completed 105171095Ssam * descriptors. 106171095Ssam * Upon getting LRO_ISED, ll driver shall 107171095Ssam * 1) initialise lro struct with mbuf if sg_num == 1. 108171095Ssam * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 109171095Ssam * append the new mbuf to the tail of mbuf chain in lro struct. 110171095Ssam * 111171095Ssam * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 112171095Ssam * being initiated. 113171095Ssam * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 114171095Ssam * is appended at the end of existing LRO. 115171095Ssam * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 116171095Ssam * frame is not LRO capable. 117171095Ssam * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 118171095Ssam * triggers LRO flush. 119171095Ssam * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 120171095Ssam * frame triggers LRO flush. Lro frame should be flushed first then 121171095Ssam * new frame should be flushed next. 122171095Ssam * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new 123171095Ssam * frame triggers close of current LRO session and opening of new LRO session 124171095Ssam * with the frame. 125171095Ssam * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 126171095Ssam * more LRO sessions can be added. 127171095Ssam * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD 128171095Ssam * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 129171095Ssam * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 130171095Ssam * allocating descriptors). 131171095Ssam * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 132171095Ssam * error if corresponding channel is not configured. 133171095Ssam * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 134171095Ssam * invoked not because of the Xframe-generated interrupt. 135171095Ssam * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 136171095Ssam * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 137171095Ssam * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 138171095Ssam * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 139171095Ssam * in a scatter-gather list. 140171095Ssam * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 141171095Ssam * Typically means wrong sequence of API calls. 142171095Ssam * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 143171095Ssam * to set Xframe byte swapper in accordnace with the host 144171095Ssam * endian-ness. 145171095Ssam * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 146171095Ssam * a "quiescent" state. 147171095Ssam * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 148171095Ssam * caller is not in the (64, 9600) range. 149171095Ssam * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 150171095Ssam * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 151171095Ssam * check for zero/non-zero only.) 152171095Ssam * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 153171095Ssam * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 154171095Ssam * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 155171095Ssam * register value (with offset) outside of the BAR0 space. 156171095Ssam * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 157171095Ssam * (passed by ULD) is invalid. 158171095Ssam * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 159171095Ssam * management "get" routines when the retrieved information does 160171095Ssam * not fit into the provided buffer. 161171095Ssam * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 162171095Ssam * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 163171095Ssam * are not compatible. 164171095Ssam * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 165171095Ssam * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 166171095Ssam * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 167171095Ssam * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 168171095Ssam * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 169171095Ssam * SPDM table. 170171095Ssam * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 171171095Ssam * synch ith the actual one. 172171095Ssam * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 173171095Ssam * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 174171095Ssam * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 175171095Ssam * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 176171095Ssam * Also returned when PIO read does not go through ("all-foxes") 177171095Ssam * because of "slot-freeze". 178171095Ssam * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 179171095Ssam * Returned by xge_hal_device_reset(). One circumstance when it could 180171095Ssam * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 181171095Ssam * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 182171095Ssam * maximum number of sessions or queues allocated 183171095Ssam * @XGE_HAL_ERR_PKT_DROP: TBD 184171095Ssam * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 185171095Ssam * the structure xge_hal_tti_config_t{} for valid values. 186171095Ssam * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 187171095Ssam * range A. See the structure xge_hal_tti_config_t{} for valid values. 188171095Ssam * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 189171095Ssam * the structure xge_hal_tti_config_t{} for valid values. 190171095Ssam * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 191171095Ssam * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 192171095Ssam * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 193171095Ssam * the structure xge_hal_tti_config_t{} for valid values. 194171095Ssam * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 195171095Ssam * range C. See the structure xge_hal_tti_config_t{} for valid values. 196171095Ssam * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 197171095Ssam * range D. See the structure xge_hal_tti_config_t{} for valid values. 198171095Ssam * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 199171095Ssam * structure xge_hal_tti_config_t{} for valid values. 200171095Ssam * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 201171095Ssam * enable. See the structure xge_hal_tti_config_t{} for valid values. 202171095Ssam * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 203171095Ssam * the structure xge_hal_rti_config_t{} for valid values. 204171095Ssam * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 205171095Ssam * range A. See the structure xge_hal_rti_config_t{} for valid values. 206171095Ssam * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 207171095Ssam * the structure xge_hal_rti_config_t{} for valid values. 208171095Ssam * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 209171095Ssam * range B. See the structure xge_hal_rti_config_t{} for valid values. 210171095Ssam * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 211171095Ssam * the structure xge_hal_rti_config_t{} for valid values. 212171095Ssam * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 213171095Ssam * range C. See the structure xge_hal_rti_config_t{} for valid values. 214171095Ssam * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 215171095Ssam * range D. See the structure xge_hal_rti_config_t{} for valid values. 216171095Ssam * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 217171095Ssam * structure xge_hal_rti_config_t{} for valid values. 218171095Ssam * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 219171095Ssam * length. See the structure xge_hal_fifo_queue_t for valid values. 220171095Ssam * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 221171095Ssam * See the structure xge_hal_fifo_queue_t for valid values. 222171095Ssam * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 223171095Ssam * See the structure xge_hal_fifo_queue_t for valid values. 224171095Ssam * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 225171095Ssam * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 226171095Ssam * valid values. 227171095Ssam * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 228171095Ssam * blocks for the ring. See the structure xge_hal_ring_queue_t for 229171095Ssam * valid values. 230171095Ssam * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 231171095Ssam * the structure xge_hal_ring_queue_t for valid values. 232171095Ssam * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 233171095Ssam * structure xge_hal_ring_queue_t for valid values. 234171095Ssam * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 235171095Ssam * for the ring. See the structure xge_hal_ring_queue_t for valid values. 236171095Ssam * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 237171095Ssam * structure xge_hal_ring_queue_t for valid values. 238171095Ssam * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 239171095Ssam * structure xge_hal_ring_queue_t for valid values. 240171095Ssam * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 241171095Ssam * structure xge_hal_mac_config_t{} for valid values. 242171095Ssam * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 243171095Ssam * structure xge_hal_mac_config_t{} for valid values. 244171095Ssam * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 245171095Ssam * structure xge_hal_mac_config_t{} for valid values. 246171095Ssam * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 247171095Ssam * structure xge_hal_mac_config_t{} for valid values. 248171095Ssam * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 249171095Ssam * frame generation for queues 0 through 3. See the structure 250171095Ssam * xge_hal_mac_config_t{} for valid values. 251171095Ssam * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 252171095Ssam * frame generation for queues 4 through 7. See the structure 253171095Ssam * xge_hal_mac_config_t{} for valid values. 254171095Ssam * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 255171095Ssam * the structure xge_hal_fifo_config_t{} for valid values. 256171095Ssam * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 257171095Ssam * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 258171095Ssam * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 259171095Ssam * size. See the structure xge_hal_fifo_config_t{} for valid values. 260171095Ssam * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 261171095Ssam * size. See the structure xge_hal_ring_config_t{} for valid values. 262171095Ssam * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 263171095Ssam * structure xge_hal_device_config_t{} for valid values. 264171095Ssam * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 265171095Ssam * structure xge_hal_device_config_t{} for valid values. 266171095Ssam * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 267171095Ssam * structure xge_hal_device_config_t{} for valid values. 268171095Ssam * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 269171095Ssam * split transactions. See the structure xge_hal_device_config_t{} for valid 270171095Ssam * values. 271171095Ssam * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 272171095Ssam * xge_hal_device_config_t{} for valid values. 273171095Ssam * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 274171095Ssam * transactions that is shared by Tx and Rx requests. See the structure 275171095Ssam * xge_hal_device_config_t{} for valid values. 276171095Ssam * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 277171095Ssam * automatic statistics transfer to the host. See the structure 278171095Ssam * xge_hal_device_config_t{} for valid values. 279171095Ssam * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 280171095Ssam * structure xge_hal_device_config_t{} for valid values. 281171095Ssam * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 282171095Ssam * xge_hal_device_config_t{} for valid values. 283171095Ssam * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 284171095Ssam * xge_hal_device_config_t{} for valid values. 285171095Ssam * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 286171095Ssam * generate interrupt. See the structure xge_hal_device_config_t{} 287171095Ssam * for valid values. 288171095Ssam * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 289171095Ssam * shot. See the structure xge_hal_device_config_t{} for valid values. 290171095Ssam * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 291171095Ssam * size. See the structure xge_hal_driver_config_t{} for valid values. 292171095Ssam * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 293171095Ssam * the structure xge_hal_driver_config_t{} for valid values. 294171095Ssam * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 295171095Ssam * the structure xge_hal_ring_queue_t for valid values. 296171095Ssam * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 297171095Ssam * indicate_max_pkts variable. 298171095Ssam * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 299171095Ssam * auto-cancel. See xge_hal_tti_config_t{}. 300171095Ssam * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 301171095Ssam * auto-cancel. See xge_hal_rti_config_t{}. 302171095Ssam * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 303171095Ssam * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 304171095Ssam * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 305171095Ssam * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 306171095Ssam * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 307171095Ssam * (in memory) trace buffer either too large or too small. See the 308171095Ssam * the corresponding header file or README for the acceptable range. 309171095Ssam * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 310171095Ssam * counter cannot have the specified value. Note that the link-valid 311171095Ssam * counting is done only at device-open time, to determine with the 312171095Ssam * specified certainty that the link is up. See the 313171095Ssam * the corresponding header file or README for the acceptable range. 314171095Ssam * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 315171095Ssam * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 316171095Ssam * link-up retry count is out of the valid range. Note that the link-up 317171095Ssam * retry counting is done only at device-open time. 318171095Ssam * See also xge_hal_device_config_t{}. 319171095Ssam * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 320171095Ssam * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 321171095Ssam * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD 322171095Ssam * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD 323171095Ssam * @XGE_HAL_BADCFG_MEDIA: TBD 324171095Ssam * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD 325171095Ssam * See the structure xge_hal_device_config_t{} for valid values. 326171095Ssam * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 327171095Ssam * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 328171095Ssam * past the buffer limits. Used to enable user to load the trace in two 329171095Ssam * or more reads. 330171095Ssam * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 331171095Ssam * the structure xge_hal_ring_queue_t for valid values. 332171095Ssam * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size. 333171095Ssam * See the structure xge_hal_device_config_t for valid values. 334171095Ssam * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length. 335171095Ssam * See the structure xge_hal_device_config_t for valid values. 336171095Ssam * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD 337171095Ssam * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts 338171095Ssam * Enumerates status and error codes returned by HAL public 339171095Ssam * API functions. 340171095Ssam * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD 341171095Ssam * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD 342171095Ssam * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD 343171095Ssam * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD 344171095Ssam * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD 345171095Ssam * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD 346171095Ssam * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD 347171095Ssam * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD 348171095Ssam * 349171095Ssam */ 350171095Ssamtypedef enum xge_hal_status_e { 351173139Srwatson XGE_HAL_OK = 0, 352173139Srwatson XGE_HAL_FAIL = 1, 353173139Srwatson XGE_HAL_COMPLETIONS_REMAIN = 2, 354171095Ssam 355171095Ssam XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 356173139Srwatson XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 357173139Srwatson XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 358173139Srwatson XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 359173139Srwatson XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 360173139Srwatson XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 361173139Srwatson XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 362173139Srwatson XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 363173139Srwatson XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 364173139Srwatson XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 365173139Srwatson XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 366173139Srwatson XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 367173139Srwatson XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, 368173139Srwatson XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, 369173139Srwatson XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, 370173139Srwatson XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 371173139Srwatson XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 372173139Srwatson XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 373173139Srwatson XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 374173139Srwatson XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 375173139Srwatson XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 376173139Srwatson XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 377173139Srwatson XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 378173139Srwatson XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 379173139Srwatson XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 380173139Srwatson XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 381173139Srwatson XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 382173139Srwatson XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 383173139Srwatson XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 384173139Srwatson XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 385173139Srwatson XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 386173139Srwatson XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 387173139Srwatson XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 388173139Srwatson XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 389173139Srwatson XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 390173139Srwatson XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 391173139Srwatson XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 392173139Srwatson XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 393173139Srwatson XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 394171095Ssam XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 395173139Srwatson XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 396173139Srwatson XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 397173139Srwatson XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 398173139Srwatson XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, 399173139Srwatson XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, 400171095Ssam 401173139Srwatson XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 402173139Srwatson XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 403173139Srwatson XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 404173139Srwatson XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 405173139Srwatson XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 406173139Srwatson XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 407173139Srwatson XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 408173139Srwatson XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 409173139Srwatson XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 410173139Srwatson XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 411173139Srwatson XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 412173139Srwatson XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 413173139Srwatson XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 414173139Srwatson XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 415173139Srwatson XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 416173139Srwatson XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 417173139Srwatson XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 418173139Srwatson XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 419171095Ssam XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 420173139Srwatson XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 421173139Srwatson XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 422173139Srwatson XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 423173139Srwatson XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 424173139Srwatson XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 425173139Srwatson XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 426173139Srwatson XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 427173139Srwatson XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 428173139Srwatson XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 429173139Srwatson XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 430173139Srwatson XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 431173139Srwatson XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 432173139Srwatson XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 433173139Srwatson XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 434173139Srwatson XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 435173139Srwatson XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 436173139Srwatson XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 437173139Srwatson XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 438173139Srwatson XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 439173139Srwatson XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 440173139Srwatson XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 441173139Srwatson XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 442173139Srwatson XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 443173139Srwatson XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 444173139Srwatson XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 445173139Srwatson XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 446173139Srwatson XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 447173139Srwatson XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 448173139Srwatson XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 449173139Srwatson XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 450173139Srwatson XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 451173139Srwatson XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 452173139Srwatson XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 453173139Srwatson XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 454173139Srwatson XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 455173139Srwatson XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 456173139Srwatson XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 457173139Srwatson XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 458173139Srwatson XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 459173139Srwatson XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 460173139Srwatson XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 461173139Srwatson XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 462173139Srwatson XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 463173139Srwatson XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 464171095Ssam XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 465173139Srwatson XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 466173139Srwatson XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 467173139Srwatson XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 468173139Srwatson XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 469173139Srwatson XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 470173139Srwatson XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, 471173139Srwatson XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, 472173139Srwatson XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, 473173139Srwatson XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, 474173139Srwatson XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, 475173139Srwatson XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, 476173139Srwatson XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, 477173139Srwatson XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, 478173139Srwatson XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, 479173139Srwatson XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, 480173139Srwatson XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, 481173139Srwatson XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, 482173139Srwatson XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, 483173139Srwatson XGE_HAL_EOF_TRACE_BUF = -1 484171095Ssam} xge_hal_status_e; 485171095Ssam 486173139Srwatson#define XGE_HAL_ETH_ALEN 6 487171095Ssamtypedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 488171095Ssam 489173139Srwatson#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 490171095Ssam 491171095Ssam/* frames sizes */ 492173139Srwatson#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 493173139Srwatson#define XGE_HAL_HEADER_802_2_SIZE 3 494173139Srwatson#define XGE_HAL_HEADER_SNAP_SIZE 5 495173139Srwatson#define XGE_HAL_HEADER_VLAN_SIZE 4 496171095Ssam#define XGE_HAL_MAC_HEADER_MAX_SIZE \ 497173139Srwatson (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 498173139Srwatson XGE_HAL_HEADER_802_2_SIZE + \ 499173139Srwatson XGE_HAL_HEADER_SNAP_SIZE) 500171095Ssam 501173139Srwatson#define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 502171095Ssam 503171095Ssam/* 32bit alignments */ 504173139Srwatson#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 505173139Srwatson#define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 506173139Srwatson#define XGE_HAL_HEADER_802_2_ALIGN 3 507173139Srwatson#define XGE_HAL_HEADER_SNAP_ALIGN 1 508171095Ssam 509173139Srwatson#define XGE_HAL_L3_CKSUM_OK 0xFFFF 510173139Srwatson#define XGE_HAL_L4_CKSUM_OK 0xFFFF 511173139Srwatson#define XGE_HAL_MIN_MTU 46 512173139Srwatson#define XGE_HAL_MAX_MTU 9600 513173139Srwatson#define XGE_HAL_DEFAULT_MTU 1500 514171095Ssam 515173139Srwatson#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 516171095Ssam 517173139Srwatson#define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 518173139Srwatson#define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 519171095Ssam 520173139Srwatson#define XGE_HAL_MAX_MSIX_MESSAGES 64 521171095Ssam#define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2 522171095Ssam/* Highest level interrupt blocks */ 523171095Ssam#define XGE_HAL_TX_PIC_INTR (0x0001<<0) 524171095Ssam#define XGE_HAL_TX_DMA_INTR (0x0001<<1) 525171095Ssam#define XGE_HAL_TX_MAC_INTR (0x0001<<2) 526171095Ssam#define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 527171095Ssam#define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 528171095Ssam#define XGE_HAL_RX_PIC_INTR (0x0001<<5) 529171095Ssam#define XGE_HAL_RX_DMA_INTR (0x0001<<6) 530171095Ssam#define XGE_HAL_RX_MAC_INTR (0x0001<<7) 531171095Ssam#define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 532171095Ssam#define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 533171095Ssam#define XGE_HAL_MC_INTR (0x0001<<10) 534171095Ssam#define XGE_HAL_SCHED_INTR (0x0001<<11) 535171095Ssam#define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 536173139Srwatson XGE_HAL_TX_DMA_INTR | \ 537173139Srwatson XGE_HAL_TX_MAC_INTR | \ 538173139Srwatson XGE_HAL_TX_XGXS_INTR | \ 539173139Srwatson XGE_HAL_TX_TRAFFIC_INTR | \ 540173139Srwatson XGE_HAL_RX_PIC_INTR | \ 541173139Srwatson XGE_HAL_RX_DMA_INTR | \ 542173139Srwatson XGE_HAL_RX_MAC_INTR | \ 543173139Srwatson XGE_HAL_RX_XGXS_INTR | \ 544173139Srwatson XGE_HAL_RX_TRAFFIC_INTR | \ 545173139Srwatson XGE_HAL_MC_INTR | \ 546173139Srwatson XGE_HAL_SCHED_INTR) 547171095Ssam#define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 548171095Ssam 549171095Ssam/* Interrupt masks for the general interrupt mask register */ 550171095Ssam#define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 551171095Ssam 552171095Ssam#define XGE_HAL_TXPIC_INT_M BIT(0) 553171095Ssam#define XGE_HAL_TXDMA_INT_M BIT(1) 554171095Ssam#define XGE_HAL_TXMAC_INT_M BIT(2) 555171095Ssam#define XGE_HAL_TXXGXS_INT_M BIT(3) 556171095Ssam#define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 557171095Ssam#define XGE_HAL_PIC_RX_INT_M BIT(32) 558171095Ssam#define XGE_HAL_RXDMA_INT_M BIT(33) 559171095Ssam#define XGE_HAL_RXMAC_INT_M BIT(34) 560171095Ssam#define XGE_HAL_MC_INT_M BIT(35) 561171095Ssam#define XGE_HAL_RXXGXS_INT_M BIT(36) 562171095Ssam#define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 563171095Ssam 564171095Ssam/* MSI level Interrupts */ 565173139Srwatson#define XGE_HAL_MAX_MSIX_VECTORS (16) 566171095Ssam 567171095Ssamtypedef struct xge_hal_ipv4 { 568171095Ssam u32 addr; 569171095Ssam}xge_hal_ipv4; 570171095Ssam 571171095Ssamtypedef struct xge_hal_ipv6 { 572171095Ssam u64 addr[2]; 573171095Ssam}xge_hal_ipv6; 574171095Ssam 575171095Ssamtypedef union xge_hal_ipaddr_t { 576171095Ssam xge_hal_ipv4 ipv4; 577171095Ssam xge_hal_ipv6 ipv6; 578171095Ssam}xge_hal_ipaddr_t; 579171095Ssam 580171095Ssam/* DMA level Interrupts */ 581173139Srwatson#define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 582171095Ssam 583171095Ssam/* PFC block interrupts */ 584173139Srwatson#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 585171095Ssamfull */ 586171095Ssam 587171095Ssam/* basic handles */ 588171095Ssamtypedef void* xge_hal_device_h; 589171095Ssamtypedef void* xge_hal_dtr_h; 590171095Ssamtypedef void* xge_hal_channel_h; 591173139Srwatson 592171095Ssam/* 593171095Ssam * I2C device id. Used in I2C control register for accessing EEPROM device 594171095Ssam * memory. 595171095Ssam */ 596173139Srwatson#define XGE_DEV_ID 5 597171095Ssam 598171095Ssamtypedef enum xge_hal_xpak_alarm_type_e { 599171095Ssam XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 600171095Ssam XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 601171095Ssam XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 602171095Ssam} xge_hal_xpak_alarm_type_e; 603171095Ssam 604171095Ssam 605171095Ssam__EXTERN_END_DECLS 606171095Ssam 607171095Ssam#endif /* XGE_HAL_TYPES_H */ 608