xgehal-mgmt.h revision 171095 
1/*-
2 * Copyright (c) 2002-2007 Neterion, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/nxge/include/xgehal-mgmt.h 171095 2007-06-29 22:47:18Z sam $
27 */
28
29/*
30 *  FileName :    xgehal-mgmt.h
31 *
32 *  Description:  management API
33 *
34 *  Created:      1 September 2004
35 */
36
37#ifndef XGE_HAL_MGMT_H
38#define XGE_HAL_MGMT_H
39
40#include <dev/nxge/include/xge-os-pal.h>
41#include <dev/nxge/include/xge-debug.h>
42#include <dev/nxge/include/xgehal-types.h>
43#include <dev/nxge/include/xgehal-config.h>
44#include <dev/nxge/include/xgehal-stats.h>
45#include <dev/nxge/include/xgehal-regs.h>
46#include <dev/nxge/include/xgehal-device.h>
47
48__EXTERN_BEGIN_DECLS
49
50/**
51 * struct xge_hal_mgmt_about_info_t - About info.
52 * @vendor: PCI Vendor ID.
53 * @device: PCI Device ID.
54 * @subsys_vendor: PCI Subsystem Vendor ID.
55 * @subsys_device: PCI Subsystem Device ID.
56 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
57 * @vendor_name: Neterion, Inc.
58 * @chip_name: Xframe.
59 * @media: Fiber, copper.
60 * @hal_major: HAL major version number.
61 * @hal_minor: HAL minor version number.
62 * @hal_fix: HAL fix number.
63 * @hal_build: HAL build number.
64 * @ll_major: Link-layer ULD major version number.
65 * @ll_minor: Link-layer ULD minor version number.
66 * @ll_fix: Link-layer ULD fix version number.
67 * @ll_build: Link-layer ULD build number.
68 * @transponder_temperature: TODO
69 */
70typedef struct xge_hal_mgmt_about_info_t {
71	u16		vendor;
72	u16		device;
73	u16		subsys_vendor;
74	u16		subsys_device;
75	u8		board_rev;
76	char		vendor_name[16];
77	char		chip_name[16];
78	char		media[16];
79	char		hal_major[4];
80	char		hal_minor[4];
81	char		hal_fix[4];
82	char		hal_build[16];
83	char		ll_major[4];
84	char		ll_minor[4];
85	char		ll_fix[4];
86	char		ll_build[16];
87	u32		transponder_temperature;
88} xge_hal_mgmt_about_info_t;
89
90typedef xge_hal_stats_hw_info_t		xge_hal_mgmt_hw_stats_t;
91typedef xge_hal_stats_pcim_info_t	xge_hal_mgmt_pcim_stats_t;
92typedef xge_hal_stats_sw_err_t		xge_hal_mgmt_sw_stats_t;
93typedef xge_hal_stats_device_info_t	xge_hal_mgmt_device_stats_t;
94typedef xge_hal_stats_channel_info_t	xge_hal_mgmt_channel_stats_t;
95typedef xge_hal_device_config_t		xge_hal_mgmt_device_config_t;
96typedef xge_hal_driver_config_t		xge_hal_mgmt_driver_config_t;
97typedef xge_hal_pci_config_t		xge_hal_mgmt_pci_config_t;
98
99xge_hal_status_e
100xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info,
101		int size);
102
103xge_hal_status_e
104xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats,
105		int size);
106
107xge_hal_status_e
108xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out);
109
110xge_hal_status_e
111xge_hal_mgmt_pcim_stats(xge_hal_device_h devh,
112		xge_hal_mgmt_pcim_stats_t *pcim_stats, int size);
113
114xge_hal_status_e
115xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size,
116		char *out);
117
118xge_hal_status_e
119xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats,
120		int size);
121
122xge_hal_status_e
123xge_hal_mgmt_device_stats(xge_hal_device_h devh,
124		xge_hal_mgmt_device_stats_t *device_stats, int size);
125
126xge_hal_status_e
127xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh,
128		xge_hal_mgmt_channel_stats_t *channel_stats, int size);
129
130xge_hal_status_e
131xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset,
132		u64 *value);
133
134xge_hal_status_e
135xge_hal_mgmt_reg_write(xge_hal_device_h	devh, int bar_id, unsigned int offset,
136		u64 value);
137
138xge_hal_status_e
139xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset,
140		int bits, u32 *value);
141
142xge_hal_status_e
143xge_hal_mgmt_device_config(xge_hal_device_h devh,
144		xge_hal_mgmt_device_config_t *dev_config, int size);
145
146xge_hal_status_e
147xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config,
148		int size);
149
150xge_hal_status_e
151xge_hal_mgmt_pci_config(xge_hal_device_h devh,
152		xge_hal_mgmt_pci_config_t *pci_config, int size);
153
154xge_hal_status_e
155xge_hal_pma_loopback( xge_hal_device_h devh, int enable );
156
157xge_hal_status_e
158xge_hal_rldram_test(xge_hal_device_h devh, u64 * data);
159
160u16
161xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr );
162
163xge_hal_status_e
164xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value );
165
166u32
167xge_hal_read_xfp_current_temp(xge_hal_device_h devh);
168
169xge_hal_status_e
170xge_hal_read_eeprom(xge_hal_device_h devh, int off, u32* data);
171
172xge_hal_status_e
173xge_hal_write_eeprom(xge_hal_device_h devh, int off, u32 data, int cnt);
174
175xge_hal_status_e
176xge_hal_register_test(xge_hal_device_h devh, u64 *data);
177
178xge_hal_status_e
179xge_hal_eeprom_test(xge_hal_device_h devh, u64 *data);
180
181xge_hal_status_e
182xge_hal_bist_test(xge_hal_device_h devh, u64 *data);
183
184xge_hal_status_e
185xge_hal_link_test(xge_hal_device_h devh, u64 *data);
186
187int
188xge_hal_setpause_data(xge_hal_device_h devh, int tx, int rx);
189
190void
191xge_hal_getpause_data(xge_hal_device_h devh, int *tx, int *rx);
192
193void
194__hal_updt_stats_xpak(xge_hal_device_t *hldev);
195
196void
197__hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value);
198
199#ifdef XGE_TRACE_INTO_CIRCULAR_ARR
200xge_hal_status_e
201xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset,
202		unsigned *read_length);
203#endif
204
205void
206xge_hal_restore_link_led(xge_hal_device_h devh);
207
208
209void
210xge_hal_flick_link_led(xge_hal_device_h devh);
211
212/*
213 * Some set of Xena3 Cards were known to have some link LED
214 * Problems. This macro identifies if the card is among them
215 * given its Sub system ID.
216 */
217#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
218		((((subid >= 0x600B) && (subid <= 0x600D)) || \
219		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0)
220#define CHECKBIT(value, nbit) (value & (1 << nbit))
221
222#ifdef XGE_HAL_USE_MGMT_AUX
223#include <dev/nxge/include/xgehal-mgmtaux.h>
224#endif
225
226__EXTERN_END_DECLS
227
228#endif /* XGE_HAL_MGMT_H */
229