xgehal-config.h revision 171095
1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nxge/include/xgehal-config.h 171095 2007-06-29 22:47:18Z sam $ 27 */ 28 29/* 30 * FileName : xgehal-config.h 31 * 32 * Description: Xframe configuration. 33 * 34 * Created: 14 May 2004 35 */ 36 37#ifndef XGE_HAL_CONFIG_H 38#define XGE_HAL_CONFIG_H 39 40#include <dev/nxge/include/xge-os-pal.h> 41#include <dev/nxge/include/xgehal-types.h> 42#include <dev/nxge/include/xge-queue.h> 43 44__EXTERN_BEGIN_DECLS 45 46#define XGE_HAL_DEFAULT_USE_HARDCODE -1 47 48#ifdef XGEHAL_RNIC 49#define XGE_HAL_MAX_VIRTUAL_PATHS 17 50#else 51#define XGE_HAL_MAX_VIRTUAL_PATHS 8 52#endif 53#define XGE_HAL_MAX_INTR_PER_VP 4 54 55 56/** 57 * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 58 * @enabled: Set to 1, if TTI feature is enabled. 59 * @urange_a: Link utilization range A. The value from 0 to 100%. 60 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 61 * each time when (and only when) the line is utilized no more 62 * than @urange_a percent in the transmit direction, 63 * and number of transmitted frames is greater or equal @ufc_a. 64 * @urange_b: Link utilization range B. 65 * @ufc_b: Frame count for the utilization range B. 66 * @urange_c: Link utilization range C. 67 * @ufc_c: Frame count for the utilization range C. 68 * @urange_d: Link utilization range D. 69 * @ufc_d: Frame count for the utilization range D. 70 * @timer_val_us: Interval of time, in microseconds, at which transmit timer 71 * interrupt is to be generated. Note that unless @timer_ci_en 72 * is set, the timer interrupt is generated only in presence 73 * of the transmit traffic. Note also that timer interrupt 74 * and utilization interrupt are two separate interrupt 75 * sources. 76 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 77 * interrupt was generated during the interval. 78 * @timer_ci_en: Enable/disable continuous interrupt. Set this value 79 * to 1 in order to generate continuous interrupt 80 * at fixed @timer_val intervals of time, independently 81 * of whether there is transmit traffic or not. 82 * @enabled: Set to 1, if TTI feature is enabled. 83 * 84 * Xframe transmit interrupt configuration. 85 * See Xframe User Guide, Section 3.5 "Device Interrupts" 86 * for more details. Note also (min, max) 87 * ranges in the body of the xge_hal_tx_intr_config_t structure. 88 * Note: Valid (min, max) range for each attribute is specified in the body of 89 * the xge_hal_tti_config_t{} structure. Please refer to the 90 * corresponding header file. 91 */ 92typedef struct xge_hal_tti_config_t { 93 94 int enabled; 95#define XGE_HAL_TTI_ENABLE 1 96#define XGE_HAL_TTI_DISABLE 0 97 98 /* Line utilization interrupts */ 99 100 int urange_a; 101#define XGE_HAL_MIN_TX_URANGE_A 0 102#define XGE_HAL_MAX_TX_URANGE_A 100 103 104 int ufc_a; 105#define XGE_HAL_MIN_TX_UFC_A 0 106#define XGE_HAL_MAX_TX_UFC_A 65535 107 108 int urange_b; 109#define XGE_HAL_MIN_TX_URANGE_B 0 110#define XGE_HAL_MAX_TX_URANGE_B 100 111 112 int ufc_b; 113#define XGE_HAL_MIN_TX_UFC_B 0 114#define XGE_HAL_MAX_TX_UFC_B 65535 115 116 int urange_c; 117#define XGE_HAL_MIN_TX_URANGE_C 0 118#define XGE_HAL_MAX_TX_URANGE_C 100 119 120 int ufc_c; 121#define XGE_HAL_MIN_TX_UFC_C 0 122#define XGE_HAL_MAX_TX_UFC_C 65535 123 124 int ufc_d; 125#define XGE_HAL_MIN_TX_UFC_D 0 126#define XGE_HAL_MAX_TX_UFC_D 65535 127 128 int timer_val_us; 129#define XGE_HAL_MIN_TX_TIMER_VAL 0 130#define XGE_HAL_MAX_TX_TIMER_VAL 65535 131 132 int timer_ac_en; 133#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 134#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 135 136 int timer_ci_en; 137#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 138#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 139 140 141} xge_hal_tti_config_t; 142 143/** 144 * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 145 * @urange_a: Link utilization range A. The value from 0 to 100%. 146 * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 147 * each time when (and only when) the line is utilized no more 148 * than @urange_a percent inbound, 149 * and number of received frames is greater or equal @ufc_a. 150 * @urange_b: Link utilization range B. 151 * @ufc_b: Frame count for the utilization range B. 152 * @urange_c: Link utilization range C. 153 * @ufc_c: Frame count for the utilization range C. 154 * @urange_d: Link utilization range D. 155 * @ufc_d: Frame count for the utilization range D. 156 * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 157 * interrupt was generated during the interval. 158 * @timer_val_us: Interval of time, in microseconds, at which receive timer 159 * interrupt is to be generated. The timer interrupt is generated 160 * only in presence of the inbound traffic. Note also that timer 161 * interrupt and utilization interrupt are two separate interrupt 162 * sources. 163 * 164 * Xframe receive interrupt configuration. 165 * See Xframe User Guide, Section 3.5 "Device Interrupts" 166 * for more details. Note also (min, max) 167 * ranges in the body of the xge_hal_intr_config_t structure. 168 * Note: Valid (min, max) range for each attribute is specified in the body of 169 * the xge_hal_rti_config_t{} structure. Please refer to the 170 * corresponding header file. 171 */ 172typedef struct xge_hal_rti_config_t { 173 174 int urange_a; 175#define XGE_HAL_MIN_RX_URANGE_A 0 176#define XGE_HAL_MAX_RX_URANGE_A 127 177 178 int ufc_a; 179#define XGE_HAL_MIN_RX_UFC_A 0 180#define XGE_HAL_MAX_RX_UFC_A 65535 181 182 int urange_b; 183#define XGE_HAL_MIN_RX_URANGE_B 0 184#define XGE_HAL_MAX_RX_URANGE_B 127 185 186 int ufc_b; 187#define XGE_HAL_MIN_RX_UFC_B 0 188#define XGE_HAL_MAX_RX_UFC_B 65535 189 190 int urange_c; 191#define XGE_HAL_MIN_RX_URANGE_C 0 192#define XGE_HAL_MAX_RX_URANGE_C 127 193 194 int ufc_c; 195#define XGE_HAL_MIN_RX_UFC_C 0 196#define XGE_HAL_MAX_RX_UFC_C 65535 197 198 int ufc_d; 199#define XGE_HAL_MIN_RX_UFC_D 0 200#define XGE_HAL_MAX_RX_UFC_D 65535 201 202 int timer_ac_en; 203#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 204#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 205 206 int timer_val_us; 207#define XGE_HAL_MIN_RX_TIMER_VAL 0 208#define XGE_HAL_MAX_RX_TIMER_VAL 65535 209 210} xge_hal_rti_config_t; 211 212/** 213 * struct xge_hal_fifo_queue_t - Single fifo configuration. 214 * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 215 * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 216 * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 217 * Use 0 otherwise. 218 * @intr_vector: TBD 219 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 220 * which generally improves latency of the host bridge operation 221 * (see PCI specification). For valid values please refer 222 * to xge_hal_fifo_queue_t{} in the driver sources. 223 * @priority: TBD 224 * @configured: Boolean. Use 1 to specify that the fifo is configured. 225 * Only "configured" fifos can be activated and used to post 226 * Tx descriptors. Any subset of 8 available fifos can be 227 * "configured". 228 * @tti: TBD 229 * 230 * Single fifo configuration. 231 * Note: Valid (min, max) range for each attribute is specified in the body of 232 * the xge_hal_fifo_queue_t{} structure. Please refer to the 233 * corresponding header file. 234 * See also: xge_hal_fifo_config_t{} 235 */ 236typedef struct xge_hal_fifo_queue_t { 237 int max; 238 int initial; 239#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 240#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 241 242 int intr; 243#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 244#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 245 246 int intr_vector; 247#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 248#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 249 250 int no_snoop_bits; 251#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 252#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 253#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 254#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 255 256 int priority; 257#define XGE_HAL_MIN_FIFO_PRIORITY 0 258#define XGE_HAL_MAX_FIFO_PRIORITY 63 259 260 int configured; 261#define XGE_HAL_MIN_FIFO_CONFIGURED 0 262#define XGE_HAL_MAX_FIFO_CONFIGURED 1 263 264#define XGE_HAL_MAX_FIFO_TTI_NUM 7 265#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 266 xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 267 268} xge_hal_fifo_queue_t; 269 270/** 271 * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 272 * @max_frags: Max number of Tx buffers per TxDL (that is, per single 273 * transmit operation). 274 * No more than 256 transmit buffers can be specified. 275 * @max_aligned_frags: Number of fragments to be aligned out of 276 * maximum fragments (see @max_frags). 277 * @reserve_threshold: Descriptor reservation threshold. 278 * At least @reserve_threshold descriptors will remain 279 * unallocated at all times. 280 * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 281 * bytes. Setting @memblock_size to page size ensures 282 * by-page allocation of descriptors. 128K bytes is the 283 * maximum supported block size. 284 * @queue: Array of per-fifo configurations. 285 * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 286 * (e.g., to align on a cache line). 287 * 288 * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 289 * structures. 290 * Note: Valid (min, max) range for each attribute is specified in the body of 291 * the xge_hal_fifo_config_t{} structure. Please refer to the 292 * corresponding header file. 293 * See also: xge_hal_ring_queue_t{}. 294 */ 295typedef struct xge_hal_fifo_config_t { 296 int max_frags; 297#define XGE_HAL_MIN_FIFO_FRAGS 1 298#define XGE_HAL_MAX_FIFO_FRAGS 256 299 300 int reserve_threshold; 301#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 302#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 303 304 int memblock_size; 305#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 306#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 307 308 int alignment_size; 309#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 310#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 311 312 int max_aligned_frags; 313 /* range: (1, @max_frags) */ 314 315#define XGE_HAL_MIN_FIFO_NUM 1 316#define XGE_HAL_MAX_FIFO_NUM_HERC 8 317#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 318#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 319 xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 320} xge_hal_fifo_config_t; 321 322/** 323 * struct xge_hal_rts_port_t - RTS port entry 324 * @num: Port number 325 * @udp: Port is UDP (default TCP) 326 * @src: Port is Source (default Destination) 327 */ 328typedef struct xge_hal_rts_port_t { 329 int num; 330 int udp; 331 int src; 332} xge_hal_rts_port_t; 333 334/** 335 * struct xge_hal_ring_queue_t - Single ring configuration. 336 * @max: Max numbers of RxD blocks per queue 337 * @initial: Initial numbers of RxD blocks per queue 338 * (can grow up to @max) 339 * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 340 * to Xframe User Guide. 341 * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 342 * Note that 64MB of available 343 * on-board DRAM is shared between receive rings. 344 * If a single ring is used, @dram_size_mb can be set to 64. 345 * Sum of all rings' @dram_size_mb cannot exceed 64. 346 * @intr_vector: TBD 347 * @backoff_interval_us: Time (in microseconds), after which Xframe 348 * tries to download RxDs posted by the host. 349 * Note that the "backoff" does not happen if host posts receive 350 * descriptors in the timely fashion. 351 * @max_frm_len: Maximum frame length that can be received on _that_ ring. 352 * Setting this field to -1 ensures that the ring will 353 * "accept" MTU-size frames (note that MTU can be changed at 354 * runtime). 355 * Any value other than (-1) specifies a certain "hard" 356 * limit on the receive frame sizes. 357 * The field can be used to activate receive frame-length based 358 * steering. 359 * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 360 * to give prioritized access to PCI-X. See Xframe documentation 361 * for details. 362 * @rth_en: Enable Receive Traffic Hashing (RTH). 363 * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 364 * which generally improves latency of the host bridge operation 365 * (see PCI specification). For valid values please refer 366 * to xge_hal_ring_queue_t{} in the driver sources. 367 * @indicate_max_pkts: Sets maximum number of received frames to be processed 368 * within single interrupt. 369 * @configured: Boolean. Use 1 to specify that the ring is configured. 370 * Only "configured" rings can be activated and used to post 371 * Rx descriptors. Any subset of 8 available rings can be 372 * "configured". 373 * @rts_mac_en: 1 - To enable Receive MAC address steering. 374 * 0 - To disable Receive MAC address steering. 375 * @rth_en: TBD 376 * @rts_port_en: TBD 377 * @rts_ports: TBD 378 * @rti: Xframe receive interrupt configuration. 379 * 380 * Single ring configuration. 381 * Note: Valid (min, max) range for each attribute is specified in the body of 382 * the xge_hal_ring_queue_t{} structure. Please refer to the 383 * corresponding header file. 384 * See also: xge_hal_fifo_config_t{}. 385 */ 386typedef struct xge_hal_ring_queue_t { 387 int max; 388 int initial; 389#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 390#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 391 392 int buffer_mode; 393#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 394#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 395#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 396#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 397 398 int dram_size_mb; 399#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 400#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 401#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 402 403 int intr_vector; 404#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 405#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 406 407 int backoff_interval_us; 408#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 409#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 410 411 int max_frm_len; 412#define XGE_HAL_MIN_MAX_FRM_LEN -1 413#define XGE_HAL_MAX_MAX_FRM_LEN 9622 414 415 int priority; 416#define XGE_HAL_MIN_RING_PRIORITY 0 417#define XGE_HAL_MAX_RING_PRIORITY 7 418 419 int no_snoop_bits; 420#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 421#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 422#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 423#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 424 425 int indicate_max_pkts; 426#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 427#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 428 429 int configured; 430#define XGE_HAL_MIN_RING_CONFIGURED 0 431#define XGE_HAL_MAX_RING_CONFIGURED 1 432 433 int rts_mac_en; 434#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 435#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 436 437 int rth_en; 438#define XGE_HAL_MIN_RING_RTH_EN 0 439#define XGE_HAL_MAX_RING_RTH_EN 1 440 441 int rts_port_en; 442#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 443#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 444 445#define XGE_HAL_MAX_STEERABLE_PORTS 32 446 xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 447 448 xge_hal_rti_config_t rti; 449 450} xge_hal_ring_queue_t; 451 452/** 453 * struct xge_hal_ring_config_t - Array of ring configurations. 454 * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 455 * bytes. Setting @memblock_size to page size ensures 456 * by-page allocation of descriptors. 128K bytes is the 457 * upper limit. 458 * @scatter_mode: Xframe supports two receive scatter modes: A and B. 459 * For details please refer to Xframe User Guide. 460 * @strip_vlan_tag: TBD 461 * @queue: Array of all Xframe ring configurations. 462 * 463 * Array of ring configurations. 464 * See also: xge_hal_ring_queue_t{}. 465 */ 466typedef struct xge_hal_ring_config_t { 467 468 int memblock_size; 469#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 470#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 471 472 int scatter_mode; 473#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 474#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 475 476 int strip_vlan_tag; 477#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 478#define XGE_HAL_RING_STRIP_VLAN_TAG 1 479 480#define XGE_HAL_MIN_RING_NUM 1 481#define XGE_HAL_MAX_RING_NUM_HERC 8 482#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 483#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 484 xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 485 486} xge_hal_ring_config_t; 487 488/** 489 * struct xge_hal_mac_config_t - MAC configuration. 490 * @media: Transponder type. 491 * @tmac_util_period: The sampling period over which the transmit utilization 492 * is calculated. 493 * @rmac_util_period: The sampling period over which the receive utilization 494 * is calculated. 495 * @rmac_strip_pad: Determines whether padding of received frames is removed by 496 * the MAC or sent to the host. 497 * @rmac_bcast_en: Enable frames containing broadcast address to be 498 * passed to the host. 499 * @rmac_pause_gen_en: Received pause generation enable. 500 * @rmac_pause_rcv_en: Receive pause enable. 501 * @rmac_pause_time: The value to be inserted in outgoing pause frames. 502 * Has units of pause quanta (one pause quanta = 512 bit times). 503 * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 504 * for queues 0 through 3. The threshold value indicates portion of the 505 * individual receive buffer queue size. Thresholds have a range of 0 to 506 * 255, allowing 256 possible watermarks in a queue. 507 * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 508 * for queues 4 through 7. The threshold value indicates portion of the 509 * individual receive buffer queue size. Thresholds have a range of 0 to 510 * 255, allowing 256 possible watermarks in a queue. 511 * 512 * MAC configuration. This includes various aspects of configuration, including: 513 * - Pause frame threshold; 514 * - sampling rate to calculate link utilization; 515 * - enabling/disabling broadcasts. 516 * 517 * See Xframe User Guide for more details. 518 * Note: Valid (min, max) range for each attribute is specified in the body of 519 * the xge_hal_mac_config_t{} structure. Please refer to the 520 * corresponding include file. 521 */ 522typedef struct xge_hal_mac_config_t { 523 int media; 524#define XGE_HAL_MIN_MEDIA 0 525#define XGE_HAL_MEDIA_SR 0 526#define XGE_HAL_MEDIA_SW 1 527#define XGE_HAL_MEDIA_LR 2 528#define XGE_HAL_MEDIA_LW 3 529#define XGE_HAL_MEDIA_ER 4 530#define XGE_HAL_MEDIA_EW 5 531#define XGE_HAL_MAX_MEDIA 5 532 533 int tmac_util_period; 534#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 535#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 536 537 int rmac_util_period; 538#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 539#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 540 541 int rmac_bcast_en; 542#define XGE_HAL_MIN_RMAC_BCAST_EN 0 543#define XGE_HAL_MAX_RMAC_BCAST_EN 1 544 545 int rmac_pause_gen_en; 546#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 547#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 548 549 int rmac_pause_rcv_en; 550#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 551#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 552 553 int rmac_pause_time; 554#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 555#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 556 557 int mc_pause_threshold_q0q3; 558#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 559#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 560 561 int mc_pause_threshold_q4q7; 562#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 563#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 564 565} xge_hal_mac_config_t; 566 567#ifdef XGEHAL_RNIC 568 569/* 570 * struct xge_hal_vp_config_t - Configuration of virtual path 571 * @vp_id: Virtual Path Id 572 * @vp_valid: Flag specifies if the configuration is valid 573 * @bitmap_intr_num: Interrupt Number associated with the bitmap 574 * @nce_oid_start: The start of the NCE ID range 575 * @nce_oid_end: The end of the NCE ID range 576 * @session_oid_start: The start of the Session ID range 577 * @session_oid_end: The end of the Session ID range 578 * @srq_oid_start: The start of the HSRQ ID range 579 * @srq_oid_end: The end of the SRQ ID range 580 * @cqrq_oid_start: The start of the CQRQ range 581 * @cqrq_oid_end: The end of the CQRQ range 582 * @umq_length: Length of up message queue 583 * @umq_int_ctrl: Interrupt control for up Message queue 584 * @umq_gen_compl: Generate completion for up message queue 585 * @dmq_length: Length of down message queue 586 * @dmq_int_ctrl: Interrupt control for down Message queue 587 * @dmq_gen_compl: Generate completion for up message queue 588 * 589 * This structure is used by the driver to pass the configuration parameters to 590 * configure Virtual Path. 591 */ 592typedef struct xge_hal_vp_config_t{ 593 u32 vp_id; 594 u32 vp_valid; 595#define XGE_HAL_VP_CONFIG_INVALID 0 596#define XGE_HAL_VP_CONFIG_VALID 1 597 598 int bitmap_intr_num; 599#define XGE_HAL_BITMAP_INTR_NUM_MIN 0 600#define XGE_HAL_BITMAP_INTR_NUM_MAX 3 601 602 u32 nce_oid_start; 603 u32 nce_oid_end; 604 u32 session_oid_start; 605 u32 session_oid_end; 606 u32 srq_oid_start; 607 u32 srq_oid_end; 608 u32 cqrq_oid_start; 609 u32 cqrq_oid_end; 610 u32 umq_length; 611 u32 umq_int_ctrl; 612 u32 umq_gen_compl; 613 u32 dmq_length; 614 u32 dmq_int_ctrl; 615 u32 dmq_gen_compl; 616}xge_hal_vp_config_t; 617 618#endif 619 620/** 621 * struct xge_hal_device_config_t - Device configuration. 622 * @mtu: Current mtu size. 623 * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 624 * completions. Used in xge_hal_device_handle_irq(). 625 * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 626 * with the PCI Specification, the value of the Latency Timer 627 * for this PCI bus master. 628 * Specify either zero or -1 to use BIOS default. 629 * @napi_weight: (TODO) 630 * @max_splits_trans: Maximum number of PCI-X split transactions. 631 * Specify (-1) to use BIOS default. 632 * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 633 * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 634 * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 635 * @shared_splits: The number of Outstanding Split Transactions that is 636 * shared by Tx and Rx requests. The device stops issuing Tx 637 * requests once the number of Outstanding Split Transactions is 638 * equal to the value of Shared_Splits. 639 * A value of zero indicates that the Tx and Rx share all allocated 640 * Split Requests, i.e. the device can issue both types (Tx and Rx) 641 * of read requests until the number of Maximum Outstanding Split 642 * Transactions is reached. 643 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 644 * to the host. This includes MAC stats as well as PCI stats. 645 * See xge_hal_stats_hw_info_t{}. 646 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 647 * @intr_mode: Line, MSI, or MSI-X interrupt. 648 * @sched_timer_us: If greater than zero, specifies time interval 649 * (in microseconds) for the device to generate 650 * interrupt. Note that unlike tti and rti interrupts, 651 * the scheduled interrupt is generated independently of 652 * whether there is transmit or receive traffic, respectively. 653 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 654 * 0 - generate scheduled interrupt periodically at the specified 655 * @sched_timer_us interval. 656 * 657 * @ring: See xge_hal_ring_config_t{}. 658 * @mac: See xge_hal_mac_config_t{}. 659 * @tti: See xge_hal_tti_config_t{}. 660 * @fifo: See xge_hal_fifo_config_t{}. 661 * 662 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 663 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 664 * ECC error. 665 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 666 * parity error. 667 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 668 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 669 * xge_hal_device_config_t{} in the driver sources. 670 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 671 * Direct Match). 672 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 673 * hash value in the RTH SPDM based steering. 674 * @rxufca_intr_thres: (TODO) 675 * @rxufca_lo_lim: (TODO) 676 * @rxufca_hi_lim: (TODO) 677 * @rxufca_lbolt_period: (TODO) 678 * @link_valid_cnt: link-valid counting is done only at device-open time, 679 * to determine with the specified certainty that the link is up. See also 680 * @link_retry_cnt. 681 * @link_retry_cnt: Max number of polls for link-up. Done only at device 682 * open time. Reducing this value as well as the previous @link_valid_cnt, 683 * speeds up device startup, which may be important if the driver 684 * is compiled into OS. 685 * @link_stability_period: Specify the period for which the link must be 686 * stable in order for the adapter to declare "LINK UP". 687 * The enumerated settings (see Xframe-II UG) are: 688 * 0 ........... instantaneous 689 * 1 ........... 500 �s 690 * 2 ........... 1 ms 691 * 3 ........... 64 ms 692 * 4 ........... 256 ms 693 * 5 ........... 512 ms 694 * 6 ........... 1 s 695 * 7 ........... 2 s 696 * @device_poll_millis: Specify the interval (in mulliseconds) between 697 * successive xge_hal_device_poll() runs. 698 * stable in order for the adapter to declare "LINK UP". 699 * @no_isr_events: TBD 700 * @lro_sg_size: TBD 701 * @lro_frm_len: TBD 702 * @bimodal_interrupts: Enable bimodal interrupts in device 703 * @bimodal_timer_lo_us: TBD 704 * @bimodal_timer_hi_us: TBD 705 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 706 * @rts_qos_en: TBD 707 * @rts_port_en: TBD 708 * @vp_config: Configuration for virtual paths 709 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 710 * can own at any one time. 711 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 712 * this S-RQ can own at any one time. 713 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 714 * WQEs before generating a message or interrupt. 715 * @refill_threshold_high:This field provides a hysteresis upper bound for 716 * automatic adapter refill operations. 717 * @refill_threshold_low:This field provides a hysteresis lower bound for 718 * automatic adapter refill operations. 719 * @eol_policy:This field sets the policy for handling the end of list condition. 720 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 721 * 2'b01 - Send UMQ message when EOL is reached. 722 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 723 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 724 * a non-zero block wrapper before giving up and sending a UMQ message 725 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 726 * by a session at any one time. 727 * @poll_or_doorbell: TBD 728 * 729 * Xframe configuration. 730 * Contains per-device configuration parameters, including: 731 * - latency timer (settable via PCI configuration space); 732 * - maximum number of split transactions; 733 * - maximum number of shared splits; 734 * - stats sampling interval, etc. 735 * 736 * In addition, xge_hal_device_config_t{} includes "subordinate" 737 * configurations, including: 738 * - fifos and rings; 739 * - MAC (see xge_hal_mac_config_t{}). 740 * 741 * See Xframe User Guide for more details. 742 * Note: Valid (min, max) range for each attribute is specified in the body of 743 * the xge_hal_device_config_t{} structure. Please refer to the 744 * corresponding include file. 745 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 746 * xge_hal_mac_config_t{}. 747 */ 748typedef struct xge_hal_device_config_t { 749 int mtu; 750#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 751#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 752 753 int isr_polling_cnt; 754#define XGE_HAL_MIN_ISR_POLLING_CNT 0 755#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 756 757 int latency_timer; 758#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 759#define XGE_HAL_MIN_LATENCY_TIMER 8 760#define XGE_HAL_MAX_LATENCY_TIMER 255 761 762 int napi_weight; 763#define XGE_HAL_DEF_NAPI_WEIGHT 64 764 765 int max_splits_trans; 766#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 767#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 768#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 769#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 770#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 771#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 772#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 773#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 774#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 775 776 int mmrb_count; 777#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 778#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 779#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 780 781 int shared_splits; 782#define XGE_HAL_MIN_SHARED_SPLITS 0 783#define XGE_HAL_MAX_SHARED_SPLITS 31 784 785 int stats_refresh_time_sec; 786#define XGE_HAL_STATS_REFRESH_DISABLE 0 787#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 788#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 789 790 int pci_freq_mherz; 791#define XGE_HAL_PCI_FREQ_MHERZ_33 33 792#define XGE_HAL_PCI_FREQ_MHERZ_66 66 793#define XGE_HAL_PCI_FREQ_MHERZ_100 100 794#define XGE_HAL_PCI_FREQ_MHERZ_133 133 795#define XGE_HAL_PCI_FREQ_MHERZ_266 266 796 797 int intr_mode; 798#define XGE_HAL_INTR_MODE_IRQLINE 0 799#define XGE_HAL_INTR_MODE_MSI 1 800#define XGE_HAL_INTR_MODE_MSIX 2 801 802 int sched_timer_us; 803#define XGE_HAL_SCHED_TIMER_DISABLED 0 804#define XGE_HAL_SCHED_TIMER_MIN 0 805#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 806 807 int sched_timer_one_shot; 808#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 809#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 810 811 xge_hal_ring_config_t ring; 812 xge_hal_mac_config_t mac; 813 xge_hal_fifo_config_t fifo; 814 815 int dump_on_serr; 816#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 817#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 818 819 int dump_on_eccerr; 820#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 821#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 822 823 int dump_on_parityerr; 824#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 825#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 826 827 int rth_en; 828#define XGE_HAL_RTH_DISABLE 0 829#define XGE_HAL_RTH_ENABLE 1 830 831 int rth_bucket_size; 832#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 833#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 834 835 int rth_spdm_en; 836#define XGE_HAL_RTH_SPDM_DISABLE 0 837#define XGE_HAL_RTH_SPDM_ENABLE 1 838 839 int rth_spdm_use_l4; 840#define XGE_HAL_RTH_SPDM_USE_L4 1 841 842 int rxufca_intr_thres; 843#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 844#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 845 846 int rxufca_lo_lim; 847#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 848#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 849 850 int rxufca_hi_lim; 851#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 852#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 853 854 int rxufca_lbolt_period; 855#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 856#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 857 858 int link_valid_cnt; 859#define XGE_HAL_LINK_VALID_CNT_MIN 0 860#define XGE_HAL_LINK_VALID_CNT_MAX 127 861 862 int link_retry_cnt; 863#define XGE_HAL_LINK_RETRY_CNT_MIN 0 864#define XGE_HAL_LINK_RETRY_CNT_MAX 127 865 866 int link_stability_period; 867#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 868#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 869#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 870 871 int device_poll_millis; 872#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 873#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 874#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 875 876 int no_isr_events; 877#define XGE_HAL_NO_ISR_EVENTS_MIN 0 878#define XGE_HAL_NO_ISR_EVENTS_MAX 1 879 880 int lro_sg_size; 881#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 882#define XGE_HAL_LRO_MIN_SG_SIZE 1 883#define XGE_HAL_LRO_MAX_SG_SIZE 64 884 885 int lro_frm_len; 886#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 887#define XGE_HAL_LRO_MIN_FRM_LEN 4096 888#define XGE_HAL_LRO_MAX_FRM_LEN 65536 889 890 int bimodal_interrupts; 891#define XGE_HAL_BIMODAL_INTR_MIN -1 892#define XGE_HAL_BIMODAL_INTR_MAX 1 893 894 int bimodal_timer_lo_us; 895#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 896#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 897 898 int bimodal_timer_hi_us; 899#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 900#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 901 902 int rts_mac_en; 903#define XGE_HAL_RTS_MAC_DISABLE 0 904#define XGE_HAL_RTS_MAC_ENABLE 1 905 906 int rts_qos_en; 907#define XGE_HAL_RTS_QOS_DISABLE 0 908#define XGE_HAL_RTS_QOS_ENABLE 1 909 910 int rts_port_en; 911#define XGE_HAL_RTS_PORT_DISABLE 0 912#define XGE_HAL_RTS_PORT_ENABLE 1 913 914#ifdef XGEHAL_RNIC 915 916 xge_hal_vp_config_t vp_config[XGE_HAL_MAX_VIRTUAL_PATHS]; 917 918 int max_cqe_groups; 919#define XGE_HAL_MAX_CQE_GROUPS_MIN 1 920#define XGE_HAL_MAX_CQE_GROUPS_MAX 16 921 922 int max_num_wqe_od_groups; 923#define XGE_HAL_MAX_NUM_OD_GROUPS_MIN 1 924#define XGE_HAL_MAX_NUM_OD_GROUPS_MAX 16 925 926 int no_wqe_threshold; 927#define XGE_HAL_NO_WQE_THRESHOLD_MIN 1 928#define XGE_HAL_NO_WQE_THRESHOLD_MAX 16 929 930 int refill_threshold_high; 931#define XGE_HAL_REFILL_THRESHOLD_HIGH_MIN 1 932#define XGE_HAL_REFILL_THRESHOLD_HIGH_MAX 16 933 934 int refill_threshold_low; 935#define XGE_HAL_REFILL_THRESHOLD_LOW_MIN 1 936#define XGE_HAL_REFILL_THRESHOLD_LOW_MAX 16 937 938 int ack_blk_limit; 939#define XGE_HAL_ACK_BLOCK_LIMIT_MIN 1 940#define XGE_HAL_ACK_BLOCK_LIMIT_MAX 16 941 942 int poll_or_doorbell; 943#define XGE_HAL_POLL_OR_DOORBELL_POLL 1 944#define XGE_HAL_POLL_OR_DOORBELL_DOORBELL 0 945 946 947#endif 948 949} xge_hal_device_config_t; 950 951/** 952 * struct xge_hal_driver_config_t - HAL (layer) configuration. 953 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 954 * periodically poll HAL, i.e, invoke 955 * xge_hal_device_poll(). 956 * Note that HAL does not maintain its own 957 * polling context. HAL relies on ULD to 958 * provide one. 959 * @queue_size_initial: Initial size of the HAL protected event queue. 960 * The queue is shared by HAL and upper-layer drivers. 961 * The queue is used to exchange and process slow-path 962 * events. See xge_hal_event_e. 963 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 964 * the queue may grow at run-time up to @queue_max_size. 965 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 966 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 967 * HAL devices.) 968 * Currently this structure contains just a few basic values. 969 * Note: Valid (min, max) range for each attribute is specified in the body of 970 * the structure. Please refer to the corresponding header file. 971 * See also: xge_hal_device_poll() 972 */ 973typedef struct xge_hal_driver_config_t { 974 int queue_size_initial; 975#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 976#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 977 978 int queue_size_max; 979#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 980#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 981 982#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 983 int tracebuf_size; 984#define XGE_HAL_MIN_CIRCULAR_ARR 4096 985#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 986#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 987 988 int tracebuf_timestamp_en; 989#define XGE_HAL_MIN_TIMESTAMP_EN 0 990#define XGE_HAL_MAX_TIMESTAMP_EN 1 991#endif 992 993} xge_hal_driver_config_t; 994 995 996/* ========================== PRIVATE API ================================= */ 997 998xge_hal_status_e 999__hal_device_config_check_common (xge_hal_device_config_t *new_config); 1000 1001xge_hal_status_e 1002__hal_device_config_check_xena (xge_hal_device_config_t *new_config); 1003 1004xge_hal_status_e 1005__hal_device_config_check_herc (xge_hal_device_config_t *new_config); 1006 1007xge_hal_status_e 1008__hal_driver_config_check (xge_hal_driver_config_t *new_config); 1009 1010__EXTERN_END_DECLS 1011 1012#endif /* XGE_HAL_CONFIG_H */ 1013