xgehal-config.h revision 173139
1214501Srpaulo/*- 2214501Srpaulo * Copyright (c) 2002-2007 Neterion, Inc. 3214501Srpaulo * All rights reserved. 4214501Srpaulo * 5214501Srpaulo * Redistribution and use in source and binary forms, with or without 6214501Srpaulo * modification, are permitted provided that the following conditions 7214501Srpaulo * are met: 8214501Srpaulo * 1. Redistributions of source code must retain the above copyright 9214501Srpaulo * notice, this list of conditions and the following disclaimer. 10214501Srpaulo * 2. Redistributions in binary form must reproduce the above copyright 11214501Srpaulo * notice, this list of conditions and the following disclaimer in the 12214501Srpaulo * documentation and/or other materials provided with the distribution. 13214501Srpaulo * 14214501Srpaulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15214501Srpaulo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16214501Srpaulo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17214501Srpaulo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18214501Srpaulo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19214501Srpaulo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20214501Srpaulo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21214501Srpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22214501Srpaulo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23214501Srpaulo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24214501Srpaulo * SUCH DAMAGE. 25214501Srpaulo * 26214501Srpaulo * $FreeBSD: head/sys/dev/nxge/include/xgehal-config.h 173139 2007-10-29 14:19:32Z rwatson $ 27214501Srpaulo */ 28214501Srpaulo 29214501Srpaulo#ifndef XGE_HAL_CONFIG_H 30214501Srpaulo#define XGE_HAL_CONFIG_H 31214501Srpaulo 32214501Srpaulo#include <dev/nxge/include/xge-os-pal.h> 33214501Srpaulo#include <dev/nxge/include/xgehal-types.h> 34214501Srpaulo#include <dev/nxge/include/xge-queue.h> 35214501Srpaulo 36214501Srpaulo__EXTERN_BEGIN_DECLS 37214501Srpaulo 38214501Srpaulo#define XGE_HAL_DEFAULT_USE_HARDCODE -1 39214501Srpaulo 40214501Srpaulo#define XGE_HAL_MAX_VIRTUAL_PATHS 8 41214501Srpaulo#define XGE_HAL_MAX_INTR_PER_VP 4 42214501Srpaulo 43214501Srpaulo 44214501Srpaulo/** 45214501Srpaulo * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 46214501Srpaulo * @enabled: Set to 1, if TTI feature is enabled. 47214501Srpaulo * @urange_a: Link utilization range A. The value from 0 to 100%. 48214501Srpaulo * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 49214501Srpaulo * each time when (and only when) the line is utilized no more 50214501Srpaulo * than @urange_a percent in the transmit direction, 51214501Srpaulo * and number of transmitted frames is greater or equal @ufc_a. 52214501Srpaulo * @urange_b: Link utilization range B. 53214501Srpaulo * @ufc_b: Frame count for the utilization range B. 54214501Srpaulo * @urange_c: Link utilization range C. 55214501Srpaulo * @ufc_c: Frame count for the utilization range C. 56214501Srpaulo * @urange_d: Link utilization range D. 57214501Srpaulo * @ufc_d: Frame count for the utilization range D. 58214501Srpaulo * @timer_val_us: Interval of time, in microseconds, at which transmit timer 59214501Srpaulo * interrupt is to be generated. Note that unless @timer_ci_en 60214501Srpaulo * is set, the timer interrupt is generated only in presence 61214501Srpaulo * of the transmit traffic. Note also that timer interrupt 62214501Srpaulo * and utilization interrupt are two separate interrupt 63214501Srpaulo * sources. 64214501Srpaulo * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 65214501Srpaulo * interrupt was generated during the interval. 66214501Srpaulo * @timer_ci_en: Enable/disable continuous interrupt. Set this value 67214501Srpaulo * to 1 in order to generate continuous interrupt 68214501Srpaulo * at fixed @timer_val intervals of time, independently 69214501Srpaulo * of whether there is transmit traffic or not. 70214501Srpaulo * @enabled: Set to 1, if TTI feature is enabled. 71214501Srpaulo * 72214501Srpaulo * Xframe transmit interrupt configuration. 73214501Srpaulo * See Xframe User Guide, Section 3.5 "Device Interrupts" 74214501Srpaulo * for more details. Note also (min, max) 75214501Srpaulo * ranges in the body of the xge_hal_tx_intr_config_t structure. 76214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 77214501Srpaulo * the xge_hal_tti_config_t{} structure. Please refer to the 78214501Srpaulo * corresponding header file. 79214501Srpaulo */ 80214501Srpaulotypedef struct xge_hal_tti_config_t { 81214501Srpaulo 82214501Srpaulo int enabled; 83214501Srpaulo#define XGE_HAL_TTI_ENABLE 1 84214501Srpaulo#define XGE_HAL_TTI_DISABLE 0 85214501Srpaulo 86214501Srpaulo /* Line utilization interrupts */ 87214501Srpaulo 88214501Srpaulo int urange_a; 89214501Srpaulo#define XGE_HAL_MIN_TX_URANGE_A 0 90214501Srpaulo#define XGE_HAL_MAX_TX_URANGE_A 100 91214501Srpaulo 92214501Srpaulo int ufc_a; 93214501Srpaulo#define XGE_HAL_MIN_TX_UFC_A 0 94214501Srpaulo#define XGE_HAL_MAX_TX_UFC_A 65535 95214501Srpaulo 96214501Srpaulo int urange_b; 97214501Srpaulo#define XGE_HAL_MIN_TX_URANGE_B 0 98214501Srpaulo#define XGE_HAL_MAX_TX_URANGE_B 100 99214501Srpaulo 100214501Srpaulo int ufc_b; 101214501Srpaulo#define XGE_HAL_MIN_TX_UFC_B 0 102214501Srpaulo#define XGE_HAL_MAX_TX_UFC_B 65535 103214501Srpaulo 104214501Srpaulo int urange_c; 105214501Srpaulo#define XGE_HAL_MIN_TX_URANGE_C 0 106214501Srpaulo#define XGE_HAL_MAX_TX_URANGE_C 100 107214501Srpaulo 108214501Srpaulo int ufc_c; 109214501Srpaulo#define XGE_HAL_MIN_TX_UFC_C 0 110214501Srpaulo#define XGE_HAL_MAX_TX_UFC_C 65535 111214501Srpaulo 112214501Srpaulo int ufc_d; 113214501Srpaulo#define XGE_HAL_MIN_TX_UFC_D 0 114214501Srpaulo#define XGE_HAL_MAX_TX_UFC_D 65535 115214501Srpaulo 116214501Srpaulo int timer_val_us; 117214501Srpaulo#define XGE_HAL_MIN_TX_TIMER_VAL 0 118214501Srpaulo#define XGE_HAL_MAX_TX_TIMER_VAL 65535 119214501Srpaulo 120214501Srpaulo int timer_ac_en; 121214501Srpaulo#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 122214501Srpaulo#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 123214501Srpaulo 124214501Srpaulo int timer_ci_en; 125214501Srpaulo#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 126214501Srpaulo#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 127214501Srpaulo 128214501Srpaulo 129214501Srpaulo} xge_hal_tti_config_t; 130214501Srpaulo 131214501Srpaulo/** 132214501Srpaulo * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 133214501Srpaulo * @urange_a: Link utilization range A. The value from 0 to 100%. 134214501Srpaulo * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 135214501Srpaulo * each time when (and only when) the line is utilized no more 136214501Srpaulo * than @urange_a percent inbound, 137214501Srpaulo * and number of received frames is greater or equal @ufc_a. 138214501Srpaulo * @urange_b: Link utilization range B. 139214501Srpaulo * @ufc_b: Frame count for the utilization range B. 140214501Srpaulo * @urange_c: Link utilization range C. 141214501Srpaulo * @ufc_c: Frame count for the utilization range C. 142214501Srpaulo * @urange_d: Link utilization range D. 143214501Srpaulo * @ufc_d: Frame count for the utilization range D. 144214501Srpaulo * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 145214501Srpaulo * interrupt was generated during the interval. 146214501Srpaulo * @timer_val_us: Interval of time, in microseconds, at which receive timer 147214501Srpaulo * interrupt is to be generated. The timer interrupt is generated 148214501Srpaulo * only in presence of the inbound traffic. Note also that timer 149214501Srpaulo * interrupt and utilization interrupt are two separate interrupt 150214501Srpaulo * sources. 151214501Srpaulo * 152214501Srpaulo * Xframe receive interrupt configuration. 153214501Srpaulo * See Xframe User Guide, Section 3.5 "Device Interrupts" 154214501Srpaulo * for more details. Note also (min, max) 155214501Srpaulo * ranges in the body of the xge_hal_intr_config_t structure. 156214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 157214501Srpaulo * the xge_hal_rti_config_t{} structure. Please refer to the 158214501Srpaulo * corresponding header file. 159214501Srpaulo */ 160214501Srpaulotypedef struct xge_hal_rti_config_t { 161214501Srpaulo 162214501Srpaulo int urange_a; 163214501Srpaulo#define XGE_HAL_MIN_RX_URANGE_A 0 164214501Srpaulo#define XGE_HAL_MAX_RX_URANGE_A 127 165214501Srpaulo 166214501Srpaulo int ufc_a; 167214501Srpaulo#define XGE_HAL_MIN_RX_UFC_A 0 168214501Srpaulo#define XGE_HAL_MAX_RX_UFC_A 65535 169214501Srpaulo 170214501Srpaulo int urange_b; 171214501Srpaulo#define XGE_HAL_MIN_RX_URANGE_B 0 172214501Srpaulo#define XGE_HAL_MAX_RX_URANGE_B 127 173214501Srpaulo 174214501Srpaulo int ufc_b; 175214501Srpaulo#define XGE_HAL_MIN_RX_UFC_B 0 176214501Srpaulo#define XGE_HAL_MAX_RX_UFC_B 65535 177214501Srpaulo 178214501Srpaulo int urange_c; 179214501Srpaulo#define XGE_HAL_MIN_RX_URANGE_C 0 180214501Srpaulo#define XGE_HAL_MAX_RX_URANGE_C 127 181214501Srpaulo 182214501Srpaulo int ufc_c; 183214501Srpaulo#define XGE_HAL_MIN_RX_UFC_C 0 184214501Srpaulo#define XGE_HAL_MAX_RX_UFC_C 65535 185214501Srpaulo 186214501Srpaulo int ufc_d; 187214501Srpaulo#define XGE_HAL_MIN_RX_UFC_D 0 188214501Srpaulo#define XGE_HAL_MAX_RX_UFC_D 65535 189214501Srpaulo 190214501Srpaulo int timer_ac_en; 191214501Srpaulo#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 192214501Srpaulo#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 193214501Srpaulo 194214501Srpaulo int timer_val_us; 195214501Srpaulo#define XGE_HAL_MIN_RX_TIMER_VAL 0 196214501Srpaulo#define XGE_HAL_MAX_RX_TIMER_VAL 65535 197214501Srpaulo 198214501Srpaulo} xge_hal_rti_config_t; 199214501Srpaulo 200214501Srpaulo/** 201214501Srpaulo * struct xge_hal_fifo_queue_t - Single fifo configuration. 202214501Srpaulo * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 203214501Srpaulo * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 204214501Srpaulo * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 205214501Srpaulo * Use 0 otherwise. 206214501Srpaulo * @intr_vector: TBD 207214501Srpaulo * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 208214501Srpaulo * which generally improves latency of the host bridge operation 209214501Srpaulo * (see PCI specification). For valid values please refer 210214501Srpaulo * to xge_hal_fifo_queue_t{} in the driver sources. 211214501Srpaulo * @priority: TBD 212214501Srpaulo * @configured: Boolean. Use 1 to specify that the fifo is configured. 213214501Srpaulo * Only "configured" fifos can be activated and used to post 214214501Srpaulo * Tx descriptors. Any subset of 8 available fifos can be 215214501Srpaulo * "configured". 216214501Srpaulo * @tti: TBD 217214501Srpaulo * 218214501Srpaulo * Single fifo configuration. 219214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 220214501Srpaulo * the xge_hal_fifo_queue_t{} structure. Please refer to the 221214501Srpaulo * corresponding header file. 222214501Srpaulo * See also: xge_hal_fifo_config_t{} 223214501Srpaulo */ 224214501Srpaulotypedef struct xge_hal_fifo_queue_t { 225214501Srpaulo int max; 226214501Srpaulo int initial; 227214501Srpaulo#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 228214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 229214501Srpaulo 230214501Srpaulo int intr; 231214501Srpaulo#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 232214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 233214501Srpaulo 234214501Srpaulo int intr_vector; 235214501Srpaulo#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 236214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 237214501Srpaulo 238214501Srpaulo int no_snoop_bits; 239214501Srpaulo#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 240214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 241214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 242214501Srpaulo#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 243214501Srpaulo 244214501Srpaulo int priority; 245214501Srpaulo#define XGE_HAL_MIN_FIFO_PRIORITY 0 246214501Srpaulo#define XGE_HAL_MAX_FIFO_PRIORITY 63 247214501Srpaulo 248214501Srpaulo int configured; 249214501Srpaulo#define XGE_HAL_MIN_FIFO_CONFIGURED 0 250214501Srpaulo#define XGE_HAL_MAX_FIFO_CONFIGURED 1 251214501Srpaulo 252214501Srpaulo#define XGE_HAL_MAX_FIFO_TTI_NUM 7 253214501Srpaulo#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 254214501Srpaulo xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 255214501Srpaulo 256214501Srpaulo} xge_hal_fifo_queue_t; 257214501Srpaulo 258214501Srpaulo/** 259214501Srpaulo * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 260214501Srpaulo * @max_frags: Max number of Tx buffers per TxDL (that is, per single 261214501Srpaulo * transmit operation). 262214501Srpaulo * No more than 256 transmit buffers can be specified. 263214501Srpaulo * @max_aligned_frags: Number of fragments to be aligned out of 264214501Srpaulo * maximum fragments (see @max_frags). 265214501Srpaulo * @reserve_threshold: Descriptor reservation threshold. 266214501Srpaulo * At least @reserve_threshold descriptors will remain 267214501Srpaulo * unallocated at all times. 268214501Srpaulo * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 269214501Srpaulo * bytes. Setting @memblock_size to page size ensures 270214501Srpaulo * by-page allocation of descriptors. 128K bytes is the 271214501Srpaulo * maximum supported block size. 272214501Srpaulo * @queue: Array of per-fifo configurations. 273214501Srpaulo * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 274214501Srpaulo * (e.g., to align on a cache line). 275214501Srpaulo * 276214501Srpaulo * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 277214501Srpaulo * structures. 278214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 279214501Srpaulo * the xge_hal_fifo_config_t{} structure. Please refer to the 280214501Srpaulo * corresponding header file. 281214501Srpaulo * See also: xge_hal_ring_queue_t{}. 282214501Srpaulo */ 283214501Srpaulotypedef struct xge_hal_fifo_config_t { 284214501Srpaulo int max_frags; 285214501Srpaulo#define XGE_HAL_MIN_FIFO_FRAGS 1 286214501Srpaulo#define XGE_HAL_MAX_FIFO_FRAGS 256 287214501Srpaulo 288214501Srpaulo int reserve_threshold; 289214501Srpaulo#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 290214501Srpaulo#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 291214501Srpaulo 292214501Srpaulo int memblock_size; 293214501Srpaulo#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 294214501Srpaulo#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 295214501Srpaulo 296214501Srpaulo int alignment_size; 297214501Srpaulo#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 298214501Srpaulo#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 299214501Srpaulo 300214501Srpaulo int max_aligned_frags; 301214501Srpaulo /* range: (1, @max_frags) */ 302214501Srpaulo 303214501Srpaulo#define XGE_HAL_MIN_FIFO_NUM 1 304214501Srpaulo#define XGE_HAL_MAX_FIFO_NUM_HERC 8 305214501Srpaulo#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 306214501Srpaulo#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 307214501Srpaulo xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 308214501Srpaulo} xge_hal_fifo_config_t; 309214501Srpaulo 310214501Srpaulo/** 311214501Srpaulo * struct xge_hal_rts_port_t - RTS port entry 312214501Srpaulo * @num: Port number 313214501Srpaulo * @udp: Port is UDP (default TCP) 314214501Srpaulo * @src: Port is Source (default Destination) 315214501Srpaulo */ 316214501Srpaulotypedef struct xge_hal_rts_port_t { 317214501Srpaulo int num; 318214501Srpaulo int udp; 319214501Srpaulo int src; 320214501Srpaulo} xge_hal_rts_port_t; 321214501Srpaulo 322214501Srpaulo/** 323214501Srpaulo * struct xge_hal_ring_queue_t - Single ring configuration. 324214501Srpaulo * @max: Max numbers of RxD blocks per queue 325214501Srpaulo * @initial: Initial numbers of RxD blocks per queue 326214501Srpaulo * (can grow up to @max) 327214501Srpaulo * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 328214501Srpaulo * to Xframe User Guide. 329214501Srpaulo * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 330214501Srpaulo * Note that 64MB of available 331214501Srpaulo * on-board DRAM is shared between receive rings. 332214501Srpaulo * If a single ring is used, @dram_size_mb can be set to 64. 333214501Srpaulo * Sum of all rings' @dram_size_mb cannot exceed 64. 334214501Srpaulo * @intr_vector: TBD 335214501Srpaulo * @backoff_interval_us: Time (in microseconds), after which Xframe 336214501Srpaulo * tries to download RxDs posted by the host. 337214501Srpaulo * Note that the "backoff" does not happen if host posts receive 338214501Srpaulo * descriptors in the timely fashion. 339214501Srpaulo * @max_frm_len: Maximum frame length that can be received on _that_ ring. 340214501Srpaulo * Setting this field to -1 ensures that the ring will 341214501Srpaulo * "accept" MTU-size frames (note that MTU can be changed at 342214501Srpaulo * runtime). 343214501Srpaulo * Any value other than (-1) specifies a certain "hard" 344214501Srpaulo * limit on the receive frame sizes. 345214501Srpaulo * The field can be used to activate receive frame-length based 346214501Srpaulo * steering. 347214501Srpaulo * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 348214501Srpaulo * to give prioritized access to PCI-X. See Xframe documentation 349214501Srpaulo * for details. 350214501Srpaulo * @rth_en: Enable Receive Traffic Hashing (RTH). 351214501Srpaulo * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 352214501Srpaulo * which generally improves latency of the host bridge operation 353214501Srpaulo * (see PCI specification). For valid values please refer 354214501Srpaulo * to xge_hal_ring_queue_t{} in the driver sources. 355214501Srpaulo * @indicate_max_pkts: Sets maximum number of received frames to be processed 356214501Srpaulo * within single interrupt. 357214501Srpaulo * @configured: Boolean. Use 1 to specify that the ring is configured. 358214501Srpaulo * Only "configured" rings can be activated and used to post 359214501Srpaulo * Rx descriptors. Any subset of 8 available rings can be 360214501Srpaulo * "configured". 361214501Srpaulo * @rts_mac_en: 1 - To enable Receive MAC address steering. 362214501Srpaulo * 0 - To disable Receive MAC address steering. 363214501Srpaulo * @rth_en: TBD 364214501Srpaulo * @rts_port_en: TBD 365214501Srpaulo * @rts_ports: TBD 366214501Srpaulo * @rti: Xframe receive interrupt configuration. 367214501Srpaulo * 368214501Srpaulo * Single ring configuration. 369214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 370214501Srpaulo * the xge_hal_ring_queue_t{} structure. Please refer to the 371214501Srpaulo * corresponding header file. 372214501Srpaulo * See also: xge_hal_fifo_config_t{}. 373214501Srpaulo */ 374214501Srpaulotypedef struct xge_hal_ring_queue_t { 375214501Srpaulo int max; 376214501Srpaulo int initial; 377214501Srpaulo#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 378214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 379214501Srpaulo 380214501Srpaulo int buffer_mode; 381214501Srpaulo#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 382214501Srpaulo#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 383214501Srpaulo#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 384214501Srpaulo#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 385214501Srpaulo 386214501Srpaulo int dram_size_mb; 387214501Srpaulo#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 388214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 389214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 390214501Srpaulo 391214501Srpaulo int intr_vector; 392214501Srpaulo#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 393214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 394214501Srpaulo 395214501Srpaulo int backoff_interval_us; 396214501Srpaulo#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 397214501Srpaulo#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 398214501Srpaulo 399214501Srpaulo int max_frm_len; 400214501Srpaulo#define XGE_HAL_MIN_MAX_FRM_LEN -1 401214501Srpaulo#define XGE_HAL_MAX_MAX_FRM_LEN 9622 402214501Srpaulo 403214501Srpaulo int priority; 404214501Srpaulo#define XGE_HAL_MIN_RING_PRIORITY 0 405214501Srpaulo#define XGE_HAL_MAX_RING_PRIORITY 7 406214501Srpaulo 407214501Srpaulo int no_snoop_bits; 408214501Srpaulo#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 409214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 410214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 411214501Srpaulo#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 412214501Srpaulo 413214501Srpaulo int indicate_max_pkts; 414214501Srpaulo#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 415214501Srpaulo#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 416214501Srpaulo 417214501Srpaulo int configured; 418214501Srpaulo#define XGE_HAL_MIN_RING_CONFIGURED 0 419214501Srpaulo#define XGE_HAL_MAX_RING_CONFIGURED 1 420214501Srpaulo 421214501Srpaulo int rts_mac_en; 422214501Srpaulo#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 423214501Srpaulo#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 424214501Srpaulo 425214501Srpaulo int rth_en; 426214501Srpaulo#define XGE_HAL_MIN_RING_RTH_EN 0 427214501Srpaulo#define XGE_HAL_MAX_RING_RTH_EN 1 428214501Srpaulo 429214501Srpaulo int rts_port_en; 430214501Srpaulo#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 431214501Srpaulo#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 432214501Srpaulo 433214501Srpaulo#define XGE_HAL_MAX_STEERABLE_PORTS 32 434214501Srpaulo xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 435214501Srpaulo 436214501Srpaulo xge_hal_rti_config_t rti; 437214501Srpaulo 438214501Srpaulo} xge_hal_ring_queue_t; 439214501Srpaulo 440214501Srpaulo/** 441214501Srpaulo * struct xge_hal_ring_config_t - Array of ring configurations. 442214501Srpaulo * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 443214501Srpaulo * bytes. Setting @memblock_size to page size ensures 444214501Srpaulo * by-page allocation of descriptors. 128K bytes is the 445214501Srpaulo * upper limit. 446214501Srpaulo * @scatter_mode: Xframe supports two receive scatter modes: A and B. 447214501Srpaulo * For details please refer to Xframe User Guide. 448214501Srpaulo * @strip_vlan_tag: TBD 449214501Srpaulo * @queue: Array of all Xframe ring configurations. 450214501Srpaulo * 451214501Srpaulo * Array of ring configurations. 452214501Srpaulo * See also: xge_hal_ring_queue_t{}. 453214501Srpaulo */ 454214501Srpaulotypedef struct xge_hal_ring_config_t { 455214501Srpaulo 456214501Srpaulo int memblock_size; 457214501Srpaulo#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 458214501Srpaulo#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 459214501Srpaulo 460214501Srpaulo int scatter_mode; 461214501Srpaulo#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 462214501Srpaulo#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 463214501Srpaulo 464214501Srpaulo int strip_vlan_tag; 465214501Srpaulo#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 466214501Srpaulo#define XGE_HAL_RING_STRIP_VLAN_TAG 1 467214501Srpaulo 468214501Srpaulo#define XGE_HAL_MIN_RING_NUM 1 469214501Srpaulo#define XGE_HAL_MAX_RING_NUM_HERC 8 470214501Srpaulo#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 471214501Srpaulo#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 472214501Srpaulo xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 473214501Srpaulo 474214501Srpaulo} xge_hal_ring_config_t; 475214501Srpaulo 476214501Srpaulo/** 477214501Srpaulo * struct xge_hal_mac_config_t - MAC configuration. 478214501Srpaulo * @media: Transponder type. 479214501Srpaulo * @tmac_util_period: The sampling period over which the transmit utilization 480214501Srpaulo * is calculated. 481214501Srpaulo * @rmac_util_period: The sampling period over which the receive utilization 482214501Srpaulo * is calculated. 483214501Srpaulo * @rmac_strip_pad: Determines whether padding of received frames is removed by 484214501Srpaulo * the MAC or sent to the host. 485214501Srpaulo * @rmac_bcast_en: Enable frames containing broadcast address to be 486214501Srpaulo * passed to the host. 487214501Srpaulo * @rmac_pause_gen_en: Received pause generation enable. 488214501Srpaulo * @rmac_pause_rcv_en: Receive pause enable. 489214501Srpaulo * @rmac_pause_time: The value to be inserted in outgoing pause frames. 490214501Srpaulo * Has units of pause quanta (one pause quanta = 512 bit times). 491214501Srpaulo * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 492214501Srpaulo * for queues 0 through 3. The threshold value indicates portion of the 493214501Srpaulo * individual receive buffer queue size. Thresholds have a range of 0 to 494214501Srpaulo * 255, allowing 256 possible watermarks in a queue. 495214501Srpaulo * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 496214501Srpaulo * for queues 4 through 7. The threshold value indicates portion of the 497214501Srpaulo * individual receive buffer queue size. Thresholds have a range of 0 to 498214501Srpaulo * 255, allowing 256 possible watermarks in a queue. 499214501Srpaulo * 500214501Srpaulo * MAC configuration. This includes various aspects of configuration, including: 501214501Srpaulo * - Pause frame threshold; 502214501Srpaulo * - sampling rate to calculate link utilization; 503214501Srpaulo * - enabling/disabling broadcasts. 504214501Srpaulo * 505214501Srpaulo * See Xframe User Guide for more details. 506214501Srpaulo * Note: Valid (min, max) range for each attribute is specified in the body of 507214501Srpaulo * the xge_hal_mac_config_t{} structure. Please refer to the 508214501Srpaulo * corresponding include file. 509214501Srpaulo */ 510214501Srpaulotypedef struct xge_hal_mac_config_t { 511214501Srpaulo int media; 512214501Srpaulo#define XGE_HAL_MIN_MEDIA 0 513214501Srpaulo#define XGE_HAL_MEDIA_SR 0 514214501Srpaulo#define XGE_HAL_MEDIA_SW 1 515214501Srpaulo#define XGE_HAL_MEDIA_LR 2 516214501Srpaulo#define XGE_HAL_MEDIA_LW 3 517214501Srpaulo#define XGE_HAL_MEDIA_ER 4 518214501Srpaulo#define XGE_HAL_MEDIA_EW 5 519214501Srpaulo#define XGE_HAL_MAX_MEDIA 5 520214501Srpaulo 521214501Srpaulo int tmac_util_period; 522214501Srpaulo#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 523214501Srpaulo#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 524214501Srpaulo 525214501Srpaulo int rmac_util_period; 526214501Srpaulo#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 527214501Srpaulo#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 528214501Srpaulo 529214501Srpaulo int rmac_bcast_en; 530214501Srpaulo#define XGE_HAL_MIN_RMAC_BCAST_EN 0 531214501Srpaulo#define XGE_HAL_MAX_RMAC_BCAST_EN 1 532214501Srpaulo 533214501Srpaulo int rmac_pause_gen_en; 534214501Srpaulo#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 535214501Srpaulo#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 536214501Srpaulo 537214501Srpaulo int rmac_pause_rcv_en; 538214501Srpaulo#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 539214501Srpaulo#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 540214501Srpaulo 541214501Srpaulo int rmac_pause_time; 542214501Srpaulo#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 543214501Srpaulo#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 544214501Srpaulo 545214501Srpaulo int mc_pause_threshold_q0q3; 546214501Srpaulo#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 547214501Srpaulo#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 548214501Srpaulo 549214501Srpaulo int mc_pause_threshold_q4q7; 550214501Srpaulo#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 551214501Srpaulo#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 552214501Srpaulo 553214501Srpaulo} xge_hal_mac_config_t; 554214501Srpaulo 555214501Srpaulo/** 556214501Srpaulo * struct xge_hal_device_config_t - Device configuration. 557214501Srpaulo * @mtu: Current mtu size. 558214501Srpaulo * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 559214501Srpaulo * completions. Used in xge_hal_device_handle_irq(). 560214501Srpaulo * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 561214501Srpaulo * with the PCI Specification, the value of the Latency Timer 562214501Srpaulo * for this PCI bus master. 563214501Srpaulo * Specify either zero or -1 to use BIOS default. 564214501Srpaulo * @napi_weight: (TODO) 565214501Srpaulo * @max_splits_trans: Maximum number of PCI-X split transactions. 566214501Srpaulo * Specify (-1) to use BIOS default. 567214501Srpaulo * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 568214501Srpaulo * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 569214501Srpaulo * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 570 * @shared_splits: The number of Outstanding Split Transactions that is 571 * shared by Tx and Rx requests. The device stops issuing Tx 572 * requests once the number of Outstanding Split Transactions is 573 * equal to the value of Shared_Splits. 574 * A value of zero indicates that the Tx and Rx share all allocated 575 * Split Requests, i.e. the device can issue both types (Tx and Rx) 576 * of read requests until the number of Maximum Outstanding Split 577 * Transactions is reached. 578 * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 579 * to the host. This includes MAC stats as well as PCI stats. 580 * See xge_hal_stats_hw_info_t{}. 581 * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 582 * @intr_mode: Line, MSI, or MSI-X interrupt. 583 * @sched_timer_us: If greater than zero, specifies time interval 584 * (in microseconds) for the device to generate 585 * interrupt. Note that unlike tti and rti interrupts, 586 * the scheduled interrupt is generated independently of 587 * whether there is transmit or receive traffic, respectively. 588 * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 589 * 0 - generate scheduled interrupt periodically at the specified 590 * @sched_timer_us interval. 591 * 592 * @ring: See xge_hal_ring_config_t{}. 593 * @mac: See xge_hal_mac_config_t{}. 594 * @tti: See xge_hal_tti_config_t{}. 595 * @fifo: See xge_hal_fifo_config_t{}. 596 * 597 * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 598 * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 599 * ECC error. 600 * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 601 * parity error. 602 * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 603 * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 604 * xge_hal_device_config_t{} in the driver sources. 605 * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 606 * Direct Match). 607 * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 608 * hash value in the RTH SPDM based steering. 609 * @rxufca_intr_thres: (TODO) 610 * @rxufca_lo_lim: (TODO) 611 * @rxufca_hi_lim: (TODO) 612 * @rxufca_lbolt_period: (TODO) 613 * @link_valid_cnt: link-valid counting is done only at device-open time, 614 * to determine with the specified certainty that the link is up. See also 615 * @link_retry_cnt. 616 * @link_retry_cnt: Max number of polls for link-up. Done only at device 617 * open time. Reducing this value as well as the previous @link_valid_cnt, 618 * speeds up device startup, which may be important if the driver 619 * is compiled into OS. 620 * @link_stability_period: Specify the period for which the link must be 621 * stable in order for the adapter to declare "LINK UP". 622 * The enumerated settings (see Xframe-II UG) are: 623 * 0 ........... instantaneous 624 * 1 ........... 500 �s 625 * 2 ........... 1 ms 626 * 3 ........... 64 ms 627 * 4 ........... 256 ms 628 * 5 ........... 512 ms 629 * 6 ........... 1 s 630 * 7 ........... 2 s 631 * @device_poll_millis: Specify the interval (in mulliseconds) between 632 * successive xge_hal_device_poll() runs. 633 * stable in order for the adapter to declare "LINK UP". 634 * @no_isr_events: TBD 635 * @lro_sg_size: TBD 636 * @lro_frm_len: TBD 637 * @bimodal_interrupts: Enable bimodal interrupts in device 638 * @bimodal_timer_lo_us: TBD 639 * @bimodal_timer_hi_us: TBD 640 * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 641 * @rts_qos_en: TBD 642 * @rts_port_en: TBD 643 * @vp_config: Configuration for virtual paths 644 * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 645 * can own at any one time. 646 * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 647 * this S-RQ can own at any one time. 648 * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 649 * WQEs before generating a message or interrupt. 650 * @refill_threshold_high:This field provides a hysteresis upper bound for 651 * automatic adapter refill operations. 652 * @refill_threshold_low:This field provides a hysteresis lower bound for 653 * automatic adapter refill operations. 654 * @eol_policy:This field sets the policy for handling the end of list condition. 655 * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 656 * 2'b01 - Send UMQ message when EOL is reached. 657 * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 658 * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 659 * a non-zero block wrapper before giving up and sending a UMQ message 660 * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 661 * by a session at any one time. 662 * @poll_or_doorbell: TBD 663 * 664 * Xframe configuration. 665 * Contains per-device configuration parameters, including: 666 * - latency timer (settable via PCI configuration space); 667 * - maximum number of split transactions; 668 * - maximum number of shared splits; 669 * - stats sampling interval, etc. 670 * 671 * In addition, xge_hal_device_config_t{} includes "subordinate" 672 * configurations, including: 673 * - fifos and rings; 674 * - MAC (see xge_hal_mac_config_t{}). 675 * 676 * See Xframe User Guide for more details. 677 * Note: Valid (min, max) range for each attribute is specified in the body of 678 * the xge_hal_device_config_t{} structure. Please refer to the 679 * corresponding include file. 680 * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 681 * xge_hal_mac_config_t{}. 682 */ 683typedef struct xge_hal_device_config_t { 684 int mtu; 685#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 686#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 687 688 int isr_polling_cnt; 689#define XGE_HAL_MIN_ISR_POLLING_CNT 0 690#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 691 692 int latency_timer; 693#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 694#define XGE_HAL_MIN_LATENCY_TIMER 8 695#define XGE_HAL_MAX_LATENCY_TIMER 255 696 697 int napi_weight; 698#define XGE_HAL_DEF_NAPI_WEIGHT 64 699 700 int max_splits_trans; 701#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 702#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 703#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 704#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 705#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 706#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 707#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 708#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 709#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 710 711 int mmrb_count; 712#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 713#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 714#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 715 716 int shared_splits; 717#define XGE_HAL_MIN_SHARED_SPLITS 0 718#define XGE_HAL_MAX_SHARED_SPLITS 31 719 720 int stats_refresh_time_sec; 721#define XGE_HAL_STATS_REFRESH_DISABLE 0 722#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 723#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 724 725 int pci_freq_mherz; 726#define XGE_HAL_PCI_FREQ_MHERZ_33 33 727#define XGE_HAL_PCI_FREQ_MHERZ_66 66 728#define XGE_HAL_PCI_FREQ_MHERZ_100 100 729#define XGE_HAL_PCI_FREQ_MHERZ_133 133 730#define XGE_HAL_PCI_FREQ_MHERZ_266 266 731 732 int intr_mode; 733#define XGE_HAL_INTR_MODE_IRQLINE 0 734#define XGE_HAL_INTR_MODE_MSI 1 735#define XGE_HAL_INTR_MODE_MSIX 2 736 737 int sched_timer_us; 738#define XGE_HAL_SCHED_TIMER_DISABLED 0 739#define XGE_HAL_SCHED_TIMER_MIN 0 740#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 741 742 int sched_timer_one_shot; 743#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 744#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 745 746 xge_hal_ring_config_t ring; 747 xge_hal_mac_config_t mac; 748 xge_hal_fifo_config_t fifo; 749 750 int dump_on_serr; 751#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 752#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 753 754 int dump_on_eccerr; 755#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 756#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 757 758 int dump_on_parityerr; 759#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 760#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 761 762 int rth_en; 763#define XGE_HAL_RTH_DISABLE 0 764#define XGE_HAL_RTH_ENABLE 1 765 766 int rth_bucket_size; 767#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 768#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 769 770 int rth_spdm_en; 771#define XGE_HAL_RTH_SPDM_DISABLE 0 772#define XGE_HAL_RTH_SPDM_ENABLE 1 773 774 int rth_spdm_use_l4; 775#define XGE_HAL_RTH_SPDM_USE_L4 1 776 777 int rxufca_intr_thres; 778#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 779#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 780 781 int rxufca_lo_lim; 782#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 783#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 784 785 int rxufca_hi_lim; 786#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 787#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 788 789 int rxufca_lbolt_period; 790#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 791#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 792 793 int link_valid_cnt; 794#define XGE_HAL_LINK_VALID_CNT_MIN 0 795#define XGE_HAL_LINK_VALID_CNT_MAX 127 796 797 int link_retry_cnt; 798#define XGE_HAL_LINK_RETRY_CNT_MIN 0 799#define XGE_HAL_LINK_RETRY_CNT_MAX 127 800 801 int link_stability_period; 802#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 803#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 804#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 805 806 int device_poll_millis; 807#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 808#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 809#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 810 811 int no_isr_events; 812#define XGE_HAL_NO_ISR_EVENTS_MIN 0 813#define XGE_HAL_NO_ISR_EVENTS_MAX 1 814 815 int lro_sg_size; 816#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 817#define XGE_HAL_LRO_MIN_SG_SIZE 1 818#define XGE_HAL_LRO_MAX_SG_SIZE 64 819 820 int lro_frm_len; 821#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 822#define XGE_HAL_LRO_MIN_FRM_LEN 4096 823#define XGE_HAL_LRO_MAX_FRM_LEN 65536 824 825 int bimodal_interrupts; 826#define XGE_HAL_BIMODAL_INTR_MIN -1 827#define XGE_HAL_BIMODAL_INTR_MAX 1 828 829 int bimodal_timer_lo_us; 830#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 831#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 832 833 int bimodal_timer_hi_us; 834#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 835#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 836 837 int rts_mac_en; 838#define XGE_HAL_RTS_MAC_DISABLE 0 839#define XGE_HAL_RTS_MAC_ENABLE 1 840 841 int rts_qos_en; 842#define XGE_HAL_RTS_QOS_DISABLE 0 843#define XGE_HAL_RTS_QOS_ENABLE 1 844 845 int rts_port_en; 846#define XGE_HAL_RTS_PORT_DISABLE 0 847#define XGE_HAL_RTS_PORT_ENABLE 1 848 849} xge_hal_device_config_t; 850 851/** 852 * struct xge_hal_driver_config_t - HAL (layer) configuration. 853 * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 854 * periodically poll HAL, i.e, invoke 855 * xge_hal_device_poll(). 856 * Note that HAL does not maintain its own 857 * polling context. HAL relies on ULD to 858 * provide one. 859 * @queue_size_initial: Initial size of the HAL protected event queue. 860 * The queue is shared by HAL and upper-layer drivers. 861 * The queue is used to exchange and process slow-path 862 * events. See xge_hal_event_e. 863 * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 864 * the queue may grow at run-time up to @queue_max_size. 865 * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 866 * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 867 * HAL devices.) 868 * Currently this structure contains just a few basic values. 869 * Note: Valid (min, max) range for each attribute is specified in the body of 870 * the structure. Please refer to the corresponding header file. 871 * See also: xge_hal_device_poll() 872 */ 873typedef struct xge_hal_driver_config_t { 874 int queue_size_initial; 875#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 876#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 877 878 int queue_size_max; 879#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 880#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 881 882#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 883 int tracebuf_size; 884#define XGE_HAL_MIN_CIRCULAR_ARR 4096 885#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 886#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 887 888 int tracebuf_timestamp_en; 889#define XGE_HAL_MIN_TIMESTAMP_EN 0 890#define XGE_HAL_MAX_TIMESTAMP_EN 1 891#endif 892 893} xge_hal_driver_config_t; 894 895 896/* ========================== PRIVATE API ================================= */ 897 898xge_hal_status_e 899__hal_device_config_check_common (xge_hal_device_config_t *new_config); 900 901xge_hal_status_e 902__hal_device_config_check_xena (xge_hal_device_config_t *new_config); 903 904xge_hal_status_e 905__hal_device_config_check_herc (xge_hal_device_config_t *new_config); 906 907xge_hal_status_e 908__hal_driver_config_check (xge_hal_driver_config_t *new_config); 909 910__EXTERN_END_DECLS 911 912#endif /* XGE_HAL_CONFIG_H */ 913