1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_CONFIG_H 30171095Ssam#define XGE_HAL_CONFIG_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xge-os-pal.h> 33171095Ssam#include <dev/nxge/include/xgehal-types.h> 34171095Ssam#include <dev/nxge/include/xge-queue.h> 35171095Ssam 36171095Ssam__EXTERN_BEGIN_DECLS 37171095Ssam 38173139Srwatson#define XGE_HAL_DEFAULT_USE_HARDCODE -1 39171095Ssam 40173139Srwatson#define XGE_HAL_MAX_VIRTUAL_PATHS 8 41173139Srwatson#define XGE_HAL_MAX_INTR_PER_VP 4 42171095Ssam 43171095Ssam 44171095Ssam/** 45171095Ssam * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration. 46171095Ssam * @enabled: Set to 1, if TTI feature is enabled. 47171095Ssam * @urange_a: Link utilization range A. The value from 0 to 100%. 48171095Ssam * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 49171095Ssam * each time when (and only when) the line is utilized no more 50171095Ssam * than @urange_a percent in the transmit direction, 51171095Ssam * and number of transmitted frames is greater or equal @ufc_a. 52171095Ssam * @urange_b: Link utilization range B. 53171095Ssam * @ufc_b: Frame count for the utilization range B. 54171095Ssam * @urange_c: Link utilization range C. 55171095Ssam * @ufc_c: Frame count for the utilization range C. 56171095Ssam * @urange_d: Link utilization range D. 57171095Ssam * @ufc_d: Frame count for the utilization range D. 58171095Ssam * @timer_val_us: Interval of time, in microseconds, at which transmit timer 59171095Ssam * interrupt is to be generated. Note that unless @timer_ci_en 60171095Ssam * is set, the timer interrupt is generated only in presence 61171095Ssam * of the transmit traffic. Note also that timer interrupt 62171095Ssam * and utilization interrupt are two separate interrupt 63171095Ssam * sources. 64171095Ssam * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 65171095Ssam * interrupt was generated during the interval. 66171095Ssam * @timer_ci_en: Enable/disable continuous interrupt. Set this value 67171095Ssam * to 1 in order to generate continuous interrupt 68171095Ssam * at fixed @timer_val intervals of time, independently 69171095Ssam * of whether there is transmit traffic or not. 70171095Ssam * @enabled: Set to 1, if TTI feature is enabled. 71171095Ssam * 72171095Ssam * Xframe transmit interrupt configuration. 73171095Ssam * See Xframe User Guide, Section 3.5 "Device Interrupts" 74171095Ssam * for more details. Note also (min, max) 75171095Ssam * ranges in the body of the xge_hal_tx_intr_config_t structure. 76171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 77171095Ssam * the xge_hal_tti_config_t{} structure. Please refer to the 78171095Ssam * corresponding header file. 79171095Ssam */ 80171095Ssamtypedef struct xge_hal_tti_config_t { 81171095Ssam 82173139Srwatson int enabled; 83173139Srwatson#define XGE_HAL_TTI_ENABLE 1 84173139Srwatson#define XGE_HAL_TTI_DISABLE 0 85171095Ssam 86171095Ssam /* Line utilization interrupts */ 87171095Ssam 88173139Srwatson int urange_a; 89173139Srwatson#define XGE_HAL_MIN_TX_URANGE_A 0 90173139Srwatson#define XGE_HAL_MAX_TX_URANGE_A 100 91171095Ssam 92173139Srwatson int ufc_a; 93173139Srwatson#define XGE_HAL_MIN_TX_UFC_A 0 94173139Srwatson#define XGE_HAL_MAX_TX_UFC_A 65535 95171095Ssam 96173139Srwatson int urange_b; 97173139Srwatson#define XGE_HAL_MIN_TX_URANGE_B 0 98173139Srwatson#define XGE_HAL_MAX_TX_URANGE_B 100 99171095Ssam 100173139Srwatson int ufc_b; 101173139Srwatson#define XGE_HAL_MIN_TX_UFC_B 0 102173139Srwatson#define XGE_HAL_MAX_TX_UFC_B 65535 103171095Ssam 104173139Srwatson int urange_c; 105173139Srwatson#define XGE_HAL_MIN_TX_URANGE_C 0 106173139Srwatson#define XGE_HAL_MAX_TX_URANGE_C 100 107171095Ssam 108173139Srwatson int ufc_c; 109173139Srwatson#define XGE_HAL_MIN_TX_UFC_C 0 110173139Srwatson#define XGE_HAL_MAX_TX_UFC_C 65535 111171095Ssam 112173139Srwatson int ufc_d; 113173139Srwatson#define XGE_HAL_MIN_TX_UFC_D 0 114173139Srwatson#define XGE_HAL_MAX_TX_UFC_D 65535 115171095Ssam 116173139Srwatson int timer_val_us; 117173139Srwatson#define XGE_HAL_MIN_TX_TIMER_VAL 0 118173139Srwatson#define XGE_HAL_MAX_TX_TIMER_VAL 65535 119171095Ssam 120173139Srwatson int timer_ac_en; 121173139Srwatson#define XGE_HAL_MIN_TX_TIMER_AC_EN 0 122173139Srwatson#define XGE_HAL_MAX_TX_TIMER_AC_EN 1 123171095Ssam 124173139Srwatson int timer_ci_en; 125173139Srwatson#define XGE_HAL_MIN_TX_TIMER_CI_EN 0 126173139Srwatson#define XGE_HAL_MAX_TX_TIMER_CI_EN 1 127171095Ssam 128171095Ssam 129171095Ssam} xge_hal_tti_config_t; 130171095Ssam 131171095Ssam/** 132171095Ssam * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration. 133171095Ssam * @urange_a: Link utilization range A. The value from 0 to 100%. 134171095Ssam * @ufc_a: Frame count for the utilization range A. Interrupt will be generated 135171095Ssam * each time when (and only when) the line is utilized no more 136171095Ssam * than @urange_a percent inbound, 137171095Ssam * and number of received frames is greater or equal @ufc_a. 138171095Ssam * @urange_b: Link utilization range B. 139171095Ssam * @ufc_b: Frame count for the utilization range B. 140171095Ssam * @urange_c: Link utilization range C. 141171095Ssam * @ufc_c: Frame count for the utilization range C. 142171095Ssam * @urange_d: Link utilization range D. 143171095Ssam * @ufc_d: Frame count for the utilization range D. 144171095Ssam * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization 145171095Ssam * interrupt was generated during the interval. 146171095Ssam * @timer_val_us: Interval of time, in microseconds, at which receive timer 147171095Ssam * interrupt is to be generated. The timer interrupt is generated 148171095Ssam * only in presence of the inbound traffic. Note also that timer 149171095Ssam * interrupt and utilization interrupt are two separate interrupt 150171095Ssam * sources. 151171095Ssam * 152171095Ssam * Xframe receive interrupt configuration. 153171095Ssam * See Xframe User Guide, Section 3.5 "Device Interrupts" 154171095Ssam * for more details. Note also (min, max) 155171095Ssam * ranges in the body of the xge_hal_intr_config_t structure. 156171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 157171095Ssam * the xge_hal_rti_config_t{} structure. Please refer to the 158171095Ssam * corresponding header file. 159171095Ssam */ 160171095Ssamtypedef struct xge_hal_rti_config_t { 161171095Ssam 162173139Srwatson int urange_a; 163173139Srwatson#define XGE_HAL_MIN_RX_URANGE_A 0 164173139Srwatson#define XGE_HAL_MAX_RX_URANGE_A 127 165171095Ssam 166173139Srwatson int ufc_a; 167173139Srwatson#define XGE_HAL_MIN_RX_UFC_A 0 168173139Srwatson#define XGE_HAL_MAX_RX_UFC_A 65535 169171095Ssam 170173139Srwatson int urange_b; 171173139Srwatson#define XGE_HAL_MIN_RX_URANGE_B 0 172173139Srwatson#define XGE_HAL_MAX_RX_URANGE_B 127 173171095Ssam 174173139Srwatson int ufc_b; 175173139Srwatson#define XGE_HAL_MIN_RX_UFC_B 0 176173139Srwatson#define XGE_HAL_MAX_RX_UFC_B 65535 177171095Ssam 178173139Srwatson int urange_c; 179173139Srwatson#define XGE_HAL_MIN_RX_URANGE_C 0 180173139Srwatson#define XGE_HAL_MAX_RX_URANGE_C 127 181171095Ssam 182173139Srwatson int ufc_c; 183173139Srwatson#define XGE_HAL_MIN_RX_UFC_C 0 184173139Srwatson#define XGE_HAL_MAX_RX_UFC_C 65535 185171095Ssam 186173139Srwatson int ufc_d; 187173139Srwatson#define XGE_HAL_MIN_RX_UFC_D 0 188173139Srwatson#define XGE_HAL_MAX_RX_UFC_D 65535 189171095Ssam 190173139Srwatson int timer_ac_en; 191173139Srwatson#define XGE_HAL_MIN_RX_TIMER_AC_EN 0 192173139Srwatson#define XGE_HAL_MAX_RX_TIMER_AC_EN 1 193171095Ssam 194173139Srwatson int timer_val_us; 195173139Srwatson#define XGE_HAL_MIN_RX_TIMER_VAL 0 196173139Srwatson#define XGE_HAL_MAX_RX_TIMER_VAL 65535 197171095Ssam 198171095Ssam} xge_hal_rti_config_t; 199171095Ssam 200171095Ssam/** 201171095Ssam * struct xge_hal_fifo_queue_t - Single fifo configuration. 202171095Ssam * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue. 203171095Ssam * @initial: Initial numbers of TxDLs per queue (can grow up to @max). 204171095Ssam * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. 205171095Ssam * Use 0 otherwise. 206171095Ssam * @intr_vector: TBD 207171095Ssam * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 208171095Ssam * which generally improves latency of the host bridge operation 209171095Ssam * (see PCI specification). For valid values please refer 210171095Ssam * to xge_hal_fifo_queue_t{} in the driver sources. 211171095Ssam * @priority: TBD 212171095Ssam * @configured: Boolean. Use 1 to specify that the fifo is configured. 213171095Ssam * Only "configured" fifos can be activated and used to post 214171095Ssam * Tx descriptors. Any subset of 8 available fifos can be 215171095Ssam * "configured". 216171095Ssam * @tti: TBD 217171095Ssam * 218171095Ssam * Single fifo configuration. 219171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 220171095Ssam * the xge_hal_fifo_queue_t{} structure. Please refer to the 221171095Ssam * corresponding header file. 222171095Ssam * See also: xge_hal_fifo_config_t{} 223171095Ssam */ 224171095Ssamtypedef struct xge_hal_fifo_queue_t { 225173139Srwatson int max; 226173139Srwatson int initial; 227173139Srwatson#define XGE_HAL_MIN_FIFO_QUEUE_LENGTH 2 228173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_LENGTH 8192 229171095Ssam 230173139Srwatson int intr; 231173139Srwatson#define XGE_HAL_MIN_FIFO_QUEUE_INTR 0 232173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_INTR 1 233171095Ssam 234173139Srwatson int intr_vector; 235173139Srwatson#define XGE_HAL_MIN_FIFO_QUEUE_INTR_VECTOR 0 236173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_INTR_VECTOR 64 237171095Ssam 238173139Srwatson int no_snoop_bits; 239173139Srwatson#define XGE_HAL_MIN_FIFO_QUEUE_NO_SNOOP_DISABLED 0 240173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_TXD 1 241173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_BUFFER 2 242173139Srwatson#define XGE_HAL_MAX_FIFO_QUEUE_NO_SNOOP_ALL 3 243171095Ssam 244173139Srwatson int priority; 245173139Srwatson#define XGE_HAL_MIN_FIFO_PRIORITY 0 246173139Srwatson#define XGE_HAL_MAX_FIFO_PRIORITY 63 247171095Ssam 248173139Srwatson int configured; 249173139Srwatson#define XGE_HAL_MIN_FIFO_CONFIGURED 0 250173139Srwatson#define XGE_HAL_MAX_FIFO_CONFIGURED 1 251171095Ssam 252173139Srwatson#define XGE_HAL_MAX_FIFO_TTI_NUM 7 253173139Srwatson#define XGE_HAL_MAX_FIFO_TTI_RING_0 56 254173139Srwatson xge_hal_tti_config_t tti[XGE_HAL_MAX_FIFO_TTI_NUM]; 255171095Ssam 256171095Ssam} xge_hal_fifo_queue_t; 257171095Ssam 258171095Ssam/** 259171095Ssam * struct xge_hal_fifo_config_t - Configuration of all 8 fifos. 260171095Ssam * @max_frags: Max number of Tx buffers per TxDL (that is, per single 261171095Ssam * transmit operation). 262171095Ssam * No more than 256 transmit buffers can be specified. 263171095Ssam * @max_aligned_frags: Number of fragments to be aligned out of 264171095Ssam * maximum fragments (see @max_frags). 265171095Ssam * @reserve_threshold: Descriptor reservation threshold. 266171095Ssam * At least @reserve_threshold descriptors will remain 267171095Ssam * unallocated at all times. 268171095Ssam * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size 269171095Ssam * bytes. Setting @memblock_size to page size ensures 270171095Ssam * by-page allocation of descriptors. 128K bytes is the 271171095Ssam * maximum supported block size. 272171095Ssam * @queue: Array of per-fifo configurations. 273171095Ssam * @alignment_size: per Tx fragment DMA-able memory used to align transmit data 274171095Ssam * (e.g., to align on a cache line). 275171095Ssam * 276171095Ssam * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t 277171095Ssam * structures. 278171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 279171095Ssam * the xge_hal_fifo_config_t{} structure. Please refer to the 280171095Ssam * corresponding header file. 281171095Ssam * See also: xge_hal_ring_queue_t{}. 282171095Ssam */ 283171095Ssamtypedef struct xge_hal_fifo_config_t { 284173139Srwatson int max_frags; 285173139Srwatson#define XGE_HAL_MIN_FIFO_FRAGS 1 286173139Srwatson#define XGE_HAL_MAX_FIFO_FRAGS 256 287171095Ssam 288173139Srwatson int reserve_threshold; 289173139Srwatson#define XGE_HAL_MIN_FIFO_RESERVE_THRESHOLD 0 290173139Srwatson#define XGE_HAL_MAX_FIFO_RESERVE_THRESHOLD 8192 291171095Ssam 292173139Srwatson int memblock_size; 293173139Srwatson#define XGE_HAL_MIN_FIFO_MEMBLOCK_SIZE 4096 294173139Srwatson#define XGE_HAL_MAX_FIFO_MEMBLOCK_SIZE 131072 295171095Ssam 296173139Srwatson int alignment_size; 297173139Srwatson#define XGE_HAL_MIN_ALIGNMENT_SIZE 0 298173139Srwatson#define XGE_HAL_MAX_ALIGNMENT_SIZE 65536 299171095Ssam 300173139Srwatson int max_aligned_frags; 301171095Ssam /* range: (1, @max_frags) */ 302171095Ssam 303173139Srwatson#define XGE_HAL_MIN_FIFO_NUM 1 304173139Srwatson#define XGE_HAL_MAX_FIFO_NUM_HERC 8 305173139Srwatson#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 306173139Srwatson#define XGE_HAL_MAX_FIFO_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 307173139Srwatson xge_hal_fifo_queue_t queue[XGE_HAL_MAX_FIFO_NUM]; 308171095Ssam} xge_hal_fifo_config_t; 309171095Ssam 310171095Ssam/** 311171095Ssam * struct xge_hal_rts_port_t - RTS port entry 312171095Ssam * @num: Port number 313171095Ssam * @udp: Port is UDP (default TCP) 314171095Ssam * @src: Port is Source (default Destination) 315171095Ssam */ 316171095Ssamtypedef struct xge_hal_rts_port_t { 317173139Srwatson int num; 318173139Srwatson int udp; 319173139Srwatson int src; 320171095Ssam} xge_hal_rts_port_t; 321171095Ssam 322171095Ssam/** 323171095Ssam * struct xge_hal_ring_queue_t - Single ring configuration. 324171095Ssam * @max: Max numbers of RxD blocks per queue 325171095Ssam * @initial: Initial numbers of RxD blocks per queue 326171095Ssam * (can grow up to @max) 327171095Ssam * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer 328171095Ssam * to Xframe User Guide. 329171095Ssam * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring. 330171095Ssam * Note that 64MB of available 331171095Ssam * on-board DRAM is shared between receive rings. 332171095Ssam * If a single ring is used, @dram_size_mb can be set to 64. 333171095Ssam * Sum of all rings' @dram_size_mb cannot exceed 64. 334171095Ssam * @intr_vector: TBD 335171095Ssam * @backoff_interval_us: Time (in microseconds), after which Xframe 336171095Ssam * tries to download RxDs posted by the host. 337171095Ssam * Note that the "backoff" does not happen if host posts receive 338171095Ssam * descriptors in the timely fashion. 339171095Ssam * @max_frm_len: Maximum frame length that can be received on _that_ ring. 340171095Ssam * Setting this field to -1 ensures that the ring will 341171095Ssam * "accept" MTU-size frames (note that MTU can be changed at 342171095Ssam * runtime). 343171095Ssam * Any value other than (-1) specifies a certain "hard" 344171095Ssam * limit on the receive frame sizes. 345171095Ssam * The field can be used to activate receive frame-length based 346171095Ssam * steering. 347171095Ssam * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used 348171095Ssam * to give prioritized access to PCI-X. See Xframe documentation 349171095Ssam * for details. 350171095Ssam * @rth_en: Enable Receive Traffic Hashing (RTH). 351171095Ssam * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, 352171095Ssam * which generally improves latency of the host bridge operation 353171095Ssam * (see PCI specification). For valid values please refer 354171095Ssam * to xge_hal_ring_queue_t{} in the driver sources. 355171095Ssam * @indicate_max_pkts: Sets maximum number of received frames to be processed 356171095Ssam * within single interrupt. 357171095Ssam * @configured: Boolean. Use 1 to specify that the ring is configured. 358171095Ssam * Only "configured" rings can be activated and used to post 359171095Ssam * Rx descriptors. Any subset of 8 available rings can be 360171095Ssam * "configured". 361171095Ssam * @rts_mac_en: 1 - To enable Receive MAC address steering. 362173139Srwatson * 0 - To disable Receive MAC address steering. 363171095Ssam * @rth_en: TBD 364171095Ssam * @rts_port_en: TBD 365171095Ssam * @rts_ports: TBD 366171095Ssam * @rti: Xframe receive interrupt configuration. 367171095Ssam * 368171095Ssam * Single ring configuration. 369171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 370171095Ssam * the xge_hal_ring_queue_t{} structure. Please refer to the 371171095Ssam * corresponding header file. 372171095Ssam * See also: xge_hal_fifo_config_t{}. 373171095Ssam */ 374171095Ssamtypedef struct xge_hal_ring_queue_t { 375173139Srwatson int max; 376173139Srwatson int initial; 377173139Srwatson#define XGE_HAL_MIN_RING_QUEUE_BLOCKS 1 378173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_BLOCKS 64 379171095Ssam 380173139Srwatson int buffer_mode; 381173139Srwatson#define XGE_HAL_RING_QUEUE_BUFFER_MODE_1 1 382173139Srwatson#define XGE_HAL_RING_QUEUE_BUFFER_MODE_2 2 383173139Srwatson#define XGE_HAL_RING_QUEUE_BUFFER_MODE_3 3 384173139Srwatson#define XGE_HAL_RING_QUEUE_BUFFER_MODE_5 5 385171095Ssam 386173139Srwatson int dram_size_mb; 387173139Srwatson#define XGE_HAL_MIN_RING_QUEUE_SIZE 0 388173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_SIZE_XENA 64 389173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_SIZE_HERC 32 390171095Ssam 391173139Srwatson int intr_vector; 392173139Srwatson#define XGE_HAL_MIN_RING_QUEUE_INTR_VECTOR 0 393173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_INTR_VECTOR 64 394171095Ssam 395173139Srwatson int backoff_interval_us; 396173139Srwatson#define XGE_HAL_MIN_BACKOFF_INTERVAL_US 1 397173139Srwatson#define XGE_HAL_MAX_BACKOFF_INTERVAL_US 125000 398171095Ssam 399173139Srwatson int max_frm_len; 400173139Srwatson#define XGE_HAL_MIN_MAX_FRM_LEN -1 401173139Srwatson#define XGE_HAL_MAX_MAX_FRM_LEN 9622 402171095Ssam 403173139Srwatson int priority; 404173139Srwatson#define XGE_HAL_MIN_RING_PRIORITY 0 405173139Srwatson#define XGE_HAL_MAX_RING_PRIORITY 7 406171095Ssam 407173139Srwatson int no_snoop_bits; 408173139Srwatson#define XGE_HAL_MIN_RING_QUEUE_NO_SNOOP_DISABLED 0 409173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_RXD 1 410173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_BUFFER 2 411173139Srwatson#define XGE_HAL_MAX_RING_QUEUE_NO_SNOOP_ALL 3 412171095Ssam 413173139Srwatson int indicate_max_pkts; 414173139Srwatson#define XGE_HAL_MIN_RING_INDICATE_MAX_PKTS 1 415173139Srwatson#define XGE_HAL_MAX_RING_INDICATE_MAX_PKTS 65536 416171095Ssam 417173139Srwatson int configured; 418173139Srwatson#define XGE_HAL_MIN_RING_CONFIGURED 0 419173139Srwatson#define XGE_HAL_MAX_RING_CONFIGURED 1 420171095Ssam 421173139Srwatson int rts_mac_en; 422173139Srwatson#define XGE_HAL_MIN_RING_RTS_MAC_EN 0 423173139Srwatson#define XGE_HAL_MAX_RING_RTS_MAC_EN 1 424171095Ssam 425173139Srwatson int rth_en; 426173139Srwatson#define XGE_HAL_MIN_RING_RTH_EN 0 427173139Srwatson#define XGE_HAL_MAX_RING_RTH_EN 1 428171095Ssam 429173139Srwatson int rts_port_en; 430173139Srwatson#define XGE_HAL_MIN_RING_RTS_PORT_EN 0 431173139Srwatson#define XGE_HAL_MAX_RING_RTS_PORT_EN 1 432171095Ssam 433173139Srwatson#define XGE_HAL_MAX_STEERABLE_PORTS 32 434173139Srwatson xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS]; 435171095Ssam 436173139Srwatson xge_hal_rti_config_t rti; 437171095Ssam 438171095Ssam} xge_hal_ring_queue_t; 439171095Ssam 440171095Ssam/** 441171095Ssam * struct xge_hal_ring_config_t - Array of ring configurations. 442171095Ssam * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size 443171095Ssam * bytes. Setting @memblock_size to page size ensures 444171095Ssam * by-page allocation of descriptors. 128K bytes is the 445171095Ssam * upper limit. 446171095Ssam * @scatter_mode: Xframe supports two receive scatter modes: A and B. 447171095Ssam * For details please refer to Xframe User Guide. 448171095Ssam * @strip_vlan_tag: TBD 449171095Ssam * @queue: Array of all Xframe ring configurations. 450171095Ssam * 451171095Ssam * Array of ring configurations. 452171095Ssam * See also: xge_hal_ring_queue_t{}. 453171095Ssam */ 454171095Ssamtypedef struct xge_hal_ring_config_t { 455171095Ssam 456173139Srwatson int memblock_size; 457173139Srwatson#define XGE_HAL_MIN_RING_MEMBLOCK_SIZE 4096 458173139Srwatson#define XGE_HAL_MAX_RING_MEMBLOCK_SIZE 131072 459171095Ssam 460173139Srwatson int scatter_mode; 461173139Srwatson#define XGE_HAL_RING_QUEUE_SCATTER_MODE_A 0 462173139Srwatson#define XGE_HAL_RING_QUEUE_SCATTER_MODE_B 1 463171095Ssam 464173139Srwatson int strip_vlan_tag; 465173139Srwatson#define XGE_HAL_RING_DONOT_STRIP_VLAN_TAG 0 466173139Srwatson#define XGE_HAL_RING_STRIP_VLAN_TAG 1 467171095Ssam 468173139Srwatson#define XGE_HAL_MIN_RING_NUM 1 469173139Srwatson#define XGE_HAL_MAX_RING_NUM_HERC 8 470173139Srwatson#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1) 471173139Srwatson#define XGE_HAL_MAX_RING_NUM (XGE_HAL_MAX_VIRTUAL_PATHS) 472173139Srwatson xge_hal_ring_queue_t queue[XGE_HAL_MAX_RING_NUM]; 473171095Ssam 474171095Ssam} xge_hal_ring_config_t; 475171095Ssam 476171095Ssam/** 477171095Ssam * struct xge_hal_mac_config_t - MAC configuration. 478171095Ssam * @media: Transponder type. 479171095Ssam * @tmac_util_period: The sampling period over which the transmit utilization 480171095Ssam * is calculated. 481171095Ssam * @rmac_util_period: The sampling period over which the receive utilization 482171095Ssam * is calculated. 483171095Ssam * @rmac_strip_pad: Determines whether padding of received frames is removed by 484171095Ssam * the MAC or sent to the host. 485171095Ssam * @rmac_bcast_en: Enable frames containing broadcast address to be 486171095Ssam * passed to the host. 487171095Ssam * @rmac_pause_gen_en: Received pause generation enable. 488171095Ssam * @rmac_pause_rcv_en: Receive pause enable. 489171095Ssam * @rmac_pause_time: The value to be inserted in outgoing pause frames. 490171095Ssam * Has units of pause quanta (one pause quanta = 512 bit times). 491171095Ssam * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation 492171095Ssam * for queues 0 through 3. The threshold value indicates portion of the 493171095Ssam * individual receive buffer queue size. Thresholds have a range of 0 to 494171095Ssam * 255, allowing 256 possible watermarks in a queue. 495171095Ssam * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation 496171095Ssam * for queues 4 through 7. The threshold value indicates portion of the 497171095Ssam * individual receive buffer queue size. Thresholds have a range of 0 to 498171095Ssam * 255, allowing 256 possible watermarks in a queue. 499171095Ssam * 500171095Ssam * MAC configuration. This includes various aspects of configuration, including: 501171095Ssam * - Pause frame threshold; 502171095Ssam * - sampling rate to calculate link utilization; 503171095Ssam * - enabling/disabling broadcasts. 504171095Ssam * 505171095Ssam * See Xframe User Guide for more details. 506171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 507171095Ssam * the xge_hal_mac_config_t{} structure. Please refer to the 508171095Ssam * corresponding include file. 509171095Ssam */ 510171095Ssamtypedef struct xge_hal_mac_config_t { 511173139Srwatson int media; 512173139Srwatson#define XGE_HAL_MIN_MEDIA 0 513173139Srwatson#define XGE_HAL_MEDIA_SR 0 514173139Srwatson#define XGE_HAL_MEDIA_SW 1 515173139Srwatson#define XGE_HAL_MEDIA_LR 2 516173139Srwatson#define XGE_HAL_MEDIA_LW 3 517173139Srwatson#define XGE_HAL_MEDIA_ER 4 518173139Srwatson#define XGE_HAL_MEDIA_EW 5 519173139Srwatson#define XGE_HAL_MAX_MEDIA 5 520171095Ssam 521173139Srwatson int tmac_util_period; 522173139Srwatson#define XGE_HAL_MIN_TMAC_UTIL_PERIOD 0 523173139Srwatson#define XGE_HAL_MAX_TMAC_UTIL_PERIOD 15 524171095Ssam 525173139Srwatson int rmac_util_period; 526173139Srwatson#define XGE_HAL_MIN_RMAC_UTIL_PERIOD 0 527173139Srwatson#define XGE_HAL_MAX_RMAC_UTIL_PERIOD 15 528171095Ssam 529173139Srwatson int rmac_bcast_en; 530173139Srwatson#define XGE_HAL_MIN_RMAC_BCAST_EN 0 531173139Srwatson#define XGE_HAL_MAX_RMAC_BCAST_EN 1 532171095Ssam 533173139Srwatson int rmac_pause_gen_en; 534173139Srwatson#define XGE_HAL_MIN_RMAC_PAUSE_GEN_EN 0 535173139Srwatson#define XGE_HAL_MAX_RMAC_PAUSE_GEN_EN 1 536171095Ssam 537173139Srwatson int rmac_pause_rcv_en; 538173139Srwatson#define XGE_HAL_MIN_RMAC_PAUSE_RCV_EN 0 539173139Srwatson#define XGE_HAL_MAX_RMAC_PAUSE_RCV_EN 1 540171095Ssam 541173139Srwatson int rmac_pause_time; 542173139Srwatson#define XGE_HAL_MIN_RMAC_HIGH_PTIME 16 543173139Srwatson#define XGE_HAL_MAX_RMAC_HIGH_PTIME 65535 544171095Ssam 545173139Srwatson int mc_pause_threshold_q0q3; 546173139Srwatson#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q0Q3 0 547173139Srwatson#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q0Q3 254 548171095Ssam 549173139Srwatson int mc_pause_threshold_q4q7; 550173139Srwatson#define XGE_HAL_MIN_MC_PAUSE_THRESHOLD_Q4Q7 0 551173139Srwatson#define XGE_HAL_MAX_MC_PAUSE_THRESHOLD_Q4Q7 254 552171095Ssam 553171095Ssam} xge_hal_mac_config_t; 554171095Ssam 555171095Ssam/** 556171095Ssam * struct xge_hal_device_config_t - Device configuration. 557171095Ssam * @mtu: Current mtu size. 558171095Ssam * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx 559171095Ssam * completions. Used in xge_hal_device_handle_irq(). 560171095Ssam * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance 561171095Ssam * with the PCI Specification, the value of the Latency Timer 562171095Ssam * for this PCI bus master. 563171095Ssam * Specify either zero or -1 to use BIOS default. 564171095Ssam * @napi_weight: (TODO) 565171095Ssam * @max_splits_trans: Maximum number of PCI-X split transactions. 566171095Ssam * Specify (-1) to use BIOS default. 567171095Ssam * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default 568171095Ssam * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B; 569171095Ssam * 1 - 1KB, 2 - 2KB, and 3 - 4KB. 570171095Ssam * @shared_splits: The number of Outstanding Split Transactions that is 571171095Ssam * shared by Tx and Rx requests. The device stops issuing Tx 572171095Ssam * requests once the number of Outstanding Split Transactions is 573171095Ssam * equal to the value of Shared_Splits. 574171095Ssam * A value of zero indicates that the Tx and Rx share all allocated 575171095Ssam * Split Requests, i.e. the device can issue both types (Tx and Rx) 576171095Ssam * of read requests until the number of Maximum Outstanding Split 577171095Ssam * Transactions is reached. 578171095Ssam * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer 579171095Ssam * to the host. This includes MAC stats as well as PCI stats. 580171095Ssam * See xge_hal_stats_hw_info_t{}. 581171095Ssam * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz. 582171095Ssam * @intr_mode: Line, MSI, or MSI-X interrupt. 583171095Ssam * @sched_timer_us: If greater than zero, specifies time interval 584171095Ssam * (in microseconds) for the device to generate 585171095Ssam * interrupt. Note that unlike tti and rti interrupts, 586171095Ssam * the scheduled interrupt is generated independently of 587171095Ssam * whether there is transmit or receive traffic, respectively. 588171095Ssam * @sched_timer_one_shot: 1 - generate scheduled interrupt only once. 589171095Ssam * 0 - generate scheduled interrupt periodically at the specified 590171095Ssam * @sched_timer_us interval. 591171095Ssam * 592171095Ssam * @ring: See xge_hal_ring_config_t{}. 593171095Ssam * @mac: See xge_hal_mac_config_t{}. 594171095Ssam * @tti: See xge_hal_tti_config_t{}. 595171095Ssam * @fifo: See xge_hal_fifo_config_t{}. 596171095Ssam * 597171095Ssam * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#. 598171095Ssam * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on 599171095Ssam * ECC error. 600171095Ssam * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on 601171095Ssam * parity error. 602171095Ssam * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). 603171095Ssam * @rth_bucket_size: RTH bucket width (in bits). For valid range please see 604171095Ssam * xge_hal_device_config_t{} in the driver sources. 605171095Ssam * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair 606173139Srwatson * Direct Match). 607171095Ssam * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of 608173139Srwatson * hash value in the RTH SPDM based steering. 609171095Ssam * @rxufca_intr_thres: (TODO) 610171095Ssam * @rxufca_lo_lim: (TODO) 611171095Ssam * @rxufca_hi_lim: (TODO) 612171095Ssam * @rxufca_lbolt_period: (TODO) 613171095Ssam * @link_valid_cnt: link-valid counting is done only at device-open time, 614171095Ssam * to determine with the specified certainty that the link is up. See also 615171095Ssam * @link_retry_cnt. 616171095Ssam * @link_retry_cnt: Max number of polls for link-up. Done only at device 617171095Ssam * open time. Reducing this value as well as the previous @link_valid_cnt, 618171095Ssam * speeds up device startup, which may be important if the driver 619171095Ssam * is compiled into OS. 620171095Ssam * @link_stability_period: Specify the period for which the link must be 621171095Ssam * stable in order for the adapter to declare "LINK UP". 622171095Ssam * The enumerated settings (see Xframe-II UG) are: 623171095Ssam * 0 ........... instantaneous 624230134Suqs * 1 ........... 500 ��s 625171095Ssam * 2 ........... 1 ms 626171095Ssam * 3 ........... 64 ms 627171095Ssam * 4 ........... 256 ms 628171095Ssam * 5 ........... 512 ms 629171095Ssam * 6 ........... 1 s 630171095Ssam * 7 ........... 2 s 631171095Ssam * @device_poll_millis: Specify the interval (in mulliseconds) between 632171095Ssam * successive xge_hal_device_poll() runs. 633171095Ssam * stable in order for the adapter to declare "LINK UP". 634171095Ssam * @no_isr_events: TBD 635171095Ssam * @lro_sg_size: TBD 636171095Ssam * @lro_frm_len: TBD 637171095Ssam * @bimodal_interrupts: Enable bimodal interrupts in device 638171095Ssam * @bimodal_timer_lo_us: TBD 639171095Ssam * @bimodal_timer_hi_us: TBD 640171095Ssam * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address 641171095Ssam * @rts_qos_en: TBD 642171095Ssam * @rts_port_en: TBD 643171095Ssam * @vp_config: Configuration for virtual paths 644171095Ssam * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ 645171095Ssam * can own at any one time. 646171095Ssam * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that 647171095Ssam * this S-RQ can own at any one time. 648171095Ssam * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for 649171095Ssam * WQEs before generating a message or interrupt. 650171095Ssam * @refill_threshold_high:This field provides a hysteresis upper bound for 651171095Ssam * automatic adapter refill operations. 652171095Ssam * @refill_threshold_low:This field provides a hysteresis lower bound for 653171095Ssam * automatic adapter refill operations. 654173139Srwatson * @eol_policy:This field sets the policy for handling the end of list condition. 655173139Srwatson * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0. 656173139Srwatson * 2'b01 - Send UMQ message when EOL is reached. 657171095Ssam * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message 658171095Ssam * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for 659171095Ssam * a non-zero block wrapper before giving up and sending a UMQ message 660171095Ssam * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held 661171095Ssam * by a session at any one time. 662171095Ssam * @poll_or_doorbell: TBD 663171095Ssam * 664171095Ssam * Xframe configuration. 665171095Ssam * Contains per-device configuration parameters, including: 666171095Ssam * - latency timer (settable via PCI configuration space); 667171095Ssam * - maximum number of split transactions; 668171095Ssam * - maximum number of shared splits; 669171095Ssam * - stats sampling interval, etc. 670171095Ssam * 671171095Ssam * In addition, xge_hal_device_config_t{} includes "subordinate" 672171095Ssam * configurations, including: 673171095Ssam * - fifos and rings; 674171095Ssam * - MAC (see xge_hal_mac_config_t{}). 675171095Ssam * 676171095Ssam * See Xframe User Guide for more details. 677171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 678171095Ssam * the xge_hal_device_config_t{} structure. Please refer to the 679171095Ssam * corresponding include file. 680171095Ssam * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{}, 681171095Ssam * xge_hal_mac_config_t{}. 682171095Ssam */ 683171095Ssamtypedef struct xge_hal_device_config_t { 684173139Srwatson int mtu; 685173139Srwatson#define XGE_HAL_MIN_INITIAL_MTU XGE_HAL_MIN_MTU 686173139Srwatson#define XGE_HAL_MAX_INITIAL_MTU XGE_HAL_MAX_MTU 687171095Ssam 688173139Srwatson int isr_polling_cnt; 689173139Srwatson#define XGE_HAL_MIN_ISR_POLLING_CNT 0 690173139Srwatson#define XGE_HAL_MAX_ISR_POLLING_CNT 65536 691171095Ssam 692173139Srwatson int latency_timer; 693173139Srwatson#define XGE_HAL_USE_BIOS_DEFAULT_LATENCY -1 694173139Srwatson#define XGE_HAL_MIN_LATENCY_TIMER 8 695173139Srwatson#define XGE_HAL_MAX_LATENCY_TIMER 255 696171095Ssam 697173139Srwatson int napi_weight; 698173139Srwatson#define XGE_HAL_DEF_NAPI_WEIGHT 64 699171095Ssam 700173139Srwatson int max_splits_trans; 701173139Srwatson#define XGE_HAL_USE_BIOS_DEFAULT_SPLITS -1 702173139Srwatson#define XGE_HAL_ONE_SPLIT_TRANSACTION 0 703173139Srwatson#define XGE_HAL_TWO_SPLIT_TRANSACTION 1 704173139Srwatson#define XGE_HAL_THREE_SPLIT_TRANSACTION 2 705173139Srwatson#define XGE_HAL_FOUR_SPLIT_TRANSACTION 3 706173139Srwatson#define XGE_HAL_EIGHT_SPLIT_TRANSACTION 4 707173139Srwatson#define XGE_HAL_TWELVE_SPLIT_TRANSACTION 5 708173139Srwatson#define XGE_HAL_SIXTEEN_SPLIT_TRANSACTION 6 709173139Srwatson#define XGE_HAL_THIRTYTWO_SPLIT_TRANSACTION 7 710171095Ssam 711173139Srwatson int mmrb_count; 712173139Srwatson#define XGE_HAL_DEFAULT_BIOS_MMRB_COUNT -1 713173139Srwatson#define XGE_HAL_MIN_MMRB_COUNT 0 /* 512b */ 714173139Srwatson#define XGE_HAL_MAX_MMRB_COUNT 3 /* 4k */ 715171095Ssam 716173139Srwatson int shared_splits; 717173139Srwatson#define XGE_HAL_MIN_SHARED_SPLITS 0 718173139Srwatson#define XGE_HAL_MAX_SHARED_SPLITS 31 719171095Ssam 720173139Srwatson int stats_refresh_time_sec; 721173139Srwatson#define XGE_HAL_STATS_REFRESH_DISABLE 0 722173139Srwatson#define XGE_HAL_MIN_STATS_REFRESH_TIME 1 723173139Srwatson#define XGE_HAL_MAX_STATS_REFRESH_TIME 300 724171095Ssam 725173139Srwatson int pci_freq_mherz; 726173139Srwatson#define XGE_HAL_PCI_FREQ_MHERZ_33 33 727173139Srwatson#define XGE_HAL_PCI_FREQ_MHERZ_66 66 728173139Srwatson#define XGE_HAL_PCI_FREQ_MHERZ_100 100 729173139Srwatson#define XGE_HAL_PCI_FREQ_MHERZ_133 133 730173139Srwatson#define XGE_HAL_PCI_FREQ_MHERZ_266 266 731171095Ssam 732173139Srwatson int intr_mode; 733173139Srwatson#define XGE_HAL_INTR_MODE_IRQLINE 0 734173139Srwatson#define XGE_HAL_INTR_MODE_MSI 1 735173139Srwatson#define XGE_HAL_INTR_MODE_MSIX 2 736171095Ssam 737173139Srwatson int sched_timer_us; 738173139Srwatson#define XGE_HAL_SCHED_TIMER_DISABLED 0 739173139Srwatson#define XGE_HAL_SCHED_TIMER_MIN 0 740173139Srwatson#define XGE_HAL_SCHED_TIMER_MAX 0xFFFFF 741171095Ssam 742173139Srwatson int sched_timer_one_shot; 743173139Srwatson#define XGE_HAL_SCHED_TIMER_ON_SHOT_DISABLE 0 744173139Srwatson#define XGE_HAL_SCHED_TIMER_ON_SHOT_ENABLE 1 745171095Ssam 746173139Srwatson xge_hal_ring_config_t ring; 747173139Srwatson xge_hal_mac_config_t mac; 748173139Srwatson xge_hal_fifo_config_t fifo; 749171095Ssam 750173139Srwatson int dump_on_serr; 751173139Srwatson#define XGE_HAL_DUMP_ON_SERR_DISABLE 0 752173139Srwatson#define XGE_HAL_DUMP_ON_SERR_ENABLE 1 753171095Ssam 754173139Srwatson int dump_on_eccerr; 755173139Srwatson#define XGE_HAL_DUMP_ON_ECCERR_DISABLE 0 756173139Srwatson#define XGE_HAL_DUMP_ON_ECCERR_ENABLE 1 757171095Ssam 758173139Srwatson int dump_on_parityerr; 759173139Srwatson#define XGE_HAL_DUMP_ON_PARITYERR_DISABLE 0 760173139Srwatson#define XGE_HAL_DUMP_ON_PARITYERR_ENABLE 1 761171095Ssam 762173139Srwatson int rth_en; 763173139Srwatson#define XGE_HAL_RTH_DISABLE 0 764173139Srwatson#define XGE_HAL_RTH_ENABLE 1 765171095Ssam 766173139Srwatson int rth_bucket_size; 767173139Srwatson#define XGE_HAL_MIN_RTH_BUCKET_SIZE 1 768173139Srwatson#define XGE_HAL_MAX_RTH_BUCKET_SIZE 8 769171095Ssam 770173139Srwatson int rth_spdm_en; 771173139Srwatson#define XGE_HAL_RTH_SPDM_DISABLE 0 772173139Srwatson#define XGE_HAL_RTH_SPDM_ENABLE 1 773171095Ssam 774173139Srwatson int rth_spdm_use_l4; 775173139Srwatson#define XGE_HAL_RTH_SPDM_USE_L4 1 776171095Ssam 777173139Srwatson int rxufca_intr_thres; 778173139Srwatson#define XGE_HAL_RXUFCA_INTR_THRES_MIN 1 779173139Srwatson#define XGE_HAL_RXUFCA_INTR_THRES_MAX 4096 780171095Ssam 781173139Srwatson int rxufca_lo_lim; 782173139Srwatson#define XGE_HAL_RXUFCA_LO_LIM_MIN 1 783173139Srwatson#define XGE_HAL_RXUFCA_LO_LIM_MAX 16 784171095Ssam 785173139Srwatson int rxufca_hi_lim; 786173139Srwatson#define XGE_HAL_RXUFCA_HI_LIM_MIN 1 787173139Srwatson#define XGE_HAL_RXUFCA_HI_LIM_MAX 256 788171095Ssam 789173139Srwatson int rxufca_lbolt_period; 790173139Srwatson#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MIN 1 791173139Srwatson#define XGE_HAL_RXUFCA_LBOLT_PERIOD_MAX 1024 792171095Ssam 793173139Srwatson int link_valid_cnt; 794173139Srwatson#define XGE_HAL_LINK_VALID_CNT_MIN 0 795173139Srwatson#define XGE_HAL_LINK_VALID_CNT_MAX 127 796171095Ssam 797173139Srwatson int link_retry_cnt; 798173139Srwatson#define XGE_HAL_LINK_RETRY_CNT_MIN 0 799173139Srwatson#define XGE_HAL_LINK_RETRY_CNT_MAX 127 800171095Ssam 801173139Srwatson int link_stability_period; 802173139Srwatson#define XGE_HAL_DEFAULT_LINK_STABILITY_PERIOD 2 /* 1ms */ 803173139Srwatson#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */ 804173139Srwatson#define XGE_HAL_MAX_LINK_STABILITY_PERIOD 7 /* 2s */ 805171095Ssam 806173139Srwatson int device_poll_millis; 807173139Srwatson#define XGE_HAL_DEFAULT_DEVICE_POLL_MILLIS 1000 808173139Srwatson#define XGE_HAL_MIN_DEVICE_POLL_MILLIS 1 809173139Srwatson#define XGE_HAL_MAX_DEVICE_POLL_MILLIS 100000 810171095Ssam 811173139Srwatson int no_isr_events; 812173139Srwatson#define XGE_HAL_NO_ISR_EVENTS_MIN 0 813173139Srwatson#define XGE_HAL_NO_ISR_EVENTS_MAX 1 814171095Ssam 815173139Srwatson int lro_sg_size; 816173139Srwatson#define XGE_HAL_LRO_DEFAULT_SG_SIZE 10 817173139Srwatson#define XGE_HAL_LRO_MIN_SG_SIZE 1 818173139Srwatson#define XGE_HAL_LRO_MAX_SG_SIZE 64 819171095Ssam 820173139Srwatson int lro_frm_len; 821173139Srwatson#define XGE_HAL_LRO_DEFAULT_FRM_LEN 65536 822173139Srwatson#define XGE_HAL_LRO_MIN_FRM_LEN 4096 823173139Srwatson#define XGE_HAL_LRO_MAX_FRM_LEN 65536 824171095Ssam 825173139Srwatson int bimodal_interrupts; 826173139Srwatson#define XGE_HAL_BIMODAL_INTR_MIN -1 827173139Srwatson#define XGE_HAL_BIMODAL_INTR_MAX 1 828171095Ssam 829173139Srwatson int bimodal_timer_lo_us; 830173139Srwatson#define XGE_HAL_BIMODAL_TIMER_LO_US_MIN 1 831173139Srwatson#define XGE_HAL_BIMODAL_TIMER_LO_US_MAX 127 832171095Ssam 833173139Srwatson int bimodal_timer_hi_us; 834173139Srwatson#define XGE_HAL_BIMODAL_TIMER_HI_US_MIN 128 835173139Srwatson#define XGE_HAL_BIMODAL_TIMER_HI_US_MAX 65535 836171095Ssam 837173139Srwatson int rts_mac_en; 838173139Srwatson#define XGE_HAL_RTS_MAC_DISABLE 0 839173139Srwatson#define XGE_HAL_RTS_MAC_ENABLE 1 840171095Ssam 841173139Srwatson int rts_qos_en; 842173139Srwatson#define XGE_HAL_RTS_QOS_DISABLE 0 843173139Srwatson#define XGE_HAL_RTS_QOS_ENABLE 1 844171095Ssam 845173139Srwatson int rts_port_en; 846173139Srwatson#define XGE_HAL_RTS_PORT_DISABLE 0 847173139Srwatson#define XGE_HAL_RTS_PORT_ENABLE 1 848171095Ssam 849171095Ssam} xge_hal_device_config_t; 850171095Ssam 851171095Ssam/** 852171095Ssam * struct xge_hal_driver_config_t - HAL (layer) configuration. 853171095Ssam * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to 854171095Ssam * periodically poll HAL, i.e, invoke 855171095Ssam * xge_hal_device_poll(). 856171095Ssam * Note that HAL does not maintain its own 857171095Ssam * polling context. HAL relies on ULD to 858171095Ssam * provide one. 859171095Ssam * @queue_size_initial: Initial size of the HAL protected event queue. 860171095Ssam * The queue is shared by HAL and upper-layer drivers. 861171095Ssam * The queue is used to exchange and process slow-path 862171095Ssam * events. See xge_hal_event_e. 863171095Ssam * @queue_size_max: Maximum size of the HAL queue. Depending on the load, 864171095Ssam * the queue may grow at run-time up to @queue_max_size. 865171095Ssam * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable. 866171095Ssam * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple) 867171095Ssam * HAL devices.) 868171095Ssam * Currently this structure contains just a few basic values. 869171095Ssam * Note: Valid (min, max) range for each attribute is specified in the body of 870171095Ssam * the structure. Please refer to the corresponding header file. 871171095Ssam * See also: xge_hal_device_poll() 872171095Ssam */ 873171095Ssamtypedef struct xge_hal_driver_config_t { 874173139Srwatson int queue_size_initial; 875173139Srwatson#define XGE_HAL_MIN_QUEUE_SIZE_INITIAL 1 876173139Srwatson#define XGE_HAL_MAX_QUEUE_SIZE_INITIAL 16 877171095Ssam 878173139Srwatson int queue_size_max; 879173139Srwatson#define XGE_HAL_MIN_QUEUE_SIZE_MAX 1 880173139Srwatson#define XGE_HAL_MAX_QUEUE_SIZE_MAX 16 881171095Ssam 882171095Ssam#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 883173139Srwatson int tracebuf_size; 884173139Srwatson#define XGE_HAL_MIN_CIRCULAR_ARR 4096 885173139Srwatson#define XGE_HAL_MAX_CIRCULAR_ARR 1048576 886173139Srwatson#define XGE_HAL_DEF_CIRCULAR_ARR XGE_OS_HOST_PAGE_SIZE 887171095Ssam 888173139Srwatson int tracebuf_timestamp_en; 889173139Srwatson#define XGE_HAL_MIN_TIMESTAMP_EN 0 890173139Srwatson#define XGE_HAL_MAX_TIMESTAMP_EN 1 891171095Ssam#endif 892171095Ssam 893171095Ssam} xge_hal_driver_config_t; 894171095Ssam 895171095Ssam 896171095Ssam/* ========================== PRIVATE API ================================= */ 897171095Ssam 898171095Ssamxge_hal_status_e 899171095Ssam__hal_device_config_check_common (xge_hal_device_config_t *new_config); 900171095Ssam 901171095Ssamxge_hal_status_e 902171095Ssam__hal_device_config_check_xena (xge_hal_device_config_t *new_config); 903171095Ssam 904171095Ssamxge_hal_status_e 905171095Ssam__hal_device_config_check_herc (xge_hal_device_config_t *new_config); 906171095Ssam 907171095Ssamxge_hal_status_e 908171095Ssam__hal_driver_config_check (xge_hal_driver_config_t *new_config); 909171095Ssam 910171095Ssam__EXTERN_END_DECLS 911171095Ssam 912171095Ssam#endif /* XGE_HAL_CONFIG_H */ 913