1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef _IF_XGE_H 30171095Ssam#define _IF_XGE_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xgehal.h> 33171095Ssam#include <dev/nxge/xge-osdep.h> 34171095Ssam 35171095Ssam/* Printing description, Copyright */ 36173139Srwatson#define XGE_DRIVER_VERSION \ 37173139Srwatson XGELL_VERSION_MAJOR"."XGELL_VERSION_MINOR"." \ 38173139Srwatson XGELL_VERSION_FIX"."XGELL_VERSION_BUILD 39173139Srwatson#define XGE_COPYRIGHT "Copyright(c) 2002-2007 Neterion Inc." 40171095Ssam 41171095Ssam/* Printing */ 42171095Ssam#define xge_trace(trace, fmt, args...) xge_debug_ll(trace, fmt, ## args); 43171095Ssam 44173139Srwatson#define XGE_ALIGN_TO(buffer_length, to) { \ 45173139Srwatson if((buffer_length % to) != 0) { \ 46173139Srwatson buffer_length += (to - (buffer_length % to)); \ 47173139Srwatson } \ 48173139Srwatson} 49171095Ssam 50173139Srwatson#define XGE_EXIT_ON_ERR(text, label, return_value) { \ 51173139Srwatson xge_trace(XGE_ERR, "%s (Status: %d)", text, return_value); \ 52173139Srwatson status = return_value; \ 53173139Srwatson goto label; \ 54171095Ssam} 55171095Ssam 56173139Srwatson#define XGE_SET_BUFFER_MODE_IN_RINGS(mode) { \ 57173139Srwatson for(index = 0; index < XGE_RING_COUNT; index++) \ 58173139Srwatson ring_config->queue[index].buffer_mode = mode; \ 59173139Srwatson} 60173139Srwatson 61171095Ssam#define XGE_DEFAULT_USER_HARDCODED -1 62173139Srwatson#define XGE_MAX_SEGS 100 /* Maximum number of segments */ 63173139Srwatson#define XGE_TX_LEVEL_LOW 16 64173139Srwatson#define XGE_FIFO_COUNT XGE_HAL_MIN_FIFO_NUM 65171095Ssam#define XGE_RING_COUNT XGE_HAL_MIN_RING_NUM 66173139Srwatson#define XGE_BUFFER_SIZE 20 67173139Srwatson#define XGE_LRO_DEFAULT_ENTRIES 12 68173139Srwatson#define XGE_BAUDRATE 1000000000 69171095Ssam 70171095Ssam/* Default values to configuration parameters */ 71173139Srwatson#define XGE_DEFAULT_ENABLED_TSO 1 72173139Srwatson#define XGE_DEFAULT_ENABLED_LRO 1 73173139Srwatson#define XGE_DEFAULT_ENABLED_MSI 1 74173139Srwatson#define XGE_DEFAULT_BUFFER_MODE 1 75171095Ssam#define XGE_DEFAULT_INITIAL_MTU 1500 76171095Ssam#define XGE_DEFAULT_LATENCY_TIMER -1 77171095Ssam#define XGE_DEFAULT_MAX_SPLITS_TRANS -1 78171095Ssam#define XGE_DEFAULT_MMRB_COUNT -1 79171095Ssam#define XGE_DEFAULT_SHARED_SPLITS 0 80171095Ssam#define XGE_DEFAULT_ISR_POLLING_CNT 8 81171095Ssam#define XGE_DEFAULT_STATS_REFRESH_TIME_SEC 4 82171095Ssam#define XGE_DEFAULT_MAC_RMAC_BCAST_EN 1 83171095Ssam#define XGE_DEFAULT_MAC_TMAC_UTIL_PERIOD 5 84171095Ssam#define XGE_DEFAULT_MAC_RMAC_UTIL_PERIOD 5 85171095Ssam#define XGE_DEFAULT_MAC_RMAC_PAUSE_GEN_EN 1 86171095Ssam#define XGE_DEFAULT_MAC_RMAC_PAUSE_RCV_EN 1 87171095Ssam#define XGE_DEFAULT_MAC_RMAC_PAUSE_TIME 65535 88171095Ssam#define XGE_DEFAULT_MAC_MC_PAUSE_THRESHOLD_Q0Q3 187 89171095Ssam#define XGE_DEFAULT_MAC_MC_PAUSE_THRESHOLD_Q4Q7 187 90171095Ssam#define XGE_DEFAULT_FIFO_MEMBLOCK_SIZE PAGE_SIZE 91171095Ssam#define XGE_DEFAULT_FIFO_RESERVE_THRESHOLD 0 92171095Ssam#define XGE_DEFAULT_FIFO_MAX_FRAGS 64 93171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_INTR 0 94171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_MAX 2048 95171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_INITIAL 2048 96171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_A 5 97171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_B 10 98171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_URANGE_C 20 99171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_A 15 100171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_B 30 101171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_C 45 102171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_UFC_D 60 103171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_CI_EN 1 104171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_AC_EN 1 105171095Ssam#define XGE_DEFAULT_FIFO_QUEUE_TTI_TIMER_VAL_US 8000 106171095Ssam#define XGE_DEFAULT_FIFO_ALIGNMENT_SIZE sizeof(u64) 107171095Ssam#define XGE_DEFAULT_RING_MEMBLOCK_SIZE PAGE_SIZE 108171095Ssam#define XGE_DEFAULT_RING_STRIP_VLAN_TAG 1 109171095Ssam#define XGE_DEFAULT_RING_QUEUE_MAX 16 110171095Ssam#define XGE_DEFAULT_RING_QUEUE_INITIAL 16 111171095Ssam#define XGE_DEFAULT_RING_QUEUE_DRAM_SIZE_MB 32 112171095Ssam#define XGE_DEFAULT_RING_QUEUE_INDICATE_MAX_PKTS 16 113171095Ssam#define XGE_DEFAULT_RING_QUEUE_BACKOFF_INTERVAL_US 1000 114171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_A 5 115171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_B 10 116171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_URANGE_C 50 117171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_UFC_A 1 118171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_UFC_B 8 119171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_UFC_C 16 120171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_UFC_D 32 121171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_TIMER_AC_EN 1 122171095Ssam#define XGE_DEFAULT_RING_QUEUE_RTI_TIMER_VAL_US 250 123171095Ssam 124173139Srwatson#define XGE_DRV_STATS(param) (lldev->driver_stats.param++) 125173139Srwatson 126173139Srwatson#define XGE_SAVE_PARAM(to, what, value) to.what = value; 127173139Srwatson 128173139Srwatson#define XGE_GET_PARAM(str_kenv, to, param, hardcode) { \ 129173139Srwatson static int param##__LINE__; \ 130173139Srwatson if(testenv(str_kenv) == 1) { \ 131173139Srwatson getenv_int(str_kenv, ¶m##__LINE__); \ 132173139Srwatson } \ 133173139Srwatson else { \ 134173139Srwatson param##__LINE__ = hardcode; \ 135173139Srwatson } \ 136173139Srwatson XGE_SAVE_PARAM(to, param, param##__LINE__); \ 137173139Srwatson} 138173139Srwatson 139173139Srwatson#define XGE_GET_PARAM_MAC(str_kenv, param, hardcode) \ 140173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).mac), param, hardcode); 141173139Srwatson 142173139Srwatson#define XGE_GET_PARAM_FIFO(str_kenv, param, hardcode) \ 143173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).fifo), param, hardcode); 144173139Srwatson 145173139Srwatson#define XGE_GET_PARAM_FIFO_QUEUE(str_kenv, param, qindex, hardcode) \ 146173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).fifo.queue[qindex]), param, \ 147173139Srwatson hardcode); 148173139Srwatson 149173139Srwatson#define XGE_GET_PARAM_FIFO_QUEUE_TTI(str_kenv, param, qindex, tindex, hardcode)\ 150173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).fifo.queue[qindex].tti[tindex]), \ 151173139Srwatson param, hardcode); 152173139Srwatson 153173139Srwatson#define XGE_GET_PARAM_RING(str_kenv, param, hardcode) \ 154173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).ring), param, hardcode); 155173139Srwatson 156173139Srwatson#define XGE_GET_PARAM_RING_QUEUE(str_kenv, param, qindex, hardcode) \ 157173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).ring.queue[qindex]), param, \ 158173139Srwatson hardcode); 159173139Srwatson 160173139Srwatson#define XGE_GET_PARAM_RING_QUEUE_RTI(str_kenv, param, qindex, hardcode) \ 161173139Srwatson XGE_GET_PARAM(str_kenv, ((*dconfig).ring.queue[qindex].rti), param, \ 162173139Srwatson hardcode); 163173139Srwatson 164171095Ssam/* Values to identify the requests from getinfo tool in ioctl */ 165171095Ssam#define XGE_QUERY_STATS 1 166171095Ssam#define XGE_QUERY_PCICONF 2 167173139Srwatson#define XGE_QUERY_DEVSTATS 3 168171095Ssam#define XGE_QUERY_DEVCONF 4 169171095Ssam#define XGE_READ_VERSION 5 170173139Srwatson#define XGE_QUERY_SWSTATS 6 171173139Srwatson#define XGE_QUERY_DRIVERSTATS 7 172173139Srwatson#define XGE_SET_BUFFER_MODE_1 8 173173139Srwatson#define XGE_SET_BUFFER_MODE_2 9 174171095Ssam#define XGE_SET_BUFFER_MODE_5 10 175171095Ssam#define XGE_QUERY_BUFFER_MODE 11 176171095Ssam 177171095Ssam#define XGE_OFFSET_OF_LAST_REG 0x3180 178171095Ssam 179171095Ssam#define VENDOR_ID_AMD 0x1022 180171095Ssam#define DEVICE_ID_8131_PCI_BRIDGE 0x7450 181171095Ssam 182171095Ssamtypedef struct mbuf *mbuf_t; 183171095Ssam 184173139Srwatsontypedef enum xge_lables { 185173139Srwatson xge_free_all = 0, 186173139Srwatson xge_free_mutex = 1, 187173139Srwatson xge_free_terminate_hal_driver = 2, 188173139Srwatson xge_free_hal_device = 3, 189173139Srwatson xge_free_pci_info = 4, 190173139Srwatson xge_free_bar0 = 5, 191173139Srwatson xge_free_bar0_resource = 6, 192173139Srwatson xge_free_bar1 = 7, 193173139Srwatson xge_free_bar1_resource = 8, 194173139Srwatson xge_free_irq_resource = 9, 195173139Srwatson xge_free_terminate_hal_device = 10, 196173139Srwatson xge_free_media_interface = 11, 197173139Srwatson} xge_lables_e; 198173139Srwatson 199173139Srwatsontypedef enum xge_option { 200173139Srwatson XGE_CHANGE_LRO = 0, 201173139Srwatson XGE_SET_MTU = 1 202173139Srwatson} xge_option_e; 203173139Srwatson 204173139Srwatsontypedef enum xge_event_e { 205171095Ssam XGE_LL_EVENT_TRY_XMIT_AGAIN = XGE_LL_EVENT_BASE + 1, 206173139Srwatson XGE_LL_EVENT_DEVICE_RESETTING = XGE_LL_EVENT_BASE + 2 207173139Srwatson} xge_event_e; 208171095Ssam 209173139Srwatsontypedef struct xge_msi_info { 210173139Srwatson u16 msi_control; /* MSI control 0x42 */ 211173139Srwatson u32 msi_lower_address; /* MSI lower address 0x44 */ 212173139Srwatson u32 msi_higher_address; /* MSI higher address 0x48 */ 213173139Srwatson u16 msi_data; /* MSI data */ 214173139Srwatson} xge_msi_info_t; 215173139Srwatson 216173139Srwatsontypedef struct xge_driver_stats_t { 217173139Srwatson /* ISR statistics */ 218173139Srwatson u64 isr_filter; 219173139Srwatson u64 isr_line; 220173139Srwatson u64 isr_msi; 221173139Srwatson 222173139Srwatson /* Tx statistics */ 223173139Srwatson u64 tx_calls; 224173139Srwatson u64 tx_completions; 225173139Srwatson u64 tx_desc_compl; 226173139Srwatson u64 tx_tcode; 227173139Srwatson u64 tx_defrag; 228173139Srwatson u64 tx_no_txd; 229173139Srwatson u64 tx_map_fail; 230173139Srwatson u64 tx_max_frags; 231173139Srwatson u64 tx_tso; 232173139Srwatson u64 tx_posted; 233173139Srwatson u64 tx_again; 234173139Srwatson u64 tx_lock_fail; 235173139Srwatson 236173139Srwatson /* Rx statistics */ 237173139Srwatson u64 rx_completions; 238173139Srwatson u64 rx_desc_compl; 239173139Srwatson u64 rx_tcode; 240173139Srwatson u64 rx_no_buf; 241173139Srwatson u64 rx_map_fail; 242173139Srwatson 243173139Srwatson /* LRO statistics */ 244173139Srwatson u64 lro_uncapable; 245173139Srwatson u64 lro_begin; 246173139Srwatson u64 lro_end1; 247173139Srwatson u64 lro_end2; 248173139Srwatson u64 lro_end3; 249173139Srwatson u64 lro_append; 250173139Srwatson u64 lro_session_exceeded; 251173139Srwatson u64 lro_close; 252173139Srwatson} xge_driver_stats_t; 253173139Srwatson 254173139Srwatsontypedef struct xge_lro_entry_t { 255173139Srwatson SLIST_ENTRY(xge_lro_entry_t) next; 256173139Srwatson struct mbuf *m_head; 257173139Srwatson struct mbuf *m_tail; 258173139Srwatson struct ip *lro_header_ip; 259173139Srwatson int timestamp; 260173139Srwatson u32 tsval; 261173139Srwatson u32 tsecr; 262173139Srwatson u32 source_ip; 263173139Srwatson u32 dest_ip; 264173139Srwatson u32 next_seq; 265173139Srwatson u32 ack_seq; 266173139Srwatson u32 len; 267173139Srwatson u32 data_csum; 268173139Srwatson u16 window; 269173139Srwatson u16 source_port; 270173139Srwatson u16 dest_port; 271173139Srwatson u16 append_cnt; 272173139Srwatson u16 mss; 273173139Srwatson} xge_lro_entry_t; 274173139Srwatson 275173139SrwatsonSLIST_HEAD(lro_head, xge_lro_entry_t); 276173139Srwatson 277171095Ssam/* Adapter structure */ 278173139Srwatsontypedef struct xge_lldev_t { 279171095Ssam device_t device; /* Device */ 280171095Ssam struct ifnet *ifnetp; /* Interface ifnet structure */ 281171095Ssam struct resource *irq; /* Resource structure for IRQ */ 282171095Ssam void *irqhandle; /* IRQ handle */ 283173139Srwatson xge_pci_info_t *pdev; /* PCI info */ 284171095Ssam xge_hal_device_t *devh; /* HAL: Device Handle */ 285173139Srwatson struct mtx mtx_drv; /* Mutex - Driver */ 286173139Srwatson struct mtx mtx_tx[XGE_FIFO_COUNT]; 287173139Srwatson /* Mutex - Tx */ 288173139Srwatson char mtx_name_drv[16];/*Mutex Name - Driver */ 289173139Srwatson char mtx_name_tx[16][XGE_FIFO_COUNT]; 290173139Srwatson /* Mutex Name - Tx */ 291171095Ssam struct callout timer; /* Timer for polling */ 292173139Srwatson struct ifmedia media; /* In-kernel representation of a */ 293173139Srwatson /* single supported media type */ 294173139Srwatson xge_hal_channel_h fifo_channel[XGE_FIFO_COUNT]; 295173139Srwatson /* FIFO channels */ 296173139Srwatson xge_hal_channel_h ring_channel[XGE_RING_COUNT]; 297173139Srwatson /* Ring channels */ 298171095Ssam bus_dma_tag_t dma_tag_tx; /* Tag for dtr dma mapping (Tx) */ 299171095Ssam bus_dma_tag_t dma_tag_rx; /* Tag for dtr dma mapping (Rx) */ 300173139Srwatson bus_dmamap_t extra_dma_map; /* Extra DMA map for Rx */ 301173139Srwatson xge_msi_info_t msi_info; /* MSI info */ 302173139Srwatson xge_driver_stats_t driver_stats; /* Driver statistics */ 303173139Srwatson int initialized; /* Flag: Initialized or not */ 304171095Ssam int all_multicast; /* All multicast flag */ 305171095Ssam int macaddr_count; /* Multicast address count */ 306171095Ssam int in_detach; /* To avoid ioctl during detach */ 307171095Ssam int buffer_mode; /* Buffer Mode */ 308171095Ssam int rxd_mbuf_cnt; /* Number of buffers used */ 309171095Ssam int rxd_mbuf_len[5];/* Buffer lengths */ 310173139Srwatson int enabled_tso; /* Flag: TSO Enabled */ 311173139Srwatson int enabled_lro; /* Flag: LRO Enabled */ 312173139Srwatson int enabled_msi; /* Flag: MSI Enabled */ 313173139Srwatson int mtu; /* Interface MTU */ 314173139Srwatson int lro_num; /* Number of LRO sessions */ 315173139Srwatson struct lro_head lro_active; /* Active LRO sessions */ 316173139Srwatson struct lro_head lro_free; /* Free LRO sessions */ 317173139Srwatson} xge_lldev_t; 318171095Ssam 319171095Ssam/* Rx descriptor private structure */ 320173139Srwatsontypedef struct xge_rx_priv_t { 321173139Srwatson mbuf_t *bufferArray; 322173139Srwatson xge_dma_mbuf_t dmainfo[5]; 323173139Srwatson} xge_rx_priv_t; 324171095Ssam 325171095Ssam/* Tx descriptor private structure */ 326173139Srwatsontypedef struct xge_tx_priv_t { 327171095Ssam mbuf_t buffer; 328171095Ssam bus_dmamap_t dma_map; 329173139Srwatson} xge_tx_priv_t; 330171095Ssam 331171095Ssam/* BAR0 Register */ 332173139Srwatsontypedef struct xge_register_t { 333173139Srwatson char option[2]; 334171095Ssam u64 offset; 335171095Ssam u64 value; 336173139Srwatson}xge_register_t; 337171095Ssam 338173139Srwatsonvoid xge_init_params(xge_hal_device_config_t *, device_t); 339171095Ssamvoid xge_init(void *); 340173139Srwatsonvoid xge_device_init(xge_lldev_t *, xge_hal_channel_reopen_e); 341173139Srwatsonvoid xge_device_stop(xge_lldev_t *, xge_hal_channel_reopen_e); 342173139Srwatsonvoid xge_stop(xge_lldev_t *); 343173139Srwatsonvoid xge_resources_free(device_t, xge_lables_e); 344173139Srwatsonvoid xge_callback_link_up(void *); 345173139Srwatsonvoid xge_callback_link_down(void *); 346173139Srwatsonvoid xge_callback_crit_err(void *, xge_hal_event_e, u64); 347173139Srwatsonvoid xge_callback_event(xge_queue_item_t *); 348171095Ssamint xge_ifmedia_change(struct ifnet *); 349171095Ssamvoid xge_ifmedia_status(struct ifnet *, struct ifmediareq *); 350171095Ssamint xge_ioctl(struct ifnet *, unsigned long, caddr_t); 351173139Srwatsonint xge_ioctl_stats(xge_lldev_t *, struct ifreq *); 352173139Srwatsonint xge_ioctl_registers(xge_lldev_t *, struct ifreq *); 353171095Ssamvoid xge_timer(void *); 354173139Srwatsonint xge_isr_filter(void *); 355173139Srwatsonvoid xge_isr_line(void *); 356173139Srwatsonvoid xge_isr_msi(void *); 357173139Srwatsonvoid xge_enable_msi(xge_lldev_t *); 358173139Srwatsonint xge_rx_open(int, xge_lldev_t *, xge_hal_channel_reopen_e); 359173139Srwatsonint xge_tx_open(xge_lldev_t *, xge_hal_channel_reopen_e); 360173139Srwatsonvoid xge_channel_close(xge_lldev_t *, xge_hal_channel_reopen_e); 361173139Srwatsonint xge_channel_open(xge_lldev_t *, xge_hal_channel_reopen_e); 362173139Srwatsonxge_hal_status_e xge_rx_compl(xge_hal_channel_h, xge_hal_dtr_h, u8, void *); 363173139Srwatsonxge_hal_status_e xge_tx_compl(xge_hal_channel_h, xge_hal_dtr_h, u8, void *); 364173139Srwatsonxge_hal_status_e xge_tx_initial_replenish(xge_hal_channel_h, xge_hal_dtr_h, 365173139Srwatson int, void *, xge_hal_channel_reopen_e); 366173139Srwatsonxge_hal_status_e xge_rx_initial_replenish(xge_hal_channel_h, xge_hal_dtr_h, 367173139Srwatson int, void *, xge_hal_channel_reopen_e); 368173139Srwatsonvoid xge_rx_term(xge_hal_channel_h, xge_hal_dtr_h, xge_hal_dtr_state_e, 369173139Srwatson void *, xge_hal_channel_reopen_e); 370173139Srwatsonvoid xge_tx_term(xge_hal_channel_h, xge_hal_dtr_h, xge_hal_dtr_state_e, 371173139Srwatson void *, xge_hal_channel_reopen_e); 372173139Srwatsonvoid xge_set_mbuf_cflags(mbuf_t); 373171095Ssamvoid xge_send(struct ifnet *); 374173139Srwatsonstatic void inline xge_send_locked(struct ifnet *, int); 375173139Srwatsonint xge_get_buf(xge_hal_dtr_h, xge_rx_priv_t *, xge_lldev_t *, int); 376173139Srwatsonint xge_ring_dtr_get(mbuf_t, xge_hal_channel_h, xge_hal_dtr_h, xge_lldev_t *, 377173139Srwatson xge_rx_priv_t *); 378173139Srwatsonint xge_get_buf_3b_5b(xge_hal_dtr_h, xge_rx_priv_t *, xge_lldev_t *); 379171095Ssamvoid dmamap_cb(void *, bus_dma_segment_t *, int, int); 380173139Srwatsonvoid xge_reset(xge_lldev_t *); 381173139Srwatsonvoid xge_setmulti(xge_lldev_t *); 382173139Srwatsonvoid xge_enable_promisc(xge_lldev_t *); 383173139Srwatsonvoid xge_disable_promisc(xge_lldev_t *); 384173139Srwatsonint xge_change_mtu(xge_lldev_t *, int); 385173139Srwatsonvoid xge_buffer_mode_init(xge_lldev_t *, int); 386171095Ssamvoid xge_initialize(device_t, xge_hal_channel_reopen_e); 387171095Ssamvoid xge_terminate(device_t, xge_hal_channel_reopen_e); 388171095Ssamint xge_probe(device_t); 389171095Ssamint xge_driver_initialize(void); 390171095Ssamvoid xge_media_init(device_t); 391171095Ssamvoid xge_pci_space_save(device_t); 392171095Ssamvoid xge_pci_space_restore(device_t); 393173139Srwatsonvoid xge_msi_info_save(xge_lldev_t *); 394173139Srwatsonvoid xge_msi_info_restore(xge_lldev_t *); 395171095Ssamint xge_attach(device_t); 396171095Ssamint xge_interface_setup(device_t); 397171095Ssamint xge_detach(device_t); 398171095Ssamint xge_shutdown(device_t); 399173139Srwatsonvoid xge_mutex_init(xge_lldev_t *); 400173139Srwatsonvoid xge_mutex_destroy(xge_lldev_t *); 401173139Srwatsonvoid xge_print_info(xge_lldev_t *); 402173139Srwatsonvoid xge_lro_flush_sessions(xge_lldev_t *); 403173139Srwatsonvoid xge_rx_buffer_sizes_set(xge_lldev_t *, int, int); 404173139Srwatsonvoid xge_accumulate_large_rx(xge_lldev_t *, struct mbuf *, int, 405173139Srwatson xge_rx_priv_t *); 406173139Srwatsonxge_hal_status_e xge_create_dma_tags(device_t); 407173139Srwatsonvoid xge_add_sysctl_handlers(xge_lldev_t *); 408173139Srwatsonvoid xge_confirm_changes(xge_lldev_t *, xge_option_e); 409173139Srwatsonstatic int xge_lro_accumulate(xge_lldev_t *, struct mbuf *); 410173139Srwatsonstatic void xge_lro_flush(xge_lldev_t *, xge_lro_entry_t *); 411171095Ssam 412171095Ssam#endif // _IF_XGE_H 413171095Ssam 414