nvme_sim.c revision 328691
1/*- 2 * Copyright (c) 2016 Netflix, Inc 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/dev/nvme/nvme_sim.c 328691 2018-02-01 16:52:03Z mav $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/buf.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/ioccom.h> 36#include <sys/malloc.h> 37#include <sys/proc.h> 38#include <sys/smp.h> 39 40#include <cam/cam.h> 41#include <cam/cam_ccb.h> 42#include <cam/cam_sim.h> 43#include <cam/cam_xpt_sim.h> 44#include <cam/cam_xpt_internal.h> // Yes, this is wrong. 45#include <cam/cam_debug.h> 46 47#include "nvme_private.h" 48 49#define ccb_accb_ptr spriv_ptr0 50#define ccb_ctrlr_ptr spriv_ptr1 51static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 52static void nvme_sim_poll(struct cam_sim *sim); 53 54#define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 55#define sim2ns(sim) (sim2softc(sim)->s_ns) 56#define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 57 58struct nvme_sim_softc 59{ 60 struct nvme_controller *s_ctrlr; 61 struct nvme_namespace *s_ns; 62 struct cam_sim *s_sim; 63 struct cam_path *s_path; 64}; 65 66static void 67nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 68{ 69 union ccb *ccb = (union ccb *)ccb_arg; 70 71 /* 72 * Let the periph know the completion, and let it sort out what 73 * it means. Make our best guess, though for the status code. 74 */ 75 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 76 if (nvme_completion_is_error(cpl)) 77 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 78 else 79 ccb->ccb_h.status = CAM_REQ_CMP; 80 xpt_done(ccb); 81} 82 83static void 84nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 85{ 86 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 87 struct nvme_request *req; 88 void *payload; 89 uint32_t size; 90 struct nvme_controller *ctrlr; 91 92 ctrlr = sim2ctrlr(sim); 93 payload = nvmeio->data_ptr; 94 size = nvmeio->dxfer_len; 95 /* SG LIST ??? */ 96 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 97 req = nvme_allocate_request_bio((struct bio *)payload, 98 nvme_sim_nvmeio_done, ccb); 99 else if (payload == NULL) 100 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 101 else 102 req = nvme_allocate_request_vaddr(payload, size, 103 nvme_sim_nvmeio_done, ccb); 104 105 if (req == NULL) { 106 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 107 xpt_done(ccb); 108 return; 109 } 110 111 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 112 113 if (ccb->ccb_h.func_code == XPT_NVME_IO) 114 nvme_ctrlr_submit_io_request(ctrlr, req); 115 else 116 nvme_ctrlr_submit_admin_request(ctrlr, req); 117 118 ccb->ccb_h.status |= CAM_SIM_QUEUED; 119} 120 121static void 122nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 123{ 124 struct nvme_controller *ctrlr; 125 struct nvme_namespace *ns; 126 127 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 128 ("nvme_sim_action: func= %#x\n", 129 ccb->ccb_h.func_code)); 130 131 /* 132 * XXX when we support multiple namespaces in the base driver we'll need 133 * to revisit how all this gets stored and saved in the periph driver's 134 * reserved areas. Right now we store all three in the softc of the sim. 135 */ 136 ns = sim2ns(sim); 137 ctrlr = sim2ctrlr(sim); 138 139 mtx_assert(&ctrlr->lock, MA_OWNED); 140 141 switch (ccb->ccb_h.func_code) { 142 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 143 /* 144 * Only meaningful for old-school SCSI disks since only the SCSI 145 * da driver generates them. Reject all these that slip through. 146 */ 147 /*FALLTHROUGH*/ 148 case XPT_ABORT: /* Abort the specified CCB */ 149 case XPT_EN_LUN: /* Enable LUN as a target */ 150 case XPT_TARGET_IO: /* Execute target I/O request */ 151 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 152 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 153 /* 154 * Only target mode generates these, and only for SCSI. They are 155 * all invalid/unsupported for NVMe. 156 */ 157 ccb->ccb_h.status = CAM_REQ_INVALID; 158 break; 159 case XPT_SET_TRAN_SETTINGS: 160 /* 161 * NVMe doesn't really have different transfer settings, but 162 * other parts of CAM think failure here is a big deal. 163 */ 164 ccb->ccb_h.status = CAM_REQ_CMP; 165 break; 166 case XPT_PATH_INQ: /* Path routing inquiry */ 167 { 168 struct ccb_pathinq *cpi = &ccb->cpi; 169 170 /* 171 * NVMe may have multiple LUNs on the same path. Current generation 172 * of NVMe devives support only a single name space. Multiple name 173 * space drives are coming, but it's unclear how we should report 174 * them up the stack. 175 */ 176 cpi->version_num = 1; 177 cpi->hba_inquiry = 0; 178 cpi->target_sprt = 0; 179 cpi->hba_misc = PIM_UNMAPPED /* | PIM_NOSCAN */; 180 cpi->hba_eng_cnt = 0; 181 cpi->max_target = 0; 182 cpi->max_lun = ctrlr->cdata.nn; 183 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns); 184 cpi->initiator_id = 0; 185 cpi->bus_id = cam_sim_bus(sim); 186 cpi->base_transfer_speed = 4000000; /* 4 GB/s 4 lanes pcie 3 */ 187 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 188 strncpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 189 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 190 cpi->unit_number = cam_sim_unit(sim); 191 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 192 cpi->transport_version = 1; /* XXX Get PCIe spec ? */ 193 cpi->protocol = PROTO_NVME; 194 cpi->protocol_version = NVME_REV_1; /* Groks all 1.x NVMe cards */ 195 cpi->xport_specific.nvme.nsid = ns->id; 196 cpi->ccb_h.status = CAM_REQ_CMP; 197 break; 198 } 199 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 200 { 201 struct ccb_trans_settings *cts; 202 struct ccb_trans_settings_nvme *nvmep; 203 struct ccb_trans_settings_nvme *nvmex; 204 205 cts = &ccb->cts; 206 nvmex = &cts->xport_specific.nvme; 207 nvmep = &cts->proto_specific.nvme; 208 209 nvmex->valid = CTS_NVME_VALID_SPEC; 210 nvmex->spec_major = 1; /* XXX read from card */ 211 nvmex->spec_minor = 2; 212 nvmex->spec_tiny = 0; 213 214 nvmep->valid = CTS_NVME_VALID_SPEC; 215 nvmep->spec_major = 1; /* XXX read from card */ 216 nvmep->spec_minor = 2; 217 nvmep->spec_tiny = 0; 218 cts->transport = XPORT_NVME; 219 cts->protocol = PROTO_NVME; 220 cts->ccb_h.status = CAM_REQ_CMP; 221 break; 222 } 223 case XPT_TERM_IO: /* Terminate the I/O process */ 224 /* 225 * every driver handles this, but nothing generates it. Assume 226 * it's OK to just say 'that worked'. 227 */ 228 /*FALLTHROUGH*/ 229 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 230 case XPT_RESET_BUS: /* Reset the specified bus */ 231 /* 232 * NVMe doesn't really support physically resetting the bus. It's part 233 * of the bus scanning dance, so return sucess to tell the process to 234 * proceed. 235 */ 236 ccb->ccb_h.status = CAM_REQ_CMP; 237 break; 238 case XPT_NVME_IO: /* Execute the requested I/O operation */ 239 case XPT_NVME_ADMIN: /* or Admin operation */ 240 nvme_sim_nvmeio(sim, ccb); 241 return; /* no done */ 242 default: 243 ccb->ccb_h.status = CAM_REQ_INVALID; 244 break; 245 } 246 xpt_done(ccb); 247} 248 249static void 250nvme_sim_poll(struct cam_sim *sim) 251{ 252 253 nvme_ctrlr_intx_handler(sim2ctrlr(sim)); 254} 255 256static void * 257nvme_sim_new_controller(struct nvme_controller *ctrlr) 258{ 259 struct cam_devq *devq; 260 int max_trans; 261 int unit; 262 struct nvme_sim_softc *sc = NULL; 263 264 max_trans = ctrlr->max_hw_pend_io; 265 unit = device_get_unit(ctrlr->dev); 266 devq = cam_simq_alloc(max_trans); 267 if (devq == NULL) 268 return NULL; 269 270 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 271 272 sc->s_ctrlr = ctrlr; 273 274 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 275 "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq); 276 if (sc->s_sim == NULL) { 277 printf("Failed to allocate a sim\n"); 278 cam_simq_free(devq); 279 free(sc, M_NVME); 280 return NULL; 281 } 282 283 return sc; 284} 285 286static void 287nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path) 288{ 289 union ccb *ccb; 290 291 ccb = xpt_alloc_ccb_nowait(); 292 if (ccb == NULL) { 293 printf("unable to alloc CCB for rescan\n"); 294 return; 295 } 296 297 if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) { 298 printf("unable to copy path for rescan\n"); 299 xpt_free_ccb(ccb); 300 return; 301 } 302 303 xpt_rescan(ccb); 304} 305 306static void * 307nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg) 308{ 309 struct nvme_sim_softc *sc = sc_arg; 310 struct nvme_controller *ctrlr = sc->s_ctrlr; 311 int i; 312 313 sc->s_ns = ns; 314 315 /* 316 * XXX this is creating one bus per ns, but it should be one 317 * XXX target per controller, and one LUN per namespace. 318 * XXX Current drives only support one NS, so there's time 319 * XXX to fix it later when new drives arrive. 320 * 321 * XXX I'm pretty sure the xpt_bus_register() call below is 322 * XXX like super lame and it really belongs in the sim_new_ctrlr 323 * XXX callback. Then the create_path below would be pretty close 324 * XXX to being right. Except we should be per-ns not per-ctrlr 325 * XXX data. 326 */ 327 328 mtx_lock(&ctrlr->lock); 329/* Create bus */ 330 331 /* 332 * XXX do I need to lock ctrlr->lock ? 333 * XXX do I need to lock the path? 334 * ata and scsi seem to in their code, but their discovery is 335 * somewhat more asynchronous. We're only every called one at a 336 * time, and nothing is in parallel. 337 */ 338 339 i = 0; 340 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) 341 goto error; 342 i++; 343 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 344 1, ns->id) != CAM_REQ_CMP) 345 goto error; 346 i++; 347 348 sc->s_path->device->nvme_data = nvme_ns_get_data(ns); 349 sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr); 350 351/* Scan bus */ 352 nvme_sim_rescan_target(ctrlr, sc->s_path); 353 354 mtx_unlock(&ctrlr->lock); 355 356 return ns; 357 358error: 359 switch (i) { 360 case 2: 361 xpt_free_path(sc->s_path); 362 case 1: 363 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 364 case 0: 365 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 366 } 367 mtx_unlock(&ctrlr->lock); 368 return NULL; 369} 370 371static void 372nvme_sim_controller_fail(void *ctrlr_arg) 373{ 374 /* XXX cleanup XXX */ 375} 376 377struct nvme_consumer *consumer_cookie; 378 379static void 380nvme_sim_init(void) 381{ 382 if (nvme_use_nvd) 383 return; 384 385 consumer_cookie = nvme_register_consumer(nvme_sim_new_ns, 386 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 387} 388 389SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 390 nvme_sim_init, NULL); 391 392static void 393nvme_sim_uninit(void) 394{ 395 if (nvme_use_nvd) 396 return; 397 /* XXX Cleanup */ 398 399 nvme_unregister_consumer(consumer_cookie); 400} 401 402SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 403 nvme_sim_uninit, NULL); 404