nvme_private.h revision 328689
1/*- 2 * Copyright (C) 2012-2014 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/nvme/nvme_private.h 328689 2018-02-01 16:50:25Z mav $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/bio.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/mutex.h> 39#include <sys/rman.h> 40#include <sys/systm.h> 41#include <sys/taskqueue.h> 42 43#include <vm/uma.h> 44 45#include <machine/bus.h> 46 47#include "nvme.h" 48 49#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51MALLOC_DECLARE(M_NVME); 52 53#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 54#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 55 56/* 57 * For commands requiring more than 2 PRP entries, one PRP will be 58 * embedded in the command (prp1), and the rest of the PRP entries 59 * will be in a list pointed to by the command (prp2). This means 60 * that real max number of PRP entries we support is 32+1, which 61 * results in a max xfer size of 32*PAGE_SIZE. 62 */ 63#define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 64 65#define NVME_ADMIN_TRACKERS (16) 66#define NVME_ADMIN_ENTRIES (128) 67/* min and max are defined in admin queue attributes section of spec */ 68#define NVME_MIN_ADMIN_ENTRIES (2) 69#define NVME_MAX_ADMIN_ENTRIES (4096) 70 71/* 72 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 73 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 74 * will allow outstanding on an I/O qpair at any time. The only advantage in 75 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 76 * the contents of the submission and completion queues, it will show a longer 77 * history of data. 78 */ 79#define NVME_IO_ENTRIES (256) 80#define NVME_IO_TRACKERS (128) 81#define NVME_MIN_IO_TRACKERS (4) 82#define NVME_MAX_IO_TRACKERS (1024) 83 84/* 85 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 86 * for each controller. 87 */ 88 89#define NVME_INT_COAL_TIME (0) /* disabled */ 90#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 91 92#define NVME_MAX_NAMESPACES (16) 93#define NVME_MAX_CONSUMERS (2) 94#define NVME_MAX_ASYNC_EVENTS (8) 95 96#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 97#define NVME_MIN_TIMEOUT_PERIOD (5) 98#define NVME_MAX_TIMEOUT_PERIOD (120) 99 100#define NVME_DEFAULT_RETRY_COUNT (4) 101 102/* Maximum log page size to fetch for AERs. */ 103#define NVME_MAX_AER_LOG_SIZE (4096) 104 105/* 106 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 107 * it. 108 */ 109#ifndef CACHE_LINE_SIZE 110#define CACHE_LINE_SIZE (64) 111#endif 112 113/* 114 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 115 * support and the bus_dmamap_load_bio API are available on the target 116 * kernel. This will ease porting back to earlier stable branches at a 117 * later point. 118 */ 119#ifdef BIO_UNMAPPED 120#define NVME_UNMAPPED_BIO_SUPPORT 121#endif 122 123extern uma_zone_t nvme_request_zone; 124extern int32_t nvme_retry_count; 125 126struct nvme_completion_poll_status { 127 128 struct nvme_completion cpl; 129 boolean_t done; 130}; 131 132#define NVME_REQUEST_VADDR 1 133#define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 134#define NVME_REQUEST_UIO 3 135#ifdef NVME_UNMAPPED_BIO_SUPPORT 136#define NVME_REQUEST_BIO 4 137#endif 138 139struct nvme_request { 140 141 struct nvme_command cmd; 142 struct nvme_qpair *qpair; 143 union { 144 void *payload; 145 struct bio *bio; 146 } u; 147 uint32_t type; 148 uint32_t payload_size; 149 boolean_t timeout; 150 nvme_cb_fn_t cb_fn; 151 void *cb_arg; 152 int32_t retries; 153 STAILQ_ENTRY(nvme_request) stailq; 154}; 155 156struct nvme_async_event_request { 157 158 struct nvme_controller *ctrlr; 159 struct nvme_request *req; 160 struct nvme_completion cpl; 161 uint32_t log_page_id; 162 uint32_t log_page_size; 163 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 164}; 165 166struct nvme_tracker { 167 168 TAILQ_ENTRY(nvme_tracker) tailq; 169 struct nvme_request *req; 170 struct nvme_qpair *qpair; 171 struct callout timer; 172 bus_dmamap_t payload_dma_map; 173 uint16_t cid; 174 175 uint64_t *prp; 176 bus_addr_t prp_bus_addr; 177}; 178 179struct nvme_qpair { 180 181 struct nvme_controller *ctrlr; 182 uint32_t id; 183 uint32_t phase; 184 185 uint16_t vector; 186 int rid; 187 struct resource *res; 188 void *tag; 189 190 uint32_t num_entries; 191 uint32_t num_trackers; 192 uint32_t sq_tdbl_off; 193 uint32_t cq_hdbl_off; 194 195 uint32_t sq_head; 196 uint32_t sq_tail; 197 uint32_t cq_head; 198 199 int64_t num_cmds; 200 int64_t num_intr_handler_calls; 201 202 struct nvme_command *cmd; 203 struct nvme_completion *cpl; 204 205 bus_dma_tag_t dma_tag; 206 bus_dma_tag_t dma_tag_payload; 207 208 bus_dmamap_t queuemem_map; 209 uint64_t cmd_bus_addr; 210 uint64_t cpl_bus_addr; 211 212 TAILQ_HEAD(, nvme_tracker) free_tr; 213 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 214 STAILQ_HEAD(, nvme_request) queued_req; 215 216 struct nvme_tracker **act_tr; 217 218 boolean_t is_enabled; 219 220 struct mtx lock __aligned(CACHE_LINE_SIZE); 221 222} __aligned(CACHE_LINE_SIZE); 223 224struct nvme_namespace { 225 226 struct nvme_controller *ctrlr; 227 struct nvme_namespace_data data; 228 uint32_t id; 229 uint32_t flags; 230 struct cdev *cdev; 231 void *cons_cookie[NVME_MAX_CONSUMERS]; 232 uint32_t stripesize; 233 struct mtx lock; 234}; 235 236/* 237 * One of these per allocated PCI device. 238 */ 239struct nvme_controller { 240 241 device_t dev; 242 243 struct mtx lock; 244 245 uint32_t ready_timeout_in_ms; 246 247 bus_space_tag_t bus_tag; 248 bus_space_handle_t bus_handle; 249 int resource_id; 250 struct resource *resource; 251 252 /* 253 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 254 * separate from the control registers which are in BAR 0/1. These 255 * members track the mapping of BAR 4/5 for that reason. 256 */ 257 int bar4_resource_id; 258 struct resource *bar4_resource; 259 260 uint32_t msix_enabled; 261 uint32_t force_intx; 262 uint32_t enable_aborts; 263 264 uint32_t num_io_queues; 265 uint32_t num_cpus_per_ioq; 266 267 /* Fields for tracking progress during controller initialization. */ 268 struct intr_config_hook config_hook; 269 uint32_t ns_identified; 270 uint32_t queues_created; 271 272 struct task reset_task; 273 struct task fail_req_task; 274 struct taskqueue *taskqueue; 275 276 /* For shared legacy interrupt. */ 277 int rid; 278 struct resource *res; 279 void *tag; 280 281 bus_dma_tag_t hw_desc_tag; 282 bus_dmamap_t hw_desc_map; 283 284 /** maximum i/o size in bytes */ 285 uint32_t max_xfer_size; 286 287 /** minimum page size supported by this controller in bytes */ 288 uint32_t min_page_size; 289 290 /** interrupt coalescing time period (in microseconds) */ 291 uint32_t int_coal_time; 292 293 /** interrupt coalescing threshold */ 294 uint32_t int_coal_threshold; 295 296 /** timeout period in seconds */ 297 uint32_t timeout_period; 298 299 struct nvme_qpair adminq; 300 struct nvme_qpair *ioq; 301 302 struct nvme_registers *regs; 303 304 struct nvme_controller_data cdata; 305 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 306 307 struct cdev *cdev; 308 309 /** bit mask of warning types currently enabled for async events */ 310 union nvme_critical_warning_state async_event_config; 311 312 uint32_t num_aers; 313 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 314 315 void *cons_cookie[NVME_MAX_CONSUMERS]; 316 317 uint32_t is_resetting; 318 uint32_t is_initialized; 319 uint32_t notification_sent; 320 321 boolean_t is_failed; 322 STAILQ_HEAD(, nvme_request) fail_req; 323}; 324 325#define nvme_mmio_offsetof(reg) \ 326 offsetof(struct nvme_registers, reg) 327 328#define nvme_mmio_read_4(sc, reg) \ 329 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 330 nvme_mmio_offsetof(reg)) 331 332#define nvme_mmio_write_4(sc, reg, val) \ 333 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 334 nvme_mmio_offsetof(reg), val) 335 336#define nvme_mmio_write_8(sc, reg, val) \ 337 do { \ 338 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 339 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 341 nvme_mmio_offsetof(reg)+4, \ 342 (val & 0xFFFFFFFF00000000UL) >> 32); \ 343 } while (0); 344 345#if __FreeBSD_version < 800054 346#define wmb() __asm volatile("sfence" ::: "memory") 347#define mb() __asm volatile("mfence" ::: "memory") 348#endif 349 350#define nvme_printf(ctrlr, fmt, args...) \ 351 device_printf(ctrlr->dev, fmt, ##args) 352 353void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 354 355void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 356 void *payload, 357 nvme_cb_fn_t cb_fn, void *cb_arg); 358void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 359 uint32_t nsid, void *payload, 360 nvme_cb_fn_t cb_fn, void *cb_arg); 361void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 362 uint32_t microseconds, 363 uint32_t threshold, 364 nvme_cb_fn_t cb_fn, 365 void *cb_arg); 366void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 367 struct nvme_error_information_entry *payload, 368 uint32_t num_entries, /* 0 = max */ 369 nvme_cb_fn_t cb_fn, 370 void *cb_arg); 371void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 372 uint32_t nsid, 373 struct nvme_health_information_page *payload, 374 nvme_cb_fn_t cb_fn, 375 void *cb_arg); 376void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 377 struct nvme_firmware_page *payload, 378 nvme_cb_fn_t cb_fn, 379 void *cb_arg); 380void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 381 struct nvme_qpair *io_que, uint16_t vector, 382 nvme_cb_fn_t cb_fn, void *cb_arg); 383void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 384 struct nvme_qpair *io_que, 385 nvme_cb_fn_t cb_fn, void *cb_arg); 386void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 387 struct nvme_qpair *io_que, 388 nvme_cb_fn_t cb_fn, void *cb_arg); 389void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 390 struct nvme_qpair *io_que, 391 nvme_cb_fn_t cb_fn, void *cb_arg); 392void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 393 uint32_t num_queues, nvme_cb_fn_t cb_fn, 394 void *cb_arg); 395void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 396 union nvme_critical_warning_state state, 397 nvme_cb_fn_t cb_fn, void *cb_arg); 398void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 399 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 400 401void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 402 403int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 404void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 405void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 406int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 407void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 408/* ctrlr defined as void * to allow use with config_intrhook. */ 409void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 410void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 411 struct nvme_request *req); 412void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 413 struct nvme_request *req); 414void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 415 struct nvme_request *req); 416 417int nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 418 uint16_t vector, uint32_t num_entries, 419 uint32_t num_trackers, 420 struct nvme_controller *ctrlr); 421void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 422 struct nvme_tracker *tr); 423void nvme_qpair_process_completions(struct nvme_qpair *qpair); 424void nvme_qpair_submit_request(struct nvme_qpair *qpair, 425 struct nvme_request *req); 426void nvme_qpair_reset(struct nvme_qpair *qpair); 427void nvme_qpair_fail(struct nvme_qpair *qpair); 428void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 429 struct nvme_request *req, 430 uint32_t sct, uint32_t sc, 431 boolean_t print_on_error); 432 433void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 434void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 435void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 436 437void nvme_io_qpair_enable(struct nvme_qpair *qpair); 438void nvme_io_qpair_disable(struct nvme_qpair *qpair); 439void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 440 441int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 442 struct nvme_controller *ctrlr); 443void nvme_ns_destruct(struct nvme_namespace *ns); 444 445void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 446 447void nvme_dump_command(struct nvme_command *cmd); 448void nvme_dump_completion(struct nvme_completion *cpl); 449 450static __inline void 451nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 452{ 453 uint64_t *bus_addr = (uint64_t *)arg; 454 455 if (error != 0) 456 printf("nvme_single_map err %d\n", error); 457 *bus_addr = seg[0].ds_addr; 458} 459 460static __inline struct nvme_request * 461_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 462{ 463 struct nvme_request *req; 464 465 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 466 if (req != NULL) { 467 req->cb_fn = cb_fn; 468 req->cb_arg = cb_arg; 469 req->timeout = TRUE; 470 } 471 return (req); 472} 473 474static __inline struct nvme_request * 475nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 476 nvme_cb_fn_t cb_fn, void *cb_arg) 477{ 478 struct nvme_request *req; 479 480 req = _nvme_allocate_request(cb_fn, cb_arg); 481 if (req != NULL) { 482 req->type = NVME_REQUEST_VADDR; 483 req->u.payload = payload; 484 req->payload_size = payload_size; 485 } 486 return (req); 487} 488 489static __inline struct nvme_request * 490nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 491{ 492 struct nvme_request *req; 493 494 req = _nvme_allocate_request(cb_fn, cb_arg); 495 if (req != NULL) 496 req->type = NVME_REQUEST_NULL; 497 return (req); 498} 499 500static __inline struct nvme_request * 501nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 502{ 503 struct nvme_request *req; 504 505 req = _nvme_allocate_request(cb_fn, cb_arg); 506 if (req != NULL) { 507#ifdef NVME_UNMAPPED_BIO_SUPPORT 508 req->type = NVME_REQUEST_BIO; 509 req->u.bio = bio; 510#else 511 req->type = NVME_REQUEST_VADDR; 512 req->u.payload = bio->bio_data; 513 req->payload_size = bio->bio_bcount; 514#endif 515 } 516 return (req); 517} 518 519#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 520 521void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 522 const struct nvme_completion *async_cpl, 523 uint32_t log_page_id, void *log_page_buffer, 524 uint32_t log_page_size); 525void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 526void nvme_notify_new_controller(struct nvme_controller *ctrlr); 527 528void nvme_ctrlr_intx_handler(void *arg); 529 530#endif /* __NVME_PRIVATE_H__ */ 531