nvme_private.h revision 256151
1/*- 2 * Copyright (C) 2012-2013 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 256151 2013-10-08 15:44:04Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/bio.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/mutex.h> 39#include <sys/rman.h> 40#include <sys/systm.h> 41#include <sys/taskqueue.h> 42 43#include <vm/uma.h> 44 45#include <machine/bus.h> 46 47#include "nvme.h" 48 49#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51MALLOC_DECLARE(M_NVME); 52 53#define CHATHAM2 54 55#ifdef CHATHAM2 56#define CHATHAM_PCI_ID 0x20118086 57#define CHATHAM_CONTROL_BAR 0 58#endif 59 60#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 61#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 62 63/* 64 * For commands requiring more than 2 PRP entries, one PRP will be 65 * embedded in the command (prp1), and the rest of the PRP entries 66 * will be in a list pointed to by the command (prp2). This means 67 * that real max number of PRP entries we support is 32+1, which 68 * results in a max xfer size of 32*PAGE_SIZE. 69 */ 70#define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 71 72#define NVME_ADMIN_TRACKERS (16) 73#define NVME_ADMIN_ENTRIES (128) 74/* min and max are defined in admin queue attributes section of spec */ 75#define NVME_MIN_ADMIN_ENTRIES (2) 76#define NVME_MAX_ADMIN_ENTRIES (4096) 77 78/* 79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 81 * will allow outstanding on an I/O qpair at any time. The only advantage in 82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 83 * the contents of the submission and completion queues, it will show a longer 84 * history of data. 85 */ 86#define NVME_IO_ENTRIES (256) 87#define NVME_IO_TRACKERS (128) 88#define NVME_MIN_IO_TRACKERS (4) 89#define NVME_MAX_IO_TRACKERS (1024) 90 91/* 92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 93 * for each controller. 94 */ 95 96#define NVME_INT_COAL_TIME (0) /* disabled */ 97#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 98 99#define NVME_MAX_NAMESPACES (16) 100#define NVME_MAX_CONSUMERS (2) 101#define NVME_MAX_ASYNC_EVENTS (8) 102 103#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 104#define NVME_MIN_TIMEOUT_PERIOD (5) 105#define NVME_MAX_TIMEOUT_PERIOD (120) 106 107#define NVME_DEFAULT_RETRY_COUNT (4) 108 109/* Maximum log page size to fetch for AERs. */ 110#define NVME_MAX_AER_LOG_SIZE (4096) 111 112/* 113 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 114 * it. 115 */ 116#ifndef CACHE_LINE_SIZE 117#define CACHE_LINE_SIZE (64) 118#endif 119 120/* 121 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 122 * support and the bus_dmamap_load_bio API are available on the target 123 * kernel. This will ease porting back to earlier stable branches at a 124 * later point. 125 */ 126#ifdef BIO_UNMAPPED 127#define NVME_UNMAPPED_BIO_SUPPORT 128#endif 129 130extern uma_zone_t nvme_request_zone; 131extern int32_t nvme_retry_count; 132 133struct nvme_completion_poll_status { 134 135 struct nvme_completion cpl; 136 boolean_t done; 137}; 138 139#define NVME_REQUEST_VADDR 1 140#define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 141#define NVME_REQUEST_UIO 3 142#ifdef NVME_UNMAPPED_BIO_SUPPORT 143#define NVME_REQUEST_BIO 4 144#endif 145 146struct nvme_request { 147 148 struct nvme_command cmd; 149 struct nvme_qpair *qpair; 150 union { 151 void *payload; 152 struct bio *bio; 153 } u; 154 uint32_t type; 155 uint32_t payload_size; 156 boolean_t timeout; 157 nvme_cb_fn_t cb_fn; 158 void *cb_arg; 159 int32_t retries; 160 STAILQ_ENTRY(nvme_request) stailq; 161}; 162 163struct nvme_async_event_request { 164 165 struct nvme_controller *ctrlr; 166 struct nvme_request *req; 167 struct nvme_completion cpl; 168 uint32_t log_page_id; 169 uint32_t log_page_size; 170 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 171}; 172 173struct nvme_tracker { 174 175 TAILQ_ENTRY(nvme_tracker) tailq; 176 struct nvme_request *req; 177 struct nvme_qpair *qpair; 178 struct callout timer; 179 bus_dmamap_t payload_dma_map; 180 uint16_t cid; 181 182 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 183 bus_addr_t prp_bus_addr; 184 bus_dmamap_t prp_dma_map; 185}; 186 187struct nvme_qpair { 188 189 struct nvme_controller *ctrlr; 190 uint32_t id; 191 uint32_t phase; 192 193 uint16_t vector; 194 int rid; 195 struct resource *res; 196 void *tag; 197 198 uint32_t num_entries; 199 uint32_t num_trackers; 200 uint32_t sq_tdbl_off; 201 uint32_t cq_hdbl_off; 202 203 uint32_t sq_head; 204 uint32_t sq_tail; 205 uint32_t cq_head; 206 207 int64_t num_cmds; 208 int64_t num_intr_handler_calls; 209 210 struct nvme_command *cmd; 211 struct nvme_completion *cpl; 212 213 bus_dma_tag_t dma_tag; 214 215 bus_dmamap_t cmd_dma_map; 216 uint64_t cmd_bus_addr; 217 218 bus_dmamap_t cpl_dma_map; 219 uint64_t cpl_bus_addr; 220 221 TAILQ_HEAD(, nvme_tracker) free_tr; 222 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 223 STAILQ_HEAD(, nvme_request) queued_req; 224 225 struct nvme_tracker **act_tr; 226 227 boolean_t is_enabled; 228 229 struct mtx lock __aligned(CACHE_LINE_SIZE); 230 231} __aligned(CACHE_LINE_SIZE); 232 233struct nvme_namespace { 234 235 struct nvme_controller *ctrlr; 236 struct nvme_namespace_data data; 237 uint16_t id; 238 uint16_t flags; 239 struct cdev *cdev; 240 void *cons_cookie[NVME_MAX_CONSUMERS]; 241 uint32_t stripesize; 242 struct mtx lock; 243}; 244 245/* 246 * One of these per allocated PCI device. 247 */ 248struct nvme_controller { 249 250 device_t dev; 251 252 struct mtx lock; 253 254 uint32_t ready_timeout_in_ms; 255 256 bus_space_tag_t bus_tag; 257 bus_space_handle_t bus_handle; 258 int resource_id; 259 struct resource *resource; 260 261 /* 262 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 263 * separate from the control registers which are in BAR 0/1. These 264 * members track the mapping of BAR 4/5 for that reason. 265 */ 266 int bar4_resource_id; 267 struct resource *bar4_resource; 268 269#ifdef CHATHAM2 270 bus_space_tag_t chatham_bus_tag; 271 bus_space_handle_t chatham_bus_handle; 272 int chatham_resource_id; 273 struct resource *chatham_resource; 274#endif 275 276 uint32_t msix_enabled; 277 uint32_t force_intx; 278 uint32_t enable_aborts; 279 280 uint32_t num_io_queues; 281 boolean_t per_cpu_io_queues; 282 283 /* Fields for tracking progress during controller initialization. */ 284 struct intr_config_hook config_hook; 285 uint32_t ns_identified; 286 uint32_t queues_created; 287 288 struct task reset_task; 289 struct task fail_req_task; 290 struct taskqueue *taskqueue; 291 292 /* For shared legacy interrupt. */ 293 int rid; 294 struct resource *res; 295 void *tag; 296 297 bus_dma_tag_t hw_desc_tag; 298 bus_dmamap_t hw_desc_map; 299 300 /** maximum i/o size in bytes */ 301 uint32_t max_xfer_size; 302 303 /** minimum page size supported by this controller in bytes */ 304 uint32_t min_page_size; 305 306 /** interrupt coalescing time period (in microseconds) */ 307 uint32_t int_coal_time; 308 309 /** interrupt coalescing threshold */ 310 uint32_t int_coal_threshold; 311 312 /** timeout period in seconds */ 313 uint32_t timeout_period; 314 315 struct nvme_qpair adminq; 316 struct nvme_qpair *ioq; 317 318 struct nvme_registers *regs; 319 320 struct nvme_controller_data cdata; 321 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 322 323 struct cdev *cdev; 324 325 uint32_t num_aers; 326 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 327 328 void *cons_cookie[NVME_MAX_CONSUMERS]; 329 330 uint32_t is_resetting; 331 332 boolean_t is_failed; 333 STAILQ_HEAD(, nvme_request) fail_req; 334 335#ifdef CHATHAM2 336 uint64_t chatham_size; 337 uint64_t chatham_lbas; 338#endif 339}; 340 341#define nvme_mmio_offsetof(reg) \ 342 offsetof(struct nvme_registers, reg) 343 344#define nvme_mmio_read_4(sc, reg) \ 345 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 346 nvme_mmio_offsetof(reg)) 347 348#define nvme_mmio_write_4(sc, reg, val) \ 349 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 350 nvme_mmio_offsetof(reg), val) 351 352#define nvme_mmio_write_8(sc, reg, val) \ 353 do { \ 354 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 355 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 356 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 357 nvme_mmio_offsetof(reg)+4, \ 358 (val & 0xFFFFFFFF00000000UL) >> 32); \ 359 } while (0); 360 361#ifdef CHATHAM2 362#define chatham_read_4(softc, reg) \ 363 bus_space_read_4((softc)->chatham_bus_tag, \ 364 (softc)->chatham_bus_handle, reg) 365 366#define chatham_write_8(sc, reg, val) \ 367 do { \ 368 bus_space_write_4((sc)->chatham_bus_tag, \ 369 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 370 bus_space_write_4((sc)->chatham_bus_tag, \ 371 (sc)->chatham_bus_handle, reg+4, \ 372 (val & 0xFFFFFFFF00000000UL) >> 32); \ 373 } while (0); 374 375#endif /* CHATHAM2 */ 376 377#if __FreeBSD_version < 800054 378#define wmb() __asm volatile("sfence" ::: "memory") 379#define mb() __asm volatile("mfence" ::: "memory") 380#endif 381 382#define nvme_printf(ctrlr, fmt, args...) \ 383 device_printf(ctrlr->dev, fmt, ##args) 384 385void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 386 387void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 388 void *payload, 389 nvme_cb_fn_t cb_fn, void *cb_arg); 390void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 391 uint16_t nsid, void *payload, 392 nvme_cb_fn_t cb_fn, void *cb_arg); 393void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 394 uint32_t microseconds, 395 uint32_t threshold, 396 nvme_cb_fn_t cb_fn, 397 void *cb_arg); 398void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 399 struct nvme_error_information_entry *payload, 400 uint32_t num_entries, /* 0 = max */ 401 nvme_cb_fn_t cb_fn, 402 void *cb_arg); 403void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 404 uint32_t nsid, 405 struct nvme_health_information_page *payload, 406 nvme_cb_fn_t cb_fn, 407 void *cb_arg); 408void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 409 struct nvme_firmware_page *payload, 410 nvme_cb_fn_t cb_fn, 411 void *cb_arg); 412void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 413 struct nvme_qpair *io_que, uint16_t vector, 414 nvme_cb_fn_t cb_fn, void *cb_arg); 415void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 416 struct nvme_qpair *io_que, 417 nvme_cb_fn_t cb_fn, void *cb_arg); 418void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 419 struct nvme_qpair *io_que, 420 nvme_cb_fn_t cb_fn, void *cb_arg); 421void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 422 struct nvme_qpair *io_que, 423 nvme_cb_fn_t cb_fn, void *cb_arg); 424void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 425 uint32_t num_queues, nvme_cb_fn_t cb_fn, 426 void *cb_arg); 427void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 428 union nvme_critical_warning_state state, 429 nvme_cb_fn_t cb_fn, void *cb_arg); 430void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 431 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 432 433void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 434 435int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 436void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 437void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 438int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 439void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 440/* ctrlr defined as void * to allow use with config_intrhook. */ 441void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 442void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 443 struct nvme_request *req); 444void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 445 struct nvme_request *req); 446void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 447 struct nvme_request *req); 448 449void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 450 uint16_t vector, uint32_t num_entries, 451 uint32_t num_trackers, 452 struct nvme_controller *ctrlr); 453void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 454 struct nvme_tracker *tr); 455void nvme_qpair_process_completions(struct nvme_qpair *qpair); 456void nvme_qpair_submit_request(struct nvme_qpair *qpair, 457 struct nvme_request *req); 458void nvme_qpair_reset(struct nvme_qpair *qpair); 459void nvme_qpair_fail(struct nvme_qpair *qpair); 460void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 461 struct nvme_request *req, 462 uint32_t sct, uint32_t sc, 463 boolean_t print_on_error); 464 465void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 466void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 467void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 468 469void nvme_io_qpair_enable(struct nvme_qpair *qpair); 470void nvme_io_qpair_disable(struct nvme_qpair *qpair); 471void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 472 473int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 474 struct nvme_controller *ctrlr); 475void nvme_ns_destruct(struct nvme_namespace *ns); 476 477void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 478 479void nvme_dump_command(struct nvme_command *cmd); 480void nvme_dump_completion(struct nvme_completion *cpl); 481 482static __inline void 483nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 484{ 485 uint64_t *bus_addr = (uint64_t *)arg; 486 487 *bus_addr = seg[0].ds_addr; 488} 489 490static __inline struct nvme_request * 491_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 492{ 493 struct nvme_request *req; 494 495 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 496 if (req != NULL) { 497 req->cb_fn = cb_fn; 498 req->cb_arg = cb_arg; 499 req->timeout = TRUE; 500 } 501 return (req); 502} 503 504static __inline struct nvme_request * 505nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 506 nvme_cb_fn_t cb_fn, void *cb_arg) 507{ 508 struct nvme_request *req; 509 510 req = _nvme_allocate_request(cb_fn, cb_arg); 511 if (req != NULL) { 512 req->type = NVME_REQUEST_VADDR; 513 req->u.payload = payload; 514 req->payload_size = payload_size; 515 } 516 return (req); 517} 518 519static __inline struct nvme_request * 520nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 521{ 522 struct nvme_request *req; 523 524 req = _nvme_allocate_request(cb_fn, cb_arg); 525 if (req != NULL) 526 req->type = NVME_REQUEST_NULL; 527 return (req); 528} 529 530static __inline struct nvme_request * 531nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 532{ 533 struct nvme_request *req; 534 535 req = _nvme_allocate_request(cb_fn, cb_arg); 536 if (req != NULL) { 537#ifdef NVME_UNMAPPED_BIO_SUPPORT 538 req->type = NVME_REQUEST_BIO; 539 req->u.bio = bio; 540#else 541 req->type = NVME_REQUEST_VADDR; 542 req->u.payload = bio->bio_data; 543 req->payload_size = bio->bio_bcount; 544#endif 545 } 546 return (req); 547} 548 549#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 550 551void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 552 const struct nvme_completion *async_cpl, 553 uint32_t log_page_id, void *log_page_buffer, 554 uint32_t log_page_size); 555void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 556 557#endif /* __NVME_PRIVATE_H__ */ 558