nvme_private.h revision 248913
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 248913 2013-03-29 20:34:28Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/bus.h> 34#include <sys/kernel.h> 35#include <sys/lock.h> 36#include <sys/malloc.h> 37#include <sys/mutex.h> 38#include <sys/rman.h> 39#include <sys/systm.h> 40#include <sys/taskqueue.h> 41 42#include <vm/uma.h> 43 44#include <machine/bus.h> 45 46#include "nvme.h" 47 48#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 49 50MALLOC_DECLARE(M_NVME); 51 52#define CHATHAM2 53 54#ifdef CHATHAM2 55#define CHATHAM_PCI_ID 0x20118086 56#define CHATHAM_CONTROL_BAR 0 57#endif 58 59#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 60#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 61 62#define NVME_MAX_PRP_LIST_ENTRIES (32) 63 64/* 65 * For commands requiring more than 2 PRP entries, one PRP will be 66 * embedded in the command (prp1), and the rest of the PRP entries 67 * will be in a list pointed to by the command (prp2). This means 68 * that real max number of PRP entries we support is 32+1, which 69 * results in a max xfer size of 32*PAGE_SIZE. 70 */ 71#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 72 73#define NVME_ADMIN_TRACKERS (16) 74#define NVME_ADMIN_ENTRIES (128) 75/* min and max are defined in admin queue attributes section of spec */ 76#define NVME_MIN_ADMIN_ENTRIES (2) 77#define NVME_MAX_ADMIN_ENTRIES (4096) 78 79/* 80 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 81 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 82 * will allow outstanding on an I/O qpair at any time. The only advantage in 83 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 84 * the contents of the submission and completion queues, it will show a longer 85 * history of data. 86 */ 87#define NVME_IO_ENTRIES (256) 88#define NVME_IO_TRACKERS (128) 89#define NVME_MIN_IO_TRACKERS (4) 90#define NVME_MAX_IO_TRACKERS (1024) 91 92/* 93 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 94 * for each controller. 95 */ 96 97#define NVME_INT_COAL_TIME (0) /* disabled */ 98#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 99 100#define NVME_MAX_NAMESPACES (16) 101#define NVME_MAX_CONSUMERS (2) 102#define NVME_MAX_ASYNC_EVENTS (8) 103 104#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 105#define NVME_MIN_TIMEOUT_PERIOD (5) 106#define NVME_MAX_TIMEOUT_PERIOD (120) 107 108#define NVME_DEFAULT_RETRY_COUNT (4) 109 110/* Maximum log page size to fetch for AERs. */ 111#define NVME_MAX_AER_LOG_SIZE (4096) 112 113#ifndef CACHE_LINE_SIZE 114#define CACHE_LINE_SIZE (64) 115#endif 116 117extern uma_zone_t nvme_request_zone; 118extern int32_t nvme_retry_count; 119 120struct nvme_completion_poll_status { 121 122 struct nvme_completion cpl; 123 boolean_t done; 124}; 125 126#define NVME_REQUEST_VADDR 1 127#define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 128#define NVME_REQUEST_UIO 3 129 130struct nvme_request { 131 132 struct nvme_command cmd; 133 struct nvme_qpair *qpair; 134 union { 135 void *payload; 136 struct uio *uio; 137 } u; 138 uint32_t type; 139 uint32_t payload_size; 140 boolean_t timeout; 141 nvme_cb_fn_t cb_fn; 142 void *cb_arg; 143 int32_t retries; 144 STAILQ_ENTRY(nvme_request) stailq; 145}; 146 147struct nvme_async_event_request { 148 149 struct nvme_controller *ctrlr; 150 struct nvme_request *req; 151 struct nvme_completion cpl; 152 uint32_t log_page_id; 153 uint32_t log_page_size; 154 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 155}; 156 157struct nvme_tracker { 158 159 TAILQ_ENTRY(nvme_tracker) tailq; 160 struct nvme_request *req; 161 struct nvme_qpair *qpair; 162 struct callout timer; 163 bus_dmamap_t payload_dma_map; 164 uint16_t cid; 165 166 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 167 bus_addr_t prp_bus_addr; 168 bus_dmamap_t prp_dma_map; 169}; 170 171struct nvme_qpair { 172 173 struct nvme_controller *ctrlr; 174 uint32_t id; 175 uint32_t phase; 176 177 uint16_t vector; 178 int rid; 179 struct resource *res; 180 void *tag; 181 182 uint32_t max_xfer_size; 183 uint32_t num_entries; 184 uint32_t num_trackers; 185 uint32_t sq_tdbl_off; 186 uint32_t cq_hdbl_off; 187 188 uint32_t sq_head; 189 uint32_t sq_tail; 190 uint32_t cq_head; 191 192 int64_t num_cmds; 193 int64_t num_intr_handler_calls; 194 195 struct nvme_command *cmd; 196 struct nvme_completion *cpl; 197 198 bus_dma_tag_t dma_tag; 199 200 bus_dmamap_t cmd_dma_map; 201 uint64_t cmd_bus_addr; 202 203 bus_dmamap_t cpl_dma_map; 204 uint64_t cpl_bus_addr; 205 206 TAILQ_HEAD(, nvme_tracker) free_tr; 207 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 208 STAILQ_HEAD(, nvme_request) queued_req; 209 210 struct nvme_tracker **act_tr; 211 212 boolean_t is_enabled; 213 214 struct mtx lock __aligned(CACHE_LINE_SIZE); 215 216} __aligned(CACHE_LINE_SIZE); 217 218struct nvme_namespace { 219 220 struct nvme_controller *ctrlr; 221 struct nvme_namespace_data data; 222 uint16_t id; 223 uint16_t flags; 224 struct cdev *cdev; 225 void *cons_cookie[NVME_MAX_CONSUMERS]; 226}; 227 228/* 229 * One of these per allocated PCI device. 230 */ 231struct nvme_controller { 232 233 device_t dev; 234 235 uint32_t ready_timeout_in_ms; 236 237 bus_space_tag_t bus_tag; 238 bus_space_handle_t bus_handle; 239 int resource_id; 240 struct resource *resource; 241 242 /* 243 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 244 * separate from the control registers which are in BAR 0/1. These 245 * members track the mapping of BAR 4/5 for that reason. 246 */ 247 int bar4_resource_id; 248 struct resource *bar4_resource; 249 250#ifdef CHATHAM2 251 bus_space_tag_t chatham_bus_tag; 252 bus_space_handle_t chatham_bus_handle; 253 int chatham_resource_id; 254 struct resource *chatham_resource; 255#endif 256 257 uint32_t msix_enabled; 258 uint32_t force_intx; 259 uint32_t enable_aborts; 260 261 uint32_t num_io_queues; 262 boolean_t per_cpu_io_queues; 263 264 /* Fields for tracking progress during controller initialization. */ 265 struct intr_config_hook config_hook; 266 uint32_t ns_identified; 267 uint32_t queues_created; 268 269 struct task reset_task; 270 struct task fail_req_task; 271 struct taskqueue *taskqueue; 272 273 /* For shared legacy interrupt. */ 274 int rid; 275 struct resource *res; 276 void *tag; 277 278 bus_dma_tag_t hw_desc_tag; 279 bus_dmamap_t hw_desc_map; 280 281 /** maximum i/o size in bytes */ 282 uint32_t max_xfer_size; 283 284 /** minimum page size supported by this controller in bytes */ 285 uint32_t min_page_size; 286 287 /** interrupt coalescing time period (in microseconds) */ 288 uint32_t int_coal_time; 289 290 /** interrupt coalescing threshold */ 291 uint32_t int_coal_threshold; 292 293 /** timeout period in seconds */ 294 uint32_t timeout_period; 295 296 struct nvme_qpair adminq; 297 struct nvme_qpair *ioq; 298 299 struct nvme_registers *regs; 300 301 struct nvme_controller_data cdata; 302 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 303 304 struct cdev *cdev; 305 306 uint32_t num_aers; 307 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 308 309 void *cons_cookie[NVME_MAX_CONSUMERS]; 310 311 uint32_t is_resetting; 312 313 struct mtx fail_req_lock; 314 boolean_t is_failed; 315 STAILQ_HEAD(, nvme_request) fail_req; 316 317#ifdef CHATHAM2 318 uint64_t chatham_size; 319 uint64_t chatham_lbas; 320#endif 321}; 322 323#define nvme_mmio_offsetof(reg) \ 324 offsetof(struct nvme_registers, reg) 325 326#define nvme_mmio_read_4(sc, reg) \ 327 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 328 nvme_mmio_offsetof(reg)) 329 330#define nvme_mmio_write_4(sc, reg, val) \ 331 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 332 nvme_mmio_offsetof(reg), val) 333 334#define nvme_mmio_write_8(sc, reg, val) \ 335 do { \ 336 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 337 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 338 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 339 nvme_mmio_offsetof(reg)+4, \ 340 (val & 0xFFFFFFFF00000000UL) >> 32); \ 341 } while (0); 342 343#ifdef CHATHAM2 344#define chatham_read_4(softc, reg) \ 345 bus_space_read_4((softc)->chatham_bus_tag, \ 346 (softc)->chatham_bus_handle, reg) 347 348#define chatham_write_8(sc, reg, val) \ 349 do { \ 350 bus_space_write_4((sc)->chatham_bus_tag, \ 351 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 352 bus_space_write_4((sc)->chatham_bus_tag, \ 353 (sc)->chatham_bus_handle, reg+4, \ 354 (val & 0xFFFFFFFF00000000UL) >> 32); \ 355 } while (0); 356 357#endif /* CHATHAM2 */ 358 359#if __FreeBSD_version < 800054 360#define wmb() __asm volatile("sfence" ::: "memory") 361#define mb() __asm volatile("mfence" ::: "memory") 362#endif 363 364#define nvme_printf(ctrlr, fmt, args...) \ 365 device_printf(ctrlr->dev, fmt, ##args) 366 367void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 368 369void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 370 void *payload, 371 nvme_cb_fn_t cb_fn, void *cb_arg); 372void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 373 uint16_t nsid, void *payload, 374 nvme_cb_fn_t cb_fn, void *cb_arg); 375void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 376 uint32_t microseconds, 377 uint32_t threshold, 378 nvme_cb_fn_t cb_fn, 379 void *cb_arg); 380void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 381 struct nvme_error_information_entry *payload, 382 uint32_t num_entries, /* 0 = max */ 383 nvme_cb_fn_t cb_fn, 384 void *cb_arg); 385void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 386 uint32_t nsid, 387 struct nvme_health_information_page *payload, 388 nvme_cb_fn_t cb_fn, 389 void *cb_arg); 390void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 391 struct nvme_firmware_page *payload, 392 nvme_cb_fn_t cb_fn, 393 void *cb_arg); 394void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 395 struct nvme_qpair *io_que, uint16_t vector, 396 nvme_cb_fn_t cb_fn, void *cb_arg); 397void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 398 struct nvme_qpair *io_que, 399 nvme_cb_fn_t cb_fn, void *cb_arg); 400void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 401 struct nvme_qpair *io_que, 402 nvme_cb_fn_t cb_fn, void *cb_arg); 403void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 404 struct nvme_qpair *io_que, 405 nvme_cb_fn_t cb_fn, void *cb_arg); 406void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 407 uint32_t num_queues, nvme_cb_fn_t cb_fn, 408 void *cb_arg); 409void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 410 union nvme_critical_warning_state state, 411 nvme_cb_fn_t cb_fn, void *cb_arg); 412void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 413 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 414 415void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 416 int error); 417void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 418 bus_size_t mapsize, int error); 419void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 420 421int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 422void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 423int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 424void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 425/* ctrlr defined as void * to allow use with config_intrhook. */ 426void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 427void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 428 struct nvme_request *req); 429void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 430 struct nvme_request *req); 431void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 432 struct nvme_request *req); 433 434void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 435 uint16_t vector, uint32_t num_entries, 436 uint32_t num_trackers, uint32_t max_xfer_size, 437 struct nvme_controller *ctrlr); 438void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 439 struct nvme_tracker *tr); 440void nvme_qpair_process_completions(struct nvme_qpair *qpair); 441void nvme_qpair_submit_request(struct nvme_qpair *qpair, 442 struct nvme_request *req); 443void nvme_qpair_reset(struct nvme_qpair *qpair); 444void nvme_qpair_fail(struct nvme_qpair *qpair); 445void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 446 struct nvme_request *req, 447 uint32_t sct, uint32_t sc, 448 boolean_t print_on_error); 449 450void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 451void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 452void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 453 454void nvme_io_qpair_enable(struct nvme_qpair *qpair); 455void nvme_io_qpair_disable(struct nvme_qpair *qpair); 456void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 457 458int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 459 struct nvme_controller *ctrlr); 460void nvme_ns_destruct(struct nvme_namespace *ns); 461 462int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 463 464void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 465 466void nvme_dump_command(struct nvme_command *cmd); 467void nvme_dump_completion(struct nvme_completion *cpl); 468 469static __inline void 470nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 471{ 472 uint64_t *bus_addr = (uint64_t *)arg; 473 474 *bus_addr = seg[0].ds_addr; 475} 476 477static __inline struct nvme_request * 478_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 479{ 480 struct nvme_request *req; 481 482 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 483 if (req != NULL) { 484 req->cb_fn = cb_fn; 485 req->cb_arg = cb_arg; 486 req->timeout = TRUE; 487 } 488 return (req); 489} 490 491static __inline struct nvme_request * 492nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 493 nvme_cb_fn_t cb_fn, void *cb_arg) 494{ 495 struct nvme_request *req; 496 497 req = _nvme_allocate_request(cb_fn, cb_arg); 498 if (req != NULL) { 499 req->type = NVME_REQUEST_VADDR; 500 req->u.payload = payload; 501 req->payload_size = payload_size; 502 } 503 return (req); 504} 505 506static __inline struct nvme_request * 507nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 508{ 509 struct nvme_request *req; 510 511 req = _nvme_allocate_request(cb_fn, cb_arg); 512 if (req != NULL) 513 req->type = NVME_REQUEST_NULL; 514 return (req); 515} 516 517static __inline struct nvme_request * 518nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 519{ 520 struct nvme_request *req; 521 522 req = _nvme_allocate_request(cb_fn, cb_arg); 523 if (req != NULL) { 524 req->type = NVME_REQUEST_UIO; 525 req->u.uio = uio; 526 } 527 return (req); 528} 529 530#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 531 532void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 533 const struct nvme_completion *async_cpl, 534 uint32_t log_page_id, void *log_page_buffer, 535 uint32_t log_page_size); 536void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 537 538#endif /* __NVME_PRIVATE_H__ */ 539