nvme_private.h revision 248763
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 248763 2013-03-26 21:19:26Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/malloc.h> 36#include <sys/mutex.h> 37#include <sys/rman.h> 38#include <sys/systm.h> 39#include <sys/taskqueue.h> 40 41#include <vm/uma.h> 42 43#include <machine/bus.h> 44 45#include "nvme.h" 46 47#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 48 49MALLOC_DECLARE(M_NVME); 50 51#define CHATHAM2 52 53#ifdef CHATHAM2 54#define CHATHAM_PCI_ID 0x20118086 55#define CHATHAM_CONTROL_BAR 0 56#endif 57 58#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 59#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 60 61#define NVME_MAX_PRP_LIST_ENTRIES (32) 62 63/* 64 * For commands requiring more than 2 PRP entries, one PRP will be 65 * embedded in the command (prp1), and the rest of the PRP entries 66 * will be in a list pointed to by the command (prp2). This means 67 * that real max number of PRP entries we support is 32+1, which 68 * results in a max xfer size of 32*PAGE_SIZE. 69 */ 70#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 71 72#define NVME_ADMIN_TRACKERS (16) 73#define NVME_ADMIN_ENTRIES (128) 74/* min and max are defined in admin queue attributes section of spec */ 75#define NVME_MIN_ADMIN_ENTRIES (2) 76#define NVME_MAX_ADMIN_ENTRIES (4096) 77 78/* 79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 81 * will allow outstanding on an I/O qpair at any time. The only advantage in 82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 83 * the contents of the submission and completion queues, it will show a longer 84 * history of data. 85 */ 86#define NVME_IO_ENTRIES (256) 87#define NVME_IO_TRACKERS (128) 88#define NVME_MIN_IO_TRACKERS (16) 89#define NVME_MAX_IO_TRACKERS (1024) 90 91/* 92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 93 * for each controller. 94 */ 95 96#define NVME_INT_COAL_TIME (0) /* disabled */ 97#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 98 99#define NVME_MAX_NAMESPACES (16) 100#define NVME_MAX_CONSUMERS (2) 101#define NVME_MAX_ASYNC_EVENTS (8) 102 103#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 104#define NVME_MIN_TIMEOUT_PERIOD (5) 105#define NVME_MAX_TIMEOUT_PERIOD (120) 106 107#define NVME_DEFAULT_RETRY_COUNT (4) 108 109/* Maximum log page size to fetch for AERs. */ 110#define NVME_MAX_AER_LOG_SIZE (4096) 111 112#ifndef CACHE_LINE_SIZE 113#define CACHE_LINE_SIZE (64) 114#endif 115 116extern uma_zone_t nvme_request_zone; 117extern int32_t nvme_retry_count; 118 119struct nvme_request { 120 121 struct nvme_command cmd; 122 void *payload; 123 uint32_t payload_size; 124 boolean_t timeout; 125 struct uio *uio; 126 nvme_cb_fn_t cb_fn; 127 void *cb_arg; 128 int32_t retries; 129 STAILQ_ENTRY(nvme_request) stailq; 130}; 131 132struct nvme_async_event_request { 133 134 struct nvme_controller *ctrlr; 135 struct nvme_request *req; 136 struct nvme_completion cpl; 137 uint32_t log_page_id; 138 uint32_t log_page_size; 139 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 140}; 141 142struct nvme_tracker { 143 144 TAILQ_ENTRY(nvme_tracker) tailq; 145 struct nvme_request *req; 146 struct nvme_qpair *qpair; 147 struct callout timer; 148 bus_dmamap_t payload_dma_map; 149 uint16_t cid; 150 151 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 152 bus_addr_t prp_bus_addr; 153 bus_dmamap_t prp_dma_map; 154}; 155 156struct nvme_qpair { 157 158 struct nvme_controller *ctrlr; 159 uint32_t id; 160 uint32_t phase; 161 162 uint16_t vector; 163 int rid; 164 struct resource *res; 165 void *tag; 166 167 uint32_t max_xfer_size; 168 uint32_t num_entries; 169 uint32_t num_trackers; 170 uint32_t sq_tdbl_off; 171 uint32_t cq_hdbl_off; 172 173 uint32_t sq_head; 174 uint32_t sq_tail; 175 uint32_t cq_head; 176 177 int64_t num_cmds; 178 int64_t num_intr_handler_calls; 179 180 struct nvme_command *cmd; 181 struct nvme_completion *cpl; 182 183 bus_dma_tag_t dma_tag; 184 185 bus_dmamap_t cmd_dma_map; 186 uint64_t cmd_bus_addr; 187 188 bus_dmamap_t cpl_dma_map; 189 uint64_t cpl_bus_addr; 190 191 TAILQ_HEAD(, nvme_tracker) free_tr; 192 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 193 STAILQ_HEAD(, nvme_request) queued_req; 194 195 struct nvme_tracker **act_tr; 196 197 boolean_t is_enabled; 198 199 struct mtx lock __aligned(CACHE_LINE_SIZE); 200 201} __aligned(CACHE_LINE_SIZE); 202 203struct nvme_namespace { 204 205 struct nvme_controller *ctrlr; 206 struct nvme_namespace_data data; 207 uint16_t id; 208 uint16_t flags; 209 struct cdev *cdev; 210 void *cons_cookie[NVME_MAX_CONSUMERS]; 211}; 212 213/* 214 * One of these per allocated PCI device. 215 */ 216struct nvme_controller { 217 218 device_t dev; 219 220 uint32_t ready_timeout_in_ms; 221 222 bus_space_tag_t bus_tag; 223 bus_space_handle_t bus_handle; 224 int resource_id; 225 struct resource *resource; 226 227 /* 228 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 229 * separate from the control registers which are in BAR 0/1. These 230 * members track the mapping of BAR 4/5 for that reason. 231 */ 232 int bar4_resource_id; 233 struct resource *bar4_resource; 234 235#ifdef CHATHAM2 236 bus_space_tag_t chatham_bus_tag; 237 bus_space_handle_t chatham_bus_handle; 238 int chatham_resource_id; 239 struct resource *chatham_resource; 240#endif 241 242 uint32_t msix_enabled; 243 uint32_t force_intx; 244 uint32_t enable_aborts; 245 246 uint32_t num_io_queues; 247 boolean_t per_cpu_io_queues; 248 249 /* Fields for tracking progress during controller initialization. */ 250 struct intr_config_hook config_hook; 251 uint32_t ns_identified; 252 uint32_t queues_created; 253 struct task reset_task; 254 struct taskqueue *taskqueue; 255 256 /* For shared legacy interrupt. */ 257 int rid; 258 struct resource *res; 259 void *tag; 260 261 bus_dma_tag_t hw_desc_tag; 262 bus_dmamap_t hw_desc_map; 263 264 /** maximum i/o size in bytes */ 265 uint32_t max_xfer_size; 266 267 /** minimum page size supported by this controller in bytes */ 268 uint32_t min_page_size; 269 270 /** interrupt coalescing time period (in microseconds) */ 271 uint32_t int_coal_time; 272 273 /** interrupt coalescing threshold */ 274 uint32_t int_coal_threshold; 275 276 /** timeout period in seconds */ 277 uint32_t timeout_period; 278 279 struct nvme_qpair adminq; 280 struct nvme_qpair *ioq; 281 282 struct nvme_registers *regs; 283 284 struct nvme_controller_data cdata; 285 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 286 287 struct cdev *cdev; 288 289 uint32_t num_aers; 290 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 291 292 void *cons_cookie[NVME_MAX_CONSUMERS]; 293 294 uint32_t is_resetting; 295 296#ifdef CHATHAM2 297 uint64_t chatham_size; 298 uint64_t chatham_lbas; 299#endif 300}; 301 302#define nvme_mmio_offsetof(reg) \ 303 offsetof(struct nvme_registers, reg) 304 305#define nvme_mmio_read_4(sc, reg) \ 306 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 307 nvme_mmio_offsetof(reg)) 308 309#define nvme_mmio_write_4(sc, reg, val) \ 310 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 311 nvme_mmio_offsetof(reg), val) 312 313#define nvme_mmio_write_8(sc, reg, val) \ 314 do { \ 315 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 316 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 317 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 318 nvme_mmio_offsetof(reg)+4, \ 319 (val & 0xFFFFFFFF00000000UL) >> 32); \ 320 } while (0); 321 322#ifdef CHATHAM2 323#define chatham_read_4(softc, reg) \ 324 bus_space_read_4((softc)->chatham_bus_tag, \ 325 (softc)->chatham_bus_handle, reg) 326 327#define chatham_write_8(sc, reg, val) \ 328 do { \ 329 bus_space_write_4((sc)->chatham_bus_tag, \ 330 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 331 bus_space_write_4((sc)->chatham_bus_tag, \ 332 (sc)->chatham_bus_handle, reg+4, \ 333 (val & 0xFFFFFFFF00000000UL) >> 32); \ 334 } while (0); 335 336#endif /* CHATHAM2 */ 337 338#if __FreeBSD_version < 800054 339#define wmb() __asm volatile("sfence" ::: "memory") 340#define mb() __asm volatile("mfence" ::: "memory") 341#endif 342 343void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 344 345void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 346 void *payload, 347 nvme_cb_fn_t cb_fn, void *cb_arg); 348void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 349 uint16_t nsid, void *payload, 350 nvme_cb_fn_t cb_fn, void *cb_arg); 351void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 352 uint32_t microseconds, 353 uint32_t threshold, 354 nvme_cb_fn_t cb_fn, 355 void *cb_arg); 356void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 357 struct nvme_error_information_entry *payload, 358 uint32_t num_entries, /* 0 = max */ 359 nvme_cb_fn_t cb_fn, 360 void *cb_arg); 361void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 362 uint32_t nsid, 363 struct nvme_health_information_page *payload, 364 nvme_cb_fn_t cb_fn, 365 void *cb_arg); 366void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 367 struct nvme_firmware_page *payload, 368 nvme_cb_fn_t cb_fn, 369 void *cb_arg); 370void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 371 struct nvme_qpair *io_que, uint16_t vector, 372 nvme_cb_fn_t cb_fn, void *cb_arg); 373void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 374 struct nvme_qpair *io_que, 375 nvme_cb_fn_t cb_fn, void *cb_arg); 376void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 377 struct nvme_qpair *io_que, 378 nvme_cb_fn_t cb_fn, void *cb_arg); 379void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 380 struct nvme_qpair *io_que, 381 nvme_cb_fn_t cb_fn, void *cb_arg); 382void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 383 uint32_t num_queues, nvme_cb_fn_t cb_fn, 384 void *cb_arg); 385void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 386 union nvme_critical_warning_state state, 387 nvme_cb_fn_t cb_fn, void *cb_arg); 388void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 389 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 390 391void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 392 int error); 393void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 394 bus_size_t mapsize, int error); 395 396int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 397void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 398int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 399void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 400/* ctrlr defined as void * to allow use with config_intrhook. */ 401void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 402void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 403 struct nvme_request *req); 404void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 405 struct nvme_request *req); 406 407void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 408 uint16_t vector, uint32_t num_entries, 409 uint32_t num_trackers, uint32_t max_xfer_size, 410 struct nvme_controller *ctrlr); 411void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 412 struct nvme_tracker *tr); 413void nvme_qpair_process_completions(struct nvme_qpair *qpair); 414void nvme_qpair_submit_request(struct nvme_qpair *qpair, 415 struct nvme_request *req); 416void nvme_qpair_reset(struct nvme_qpair *qpair); 417 418void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 419void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 420void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 421 422void nvme_io_qpair_enable(struct nvme_qpair *qpair); 423void nvme_io_qpair_disable(struct nvme_qpair *qpair); 424void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 425 426int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 427 struct nvme_controller *ctrlr); 428void nvme_ns_destruct(struct nvme_namespace *ns); 429 430int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 431 432void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 433 434void nvme_dump_command(struct nvme_command *cmd); 435void nvme_dump_completion(struct nvme_completion *cpl); 436 437static __inline void 438nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 439{ 440 uint64_t *bus_addr = (uint64_t *)arg; 441 442 *bus_addr = seg[0].ds_addr; 443} 444 445static __inline struct nvme_request * 446nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn, 447 void *cb_arg) 448{ 449 struct nvme_request *req; 450 451 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 452 if (req == NULL) 453 return (NULL); 454 455 req->payload = payload; 456 req->payload_size = payload_size; 457 req->cb_fn = cb_fn; 458 req->cb_arg = cb_arg; 459 req->timeout = TRUE; 460 461 return (req); 462} 463 464static __inline struct nvme_request * 465nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 466{ 467 struct nvme_request *req; 468 469 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 470 if (req == NULL) 471 return (NULL); 472 473 req->uio = uio; 474 req->cb_fn = cb_fn; 475 req->cb_arg = cb_arg; 476 req->timeout = TRUE; 477 478 return (req); 479} 480 481#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 482 483void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 484 const struct nvme_completion *async_cpl, 485 uint32_t log_page_id, void *log_page_buffer, 486 uint32_t log_page_size); 487 488#endif /* __NVME_PRIVATE_H__ */ 489