nvme_private.h revision 248760
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 248760 2013-03-26 21:08:32Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/malloc.h> 36#include <sys/mutex.h> 37#include <sys/rman.h> 38#include <sys/systm.h> 39#include <sys/taskqueue.h> 40 41#include <vm/uma.h> 42 43#include <machine/bus.h> 44 45#include "nvme.h" 46 47#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 48 49MALLOC_DECLARE(M_NVME); 50 51#define CHATHAM2 52 53#ifdef CHATHAM2 54#define CHATHAM_PCI_ID 0x20118086 55#define CHATHAM_CONTROL_BAR 0 56#endif 57 58#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 59#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 60 61#define NVME_MAX_PRP_LIST_ENTRIES (32) 62 63/* 64 * For commands requiring more than 2 PRP entries, one PRP will be 65 * embedded in the command (prp1), and the rest of the PRP entries 66 * will be in a list pointed to by the command (prp2). This means 67 * that real max number of PRP entries we support is 32+1, which 68 * results in a max xfer size of 32*PAGE_SIZE. 69 */ 70#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 71 72#define NVME_ADMIN_TRACKERS (16) 73#define NVME_ADMIN_ENTRIES (128) 74/* min and max are defined in admin queue attributes section of spec */ 75#define NVME_MIN_ADMIN_ENTRIES (2) 76#define NVME_MAX_ADMIN_ENTRIES (4096) 77 78/* 79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 81 * will allow outstanding on an I/O qpair at any time. The only advantage in 82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 83 * the contents of the submission and completion queues, it will show a longer 84 * history of data. 85 */ 86#define NVME_IO_ENTRIES (256) 87#define NVME_IO_TRACKERS (128) 88#define NVME_MIN_IO_TRACKERS (16) 89#define NVME_MAX_IO_TRACKERS (1024) 90 91/* 92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 93 * for each controller. 94 */ 95 96#define NVME_INT_COAL_TIME (0) /* disabled */ 97#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 98 99#define NVME_MAX_NAMESPACES (16) 100#define NVME_MAX_CONSUMERS (2) 101#define NVME_MAX_ASYNC_EVENTS (8) 102 103#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 104#define NVME_MIN_TIMEOUT_PERIOD (5) 105#define NVME_MAX_TIMEOUT_PERIOD (120) 106 107/* Maximum log page size to fetch for AERs. */ 108#define NVME_MAX_AER_LOG_SIZE (4096) 109 110#ifndef CACHE_LINE_SIZE 111#define CACHE_LINE_SIZE (64) 112#endif 113 114extern uma_zone_t nvme_request_zone; 115 116struct nvme_request { 117 118 struct nvme_command cmd; 119 void *payload; 120 uint32_t payload_size; 121 boolean_t timeout; 122 struct uio *uio; 123 nvme_cb_fn_t cb_fn; 124 void *cb_arg; 125 STAILQ_ENTRY(nvme_request) stailq; 126}; 127 128struct nvme_async_event_request { 129 130 struct nvme_controller *ctrlr; 131 struct nvme_request *req; 132 struct nvme_completion cpl; 133 uint32_t log_page_id; 134 uint32_t log_page_size; 135 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 136}; 137 138struct nvme_tracker { 139 140 TAILQ_ENTRY(nvme_tracker) tailq; 141 struct nvme_request *req; 142 struct nvme_qpair *qpair; 143 struct callout timer; 144 bus_dmamap_t payload_dma_map; 145 uint16_t cid; 146 147 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 148 bus_addr_t prp_bus_addr; 149 bus_dmamap_t prp_dma_map; 150}; 151 152struct nvme_qpair { 153 154 struct nvme_controller *ctrlr; 155 uint32_t id; 156 uint32_t phase; 157 158 uint16_t vector; 159 int rid; 160 struct resource *res; 161 void *tag; 162 163 uint32_t max_xfer_size; 164 uint32_t num_entries; 165 uint32_t num_trackers; 166 uint32_t sq_tdbl_off; 167 uint32_t cq_hdbl_off; 168 169 uint32_t sq_head; 170 uint32_t sq_tail; 171 uint32_t cq_head; 172 173 int64_t num_cmds; 174 int64_t num_intr_handler_calls; 175 176 struct nvme_command *cmd; 177 struct nvme_completion *cpl; 178 179 bus_dma_tag_t dma_tag; 180 181 bus_dmamap_t cmd_dma_map; 182 uint64_t cmd_bus_addr; 183 184 bus_dmamap_t cpl_dma_map; 185 uint64_t cpl_bus_addr; 186 187 TAILQ_HEAD(, nvme_tracker) free_tr; 188 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 189 STAILQ_HEAD(, nvme_request) queued_req; 190 191 struct nvme_tracker **act_tr; 192 193 boolean_t is_enabled; 194 195 struct mtx lock __aligned(CACHE_LINE_SIZE); 196 197} __aligned(CACHE_LINE_SIZE); 198 199struct nvme_namespace { 200 201 struct nvme_controller *ctrlr; 202 struct nvme_namespace_data data; 203 uint16_t id; 204 uint16_t flags; 205 struct cdev *cdev; 206 void *cons_cookie[NVME_MAX_CONSUMERS]; 207}; 208 209/* 210 * One of these per allocated PCI device. 211 */ 212struct nvme_controller { 213 214 device_t dev; 215 216 uint32_t ready_timeout_in_ms; 217 218 bus_space_tag_t bus_tag; 219 bus_space_handle_t bus_handle; 220 int resource_id; 221 struct resource *resource; 222 223 /* 224 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 225 * separate from the control registers which are in BAR 0/1. These 226 * members track the mapping of BAR 4/5 for that reason. 227 */ 228 int bar4_resource_id; 229 struct resource *bar4_resource; 230 231#ifdef CHATHAM2 232 bus_space_tag_t chatham_bus_tag; 233 bus_space_handle_t chatham_bus_handle; 234 int chatham_resource_id; 235 struct resource *chatham_resource; 236#endif 237 238 uint32_t msix_enabled; 239 uint32_t force_intx; 240 uint32_t enable_aborts; 241 242 uint32_t num_io_queues; 243 boolean_t per_cpu_io_queues; 244 245 /* Fields for tracking progress during controller initialization. */ 246 struct intr_config_hook config_hook; 247 uint32_t ns_identified; 248 uint32_t queues_created; 249 uint32_t num_start_attempts; 250 struct task reset_task; 251 struct taskqueue *taskqueue; 252 253 /* For shared legacy interrupt. */ 254 int rid; 255 struct resource *res; 256 void *tag; 257 258 bus_dma_tag_t hw_desc_tag; 259 bus_dmamap_t hw_desc_map; 260 261 /** maximum i/o size in bytes */ 262 uint32_t max_xfer_size; 263 264 /** interrupt coalescing time period (in microseconds) */ 265 uint32_t int_coal_time; 266 267 /** interrupt coalescing threshold */ 268 uint32_t int_coal_threshold; 269 270 /** timeout period in seconds */ 271 uint32_t timeout_period; 272 273 struct nvme_qpair adminq; 274 struct nvme_qpair *ioq; 275 276 struct nvme_registers *regs; 277 278 struct nvme_controller_data cdata; 279 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 280 281 struct cdev *cdev; 282 283 boolean_t is_started; 284 285 uint32_t num_aers; 286 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 287 288 void *cons_cookie[NVME_MAX_CONSUMERS]; 289 290 uint32_t is_resetting; 291 292#ifdef CHATHAM2 293 uint64_t chatham_size; 294 uint64_t chatham_lbas; 295#endif 296}; 297 298#define nvme_mmio_offsetof(reg) \ 299 offsetof(struct nvme_registers, reg) 300 301#define nvme_mmio_read_4(sc, reg) \ 302 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 303 nvme_mmio_offsetof(reg)) 304 305#define nvme_mmio_write_4(sc, reg, val) \ 306 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 307 nvme_mmio_offsetof(reg), val) 308 309#define nvme_mmio_write_8(sc, reg, val) \ 310 do { \ 311 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 312 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 313 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 314 nvme_mmio_offsetof(reg)+4, \ 315 (val & 0xFFFFFFFF00000000UL) >> 32); \ 316 } while (0); 317 318#ifdef CHATHAM2 319#define chatham_read_4(softc, reg) \ 320 bus_space_read_4((softc)->chatham_bus_tag, \ 321 (softc)->chatham_bus_handle, reg) 322 323#define chatham_write_8(sc, reg, val) \ 324 do { \ 325 bus_space_write_4((sc)->chatham_bus_tag, \ 326 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 327 bus_space_write_4((sc)->chatham_bus_tag, \ 328 (sc)->chatham_bus_handle, reg+4, \ 329 (val & 0xFFFFFFFF00000000UL) >> 32); \ 330 } while (0); 331 332#endif /* CHATHAM2 */ 333 334#if __FreeBSD_version < 800054 335#define wmb() __asm volatile("sfence" ::: "memory") 336#define mb() __asm volatile("mfence" ::: "memory") 337#endif 338 339void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 340 341void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 342 void *payload, 343 nvme_cb_fn_t cb_fn, void *cb_arg); 344void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 345 uint16_t nsid, void *payload, 346 nvme_cb_fn_t cb_fn, void *cb_arg); 347void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 348 uint32_t microseconds, 349 uint32_t threshold, 350 nvme_cb_fn_t cb_fn, 351 void *cb_arg); 352void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 353 struct nvme_error_information_entry *payload, 354 uint32_t num_entries, /* 0 = max */ 355 nvme_cb_fn_t cb_fn, 356 void *cb_arg); 357void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 358 uint32_t nsid, 359 struct nvme_health_information_page *payload, 360 nvme_cb_fn_t cb_fn, 361 void *cb_arg); 362void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 363 struct nvme_firmware_page *payload, 364 nvme_cb_fn_t cb_fn, 365 void *cb_arg); 366void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 367 struct nvme_qpair *io_que, uint16_t vector, 368 nvme_cb_fn_t cb_fn, void *cb_arg); 369void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 370 struct nvme_qpair *io_que, 371 nvme_cb_fn_t cb_fn, void *cb_arg); 372void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 373 struct nvme_qpair *io_que, 374 nvme_cb_fn_t cb_fn, void *cb_arg); 375void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 376 struct nvme_qpair *io_que, 377 nvme_cb_fn_t cb_fn, void *cb_arg); 378void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 379 uint32_t num_queues, nvme_cb_fn_t cb_fn, 380 void *cb_arg); 381void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 382 union nvme_critical_warning_state state, 383 nvme_cb_fn_t cb_fn, void *cb_arg); 384void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 385 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 386 387void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 388 int error); 389void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 390 bus_size_t mapsize, int error); 391 392int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 393void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 394int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 395void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 396/* ctrlr defined as void * to allow use with config_intrhook. */ 397void nvme_ctrlr_start(void *ctrlr_arg); 398void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 399 struct nvme_request *req); 400void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 401 struct nvme_request *req); 402 403void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 404 uint16_t vector, uint32_t num_entries, 405 uint32_t num_trackers, uint32_t max_xfer_size, 406 struct nvme_controller *ctrlr); 407void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 408 struct nvme_tracker *tr); 409void nvme_qpair_process_completions(struct nvme_qpair *qpair); 410void nvme_qpair_submit_request(struct nvme_qpair *qpair, 411 struct nvme_request *req); 412 413void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 414void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 415void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 416 417void nvme_io_qpair_enable(struct nvme_qpair *qpair); 418void nvme_io_qpair_disable(struct nvme_qpair *qpair); 419void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 420 421int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 422 struct nvme_controller *ctrlr); 423void nvme_ns_destruct(struct nvme_namespace *ns); 424 425int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 426 427void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 428 429void nvme_dump_command(struct nvme_command *cmd); 430void nvme_dump_completion(struct nvme_completion *cpl); 431 432static __inline void 433nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 434{ 435 uint64_t *bus_addr = (uint64_t *)arg; 436 437 *bus_addr = seg[0].ds_addr; 438} 439 440static __inline struct nvme_request * 441nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn, 442 void *cb_arg) 443{ 444 struct nvme_request *req; 445 446 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 447 if (req == NULL) 448 return (NULL); 449 450 req->payload = payload; 451 req->payload_size = payload_size; 452 req->cb_fn = cb_fn; 453 req->cb_arg = cb_arg; 454 req->timeout = TRUE; 455 456 return (req); 457} 458 459static __inline struct nvme_request * 460nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 461{ 462 struct nvme_request *req; 463 464 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 465 if (req == NULL) 466 return (NULL); 467 468 req->uio = uio; 469 req->cb_fn = cb_fn; 470 req->cb_arg = cb_arg; 471 req->timeout = TRUE; 472 473 return (req); 474} 475 476#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 477 478void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 479 const struct nvme_completion *async_cpl, 480 uint32_t log_page_id, void *log_page_buffer, 481 uint32_t log_page_size); 482 483#endif /* __NVME_PRIVATE_H__ */ 484