nvme_private.h revision 248759
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 248759 2013-03-26 21:05:15Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/malloc.h> 36#include <sys/mutex.h> 37#include <sys/rman.h> 38#include <sys/systm.h> 39#include <sys/taskqueue.h> 40 41#include <vm/uma.h> 42 43#include <machine/bus.h> 44 45#include "nvme.h" 46 47#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 48 49MALLOC_DECLARE(M_NVME); 50 51#define CHATHAM2 52 53#ifdef CHATHAM2 54#define CHATHAM_PCI_ID 0x20118086 55#define CHATHAM_CONTROL_BAR 0 56#endif 57 58#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 59#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 60 61#define NVME_MAX_PRP_LIST_ENTRIES (32) 62 63/* 64 * For commands requiring more than 2 PRP entries, one PRP will be 65 * embedded in the command (prp1), and the rest of the PRP entries 66 * will be in a list pointed to by the command (prp2). This means 67 * that real max number of PRP entries we support is 32+1, which 68 * results in a max xfer size of 32*PAGE_SIZE. 69 */ 70#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 71 72#define NVME_ADMIN_TRACKERS (16) 73#define NVME_ADMIN_ENTRIES (128) 74/* min and max are defined in admin queue attributes section of spec */ 75#define NVME_MIN_ADMIN_ENTRIES (2) 76#define NVME_MAX_ADMIN_ENTRIES (4096) 77 78/* 79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 81 * will allow outstanding on an I/O qpair at any time. The only advantage in 82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 83 * the contents of the submission and completion queues, it will show a longer 84 * history of data. 85 */ 86#define NVME_IO_ENTRIES (256) 87#define NVME_IO_TRACKERS (128) 88#define NVME_MIN_IO_TRACKERS (16) 89#define NVME_MAX_IO_TRACKERS (1024) 90 91/* 92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 93 * for each controller. 94 */ 95 96#define NVME_INT_COAL_TIME (0) /* disabled */ 97#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 98 99#define NVME_MAX_NAMESPACES (16) 100#define NVME_MAX_CONSUMERS (2) 101#define NVME_MAX_ASYNC_EVENTS (8) 102 103#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 104#define NVME_MIN_TIMEOUT_PERIOD (5) 105#define NVME_MAX_TIMEOUT_PERIOD (120) 106 107/* Maximum log page size to fetch for AERs. */ 108#define NVME_MAX_AER_LOG_SIZE (4096) 109 110#ifndef CACHE_LINE_SIZE 111#define CACHE_LINE_SIZE (64) 112#endif 113 114extern uma_zone_t nvme_request_zone; 115 116struct nvme_request { 117 118 struct nvme_command cmd; 119 void *payload; 120 uint32_t payload_size; 121 boolean_t timeout; 122 struct uio *uio; 123 nvme_cb_fn_t cb_fn; 124 void *cb_arg; 125 STAILQ_ENTRY(nvme_request) stailq; 126}; 127 128struct nvme_async_event_request { 129 130 struct nvme_controller *ctrlr; 131 struct nvme_request *req; 132 struct nvme_completion cpl; 133 uint32_t log_page_size; 134 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 135}; 136 137struct nvme_tracker { 138 139 TAILQ_ENTRY(nvme_tracker) tailq; 140 struct nvme_request *req; 141 struct nvme_qpair *qpair; 142 struct callout timer; 143 bus_dmamap_t payload_dma_map; 144 uint16_t cid; 145 146 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 147 bus_addr_t prp_bus_addr; 148 bus_dmamap_t prp_dma_map; 149}; 150 151struct nvme_qpair { 152 153 struct nvme_controller *ctrlr; 154 uint32_t id; 155 uint32_t phase; 156 157 uint16_t vector; 158 int rid; 159 struct resource *res; 160 void *tag; 161 162 uint32_t max_xfer_size; 163 uint32_t num_entries; 164 uint32_t num_trackers; 165 uint32_t sq_tdbl_off; 166 uint32_t cq_hdbl_off; 167 168 uint32_t sq_head; 169 uint32_t sq_tail; 170 uint32_t cq_head; 171 172 int64_t num_cmds; 173 int64_t num_intr_handler_calls; 174 175 struct nvme_command *cmd; 176 struct nvme_completion *cpl; 177 178 bus_dma_tag_t dma_tag; 179 180 bus_dmamap_t cmd_dma_map; 181 uint64_t cmd_bus_addr; 182 183 bus_dmamap_t cpl_dma_map; 184 uint64_t cpl_bus_addr; 185 186 TAILQ_HEAD(, nvme_tracker) free_tr; 187 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 188 STAILQ_HEAD(, nvme_request) queued_req; 189 190 struct nvme_tracker **act_tr; 191 192 boolean_t is_enabled; 193 194 struct mtx lock __aligned(CACHE_LINE_SIZE); 195 196} __aligned(CACHE_LINE_SIZE); 197 198struct nvme_namespace { 199 200 struct nvme_controller *ctrlr; 201 struct nvme_namespace_data data; 202 uint16_t id; 203 uint16_t flags; 204 struct cdev *cdev; 205 void *cons_cookie[NVME_MAX_CONSUMERS]; 206}; 207 208/* 209 * One of these per allocated PCI device. 210 */ 211struct nvme_controller { 212 213 device_t dev; 214 215 uint32_t ready_timeout_in_ms; 216 217 bus_space_tag_t bus_tag; 218 bus_space_handle_t bus_handle; 219 int resource_id; 220 struct resource *resource; 221 222 /* 223 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 224 * separate from the control registers which are in BAR 0/1. These 225 * members track the mapping of BAR 4/5 for that reason. 226 */ 227 int bar4_resource_id; 228 struct resource *bar4_resource; 229 230#ifdef CHATHAM2 231 bus_space_tag_t chatham_bus_tag; 232 bus_space_handle_t chatham_bus_handle; 233 int chatham_resource_id; 234 struct resource *chatham_resource; 235#endif 236 237 uint32_t msix_enabled; 238 uint32_t force_intx; 239 uint32_t enable_aborts; 240 241 uint32_t num_io_queues; 242 boolean_t per_cpu_io_queues; 243 244 /* Fields for tracking progress during controller initialization. */ 245 struct intr_config_hook config_hook; 246 uint32_t ns_identified; 247 uint32_t queues_created; 248 uint32_t num_start_attempts; 249 struct task reset_task; 250 struct taskqueue *taskqueue; 251 252 /* For shared legacy interrupt. */ 253 int rid; 254 struct resource *res; 255 void *tag; 256 257 bus_dma_tag_t hw_desc_tag; 258 bus_dmamap_t hw_desc_map; 259 260 /** maximum i/o size in bytes */ 261 uint32_t max_xfer_size; 262 263 /** interrupt coalescing time period (in microseconds) */ 264 uint32_t int_coal_time; 265 266 /** interrupt coalescing threshold */ 267 uint32_t int_coal_threshold; 268 269 /** timeout period in seconds */ 270 uint32_t timeout_period; 271 272 struct nvme_qpair adminq; 273 struct nvme_qpair *ioq; 274 275 struct nvme_registers *regs; 276 277 struct nvme_controller_data cdata; 278 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 279 280 struct cdev *cdev; 281 282 boolean_t is_started; 283 284 uint32_t num_aers; 285 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 286 287 void *cons_cookie[NVME_MAX_CONSUMERS]; 288 289 uint32_t is_resetting; 290 291#ifdef CHATHAM2 292 uint64_t chatham_size; 293 uint64_t chatham_lbas; 294#endif 295}; 296 297#define nvme_mmio_offsetof(reg) \ 298 offsetof(struct nvme_registers, reg) 299 300#define nvme_mmio_read_4(sc, reg) \ 301 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 302 nvme_mmio_offsetof(reg)) 303 304#define nvme_mmio_write_4(sc, reg, val) \ 305 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 306 nvme_mmio_offsetof(reg), val) 307 308#define nvme_mmio_write_8(sc, reg, val) \ 309 do { \ 310 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 311 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 312 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 313 nvme_mmio_offsetof(reg)+4, \ 314 (val & 0xFFFFFFFF00000000UL) >> 32); \ 315 } while (0); 316 317#ifdef CHATHAM2 318#define chatham_read_4(softc, reg) \ 319 bus_space_read_4((softc)->chatham_bus_tag, \ 320 (softc)->chatham_bus_handle, reg) 321 322#define chatham_write_8(sc, reg, val) \ 323 do { \ 324 bus_space_write_4((sc)->chatham_bus_tag, \ 325 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 326 bus_space_write_4((sc)->chatham_bus_tag, \ 327 (sc)->chatham_bus_handle, reg+4, \ 328 (val & 0xFFFFFFFF00000000UL) >> 32); \ 329 } while (0); 330 331#endif /* CHATHAM2 */ 332 333#if __FreeBSD_version < 800054 334#define wmb() __asm volatile("sfence" ::: "memory") 335#define mb() __asm volatile("mfence" ::: "memory") 336#endif 337 338void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 339 340void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 341 void *payload, 342 nvme_cb_fn_t cb_fn, void *cb_arg); 343void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 344 uint16_t nsid, void *payload, 345 nvme_cb_fn_t cb_fn, void *cb_arg); 346void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 347 uint32_t microseconds, 348 uint32_t threshold, 349 nvme_cb_fn_t cb_fn, 350 void *cb_arg); 351void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 352 struct nvme_error_information_entry *payload, 353 uint32_t num_entries, /* 0 = max */ 354 nvme_cb_fn_t cb_fn, 355 void *cb_arg); 356void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 357 uint32_t nsid, 358 struct nvme_health_information_page *payload, 359 nvme_cb_fn_t cb_fn, 360 void *cb_arg); 361void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 362 struct nvme_firmware_page *payload, 363 nvme_cb_fn_t cb_fn, 364 void *cb_arg); 365void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 366 struct nvme_qpair *io_que, uint16_t vector, 367 nvme_cb_fn_t cb_fn, void *cb_arg); 368void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 369 struct nvme_qpair *io_que, 370 nvme_cb_fn_t cb_fn, void *cb_arg); 371void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 372 struct nvme_qpair *io_que, 373 nvme_cb_fn_t cb_fn, void *cb_arg); 374void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 375 struct nvme_qpair *io_que, 376 nvme_cb_fn_t cb_fn, void *cb_arg); 377void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 378 uint32_t num_queues, nvme_cb_fn_t cb_fn, 379 void *cb_arg); 380void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 381 union nvme_critical_warning_state state, 382 nvme_cb_fn_t cb_fn, void *cb_arg); 383void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 384 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 385 386void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 387 int error); 388void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 389 bus_size_t mapsize, int error); 390 391int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 392void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 393int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 394void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 395/* ctrlr defined as void * to allow use with config_intrhook. */ 396void nvme_ctrlr_start(void *ctrlr_arg); 397void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 398 struct nvme_request *req); 399void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 400 struct nvme_request *req); 401 402void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 403 uint16_t vector, uint32_t num_entries, 404 uint32_t num_trackers, uint32_t max_xfer_size, 405 struct nvme_controller *ctrlr); 406void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 407 struct nvme_tracker *tr); 408void nvme_qpair_process_completions(struct nvme_qpair *qpair); 409void nvme_qpair_submit_request(struct nvme_qpair *qpair, 410 struct nvme_request *req); 411 412void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 413void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 414void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 415 416void nvme_io_qpair_enable(struct nvme_qpair *qpair); 417void nvme_io_qpair_disable(struct nvme_qpair *qpair); 418void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 419 420int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 421 struct nvme_controller *ctrlr); 422void nvme_ns_destruct(struct nvme_namespace *ns); 423 424int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 425 426void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 427 428void nvme_dump_command(struct nvme_command *cmd); 429void nvme_dump_completion(struct nvme_completion *cpl); 430 431static __inline void 432nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 433{ 434 uint64_t *bus_addr = (uint64_t *)arg; 435 436 *bus_addr = seg[0].ds_addr; 437} 438 439static __inline struct nvme_request * 440nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn, 441 void *cb_arg) 442{ 443 struct nvme_request *req; 444 445 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 446 if (req == NULL) 447 return (NULL); 448 449 req->payload = payload; 450 req->payload_size = payload_size; 451 req->cb_fn = cb_fn; 452 req->cb_arg = cb_arg; 453 req->timeout = TRUE; 454 455 return (req); 456} 457 458static __inline struct nvme_request * 459nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 460{ 461 struct nvme_request *req; 462 463 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 464 if (req == NULL) 465 return (NULL); 466 467 req->uio = uio; 468 req->cb_fn = cb_fn; 469 req->cb_arg = cb_arg; 470 req->timeout = TRUE; 471 472 return (req); 473} 474 475#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 476 477void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 478 const struct nvme_completion *async_cpl); 479 480#endif /* __NVME_PRIVATE_H__ */ 481