nvme_private.h revision 248735
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 248735 2013-03-26 18:31:46Z jimharris $ 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/malloc.h> 36#include <sys/mutex.h> 37#include <sys/rman.h> 38#include <sys/systm.h> 39 40#include <vm/uma.h> 41 42#include <machine/bus.h> 43 44#include "nvme.h" 45 46#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 47 48MALLOC_DECLARE(M_NVME); 49 50#define CHATHAM2 51 52#ifdef CHATHAM2 53#define CHATHAM_PCI_ID 0x20118086 54#define CHATHAM_CONTROL_BAR 0 55#endif 56 57#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 58#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 59 60#define NVME_MAX_PRP_LIST_ENTRIES (32) 61 62/* 63 * For commands requiring more than 2 PRP entries, one PRP will be 64 * embedded in the command (prp1), and the rest of the PRP entries 65 * will be in a list pointed to by the command (prp2). This means 66 * that real max number of PRP entries we support is 32+1, which 67 * results in a max xfer size of 32*PAGE_SIZE. 68 */ 69#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 70 71#define NVME_ADMIN_TRACKERS (16) 72#define NVME_ADMIN_ENTRIES (128) 73/* min and max are defined in admin queue attributes section of spec */ 74#define NVME_MIN_ADMIN_ENTRIES (2) 75#define NVME_MAX_ADMIN_ENTRIES (4096) 76 77/* 78 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 79 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 80 * will allow outstanding on an I/O qpair at any time. The only advantage in 81 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 82 * the contents of the submission and completion queues, it will show a longer 83 * history of data. 84 */ 85#define NVME_IO_ENTRIES (256) 86#define NVME_IO_TRACKERS (128) 87#define NVME_MIN_IO_TRACKERS (16) 88#define NVME_MAX_IO_TRACKERS (1024) 89 90/* 91 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 92 * for each controller. 93 */ 94 95#define NVME_INT_COAL_TIME (0) /* disabled */ 96#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 97 98#define NVME_MAX_NAMESPACES (16) 99#define NVME_MAX_CONSUMERS (2) 100#define NVME_MAX_ASYNC_EVENTS (4) 101 102#define NVME_TIMEOUT_IN_SEC (30) 103 104#ifndef CACHE_LINE_SIZE 105#define CACHE_LINE_SIZE (64) 106#endif 107 108extern uma_zone_t nvme_request_zone; 109 110struct nvme_request { 111 112 struct nvme_command cmd; 113 void *payload; 114 uint32_t payload_size; 115 uint32_t timeout; 116 struct uio *uio; 117 nvme_cb_fn_t cb_fn; 118 void *cb_arg; 119 STAILQ_ENTRY(nvme_request) stailq; 120}; 121 122struct nvme_tracker { 123 124 SLIST_ENTRY(nvme_tracker) slist; 125 struct nvme_request *req; 126 struct nvme_qpair *qpair; 127 struct callout timer; 128 bus_dmamap_t payload_dma_map; 129 uint16_t cid; 130 131 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 132 bus_addr_t prp_bus_addr; 133 bus_dmamap_t prp_dma_map; 134}; 135 136struct nvme_qpair { 137 138 struct nvme_controller *ctrlr; 139 uint32_t id; 140 uint32_t phase; 141 142 uint16_t vector; 143 int rid; 144 struct resource *res; 145 void *tag; 146 147 uint32_t max_xfer_size; 148 uint32_t num_entries; 149 uint32_t num_trackers; 150 uint32_t sq_tdbl_off; 151 uint32_t cq_hdbl_off; 152 153 uint32_t sq_head; 154 uint32_t sq_tail; 155 uint32_t cq_head; 156 157 int64_t num_cmds; 158 int64_t num_intr_handler_calls; 159 160 struct nvme_command *cmd; 161 struct nvme_completion *cpl; 162 163 bus_dma_tag_t dma_tag; 164 165 bus_dmamap_t cmd_dma_map; 166 uint64_t cmd_bus_addr; 167 168 bus_dmamap_t cpl_dma_map; 169 uint64_t cpl_bus_addr; 170 171 SLIST_HEAD(, nvme_tracker) free_tr; 172 STAILQ_HEAD(, nvme_request) queued_req; 173 174 struct nvme_tracker **act_tr; 175 176 struct mtx lock __aligned(CACHE_LINE_SIZE); 177 178} __aligned(CACHE_LINE_SIZE); 179 180struct nvme_namespace { 181 182 struct nvme_controller *ctrlr; 183 struct nvme_namespace_data data; 184 uint16_t id; 185 uint16_t flags; 186 struct cdev *cdev; 187}; 188 189/* 190 * One of these per allocated PCI device. 191 */ 192struct nvme_controller { 193 194 device_t dev; 195 196 uint32_t ready_timeout_in_ms; 197 198 bus_space_tag_t bus_tag; 199 bus_space_handle_t bus_handle; 200 int resource_id; 201 struct resource *resource; 202 203 /* 204 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 205 * separate from the control registers which are in BAR 0/1. These 206 * members track the mapping of BAR 4/5 for that reason. 207 */ 208 int bar4_resource_id; 209 struct resource *bar4_resource; 210 211#ifdef CHATHAM2 212 bus_space_tag_t chatham_bus_tag; 213 bus_space_handle_t chatham_bus_handle; 214 int chatham_resource_id; 215 struct resource *chatham_resource; 216#endif 217 218 uint32_t msix_enabled; 219 uint32_t force_intx; 220 221 uint32_t num_io_queues; 222 boolean_t per_cpu_io_queues; 223 224 /* Fields for tracking progress during controller initialization. */ 225 struct intr_config_hook config_hook; 226 uint32_t ns_identified; 227 uint32_t queues_created; 228 229 /* For shared legacy interrupt. */ 230 int rid; 231 struct resource *res; 232 void *tag; 233 234 bus_dma_tag_t hw_desc_tag; 235 bus_dmamap_t hw_desc_map; 236 237 /** maximum i/o size in bytes */ 238 uint32_t max_xfer_size; 239 240 /** interrupt coalescing time period (in microseconds) */ 241 uint32_t int_coal_time; 242 243 /** interrupt coalescing threshold */ 244 uint32_t int_coal_threshold; 245 246 struct nvme_qpair adminq; 247 struct nvme_qpair *ioq; 248 249 struct nvme_registers *regs; 250 251 struct nvme_controller_data cdata; 252 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 253 254 struct cdev *cdev; 255 256 boolean_t is_started; 257 258#ifdef CHATHAM2 259 uint64_t chatham_size; 260 uint64_t chatham_lbas; 261#endif 262}; 263 264#define nvme_mmio_offsetof(reg) \ 265 offsetof(struct nvme_registers, reg) 266 267#define nvme_mmio_read_4(sc, reg) \ 268 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 269 nvme_mmio_offsetof(reg)) 270 271#define nvme_mmio_write_4(sc, reg, val) \ 272 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 273 nvme_mmio_offsetof(reg), val) 274 275#define nvme_mmio_write_8(sc, reg, val) \ 276 do { \ 277 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 278 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 279 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 280 nvme_mmio_offsetof(reg)+4, \ 281 (val & 0xFFFFFFFF00000000UL) >> 32); \ 282 } while (0); 283 284#ifdef CHATHAM2 285#define chatham_read_4(softc, reg) \ 286 bus_space_read_4((softc)->chatham_bus_tag, \ 287 (softc)->chatham_bus_handle, reg) 288 289#define chatham_write_8(sc, reg, val) \ 290 do { \ 291 bus_space_write_4((sc)->chatham_bus_tag, \ 292 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 293 bus_space_write_4((sc)->chatham_bus_tag, \ 294 (sc)->chatham_bus_handle, reg+4, \ 295 (val & 0xFFFFFFFF00000000UL) >> 32); \ 296 } while (0); 297 298#endif /* CHATHAM2 */ 299 300#if __FreeBSD_version < 800054 301#define wmb() __asm volatile("sfence" ::: "memory") 302#define mb() __asm volatile("mfence" ::: "memory") 303#endif 304 305void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 306 307void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 308 uint8_t feature, uint32_t cdw11, 309 void *payload, uint32_t payload_size, 310 nvme_cb_fn_t cb_fn, void *cb_arg); 311void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 312 uint8_t feature, uint32_t cdw11, 313 void *payload, uint32_t payload_size, 314 nvme_cb_fn_t cb_fn, void *cb_arg); 315void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 316 void *payload, 317 nvme_cb_fn_t cb_fn, void *cb_arg); 318void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 319 uint16_t nsid, void *payload, 320 nvme_cb_fn_t cb_fn, void *cb_arg); 321void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 322 uint32_t microseconds, 323 uint32_t threshold, 324 nvme_cb_fn_t cb_fn, 325 void *cb_arg); 326void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 327 uint32_t nsid, 328 struct nvme_health_information_page *payload, 329 nvme_cb_fn_t cb_fn, 330 void *cb_arg); 331void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 332 struct nvme_qpair *io_que, uint16_t vector, 333 nvme_cb_fn_t cb_fn, void *cb_arg); 334void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 335 struct nvme_qpair *io_que, 336 nvme_cb_fn_t cb_fn, void *cb_arg); 337void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 338 struct nvme_qpair *io_que, 339 nvme_cb_fn_t cb_fn, void *cb_arg); 340void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 341 struct nvme_qpair *io_que, 342 nvme_cb_fn_t cb_fn, void *cb_arg); 343void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 344 uint32_t num_queues, nvme_cb_fn_t cb_fn, 345 void *cb_arg); 346void nvme_ctrlr_cmd_set_asynchronous_event_config(struct nvme_controller *ctrlr, 347 union nvme_critical_warning_state state, 348 nvme_cb_fn_t cb_fn, void *cb_arg); 349void nvme_ctrlr_cmd_asynchronous_event_request(struct nvme_controller *ctrlr, 350 nvme_cb_fn_t cb_fn, 351 void *cb_arg); 352void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 353 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 354 355void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 356 int error); 357void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 358 bus_size_t mapsize, int error); 359 360int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 361int nvme_ctrlr_reset(struct nvme_controller *ctrlr); 362/* ctrlr defined as void * to allow use with config_intrhook. */ 363void nvme_ctrlr_start(void *ctrlr_arg); 364void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 365 struct nvme_request *req); 366void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 367 struct nvme_request *req); 368 369void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 370 uint16_t vector, uint32_t num_entries, 371 uint32_t num_trackers, uint32_t max_xfer_size, 372 struct nvme_controller *ctrlr); 373void nvme_qpair_submit_cmd(struct nvme_qpair *qpair, 374 struct nvme_tracker *tr); 375void nvme_qpair_process_completions(struct nvme_qpair *qpair); 376void nvme_qpair_submit_request(struct nvme_qpair *qpair, 377 struct nvme_request *req); 378 379void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 380 381void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 382 383int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 384 struct nvme_controller *ctrlr); 385 386int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 387 388void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 389 390void nvme_dump_command(struct nvme_command *cmd); 391void nvme_dump_completion(struct nvme_completion *cpl); 392 393static __inline void 394nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 395{ 396 uint64_t *bus_addr = (uint64_t *)arg; 397 398 *bus_addr = seg[0].ds_addr; 399} 400 401static __inline struct nvme_request * 402nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn, 403 void *cb_arg) 404{ 405 struct nvme_request *req; 406 407 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 408 if (req == NULL) 409 return (NULL); 410 411 req->payload = payload; 412 req->payload_size = payload_size; 413 req->cb_fn = cb_fn; 414 req->cb_arg = cb_arg; 415 req->timeout = NVME_TIMEOUT_IN_SEC; 416 417 return (req); 418} 419 420static __inline struct nvme_request * 421nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 422{ 423 struct nvme_request *req; 424 425 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 426 if (req == NULL) 427 return (NULL); 428 429 req->uio = uio; 430 req->cb_fn = cb_fn; 431 req->cb_arg = cb_arg; 432 req->timeout = NVME_TIMEOUT_IN_SEC; 433 434 return (req); 435} 436 437#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 438 439#endif /* __NVME_PRIVATE_H__ */ 440