nvme_private.h revision 244410
145296Sdfr/*- 245296Sdfr * Copyright (C) 2012 Intel Corporation 345296Sdfr * All rights reserved. 445296Sdfr * 545296Sdfr * Redistribution and use in source and binary forms, with or without 645296Sdfr * modification, are permitted provided that the following conditions 745296Sdfr * are met: 845296Sdfr * 1. Redistributions of source code must retain the above copyright 945296Sdfr * notice, this list of conditions and the following disclaimer. 1045296Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1145296Sdfr * notice, this list of conditions and the following disclaimer in the 1245296Sdfr * documentation and/or other materials provided with the distribution. 1345296Sdfr * 1445296Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1545296Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1645296Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1745296Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1845296Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1945296Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2045296Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2145296Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2245296Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2345296Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2445296Sdfr * SUCH DAMAGE. 2545296Sdfr * 2650476Speter * $FreeBSD: head/sys/dev/nvme/nvme_private.h 244410 2012-12-18 21:50:48Z jimharris $ 2745296Sdfr */ 28186489Strhodes 2945296Sdfr#ifndef __NVME_PRIVATE_H__ 3079531Sru#define __NVME_PRIVATE_H__ 3145296Sdfr 32177144Sru#include <sys/param.h> 3345296Sdfr#include <sys/kernel.h> 3459460Sphantom#include <sys/lock.h> 3559460Sphantom#include <sys/malloc.h> 3645296Sdfr#include <sys/mutex.h> 3784306Sru#include <sys/rman.h> 3884306Sru#include <sys/systm.h> 3945296Sdfr 4045296Sdfr#include <vm/uma.h> 41177012Srwatson 42177144Sru#include <machine/bus.h> 4345296Sdfr 44108028Sru#include "nvme.h" 4545296Sdfr 46108028Sru#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 4745296Sdfr 4849699SchrisMALLOC_DECLARE(M_NVME); 49177012Srwatson 50177012Srwatson#define CHATHAM2 51177012Srwatson 52177012Srwatson#ifdef CHATHAM2 53177012Srwatson#define CHATHAM_PCI_ID 0x20118086 54177012Srwatson#define CHATHAM_CONTROL_BAR 0 55177012Srwatson#endif 56177012Srwatson 57177012Srwatson#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 58177012Srwatson#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 5945296Sdfr 60104329Sdd#define NVME_MAX_PRP_LIST_ENTRIES (32) 6145296Sdfr 6245296Sdfr/* 6361988Schris * For commands requiring more than 2 PRP entries, one PRP will be 6445296Sdfr * embedded in the command (prp1), and the rest of the PRP entries 6545296Sdfr * will be in a list pointed to by the command (prp2). This means 6645296Sdfr * that real max number of PRP entries we support is 32+1, which 67141846Sru * results in a max xfer size of 32*PAGE_SIZE. 6845296Sdfr */ 6945296Sdfr#define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 7045296Sdfr 7145296Sdfr#define NVME_ADMIN_TRACKERS (16) 72186489Strhodes#define NVME_ADMIN_ENTRIES (128) 73186489Strhodes/* min and max are defined in admin queue attributes section of spec */ 74186489Strhodes#define NVME_MIN_ADMIN_ENTRIES (2) 75186489Strhodes#define NVME_MAX_ADMIN_ENTRIES (4096) 7670481Sru 7748389Ssheldonh/* 7848389Ssheldonh * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 7948389Ssheldonh * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 8048389Ssheldonh * will allow outstanding on an I/O qpair at any time. The only advantage in 8148389Ssheldonh * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 8248389Ssheldonh * the contents of the submission and completion queues, it will show a longer 8380433Schris * history of data. 8466430Speter */ 8580252Syar#define NVME_IO_ENTRIES (256) 8666430Speter#define NVME_IO_TRACKERS (128) 8766430Speter#define NVME_MIN_IO_TRACKERS (16) 8848389Ssheldonh#define NVME_MAX_IO_TRACKERS (1024) 8948389Ssheldonh 9045296Sdfr/* 9145296Sdfr * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 9245296Sdfr * for each controller. 9350944Sphantom */ 9450944Sphantom 95#define NVME_INT_COAL_TIME (0) /* disabled */ 96#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 97 98#define NVME_MAX_NAMESPACES (16) 99#define NVME_MAX_CONSUMERS (2) 100#define NVME_MAX_ASYNC_EVENTS (4) 101 102#define NVME_TIMEOUT_IN_SEC (30) 103 104#ifndef CACHE_LINE_SIZE 105#define CACHE_LINE_SIZE (64) 106#endif 107 108extern uma_zone_t nvme_request_zone; 109 110struct nvme_request { 111 112 struct nvme_command cmd; 113 void *payload; 114 uint32_t payload_size; 115 struct uio *uio; 116 nvme_cb_fn_t cb_fn; 117 void *cb_arg; 118 STAILQ_ENTRY(nvme_request) stailq; 119}; 120 121struct nvme_tracker { 122 123 SLIST_ENTRY(nvme_tracker) slist; 124 struct nvme_request *req; 125 struct nvme_qpair *qpair; 126 struct callout timer; 127 bus_dmamap_t payload_dma_map; 128 uint16_t cid; 129 130 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 131 bus_addr_t prp_bus_addr; 132 bus_dmamap_t prp_dma_map; 133}; 134 135struct nvme_qpair { 136 137 struct nvme_controller *ctrlr; 138 uint32_t id; 139 uint32_t phase; 140 141 uint16_t vector; 142 int rid; 143 struct resource *res; 144 void *tag; 145 146 uint32_t max_xfer_size; 147 uint32_t num_entries; 148 uint32_t num_trackers; 149 uint32_t sq_tdbl_off; 150 uint32_t cq_hdbl_off; 151 152 uint32_t sq_head; 153 uint32_t sq_tail; 154 uint32_t cq_head; 155 156 int64_t num_cmds; 157 int64_t num_intr_handler_calls; 158 159 struct nvme_command *cmd; 160 struct nvme_completion *cpl; 161 162 bus_dma_tag_t dma_tag; 163 164 bus_dmamap_t cmd_dma_map; 165 uint64_t cmd_bus_addr; 166 167 bus_dmamap_t cpl_dma_map; 168 uint64_t cpl_bus_addr; 169 170 SLIST_HEAD(, nvme_tracker) free_tr; 171 STAILQ_HEAD(, nvme_request) queued_req; 172 173 struct nvme_tracker **act_tr; 174 175 struct mtx lock __aligned(CACHE_LINE_SIZE); 176 177} __aligned(CACHE_LINE_SIZE); 178 179struct nvme_namespace { 180 181 struct nvme_controller *ctrlr; 182 struct nvme_namespace_data data; 183 uint16_t id; 184 uint16_t flags; 185 struct cdev *cdev; 186}; 187 188/* 189 * One of these per allocated PCI device. 190 */ 191struct nvme_controller { 192 193 device_t dev; 194 195 uint32_t ready_timeout_in_ms; 196 197 bus_space_tag_t bus_tag; 198 bus_space_handle_t bus_handle; 199 int resource_id; 200 struct resource *resource; 201 202#ifdef CHATHAM2 203 bus_space_tag_t chatham_bus_tag; 204 bus_space_handle_t chatham_bus_handle; 205 int chatham_resource_id; 206 struct resource *chatham_resource; 207#endif 208 209 uint32_t msix_enabled; 210 uint32_t force_intx; 211 212 uint32_t num_io_queues; 213 boolean_t per_cpu_io_queues; 214 215 /* Fields for tracking progress during controller initialization. */ 216 struct intr_config_hook config_hook; 217 uint32_t ns_identified; 218 uint32_t queues_created; 219 220 /* For shared legacy interrupt. */ 221 int rid; 222 struct resource *res; 223 void *tag; 224 225 bus_dma_tag_t hw_desc_tag; 226 bus_dmamap_t hw_desc_map; 227 228 /** maximum i/o size in bytes */ 229 uint32_t max_xfer_size; 230 231 /** interrupt coalescing time period (in microseconds) */ 232 uint32_t int_coal_time; 233 234 /** interrupt coalescing threshold */ 235 uint32_t int_coal_threshold; 236 237 struct nvme_qpair adminq; 238 struct nvme_qpair *ioq; 239 240 struct nvme_registers *regs; 241 242 struct nvme_controller_data cdata; 243 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 244 245 struct cdev *cdev; 246 247 boolean_t is_started; 248 249#ifdef CHATHAM2 250 uint64_t chatham_size; 251 uint64_t chatham_lbas; 252#endif 253}; 254 255#define nvme_mmio_offsetof(reg) \ 256 offsetof(struct nvme_registers, reg) 257 258#define nvme_mmio_read_4(sc, reg) \ 259 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 260 nvme_mmio_offsetof(reg)) 261 262#define nvme_mmio_write_4(sc, reg, val) \ 263 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 264 nvme_mmio_offsetof(reg), val) 265 266#define nvme_mmio_write_8(sc, reg, val) \ 267 do { \ 268 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 269 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 270 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 271 nvme_mmio_offsetof(reg)+4, \ 272 (val & 0xFFFFFFFF00000000UL) >> 32); \ 273 } while (0); 274 275#ifdef CHATHAM2 276#define chatham_read_4(softc, reg) \ 277 bus_space_read_4((softc)->chatham_bus_tag, \ 278 (softc)->chatham_bus_handle, reg) 279 280#define chatham_write_8(sc, reg, val) \ 281 do { \ 282 bus_space_write_4((sc)->chatham_bus_tag, \ 283 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 284 bus_space_write_4((sc)->chatham_bus_tag, \ 285 (sc)->chatham_bus_handle, reg+4, \ 286 (val & 0xFFFFFFFF00000000UL) >> 32); \ 287 } while (0); 288 289#endif /* CHATHAM2 */ 290 291#if __FreeBSD_version < 800054 292#define wmb() __asm volatile("sfence" ::: "memory") 293#define mb() __asm volatile("mfence" ::: "memory") 294#endif 295 296void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 297 298void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 299 uint8_t feature, uint32_t cdw11, 300 void *payload, uint32_t payload_size, 301 nvme_cb_fn_t cb_fn, void *cb_arg); 302void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 303 uint8_t feature, uint32_t cdw11, 304 void *payload, uint32_t payload_size, 305 nvme_cb_fn_t cb_fn, void *cb_arg); 306void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 307 void *payload, 308 nvme_cb_fn_t cb_fn, void *cb_arg); 309void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 310 uint16_t nsid, void *payload, 311 nvme_cb_fn_t cb_fn, void *cb_arg); 312void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 313 uint32_t microseconds, 314 uint32_t threshold, 315 nvme_cb_fn_t cb_fn, 316 void *cb_arg); 317void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 318 uint32_t nsid, 319 struct nvme_health_information_page *payload, 320 nvme_cb_fn_t cb_fn, 321 void *cb_arg); 322void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 323 struct nvme_qpair *io_que, uint16_t vector, 324 nvme_cb_fn_t cb_fn, void *cb_arg); 325void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 326 struct nvme_qpair *io_que, 327 nvme_cb_fn_t cb_fn, void *cb_arg); 328void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 329 struct nvme_qpair *io_que, 330 nvme_cb_fn_t cb_fn, void *cb_arg); 331void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 332 struct nvme_qpair *io_que, 333 nvme_cb_fn_t cb_fn, void *cb_arg); 334void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 335 uint32_t num_queues, nvme_cb_fn_t cb_fn, 336 void *cb_arg); 337void nvme_ctrlr_cmd_set_asynchronous_event_config(struct nvme_controller *ctrlr, 338 union nvme_critical_warning_state state, 339 nvme_cb_fn_t cb_fn, void *cb_arg); 340void nvme_ctrlr_cmd_asynchronous_event_request(struct nvme_controller *ctrlr, 341 nvme_cb_fn_t cb_fn, 342 void *cb_arg); 343 344void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 345 int error); 346void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 347 bus_size_t mapsize, int error); 348 349int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 350int nvme_ctrlr_reset(struct nvme_controller *ctrlr); 351/* ctrlr defined as void * to allow use with config_intrhook. */ 352void nvme_ctrlr_start(void *ctrlr_arg); 353void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 354 struct nvme_request *req); 355void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 356 struct nvme_request *req); 357 358void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 359 uint16_t vector, uint32_t num_entries, 360 uint32_t num_trackers, uint32_t max_xfer_size, 361 struct nvme_controller *ctrlr); 362void nvme_qpair_submit_cmd(struct nvme_qpair *qpair, 363 struct nvme_tracker *tr); 364void nvme_qpair_process_completions(struct nvme_qpair *qpair); 365void nvme_qpair_submit_request(struct nvme_qpair *qpair, 366 struct nvme_request *req); 367 368void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 369 370void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 371 372int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 373 struct nvme_controller *ctrlr); 374 375int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 376 377void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 378 379void nvme_dump_command(struct nvme_command *cmd); 380void nvme_dump_completion(struct nvme_completion *cpl); 381 382static __inline void 383nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 384{ 385 uint64_t *bus_addr = (uint64_t *)arg; 386 387 *bus_addr = seg[0].ds_addr; 388} 389 390static __inline struct nvme_request * 391nvme_allocate_request(void *payload, uint32_t payload_size, nvme_cb_fn_t cb_fn, 392 void *cb_arg) 393{ 394 struct nvme_request *req; 395 396 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 397 if (req == NULL) 398 return (NULL); 399 400 req->payload = payload; 401 req->payload_size = payload_size; 402 req->cb_fn = cb_fn; 403 req->cb_arg = cb_arg; 404 405 return (req); 406} 407 408static __inline struct nvme_request * 409nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 410{ 411 struct nvme_request *req; 412 413 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 414 if (req == NULL) 415 return (NULL); 416 417 req->uio = uio; 418 req->cb_fn = cb_fn; 419 req->cb_arg = cb_arg; 420 421 return (req); 422} 423 424#define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 425 426#endif /* __NVME_PRIVATE_H__ */ 427