nvme.h revision 248747
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nvme/nvme.h 248747 2013-03-26 19:52:57Z jimharris $ 27 */ 28 29#ifndef __NVME_H__ 30#define __NVME_H__ 31 32#ifdef _KERNEL 33#include <sys/types.h> 34#endif 35 36#define NVME_IDENTIFY_CONTROLLER _IOR('n', 0, struct nvme_controller_data) 37#define NVME_IDENTIFY_NAMESPACE _IOR('n', 1, struct nvme_namespace_data) 38#define NVME_IO_TEST _IOWR('n', 2, struct nvme_io_test) 39#define NVME_BIO_TEST _IOWR('n', 4, struct nvme_io_test) 40#define NVME_RESET_CONTROLLER _IO('n', 5) 41 42/* 43 * Use to mark a command to apply to all namespaces, or to retrieve global 44 * log pages. 45 */ 46#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 47 48union cap_lo_register { 49 uint32_t raw; 50 struct { 51 /** maximum queue entries supported */ 52 uint32_t mqes : 16; 53 54 /** contiguous queues required */ 55 uint32_t cqr : 1; 56 57 /** arbitration mechanism supported */ 58 uint32_t ams : 2; 59 60 uint32_t reserved1 : 5; 61 62 /** timeout */ 63 uint32_t to : 8; 64 } bits __packed; 65} __packed; 66 67union cap_hi_register { 68 uint32_t raw; 69 struct { 70 /** doorbell stride */ 71 uint32_t dstrd : 4; 72 73 uint32_t reserved3 : 1; 74 75 /** command sets supported */ 76 uint32_t css_nvm : 1; 77 78 uint32_t css_reserved : 3; 79 uint32_t reserved2 : 7; 80 81 /** memory page size minimum */ 82 uint32_t mpsmin : 4; 83 84 /** memory page size maximum */ 85 uint32_t mpsmax : 4; 86 87 uint32_t reserved1 : 8; 88 } bits __packed; 89} __packed; 90 91union cc_register { 92 uint32_t raw; 93 struct { 94 /** enable */ 95 uint32_t en : 1; 96 97 uint32_t reserved1 : 3; 98 99 /** i/o command set selected */ 100 uint32_t css : 3; 101 102 /** memory page size */ 103 uint32_t mps : 4; 104 105 /** arbitration mechanism selected */ 106 uint32_t ams : 3; 107 108 /** shutdown notification */ 109 uint32_t shn : 2; 110 111 /** i/o submission queue entry size */ 112 uint32_t iosqes : 4; 113 114 /** i/o completion queue entry size */ 115 uint32_t iocqes : 4; 116 117 uint32_t reserved2 : 8; 118 } bits __packed; 119} __packed; 120 121enum shn_value { 122 NVME_SHN_NORMAL = 0x1, 123 NVME_SHN_ABRUPT = 0x2, 124}; 125 126union csts_register { 127 uint32_t raw; 128 struct { 129 /** ready */ 130 uint32_t rdy : 1; 131 132 /** controller fatal status */ 133 uint32_t cfs : 1; 134 135 /** shutdown status */ 136 uint32_t shst : 2; 137 138 uint32_t reserved1 : 28; 139 } bits __packed; 140} __packed; 141 142enum shst_value { 143 NVME_SHST_NORMAL = 0x0, 144 NVME_SHST_OCCURRING = 0x1, 145 NVME_SHST_COMPLETE = 0x2, 146}; 147 148union aqa_register { 149 uint32_t raw; 150 struct { 151 /** admin submission queue size */ 152 uint32_t asqs : 12; 153 154 uint32_t reserved1 : 4; 155 156 /** admin completion queue size */ 157 uint32_t acqs : 12; 158 159 uint32_t reserved2 : 4; 160 } bits __packed; 161} __packed; 162 163struct nvme_registers 164{ 165 /** controller capabilities */ 166 union cap_lo_register cap_lo; 167 union cap_hi_register cap_hi; 168 169 uint32_t vs; /* version */ 170 uint32_t intms; /* interrupt mask set */ 171 uint32_t intmc; /* interrupt mask clear */ 172 173 /** controller configuration */ 174 union cc_register cc; 175 176 uint32_t reserved1; 177 uint32_t csts; /* controller status */ 178 uint32_t reserved2; 179 180 /** admin queue attributes */ 181 union aqa_register aqa; 182 183 uint64_t asq; /* admin submission queue base addr */ 184 uint64_t acq; /* admin completion queue base addr */ 185 uint32_t reserved3[0x3f2]; 186 187 struct { 188 uint32_t sq_tdbl; /* submission queue tail doorbell */ 189 uint32_t cq_hdbl; /* completion queue head doorbell */ 190 } doorbell[1] __packed; 191} __packed; 192 193struct nvme_command 194{ 195 /* dword 0 */ 196 uint16_t opc : 8; /* opcode */ 197 uint16_t fuse : 2; /* fused operation */ 198 uint16_t rsvd1 : 6; 199 uint16_t cid; /* command identifier */ 200 201 /* dword 1 */ 202 uint32_t nsid; /* namespace identifier */ 203 204 /* dword 2-3 */ 205 uint32_t rsvd2; 206 uint32_t rsvd3; 207 208 /* dword 4-5 */ 209 uint64_t mptr; /* metadata pointer */ 210 211 /* dword 6-7 */ 212 uint64_t prp1; /* prp entry 1 */ 213 214 /* dword 8-9 */ 215 uint64_t prp2; /* prp entry 2 */ 216 217 /* dword 10-15 */ 218 uint32_t cdw10; /* command-specific */ 219 uint32_t cdw11; /* command-specific */ 220 uint32_t cdw12; /* command-specific */ 221 uint32_t cdw13; /* command-specific */ 222 uint32_t cdw14; /* command-specific */ 223 uint32_t cdw15; /* command-specific */ 224} __packed; 225 226struct nvme_completion { 227 228 /* dword 0 */ 229 uint32_t cdw0; /* command-specific */ 230 231 /* dword 1 */ 232 uint32_t rsvd1; 233 234 /* dword 2 */ 235 uint16_t sqhd; /* submission queue head pointer */ 236 uint16_t sqid; /* submission queue identifier */ 237 238 /* dword 3 */ 239 uint16_t cid; /* command identifier */ 240 uint16_t p : 1; /* phase tag */ 241 uint16_t sf_sc : 8; /* status field - status code */ 242 uint16_t sf_sct : 3; /* status field - status code type */ 243 uint16_t rsvd2 : 2; 244 uint16_t sf_m : 1; /* status field - more */ 245 uint16_t sf_dnr : 1; /* status field - do not retry */ 246} __packed; 247 248struct nvme_dsm_range { 249 250 uint32_t attributes; 251 uint32_t length; 252 uint64_t starting_lba; 253} __packed; 254 255/* status code types */ 256enum nvme_status_code_type { 257 NVME_SCT_GENERIC = 0x0, 258 NVME_SCT_COMMAND_SPECIFIC = 0x1, 259 NVME_SCT_MEDIA_ERROR = 0x2, 260 /* 0x3-0x6 - reserved */ 261 NVME_SCT_VENDOR_SPECIFIC = 0x7, 262}; 263 264/* generic command status codes */ 265enum nvme_generic_command_status_code { 266 NVME_SC_SUCCESS = 0x00, 267 NVME_SC_INVALID_OPCODE = 0x01, 268 NVME_SC_INVALID_FIELD = 0x02, 269 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 270 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 271 NVME_SC_ABORTED_POWER_LOSS = 0x05, 272 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 273 NVME_SC_ABORTED_BY_REQUEST = 0x07, 274 NVME_SC_ABORTED_SQ_DELETION = 0x08, 275 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 276 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 277 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 278 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 279 280 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 281 NVME_SC_CAPACITY_EXCEEDED = 0x81, 282 NVME_SC_NAMESPACE_NOT_READY = 0x82, 283}; 284 285/* command specific status codes */ 286enum nvme_command_specific_status_code { 287 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 288 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 289 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 290 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 291 /* 0x04 - reserved */ 292 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 293 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 294 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 295 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 296 NVME_SC_INVALID_LOG_PAGE = 0x09, 297 NVME_SC_INVALID_FORMAT = 0x0a, 298 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 299 300 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 301 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 302 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 303}; 304 305/* media error status codes */ 306enum nvme_media_error_status_code { 307 NVME_SC_WRITE_FAULTS = 0x80, 308 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 309 NVME_SC_GUARD_CHECK_ERROR = 0x82, 310 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 311 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 312 NVME_SC_COMPARE_FAILURE = 0x85, 313 NVME_SC_ACCESS_DENIED = 0x86, 314}; 315 316/* admin opcodes */ 317enum nvme_admin_opcode { 318 NVME_OPC_DELETE_IO_SQ = 0x00, 319 NVME_OPC_CREATE_IO_SQ = 0x01, 320 NVME_OPC_GET_LOG_PAGE = 0x02, 321 /* 0x03 - reserved */ 322 NVME_OPC_DELETE_IO_CQ = 0x04, 323 NVME_OPC_CREATE_IO_CQ = 0x05, 324 NVME_OPC_IDENTIFY = 0x06, 325 /* 0x07 - reserved */ 326 NVME_OPC_ABORT = 0x08, 327 NVME_OPC_SET_FEATURES = 0x09, 328 NVME_OPC_GET_FEATURES = 0x0a, 329 /* 0x0b - reserved */ 330 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 331 /* 0x0d-0x0f - reserved */ 332 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 333 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 334 335 NVME_OPC_FORMAT_NVM = 0x80, 336 NVME_OPC_SECURITY_SEND = 0x81, 337 NVME_OPC_SECURITY_RECEIVE = 0x82, 338}; 339 340/* nvme nvm opcodes */ 341enum nvme_nvm_opcode { 342 NVME_OPC_FLUSH = 0x00, 343 NVME_OPC_WRITE = 0x01, 344 NVME_OPC_READ = 0x02, 345 /* 0x03 - reserved */ 346 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 347 NVME_OPC_COMPARE = 0x05, 348 /* 0x06-0x07 - reserved */ 349 NVME_OPC_DATASET_MANAGEMENT = 0x09, 350}; 351 352enum nvme_feature { 353 /* 0x00 - reserved */ 354 NVME_FEAT_ARBITRATION = 0x01, 355 NVME_FEAT_POWER_MANAGEMENT = 0x02, 356 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 357 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 358 NVME_FEAT_ERROR_RECOVERY = 0x05, 359 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 360 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 361 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 362 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 363 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 364 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 365 /* 0x0C-0x7F - reserved */ 366 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 367 /* 0x81-0xBF - command set specific (reserved) */ 368 /* 0xC0-0xFF - vendor specific */ 369}; 370 371enum nvme_dsm_attribute { 372 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 373 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 374 NVME_DSM_ATTR_DEALLOCATE = 0x4, 375}; 376 377struct nvme_controller_data { 378 379 /* bytes 0-255: controller capabilities and features */ 380 381 /** pci vendor id */ 382 uint16_t vid; 383 384 /** pci subsystem vendor id */ 385 uint16_t ssvid; 386 387 /** serial number */ 388 int8_t sn[20]; 389 390 /** model number */ 391 int8_t mn[40]; 392 393 /** firmware revision */ 394 uint8_t fr[8]; 395 396 /** recommended arbitration burst */ 397 uint8_t rab; 398 399 /** ieee oui identifier */ 400 uint8_t ieee[3]; 401 402 /** multi-interface capabilities */ 403 uint8_t mic; 404 405 /** maximum data transfer size */ 406 uint8_t mdts; 407 408 uint8_t reserved1[178]; 409 410 /* bytes 256-511: admin command set attributes */ 411 412 /** optional admin command support */ 413 struct { 414 /* supports security send/receive commands */ 415 uint16_t security : 1; 416 417 /* supports format nvm command */ 418 uint16_t format : 1; 419 420 /* supports firmware activate/download commands */ 421 uint16_t firmware : 1; 422 423 uint16_t oacs_rsvd : 13; 424 } __packed oacs; 425 426 /** abort command limit */ 427 uint8_t acl; 428 429 /** asynchronous event request limit */ 430 uint8_t aerl; 431 432 /** firmware updates */ 433 struct { 434 /* first slot is read-only */ 435 uint8_t slot1_ro : 1; 436 437 /* number of firmware slots */ 438 uint8_t num_slots : 3; 439 440 uint8_t frmw_rsvd : 4; 441 } __packed frmw; 442 443 /** log page attributes */ 444 struct { 445 /* per namespace smart/health log page */ 446 uint8_t ns_smart : 1; 447 448 uint8_t lpa_rsvd : 7; 449 } __packed lpa; 450 451 /** error log page entries */ 452 uint8_t elpe; 453 454 /** number of power states supported */ 455 uint8_t npss; 456 457 /** admin vendor specific command configuration */ 458 struct { 459 /* admin vendor specific commands use spec format */ 460 uint8_t spec_format : 1; 461 462 uint8_t avscc_rsvd : 7; 463 } __packed avscc; 464 465 uint8_t reserved2[247]; 466 467 /* bytes 512-703: nvm command set attributes */ 468 469 /** submission queue entry size */ 470 struct { 471 uint8_t min : 4; 472 uint8_t max : 4; 473 } __packed sqes; 474 475 /** completion queue entry size */ 476 struct { 477 uint8_t min : 4; 478 uint8_t max : 4; 479 } __packed cqes; 480 481 uint8_t reserved3[2]; 482 483 /** number of namespaces */ 484 uint32_t nn; 485 486 /** optional nvm command support */ 487 struct { 488 uint16_t compare : 1; 489 uint16_t write_unc : 1; 490 uint16_t dsm: 1; 491 uint16_t reserved: 13; 492 } __packed oncs; 493 494 /** fused operation support */ 495 uint16_t fuses; 496 497 /** format nvm attributes */ 498 uint8_t fna; 499 500 /** volatile write cache */ 501 struct { 502 uint8_t present : 1; 503 uint8_t reserved : 7; 504 } __packed vwc; 505 506 /* TODO: flesh out remaining nvm command set attributes */ 507 uint8_t reserved4[178]; 508 509 /* bytes 704-2047: i/o command set attributes */ 510 uint8_t reserved5[1344]; 511 512 /* bytes 2048-3071: power state descriptors */ 513 uint8_t reserved6[1024]; 514 515 /* bytes 3072-4095: vendor specific */ 516 uint8_t reserved7[1024]; 517} __packed __aligned(4); 518 519struct nvme_namespace_data { 520 521 /** namespace size */ 522 uint64_t nsze; 523 524 /** namespace capacity */ 525 uint64_t ncap; 526 527 /** namespace utilization */ 528 uint64_t nuse; 529 530 /** namespace features */ 531 struct { 532 /** thin provisioning */ 533 uint8_t thin_prov : 1; 534 uint8_t reserved1 : 7; 535 } __packed nsfeat; 536 537 /** number of lba formats */ 538 uint8_t nlbaf; 539 540 /** formatted lba size */ 541 struct { 542 uint8_t format : 4; 543 uint8_t extended : 1; 544 uint8_t reserved2 : 3; 545 } __packed flbas; 546 547 /** metadata capabilities */ 548 struct { 549 /* metadata can be transferred as part of data prp list */ 550 uint8_t extended : 1; 551 552 /* metadata can be transferred with separate metadata pointer */ 553 uint8_t pointer : 1; 554 555 uint8_t reserved3 : 6; 556 } __packed mc; 557 558 /** end-to-end data protection capabilities */ 559 struct { 560 /* protection information type 1 */ 561 uint8_t pit1 : 1; 562 563 /* protection information type 2 */ 564 uint8_t pit2 : 1; 565 566 /* protection information type 3 */ 567 uint8_t pit3 : 1; 568 569 /* first eight bytes of metadata */ 570 uint8_t md_start : 1; 571 572 /* last eight bytes of metadata */ 573 uint8_t md_end : 1; 574 } __packed dpc; 575 576 /** end-to-end data protection type settings */ 577 struct { 578 /* protection information type */ 579 uint8_t pit : 3; 580 581 /* 1 == protection info transferred at start of metadata */ 582 /* 0 == protection info transferred at end of metadata */ 583 uint8_t md_start : 1; 584 585 uint8_t reserved4 : 4; 586 } __packed dps; 587 588 uint8_t reserved5[98]; 589 590 /** lba format support */ 591 struct { 592 /** metadata size */ 593 uint32_t ms : 16; 594 595 /** lba data size */ 596 uint32_t lbads : 8; 597 598 /** relative performance */ 599 uint32_t rp : 2; 600 601 uint32_t reserved6 : 6; 602 } __packed lbaf[16]; 603 604 uint8_t reserved6[192]; 605 606 uint8_t vendor_specific[3712]; 607} __packed __aligned(4); 608 609enum nvme_log_page { 610 611 /* 0x00 - reserved */ 612 NVME_LOG_ERROR = 0x01, 613 NVME_LOG_HEALTH_INFORMATION = 0x02, 614 NVME_LOG_FIRMWARE_SLOT = 0x03, 615 /* 0x04-0x7F - reserved */ 616 /* 0x80-0xBF - I/O command set specific */ 617 /* 0xC0-0xFF - vendor specific */ 618}; 619 620union nvme_critical_warning_state { 621 622 uint8_t raw; 623 624 struct { 625 uint8_t available_spare : 1; 626 uint8_t temperature : 1; 627 uint8_t device_reliability : 1; 628 uint8_t read_only : 1; 629 uint8_t volatile_memory_backup : 1; 630 uint8_t reserved : 3; 631 } __packed bits; 632} __packed; 633 634struct nvme_health_information_page { 635 636 union nvme_critical_warning_state critical_warning; 637 638 uint16_t temperature; 639 uint8_t available_spare; 640 uint8_t available_spare_threshold; 641 uint8_t percentage_used; 642 643 uint8_t reserved[26]; 644 645 /* 646 * Note that the following are 128-bit values, but are 647 * defined as an array of 2 64-bit values. 648 */ 649 /* Data Units Read is always in 512-byte units. */ 650 uint64_t data_units_read[2]; 651 /* Data Units Written is always in 512-byte units. */ 652 uint64_t data_units_written[2]; 653 /* For NVM command set, this includes Compare commands. */ 654 uint64_t host_read_commands[2]; 655 uint64_t host_write_commands[2]; 656 /* Controller Busy Time is reported in minutes. */ 657 uint64_t controller_busy_time[2]; 658 uint64_t power_cycles[2]; 659 uint64_t power_on_hours[2]; 660 uint64_t unsafe_shutdowns[2]; 661 uint64_t media_errors[2]; 662 uint64_t num_error_info_log_entries[2]; 663 664 uint8_t reserved2[320]; 665} __packed __aligned(4); 666 667#define NVME_TEST_MAX_THREADS 128 668 669struct nvme_io_test { 670 671 enum nvme_nvm_opcode opc; 672 uint32_t size; 673 uint32_t time; /* in seconds */ 674 uint32_t num_threads; 675 uint32_t flags; 676 uint32_t io_completed[NVME_TEST_MAX_THREADS]; 677}; 678 679enum nvme_io_test_flags { 680 681 /* 682 * Specifies whether dev_refthread/dev_relthread should be 683 * called during NVME_BIO_TEST. Ignored for other test 684 * types. 685 */ 686 NVME_TEST_FLAG_REFTHREAD = 0x1, 687}; 688 689#ifdef _KERNEL 690 691struct bio; 692 693struct nvme_namespace; 694struct nvme_controller; 695struct nvme_consumer; 696 697typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 698 699typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 700typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 701typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *); 702 703enum nvme_namespace_flags { 704 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 705 NVME_NS_FLUSH_SUPPORTED = 0x2, 706}; 707 708/* Admin functions */ 709void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 710 uint8_t feature, uint32_t cdw11, 711 void *payload, uint32_t payload_size, 712 nvme_cb_fn_t cb_fn, void *cb_arg); 713void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 714 uint8_t feature, uint32_t cdw11, 715 void *payload, uint32_t payload_size, 716 nvme_cb_fn_t cb_fn, void *cb_arg); 717void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 718 uint8_t log_page, uint32_t nsid, 719 void *payload, uint32_t payload_size, 720 nvme_cb_fn_t cb_fn, void *cb_arg); 721 722/* NVM I/O functions */ 723int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 724 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 725 void *cb_arg); 726int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 727 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 728 void *cb_arg); 729int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 730 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 731 void *cb_arg); 732int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 733 void *cb_arg); 734 735/* Registration functions */ 736struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 737 nvme_cons_ctrlr_fn_t ctrlr_fn, 738 nvme_cons_async_fn_t async_fn); 739void nvme_unregister_consumer(struct nvme_consumer *consumer); 740 741/* Controller helper functions */ 742device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 743const struct nvme_controller_data * 744 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 745 746/* Namespace helper functions */ 747uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 748uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 749uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 750uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 751uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 752const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 753const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 754const struct nvme_namespace_data * 755 nvme_ns_get_data(struct nvme_namespace *ns); 756 757int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 758 nvme_cb_fn_t cb_fn); 759 760#endif /* _KERNEL */ 761 762#endif /* __NVME_H__ */ 763