1250079Scarl/*- 2302484Smav * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 3250079Scarl * Copyright (C) 2013 Intel Corporation 4289542Scem * Copyright (C) 2015 EMC Corporation 5250079Scarl * All rights reserved. 6250079Scarl * 7250079Scarl * Redistribution and use in source and binary forms, with or without 8250079Scarl * modification, are permitted provided that the following conditions 9250079Scarl * are met: 10250079Scarl * 1. Redistributions of source code must retain the above copyright 11250079Scarl * notice, this list of conditions and the following disclaimer. 12250079Scarl * 2. Redistributions in binary form must reproduce the above copyright 13250079Scarl * notice, this list of conditions and the following disclaimer in the 14250079Scarl * documentation and/or other materials provided with the distribution. 15250079Scarl * 16250079Scarl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17250079Scarl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18250079Scarl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19250079Scarl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20250079Scarl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21250079Scarl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22250079Scarl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23250079Scarl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24250079Scarl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25250079Scarl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26250079Scarl * SUCH DAMAGE. 27250079Scarl * 28250079Scarl * $FreeBSD: stable/11/sys/dev/ntb/ntb_hw/ntb_hw_intel.h 323453 2017-09-11 18:48:09Z mav $ 29250079Scarl */ 30250079Scarl 31250079Scarl#ifndef _NTB_REGS_H_ 32250079Scarl#define _NTB_REGS_H_ 33250079Scarl 34250079Scarl#define NTB_LINK_STATUS_ACTIVE 0x2000 35250079Scarl#define NTB_LINK_SPEED_MASK 0x000f 36250079Scarl#define NTB_LINK_WIDTH_MASK 0x03f0 37289546Scem#define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4) 38250079Scarl 39289539Scem#define XEON_SNB_MW_COUNT 2 40289539Scem#define XEON_HSX_SPLIT_MW_COUNT 3 41250079Scarl/* Reserve the uppermost bit for link interrupt */ 42289538Scem#define XEON_DB_COUNT 15 43290680Scem#define XEON_DB_TOTAL_SHIFT 16 44289538Scem#define XEON_DB_LINK 15 45289538Scem#define XEON_DB_MSIX_VECTOR_COUNT 4 46289538Scem#define XEON_DB_MSIX_VECTOR_SHIFT 5 47289538Scem#define XEON_DB_LINK_BIT (1 << XEON_DB_LINK) 48295618Scem#define XEON_NONLINK_DB_MSIX_BITS 3 49250079Scarl 50290682Scem#define XEON_SPCICMD_OFFSET 0x0504 51250079Scarl#define XEON_DEVCTRL_OFFSET 0x0598 52289774Scem#define XEON_DEVSTS_OFFSET 0x059a 53255277Scarl#define XEON_LINK_STATUS_OFFSET 0x01a2 54289257Scem#define XEON_SLINK_STATUS_OFFSET 0x05a2 55250079Scarl 56250079Scarl#define XEON_PBAR2LMT_OFFSET 0x0000 57250079Scarl#define XEON_PBAR4LMT_OFFSET 0x0008 58289397Scem#define XEON_PBAR5LMT_OFFSET 0x000c 59250079Scarl#define XEON_PBAR2XLAT_OFFSET 0x0010 60250079Scarl#define XEON_PBAR4XLAT_OFFSET 0x0018 61289397Scem#define XEON_PBAR5XLAT_OFFSET 0x001c 62250079Scarl#define XEON_SBAR2LMT_OFFSET 0x0020 63250079Scarl#define XEON_SBAR4LMT_OFFSET 0x0028 64289397Scem#define XEON_SBAR5LMT_OFFSET 0x002c 65250079Scarl#define XEON_SBAR2XLAT_OFFSET 0x0030 66250079Scarl#define XEON_SBAR4XLAT_OFFSET 0x0038 67289397Scem#define XEON_SBAR5XLAT_OFFSET 0x003c 68250079Scarl#define XEON_SBAR0BASE_OFFSET 0x0040 69250079Scarl#define XEON_SBAR2BASE_OFFSET 0x0048 70250079Scarl#define XEON_SBAR4BASE_OFFSET 0x0050 71289397Scem#define XEON_SBAR5BASE_OFFSET 0x0054 72250079Scarl#define XEON_NTBCNTL_OFFSET 0x0058 73255277Scarl#define XEON_SBDF_OFFSET 0x005c 74250079Scarl#define XEON_PDOORBELL_OFFSET 0x0060 75250079Scarl#define XEON_PDBMSK_OFFSET 0x0062 76250079Scarl#define XEON_SDOORBELL_OFFSET 0x0064 77250079Scarl#define XEON_SDBMSK_OFFSET 0x0066 78289774Scem#define XEON_USMEMMISS_OFFSET 0x0070 79255277Scarl#define XEON_SPAD_OFFSET 0x0080 80302484Smav#define XEON_SPAD_COUNT 16 81250079Scarl#define XEON_SPADSEMA4_OFFSET 0x00c0 82250079Scarl#define XEON_WCCNTRL_OFFSET 0x00e0 83289774Scem#define XEON_UNCERRSTS_OFFSET 0x014c 84289774Scem#define XEON_CORERRSTS_OFFSET 0x0158 85250079Scarl#define XEON_B2B_SPAD_OFFSET 0x0100 86250079Scarl#define XEON_B2B_DOORBELL_OFFSET 0x0140 87289208Scem#define XEON_B2B_XLAT_OFFSETL 0x0144 88289208Scem#define XEON_B2B_XLAT_OFFSETU 0x0148 89250079Scarl 90289648Scem#define ATOM_MW_COUNT 2 91289648Scem#define ATOM_DB_COUNT 34 92289648Scem#define ATOM_DB_MSIX_VECTOR_COUNT 34 93289648Scem#define ATOM_DB_MSIX_VECTOR_SHIFT 1 94250079Scarl 95290682Scem#define ATOM_SPCICMD_OFFSET 0xb004 96289648Scem#define ATOM_MBAR23_OFFSET 0xb018 97289648Scem#define ATOM_MBAR45_OFFSET 0xb020 98289648Scem#define ATOM_DEVCTRL_OFFSET 0xb048 99289648Scem#define ATOM_LINK_STATUS_OFFSET 0xb052 100289648Scem#define ATOM_ERRCORSTS_OFFSET 0xb110 101250079Scarl 102289648Scem#define ATOM_SBAR2XLAT_OFFSET 0x0008 103289648Scem#define ATOM_SBAR4XLAT_OFFSET 0x0010 104289648Scem#define ATOM_PDOORBELL_OFFSET 0x0020 105289648Scem#define ATOM_PDBMSK_OFFSET 0x0028 106289648Scem#define ATOM_NTBCNTL_OFFSET 0x0060 107289648Scem#define ATOM_EBDF_OFFSET 0x0064 108289648Scem#define ATOM_SPAD_OFFSET 0x0080 109302484Smav#define ATOM_SPAD_COUNT 16 110289648Scem#define ATOM_SPADSEMA_OFFSET 0x00c0 111289648Scem#define ATOM_STKYSPAD_OFFSET 0x00c4 112289648Scem#define ATOM_PBAR2XLAT_OFFSET 0x8008 113289648Scem#define ATOM_PBAR4XLAT_OFFSET 0x8010 114289648Scem#define ATOM_B2B_DOORBELL_OFFSET 0x8020 115289648Scem#define ATOM_B2B_SPAD_OFFSET 0x8080 116289648Scem#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0 117289648Scem#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4 118250079Scarl 119289648Scem#define ATOM_MODPHY_PCSREG4 0x1c004 120289648Scem#define ATOM_MODPHY_PCSREG6 0x1c006 121250079Scarl 122289648Scem#define ATOM_IP_BASE 0xc000 123289648Scem#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024) 124289648Scem#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180) 125289648Scem#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040) 126289648Scem#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324) 127250079Scarl 128289648Scem#define ATOM_DESKEWSTS_DBERR (1 << 15) 129289648Scem#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) 130289648Scem#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2) 131289648Scem#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff 132250079Scarl 133289280Scem#define NTB_CNTL_CFG_LOCK (1 << 0) 134289280Scem#define NTB_CNTL_LINK_DISABLE (1 << 1) 135289280Scem#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2) 136289280Scem#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4) 137289397Scem#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6) 138289397Scem#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8) 139289397Scem#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12) 140289397Scem#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14) 141289648Scem#define ATOM_CNTL_LINK_DOWN (1 << 16) 142250079Scarl 143255276Scarl#define XEON_PBAR23SZ_OFFSET 0x00d0 144255276Scarl#define XEON_PBAR45SZ_OFFSET 0x00d1 145289543Scem#define XEON_PBAR4SZ_OFFSET 0x00d1 146289543Scem#define XEON_PBAR5SZ_OFFSET 0x00d5 147289543Scem#define XEON_SBAR23SZ_OFFSET 0x00d2 148289543Scem#define XEON_SBAR4SZ_OFFSET 0x00d3 149289543Scem#define XEON_SBAR5SZ_OFFSET 0x00d6 150255277Scarl#define NTB_PPD_OFFSET 0x00d4 151250079Scarl#define XEON_PPD_CONN_TYPE 0x0003 152250079Scarl#define XEON_PPD_DEV_TYPE 0x0010 153289397Scem#define XEON_PPD_SPLIT_BAR 0x0040 154289648Scem#define ATOM_PPD_INIT_LINK 0x0008 155289648Scem#define ATOM_PPD_CONN_TYPE 0x0300 156289648Scem#define ATOM_PPD_DEV_TYPE 0x1000 157250079Scarl 158289397Scem/* All addresses are in low 32-bit space so 32-bit BARs can function */ 159290725Scem#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull 160290725Scem#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull 161290725Scem#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull 162290725Scem#define XEON_B2B_BAR4_ADDR32 0x20000000ull 163290725Scem#define XEON_B2B_BAR5_ADDR32 0x40000000ull 164250079Scarl 165289542Scem/* The peer ntb secondary config space is 32KB fixed size */ 166289542Scem#define XEON_B2B_MIN_SIZE 0x8000 167289542Scem 168250079Scarl#endif /* _NTB_REGS_H_ */ 169