ntb_hw_intel.c revision 295486
1250079Scarl/*- 2250079Scarl * Copyright (C) 2013 Intel Corporation 3289542Scem * Copyright (C) 2015 EMC Corporation 4250079Scarl * All rights reserved. 5250079Scarl * 6250079Scarl * Redistribution and use in source and binary forms, with or without 7250079Scarl * modification, are permitted provided that the following conditions 8250079Scarl * are met: 9250079Scarl * 1. Redistributions of source code must retain the above copyright 10250079Scarl * notice, this list of conditions and the following disclaimer. 11250079Scarl * 2. Redistributions in binary form must reproduce the above copyright 12250079Scarl * notice, this list of conditions and the following disclaimer in the 13250079Scarl * documentation and/or other materials provided with the distribution. 14250079Scarl * 15250079Scarl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16250079Scarl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250079Scarl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250079Scarl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19250079Scarl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20250079Scarl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21250079Scarl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22250079Scarl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23250079Scarl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24250079Scarl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25250079Scarl * SUCH DAMAGE. 26250079Scarl */ 27250079Scarl 28250079Scarl#include <sys/cdefs.h> 29250079Scarl__FBSDID("$FreeBSD: head/sys/dev/ntb/ntb_hw/ntb_hw.c 295486 2016-02-10 20:28:28Z cem $"); 30250079Scarl 31250079Scarl#include <sys/param.h> 32250079Scarl#include <sys/kernel.h> 33250079Scarl#include <sys/systm.h> 34250079Scarl#include <sys/bus.h> 35289774Scem#include <sys/endian.h> 36250079Scarl#include <sys/malloc.h> 37250079Scarl#include <sys/module.h> 38250079Scarl#include <sys/queue.h> 39250079Scarl#include <sys/rman.h> 40289774Scem#include <sys/sbuf.h> 41289207Scem#include <sys/sysctl.h> 42250079Scarl#include <vm/vm.h> 43250079Scarl#include <vm/pmap.h> 44250079Scarl#include <machine/bus.h> 45250079Scarl#include <machine/pmap.h> 46250079Scarl#include <machine/resource.h> 47250079Scarl#include <dev/pci/pcireg.h> 48250079Scarl#include <dev/pci/pcivar.h> 49250079Scarl 50250079Scarl#include "ntb_regs.h" 51250079Scarl#include "ntb_hw.h" 52250079Scarl 53250079Scarl/* 54250079Scarl * The Non-Transparent Bridge (NTB) is a device on some Intel processors that 55250079Scarl * allows you to connect two systems using a PCI-e link. 56250079Scarl * 57250079Scarl * This module contains the hardware abstraction layer for the NTB. It allows 58250079Scarl * you to send and recieve interrupts, map the memory windows and send and 59250079Scarl * receive messages in the scratch-pad registers. 60250079Scarl * 61250079Scarl * NOTE: Much of the code in this module is shared with Linux. Any patches may 62250079Scarl * be picked up and redistributed in Linux with a dual GPL/BSD license. 63250079Scarl */ 64250079Scarl 65289648Scem#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 66250079Scarl 67289539Scem#define NTB_HB_TIMEOUT 1 /* second */ 68289648Scem#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 69291032Scem#define BAR_HIGH_MASK (~((1ull << 12) - 1)) 70250079Scarl 71250079Scarl#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) 72250079Scarl 73250079Scarlenum ntb_device_type { 74250079Scarl NTB_XEON, 75289648Scem NTB_ATOM 76250079Scarl}; 77250079Scarl 78289610Scem/* ntb_conn_type are hardware numbers, cannot change. */ 79289610Scemenum ntb_conn_type { 80289610Scem NTB_CONN_TRANSPARENT = 0, 81289610Scem NTB_CONN_B2B = 1, 82289610Scem NTB_CONN_RP = 2, 83289610Scem}; 84289610Scem 85289610Scemenum ntb_b2b_direction { 86289610Scem NTB_DEV_USD = 0, 87289610Scem NTB_DEV_DSD = 1, 88289610Scem}; 89289610Scem 90289539Scemenum ntb_bar { 91289539Scem NTB_CONFIG_BAR = 0, 92289539Scem NTB_B2B_BAR_1, 93289539Scem NTB_B2B_BAR_2, 94289539Scem NTB_B2B_BAR_3, 95289539Scem NTB_MAX_BARS 96289539Scem}; 97289539Scem 98255274Scarl/* Device features and workarounds */ 99255274Scarl#define HAS_FEATURE(feature) \ 100255274Scarl ((ntb->features & (feature)) != 0) 101255274Scarl 102250079Scarlstruct ntb_hw_info { 103250079Scarl uint32_t device_id; 104255274Scarl const char *desc; 105250079Scarl enum ntb_device_type type; 106289397Scem uint32_t features; 107250079Scarl}; 108250079Scarl 109250079Scarlstruct ntb_pci_bar_info { 110250079Scarl bus_space_tag_t pci_bus_tag; 111250079Scarl bus_space_handle_t pci_bus_handle; 112250079Scarl int pci_resource_id; 113250079Scarl struct resource *pci_resource; 114250079Scarl vm_paddr_t pbase; 115290679Scem caddr_t vbase; 116290679Scem vm_size_t size; 117291280Scem vm_memattr_t map_mode; 118289543Scem 119289543Scem /* Configuration register offsets */ 120289543Scem uint32_t psz_off; 121289543Scem uint32_t ssz_off; 122289543Scem uint32_t pbarxlat_off; 123250079Scarl}; 124250079Scarl 125250079Scarlstruct ntb_int_info { 126250079Scarl struct resource *res; 127250079Scarl int rid; 128250079Scarl void *tag; 129250079Scarl}; 130250079Scarl 131289546Scemstruct ntb_vec { 132250079Scarl struct ntb_softc *ntb; 133289546Scem uint32_t num; 134250079Scarl}; 135250079Scarl 136289542Scemstruct ntb_reg { 137289542Scem uint32_t ntb_ctl; 138289542Scem uint32_t lnk_sta; 139289542Scem uint8_t db_size; 140289542Scem unsigned mw_bar[NTB_MAX_BARS]; 141289542Scem}; 142289542Scem 143289542Scemstruct ntb_alt_reg { 144289542Scem uint32_t db_bell; 145289542Scem uint32_t db_mask; 146289542Scem uint32_t spad; 147289542Scem}; 148289542Scem 149289542Scemstruct ntb_xlat_reg { 150289546Scem uint32_t bar0_base; 151289546Scem uint32_t bar2_base; 152289546Scem uint32_t bar4_base; 153289546Scem uint32_t bar5_base; 154289546Scem 155289546Scem uint32_t bar2_xlat; 156289546Scem uint32_t bar4_xlat; 157289546Scem uint32_t bar5_xlat; 158289546Scem 159289546Scem uint32_t bar2_limit; 160289546Scem uint32_t bar4_limit; 161289546Scem uint32_t bar5_limit; 162289542Scem}; 163289542Scem 164289542Scemstruct ntb_b2b_addr { 165289542Scem uint64_t bar0_addr; 166289542Scem uint64_t bar2_addr64; 167289542Scem uint64_t bar4_addr64; 168289542Scem uint64_t bar4_addr32; 169289542Scem uint64_t bar5_addr32; 170289542Scem}; 171289542Scem 172250079Scarlstruct ntb_softc { 173250079Scarl device_t device; 174250079Scarl enum ntb_device_type type; 175289774Scem uint32_t features; 176250079Scarl 177250079Scarl struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 178250079Scarl struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 179250079Scarl uint32_t allocated_interrupts; 180250079Scarl 181250079Scarl struct callout heartbeat_timer; 182250079Scarl struct callout lr_timer; 183250079Scarl 184289546Scem void *ntb_ctx; 185289546Scem const struct ntb_ctx_ops *ctx_ops; 186289546Scem struct ntb_vec *msix_vec; 187290683Scem#define CTX_LOCK(sc) mtx_lock(&(sc)->ctx_lock) 188290683Scem#define CTX_UNLOCK(sc) mtx_unlock(&(sc)->ctx_lock) 189289546Scem#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f)) 190289546Scem struct mtx ctx_lock; 191250079Scarl 192289610Scem uint32_t ppd; 193289610Scem enum ntb_conn_type conn_type; 194289610Scem enum ntb_b2b_direction dev_type; 195289539Scem 196289542Scem /* Offset of peer bar0 in B2B BAR */ 197289542Scem uint64_t b2b_off; 198289542Scem /* Memory window used to access peer bar0 */ 199289543Scem#define B2B_MW_DISABLED UINT8_MAX 200289542Scem uint8_t b2b_mw_idx; 201289542Scem 202289539Scem uint8_t mw_count; 203289539Scem uint8_t spad_count; 204289539Scem uint8_t db_count; 205289539Scem uint8_t db_vec_count; 206289539Scem uint8_t db_vec_shift; 207289542Scem 208289546Scem /* Protects local db_mask. */ 209289546Scem#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 210289546Scem#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 211289546Scem#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 212289542Scem struct mtx db_mask_lock; 213289542Scem 214290686Scem volatile uint32_t ntb_ctl; 215290686Scem volatile uint32_t lnk_sta; 216289542Scem 217289542Scem uint64_t db_valid_mask; 218289542Scem uint64_t db_link_mask; 219289546Scem uint64_t db_mask; 220289542Scem 221289542Scem int last_ts; /* ticks @ last irq */ 222289542Scem 223289542Scem const struct ntb_reg *reg; 224289542Scem const struct ntb_alt_reg *self_reg; 225289542Scem const struct ntb_alt_reg *peer_reg; 226289542Scem const struct ntb_xlat_reg *xlat_reg; 227250079Scarl}; 228250079Scarl 229289234Scem#ifdef __i386__ 230289234Scemstatic __inline uint64_t 231289234Scembus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 232289234Scem bus_size_t offset) 233289234Scem{ 234289234Scem 235289234Scem return (bus_space_read_4(tag, handle, offset) | 236289234Scem ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 237289234Scem} 238289234Scem 239289234Scemstatic __inline void 240289234Scembus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 241289234Scem bus_size_t offset, uint64_t val) 242289234Scem{ 243289234Scem 244289234Scem bus_space_write_4(tag, handle, offset, val); 245289234Scem bus_space_write_4(tag, handle, offset + 4, val >> 32); 246289234Scem} 247289234Scem#endif 248289234Scem 249255279Scarl#define ntb_bar_read(SIZE, bar, offset) \ 250255279Scarl bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 251255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset)) 252255279Scarl#define ntb_bar_write(SIZE, bar, offset, val) \ 253255279Scarl bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 254255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 255255279Scarl#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 256250079Scarl#define ntb_reg_write(SIZE, offset, val) \ 257255279Scarl ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 258289397Scem#define ntb_mw_read(SIZE, offset) \ 259289542Scem ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 260255279Scarl#define ntb_mw_write(SIZE, offset, val) \ 261289542Scem ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 262289397Scem offset, val) 263250079Scarl 264250079Scarlstatic int ntb_probe(device_t device); 265250079Scarlstatic int ntb_attach(device_t device); 266250079Scarlstatic int ntb_detach(device_t device); 267291263Scemstatic unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 268289539Scemstatic inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 269289546Scemstatic inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 270289546Scemstatic inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 271289546Scem uint32_t *base, uint32_t *xlat, uint32_t *lmt); 272255272Scarlstatic int ntb_map_pci_bars(struct ntb_softc *ntb); 273291280Scemstatic int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 274291280Scem vm_memattr_t); 275289647Scemstatic void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 276289647Scem const char *); 277255272Scarlstatic int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 278255272Scarlstatic int map_memory_window_bar(struct ntb_softc *ntb, 279255272Scarl struct ntb_pci_bar_info *bar); 280250079Scarlstatic void ntb_unmap_pci_bar(struct ntb_softc *ntb); 281289344Scemstatic int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 282289540Scemstatic int ntb_init_isr(struct ntb_softc *ntb); 283289342Scemstatic int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 284289540Scemstatic int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 285250079Scarlstatic void ntb_teardown_interrupts(struct ntb_softc *ntb); 286289540Scemstatic inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 287289546Scemstatic void ntb_interrupt(struct ntb_softc *, uint32_t vec); 288289546Scemstatic void ndev_vec_isr(void *arg); 289289546Scemstatic void ndev_irq_isr(void *arg); 290289546Scemstatic inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 291290678Scemstatic inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 292290678Scemstatic inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 293289546Scemstatic int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 294289546Scemstatic void ntb_free_msix_vec(struct ntb_softc *ntb); 295250079Scarlstatic struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 296289397Scemstatic void ntb_detect_max_mw(struct ntb_softc *ntb); 297289348Scemstatic int ntb_detect_xeon(struct ntb_softc *ntb); 298289648Scemstatic int ntb_detect_atom(struct ntb_softc *ntb); 299289542Scemstatic int ntb_xeon_init_dev(struct ntb_softc *ntb); 300289648Scemstatic int ntb_atom_init_dev(struct ntb_softc *ntb); 301289272Scemstatic void ntb_teardown_xeon(struct ntb_softc *ntb); 302289648Scemstatic void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 303289543Scemstatic void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 304289543Scem enum ntb_bar regbar); 305289543Scemstatic void xeon_set_sbar_base_and_limit(struct ntb_softc *, 306289543Scem uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 307289543Scemstatic void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 308289543Scem enum ntb_bar idx); 309289542Scemstatic int xeon_setup_b2b_mw(struct ntb_softc *, 310289542Scem const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 311289546Scemstatic inline bool link_is_up(struct ntb_softc *ntb); 312289648Scemstatic inline bool atom_link_is_err(struct ntb_softc *ntb); 313289546Scemstatic inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 314289546Scemstatic inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 315289648Scemstatic void atom_link_hb(void *arg); 316289546Scemstatic void ntb_db_event(struct ntb_softc *ntb, uint32_t vec); 317289648Scemstatic void recover_atom_link(void *arg); 318289546Scemstatic bool ntb_poll_link(struct ntb_softc *ntb); 319255274Scarlstatic void save_bar_parameters(struct ntb_pci_bar_info *bar); 320289774Scemstatic void ntb_sysctl_init(struct ntb_softc *); 321289774Scemstatic int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 322289774Scemstatic int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 323289774Scemstatic int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 324250079Scarl 325290685Scemstatic unsigned g_ntb_hw_debug_level; 326290685ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 327290685Scem &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 328290685Scem#define ntb_printf(lvl, ...) do { \ 329290685Scem if ((lvl) <= g_ntb_hw_debug_level) { \ 330290685Scem device_printf(ntb->device, __VA_ARGS__); \ 331290685Scem } \ 332290685Scem} while (0) 333290685Scem 334295486Scem#define _NTB_PAT_UC 0 335295486Scem#define _NTB_PAT_WC 1 336295486Scem#define _NTB_PAT_WT 4 337295486Scem#define _NTB_PAT_WP 5 338295486Scem#define _NTB_PAT_WB 6 339295486Scem#define _NTB_PAT_UCM 7 340295486Scemstatic unsigned g_ntb_mw_pat = _NTB_PAT_UC; 341295486ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, 342295486Scem &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " 343295486Scem "UC: " __XSTRING(_NTB_PAT_UC) ", " 344295486Scem "WC: " __XSTRING(_NTB_PAT_WC) ", " 345295486Scem "WT: " __XSTRING(_NTB_PAT_WT) ", " 346295486Scem "WP: " __XSTRING(_NTB_PAT_WP) ", " 347295486Scem "WB: " __XSTRING(_NTB_PAT_WB) ", " 348295486Scem "UC-: " __XSTRING(_NTB_PAT_UCM)); 349291030Scem 350295486Scemstatic inline vm_memattr_t 351295486Scemntb_pat_flags(void) 352295486Scem{ 353295486Scem 354295486Scem switch (g_ntb_mw_pat) { 355295486Scem case _NTB_PAT_WC: 356295486Scem return (VM_MEMATTR_WRITE_COMBINING); 357295486Scem case _NTB_PAT_WT: 358295486Scem return (VM_MEMATTR_WRITE_THROUGH); 359295486Scem case _NTB_PAT_WP: 360295486Scem return (VM_MEMATTR_WRITE_PROTECTED); 361295486Scem case _NTB_PAT_WB: 362295486Scem return (VM_MEMATTR_WRITE_BACK); 363295486Scem case _NTB_PAT_UCM: 364295486Scem return (VM_MEMATTR_WEAK_UNCACHEABLE); 365295486Scem case _NTB_PAT_UC: 366295486Scem /* FALLTHROUGH */ 367295486Scem default: 368295486Scem return (VM_MEMATTR_UNCACHEABLE); 369295486Scem } 370295486Scem} 371295486Scem 372291263Scemstatic int g_ntb_mw_idx = -1; 373291263ScemSYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 374291263Scem 0, "Use this memory window to access the peer NTB registers. A " 375291263Scem "non-negative value starts from the first MW index; a negative value " 376291263Scem "starts from the last MW index. The default is -1, i.e., the last " 377291263Scem "available memory window. Both sides of the NTB MUST set the same " 378291263Scem "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 379291263Scem 380250079Scarlstatic struct ntb_hw_info pci_ids[] = { 381289612Scem /* XXX: PS/SS IDs left out until they are supported. */ 382289612Scem { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 383289648Scem NTB_ATOM, 0 }, 384289233Scem 385289233Scem { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 386289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 387289233Scem { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 388289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 389289233Scem { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 390289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 391289538Scem NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 392289233Scem { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 393289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 394289538Scem NTB_SB01BASE_LOCKUP }, 395289233Scem { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 396289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 397289538Scem NTB_SB01BASE_LOCKUP }, 398289233Scem 399289648Scem { 0x00000000, NULL, NTB_ATOM, 0 } 400250079Scarl}; 401250079Scarl 402289648Scemstatic const struct ntb_reg atom_reg = { 403289648Scem .ntb_ctl = ATOM_NTBCNTL_OFFSET, 404289648Scem .lnk_sta = ATOM_LINK_STATUS_OFFSET, 405289542Scem .db_size = sizeof(uint64_t), 406289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 407289542Scem}; 408289542Scem 409289648Scemstatic const struct ntb_alt_reg atom_pri_reg = { 410289648Scem .db_bell = ATOM_PDOORBELL_OFFSET, 411289648Scem .db_mask = ATOM_PDBMSK_OFFSET, 412289648Scem .spad = ATOM_SPAD_OFFSET, 413289607Scem}; 414289607Scem 415289648Scemstatic const struct ntb_alt_reg atom_b2b_reg = { 416289648Scem .db_bell = ATOM_B2B_DOORBELL_OFFSET, 417289648Scem .spad = ATOM_B2B_SPAD_OFFSET, 418289542Scem}; 419289542Scem 420289648Scemstatic const struct ntb_xlat_reg atom_sec_xlat = { 421289542Scem#if 0 422289542Scem /* "FIXME" says the Linux driver. */ 423289648Scem .bar0_base = ATOM_SBAR0BASE_OFFSET, 424289648Scem .bar2_base = ATOM_SBAR2BASE_OFFSET, 425289648Scem .bar4_base = ATOM_SBAR4BASE_OFFSET, 426289546Scem 427289648Scem .bar2_limit = ATOM_SBAR2LMT_OFFSET, 428289648Scem .bar4_limit = ATOM_SBAR4LMT_OFFSET, 429289542Scem#endif 430289546Scem 431289648Scem .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 432289648Scem .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 433289542Scem}; 434289542Scem 435289542Scemstatic const struct ntb_reg xeon_reg = { 436289542Scem .ntb_ctl = XEON_NTBCNTL_OFFSET, 437289542Scem .lnk_sta = XEON_LINK_STATUS_OFFSET, 438289542Scem .db_size = sizeof(uint16_t), 439289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 440289542Scem}; 441289542Scem 442289607Scemstatic const struct ntb_alt_reg xeon_pri_reg = { 443289607Scem .db_bell = XEON_PDOORBELL_OFFSET, 444289607Scem .db_mask = XEON_PDBMSK_OFFSET, 445289607Scem .spad = XEON_SPAD_OFFSET, 446289607Scem}; 447289607Scem 448289542Scemstatic const struct ntb_alt_reg xeon_b2b_reg = { 449289542Scem .db_bell = XEON_B2B_DOORBELL_OFFSET, 450289542Scem .spad = XEON_B2B_SPAD_OFFSET, 451289542Scem}; 452289542Scem 453289542Scemstatic const struct ntb_xlat_reg xeon_sec_xlat = { 454289542Scem .bar0_base = XEON_SBAR0BASE_OFFSET, 455289546Scem .bar2_base = XEON_SBAR2BASE_OFFSET, 456289546Scem .bar4_base = XEON_SBAR4BASE_OFFSET, 457289546Scem .bar5_base = XEON_SBAR5BASE_OFFSET, 458289546Scem 459289542Scem .bar2_limit = XEON_SBAR2LMT_OFFSET, 460289546Scem .bar4_limit = XEON_SBAR4LMT_OFFSET, 461289546Scem .bar5_limit = XEON_SBAR5LMT_OFFSET, 462289546Scem 463289542Scem .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 464289546Scem .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 465289546Scem .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 466289542Scem}; 467289542Scem 468289614Scemstatic struct ntb_b2b_addr xeon_b2b_usd_addr = { 469290725Scem .bar0_addr = XEON_B2B_BAR0_ADDR, 470290725Scem .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 471290725Scem .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 472290725Scem .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 473290725Scem .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 474289542Scem}; 475289542Scem 476289614Scemstatic struct ntb_b2b_addr xeon_b2b_dsd_addr = { 477290725Scem .bar0_addr = XEON_B2B_BAR0_ADDR, 478290725Scem .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 479290725Scem .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 480290725Scem .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 481290725Scem .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 482289542Scem}; 483289542Scem 484289614ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 485289614Scem "B2B MW segment overrides -- MUST be the same on both sides"); 486289614Scem 487289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 488289614Scem &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 489289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 490289614Scem "the window at BAR2, on the upstream side of the link. MUST be the same " 491289614Scem "address on both sides."); 492289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 493289614Scem &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 494289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 495289614Scem &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 496289614Scem "(split-BAR mode)."); 497289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 498289646Scem &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 499289614Scem "(split-BAR mode)."); 500289614Scem 501289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 502289614Scem &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 503289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 504289614Scem "the window at BAR2, on the downstream side of the link. MUST be the same" 505289614Scem " address on both sides."); 506289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 507289614Scem &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 508289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 509289614Scem &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 510289614Scem "(split-BAR mode)."); 511289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 512289646Scem &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 513289614Scem "(split-BAR mode)."); 514289614Scem 515250079Scarl/* 516250079Scarl * OS <-> Driver interface structures 517250079Scarl */ 518250079ScarlMALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 519250079Scarl 520250079Scarlstatic device_method_t ntb_pci_methods[] = { 521250079Scarl /* Device interface */ 522250079Scarl DEVMETHOD(device_probe, ntb_probe), 523250079Scarl DEVMETHOD(device_attach, ntb_attach), 524250079Scarl DEVMETHOD(device_detach, ntb_detach), 525250079Scarl DEVMETHOD_END 526250079Scarl}; 527250079Scarl 528250079Scarlstatic driver_t ntb_pci_driver = { 529250079Scarl "ntb_hw", 530250079Scarl ntb_pci_methods, 531250079Scarl sizeof(struct ntb_softc), 532250079Scarl}; 533250079Scarl 534250079Scarlstatic devclass_t ntb_devclass; 535250079ScarlDRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); 536250079ScarlMODULE_VERSION(ntb_hw, 1); 537250079Scarl 538289207ScemSYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 539289207Scem 540250079Scarl/* 541250079Scarl * OS <-> Driver linkage functions 542250079Scarl */ 543250079Scarlstatic int 544250079Scarlntb_probe(device_t device) 545250079Scarl{ 546289209Scem struct ntb_hw_info *p; 547250079Scarl 548289209Scem p = ntb_get_device_info(pci_get_devid(device)); 549289209Scem if (p == NULL) 550250079Scarl return (ENXIO); 551289209Scem 552289209Scem device_set_desc(device, p->desc); 553289209Scem return (0); 554250079Scarl} 555250079Scarl 556250079Scarlstatic int 557250079Scarlntb_attach(device_t device) 558250079Scarl{ 559289209Scem struct ntb_softc *ntb; 560289209Scem struct ntb_hw_info *p; 561250079Scarl int error; 562250079Scarl 563289209Scem ntb = DEVICE2SOFTC(device); 564289209Scem p = ntb_get_device_info(pci_get_devid(device)); 565289209Scem 566250079Scarl ntb->device = device; 567250079Scarl ntb->type = p->type; 568255274Scarl ntb->features = p->features; 569289543Scem ntb->b2b_mw_idx = B2B_MW_DISABLED; 570250079Scarl 571289648Scem /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 572283291Sjkim callout_init(&ntb->heartbeat_timer, 1); 573283291Sjkim callout_init(&ntb->lr_timer, 1); 574289542Scem mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 575290683Scem mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_DEF); 576250079Scarl 577289648Scem if (ntb->type == NTB_ATOM) 578289648Scem error = ntb_detect_atom(ntb); 579289348Scem else 580289348Scem error = ntb_detect_xeon(ntb); 581290682Scem if (error != 0) 582289348Scem goto out; 583289348Scem 584289397Scem ntb_detect_max_mw(ntb); 585289396Scem 586290682Scem pci_enable_busmaster(ntb->device); 587290682Scem 588289209Scem error = ntb_map_pci_bars(ntb); 589290682Scem if (error != 0) 590289209Scem goto out; 591289648Scem if (ntb->type == NTB_ATOM) 592289648Scem error = ntb_atom_init_dev(ntb); 593289272Scem else 594289542Scem error = ntb_xeon_init_dev(ntb); 595290682Scem if (error != 0) 596289209Scem goto out; 597290682Scem 598290682Scem ntb_poll_link(ntb); 599290682Scem 600289774Scem ntb_sysctl_init(ntb); 601250079Scarl 602289209Scemout: 603289209Scem if (error != 0) 604289209Scem ntb_detach(device); 605250079Scarl return (error); 606250079Scarl} 607250079Scarl 608250079Scarlstatic int 609250079Scarlntb_detach(device_t device) 610250079Scarl{ 611289209Scem struct ntb_softc *ntb; 612250079Scarl 613289209Scem ntb = DEVICE2SOFTC(device); 614289542Scem 615289617Scem if (ntb->self_reg != NULL) 616289617Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 617250079Scarl callout_drain(&ntb->heartbeat_timer); 618250079Scarl callout_drain(&ntb->lr_timer); 619290682Scem pci_disable_busmaster(ntb->device); 620289272Scem if (ntb->type == NTB_XEON) 621289272Scem ntb_teardown_xeon(ntb); 622250079Scarl ntb_teardown_interrupts(ntb); 623289397Scem 624289542Scem mtx_destroy(&ntb->db_mask_lock); 625289546Scem mtx_destroy(&ntb->ctx_lock); 626289542Scem 627250079Scarl ntb_unmap_pci_bar(ntb); 628250079Scarl 629250079Scarl return (0); 630250079Scarl} 631250079Scarl 632289542Scem/* 633289542Scem * Driver internal routines 634289542Scem */ 635289539Scemstatic inline enum ntb_bar 636289539Scemntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 637289539Scem{ 638289539Scem 639291263Scem KASSERT(mw < ntb->mw_count, 640289542Scem ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 641289546Scem KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 642289539Scem 643289542Scem return (ntb->reg->mw_bar[mw]); 644289539Scem} 645289539Scem 646289546Scemstatic inline bool 647289546Scembar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 648289546Scem{ 649289546Scem /* XXX This assertion could be stronger. */ 650289546Scem KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 651289546Scem return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR)); 652289546Scem} 653289546Scem 654289546Scemstatic inline void 655289546Scembar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 656289546Scem uint32_t *xlat, uint32_t *lmt) 657289546Scem{ 658289546Scem uint32_t basev, lmtv, xlatv; 659289546Scem 660289546Scem switch (bar) { 661289546Scem case NTB_B2B_BAR_1: 662289546Scem basev = ntb->xlat_reg->bar2_base; 663289546Scem lmtv = ntb->xlat_reg->bar2_limit; 664289546Scem xlatv = ntb->xlat_reg->bar2_xlat; 665289546Scem break; 666289546Scem case NTB_B2B_BAR_2: 667289546Scem basev = ntb->xlat_reg->bar4_base; 668289546Scem lmtv = ntb->xlat_reg->bar4_limit; 669289546Scem xlatv = ntb->xlat_reg->bar4_xlat; 670289546Scem break; 671289546Scem case NTB_B2B_BAR_3: 672289546Scem basev = ntb->xlat_reg->bar5_base; 673289546Scem lmtv = ntb->xlat_reg->bar5_limit; 674289546Scem xlatv = ntb->xlat_reg->bar5_xlat; 675289546Scem break; 676289546Scem default: 677289546Scem KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 678289546Scem ("bad bar")); 679289546Scem basev = lmtv = xlatv = 0; 680289546Scem break; 681289546Scem } 682289546Scem 683289546Scem if (base != NULL) 684289546Scem *base = basev; 685289546Scem if (xlat != NULL) 686289546Scem *xlat = xlatv; 687289546Scem if (lmt != NULL) 688289546Scem *lmt = lmtv; 689289546Scem} 690289546Scem 691250079Scarlstatic int 692255272Scarlntb_map_pci_bars(struct ntb_softc *ntb) 693250079Scarl{ 694255272Scarl int rc; 695250079Scarl 696250079Scarl ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 697289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 698255272Scarl if (rc != 0) 699289541Scem goto out; 700255272Scarl 701289209Scem ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 702289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 703255272Scarl if (rc != 0) 704289541Scem goto out; 705289543Scem ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 706289543Scem ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 707289543Scem ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 708255272Scarl 709289209Scem ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 710291263Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 711291263Scem if (rc != 0) 712291263Scem goto out; 713289543Scem ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 714289543Scem ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 715289543Scem ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 716289543Scem 717289397Scem if (!HAS_FEATURE(NTB_SPLIT_BAR)) 718289541Scem goto out; 719289397Scem 720289397Scem ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 721291263Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 722289543Scem ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 723289543Scem ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 724289543Scem ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 725250079Scarl 726289541Scemout: 727289209Scem if (rc != 0) 728255272Scarl device_printf(ntb->device, 729255272Scarl "unable to allocate pci resource\n"); 730255272Scarl return (rc); 731255272Scarl} 732255272Scarl 733289541Scemstatic void 734289647Scemprint_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 735289647Scem const char *kind) 736289541Scem{ 737289541Scem 738289647Scem device_printf(ntb->device, 739289647Scem "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 740289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 741289647Scem (char *)bar->vbase + bar->size - 1, 742289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 743289647Scem (uintmax_t)bar->size, kind); 744289541Scem} 745289541Scem 746255272Scarlstatic int 747255272Scarlmap_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 748255272Scarl{ 749255272Scarl 750255275Scarl bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 751289209Scem &bar->pci_resource_id, RF_ACTIVE); 752255272Scarl if (bar->pci_resource == NULL) 753255272Scarl return (ENXIO); 754289209Scem 755289209Scem save_bar_parameters(bar); 756291280Scem bar->map_mode = VM_MEMATTR_UNCACHEABLE; 757289647Scem print_map_success(ntb, bar, "mmr"); 758289209Scem return (0); 759255272Scarl} 760255272Scarl 761255272Scarlstatic int 762255272Scarlmap_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 763255272Scarl{ 764255272Scarl int rc; 765291280Scem vm_memattr_t mapmode; 766255276Scarl uint8_t bar_size_bits = 0; 767255272Scarl 768289209Scem bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 769289209Scem &bar->pci_resource_id, RF_ACTIVE); 770250079Scarl 771255272Scarl if (bar->pci_resource == NULL) 772255272Scarl return (ENXIO); 773255276Scarl 774289209Scem save_bar_parameters(bar); 775289209Scem /* 776289209Scem * Ivytown NTB BAR sizes are misreported by the hardware due to a 777289209Scem * hardware issue. To work around this, query the size it should be 778289209Scem * configured to by the device and modify the resource to correspond to 779289209Scem * this new size. The BIOS on systems with this problem is required to 780289209Scem * provide enough address space to allow the driver to make this change 781289209Scem * safely. 782289209Scem * 783289209Scem * Ideally I could have just specified the size when I allocated the 784289209Scem * resource like: 785289209Scem * bus_alloc_resource(ntb->device, 786289209Scem * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 787289209Scem * 1ul << bar_size_bits, RF_ACTIVE); 788289209Scem * but the PCI driver does not honor the size in this call, so we have 789289209Scem * to modify it after the fact. 790289209Scem */ 791289209Scem if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { 792289209Scem if (bar->pci_resource_id == PCIR_BAR(2)) 793289209Scem bar_size_bits = pci_read_config(ntb->device, 794289209Scem XEON_PBAR23SZ_OFFSET, 1); 795289209Scem else 796289209Scem bar_size_bits = pci_read_config(ntb->device, 797289209Scem XEON_PBAR45SZ_OFFSET, 1); 798289209Scem 799289209Scem rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 800289209Scem bar->pci_resource, bar->pbase, 801289209Scem bar->pbase + (1ul << bar_size_bits) - 1); 802255272Scarl if (rc != 0) { 803289209Scem device_printf(ntb->device, 804289209Scem "unable to resize bar\n"); 805255272Scarl return (rc); 806250079Scarl } 807289209Scem 808289209Scem save_bar_parameters(bar); 809250079Scarl } 810289209Scem 811291280Scem bar->map_mode = VM_MEMATTR_UNCACHEABLE; 812291030Scem print_map_success(ntb, bar, "mw"); 813291280Scem 814295486Scem /* 815295486Scem * Optionally, mark MW BARs as anything other than UC to improve 816295486Scem * performance. 817295486Scem */ 818295486Scem mapmode = ntb_pat_flags(); 819295486Scem if (mapmode == bar->map_mode) 820295486Scem return (0); 821291030Scem 822291280Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 823291031Scem if (rc == 0) { 824291280Scem bar->map_mode = mapmode; 825289209Scem device_printf(ntb->device, 826289647Scem "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 827291280Scem "%s.\n", 828289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 829289647Scem (char *)bar->vbase + bar->size - 1, 830291280Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 831291280Scem (mapmode == VM_MEMATTR_WRITE_COMBINING) ? "WRITE_COMBINING" 832291280Scem : "WRITE_BACK"); 833291031Scem } else 834289647Scem device_printf(ntb->device, 835289647Scem "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 836291280Scem "%s: %d\n", 837289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 838289647Scem (char *)bar->vbase + bar->size - 1, 839289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 840291280Scem (mapmode == VM_MEMATTR_WRITE_COMBINING) ? "WRITE_COMBINING" 841291280Scem : "WRITE_BACK", rc); 842289647Scem /* Proceed anyway */ 843250079Scarl return (0); 844250079Scarl} 845250079Scarl 846250079Scarlstatic void 847250079Scarlntb_unmap_pci_bar(struct ntb_softc *ntb) 848250079Scarl{ 849250079Scarl struct ntb_pci_bar_info *current_bar; 850250079Scarl int i; 851250079Scarl 852289397Scem for (i = 0; i < NTB_MAX_BARS; i++) { 853250079Scarl current_bar = &ntb->bar_info[i]; 854250079Scarl if (current_bar->pci_resource != NULL) 855250079Scarl bus_release_resource(ntb->device, SYS_RES_MEMORY, 856250079Scarl current_bar->pci_resource_id, 857250079Scarl current_bar->pci_resource); 858250079Scarl } 859250079Scarl} 860250079Scarl 861250079Scarlstatic int 862289540Scemntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 863250079Scarl{ 864289342Scem uint32_t i; 865289342Scem int rc; 866289342Scem 867289342Scem for (i = 0; i < num_vectors; i++) { 868289342Scem ntb->int_info[i].rid = i + 1; 869289342Scem ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 870289342Scem SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 871289342Scem if (ntb->int_info[i].res == NULL) { 872289342Scem device_printf(ntb->device, 873289342Scem "bus_alloc_resource failed\n"); 874289342Scem return (ENOMEM); 875289342Scem } 876289342Scem ntb->int_info[i].tag = NULL; 877289342Scem ntb->allocated_interrupts++; 878289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 879289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 880289546Scem &ntb->msix_vec[i], &ntb->int_info[i].tag); 881289342Scem if (rc != 0) { 882289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 883289342Scem return (ENXIO); 884289342Scem } 885289342Scem } 886289342Scem return (0); 887289342Scem} 888289342Scem 889289344Scem/* 890289344Scem * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 891289344Scem * cannot be allocated for each MSI-X message. JHB seems to think remapping 892289344Scem * should be okay. This tunable should enable us to test that hypothesis 893289344Scem * when someone gets their hands on some Xeon hardware. 894289344Scem */ 895289344Scemstatic int ntb_force_remap_mode; 896289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 897289344Scem &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 898289344Scem " to a smaller number of ithreads, even if the desired number are " 899289344Scem "available"); 900289344Scem 901289344Scem/* 902289344Scem * In case it is NOT ok, give consumers an abort button. 903289344Scem */ 904289344Scemstatic int ntb_prefer_intx; 905289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 906289344Scem &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 907289344Scem "than remapping MSI-X messages over available slots (match Linux driver " 908289344Scem "behavior)"); 909289344Scem 910289344Scem/* 911289344Scem * Remap the desired number of MSI-X messages to available ithreads in a simple 912289344Scem * round-robin fashion. 913289344Scem */ 914289342Scemstatic int 915289344Scemntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 916289344Scem{ 917289344Scem u_int *vectors; 918289344Scem uint32_t i; 919289344Scem int rc; 920289344Scem 921289344Scem if (ntb_prefer_intx != 0) 922289344Scem return (ENXIO); 923289344Scem 924289344Scem vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 925289344Scem 926289344Scem for (i = 0; i < desired; i++) 927289344Scem vectors[i] = (i % avail) + 1; 928289344Scem 929289344Scem rc = pci_remap_msix(dev, desired, vectors); 930289344Scem free(vectors, M_NTB); 931289344Scem return (rc); 932289344Scem} 933289344Scem 934289344Scemstatic int 935289540Scemntb_init_isr(struct ntb_softc *ntb) 936289342Scem{ 937289344Scem uint32_t desired_vectors, num_vectors; 938289342Scem int rc; 939250079Scarl 940250079Scarl ntb->allocated_interrupts = 0; 941289542Scem ntb->last_ts = ticks; 942289347Scem 943250079Scarl /* 944289546Scem * Mask all doorbell interrupts. 945250079Scarl */ 946289546Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 947250079Scarl 948289344Scem num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 949289539Scem ntb->db_count); 950289344Scem if (desired_vectors >= 1) { 951289344Scem rc = pci_alloc_msix(ntb->device, &num_vectors); 952250079Scarl 953289344Scem if (ntb_force_remap_mode != 0 && rc == 0 && 954289344Scem num_vectors == desired_vectors) 955289344Scem num_vectors--; 956289344Scem 957289344Scem if (rc == 0 && num_vectors < desired_vectors) { 958289344Scem rc = ntb_remap_msix(ntb->device, desired_vectors, 959289344Scem num_vectors); 960289344Scem if (rc == 0) 961289344Scem num_vectors = desired_vectors; 962289344Scem else 963289344Scem pci_release_msi(ntb->device); 964289344Scem } 965289344Scem if (rc != 0) 966289344Scem num_vectors = 1; 967289344Scem } else 968289344Scem num_vectors = 1; 969289344Scem 970289539Scem if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 971289539Scem ntb->db_vec_count = 1; 972290680Scem ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 973289539Scem rc = ntb_setup_legacy_interrupt(ntb); 974289539Scem } else { 975289546Scem ntb_create_msix_vec(ntb, num_vectors); 976289540Scem rc = ntb_setup_msix(ntb, num_vectors); 977289539Scem } 978289539Scem if (rc != 0) { 979289539Scem device_printf(ntb->device, 980289539Scem "Error allocating interrupts: %d\n", rc); 981289546Scem ntb_free_msix_vec(ntb); 982289396Scem } 983289396Scem 984289342Scem return (rc); 985289342Scem} 986289342Scem 987289342Scemstatic int 988289342Scemntb_setup_legacy_interrupt(struct ntb_softc *ntb) 989289342Scem{ 990289342Scem int rc; 991289342Scem 992289342Scem ntb->int_info[0].rid = 0; 993289342Scem ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 994289342Scem &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 995289342Scem if (ntb->int_info[0].res == NULL) { 996289342Scem device_printf(ntb->device, "bus_alloc_resource failed\n"); 997289342Scem return (ENOMEM); 998250079Scarl } 999250079Scarl 1000289342Scem ntb->int_info[0].tag = NULL; 1001289342Scem ntb->allocated_interrupts = 1; 1002289342Scem 1003289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 1004289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 1005289342Scem ntb, &ntb->int_info[0].tag); 1006289342Scem if (rc != 0) { 1007289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 1008289342Scem return (ENXIO); 1009289342Scem } 1010289342Scem 1011250079Scarl return (0); 1012250079Scarl} 1013250079Scarl 1014250079Scarlstatic void 1015250079Scarlntb_teardown_interrupts(struct ntb_softc *ntb) 1016250079Scarl{ 1017250079Scarl struct ntb_int_info *current_int; 1018250079Scarl int i; 1019250079Scarl 1020289209Scem for (i = 0; i < ntb->allocated_interrupts; i++) { 1021250079Scarl current_int = &ntb->int_info[i]; 1022250079Scarl if (current_int->tag != NULL) 1023250079Scarl bus_teardown_intr(ntb->device, current_int->res, 1024250079Scarl current_int->tag); 1025250079Scarl 1026250079Scarl if (current_int->res != NULL) 1027250079Scarl bus_release_resource(ntb->device, SYS_RES_IRQ, 1028250079Scarl rman_get_rid(current_int->res), current_int->res); 1029250079Scarl } 1030250079Scarl 1031289546Scem ntb_free_msix_vec(ntb); 1032250079Scarl pci_release_msi(ntb->device); 1033250079Scarl} 1034250079Scarl 1035289347Scem/* 1036289648Scem * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 1037289347Scem * out to make code clearer. 1038289347Scem */ 1039289539Scemstatic inline uint64_t 1040289546Scemdb_ioread(struct ntb_softc *ntb, uint64_t regoff) 1041289347Scem{ 1042289347Scem 1043289648Scem if (ntb->type == NTB_ATOM) 1044289347Scem return (ntb_reg_read(8, regoff)); 1045289347Scem 1046289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1047289347Scem 1048289347Scem return (ntb_reg_read(2, regoff)); 1049289347Scem} 1050289347Scem 1051289539Scemstatic inline void 1052289546Scemdb_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1053289347Scem{ 1054289347Scem 1055289542Scem KASSERT((val & ~ntb->db_valid_mask) == 0, 1056289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1057289542Scem (uintmax_t)(val & ~ntb->db_valid_mask), 1058289542Scem (uintmax_t)ntb->db_valid_mask)); 1059289542Scem 1060289607Scem if (regoff == ntb->self_reg->db_mask) 1061289546Scem DB_MASK_ASSERT(ntb, MA_OWNED); 1062290678Scem db_iowrite_raw(ntb, regoff, val); 1063290678Scem} 1064289542Scem 1065290678Scemstatic inline void 1066290678Scemdb_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1067290678Scem{ 1068290678Scem 1069289648Scem if (ntb->type == NTB_ATOM) { 1070289347Scem ntb_reg_write(8, regoff, val); 1071289347Scem return; 1072289347Scem } 1073289347Scem 1074289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1075289347Scem ntb_reg_write(2, regoff, (uint16_t)val); 1076289347Scem} 1077289347Scem 1078289546Scemvoid 1079289542Scemntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits) 1080289542Scem{ 1081289542Scem 1082289546Scem DB_MASK_LOCK(ntb); 1083289542Scem ntb->db_mask |= bits; 1084289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1085289546Scem DB_MASK_UNLOCK(ntb); 1086289542Scem} 1087289542Scem 1088289546Scemvoid 1089289542Scemntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits) 1090289542Scem{ 1091289542Scem 1092289542Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1093289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1094289542Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1095289542Scem (uintmax_t)ntb->db_valid_mask)); 1096289542Scem 1097289546Scem DB_MASK_LOCK(ntb); 1098289542Scem ntb->db_mask &= ~bits; 1099289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1100289546Scem DB_MASK_UNLOCK(ntb); 1101289542Scem} 1102289542Scem 1103289546Scemuint64_t 1104289546Scemntb_db_read(struct ntb_softc *ntb) 1105289281Scem{ 1106289281Scem 1107289607Scem return (db_ioread(ntb, ntb->self_reg->db_bell)); 1108289281Scem} 1109289281Scem 1110289546Scemvoid 1111289546Scemntb_db_clear(struct ntb_softc *ntb, uint64_t bits) 1112289281Scem{ 1113289281Scem 1114289546Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1115289546Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1116289546Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1117289546Scem (uintmax_t)ntb->db_valid_mask)); 1118289546Scem 1119289607Scem db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1120289281Scem} 1121289281Scem 1122289540Scemstatic inline uint64_t 1123289540Scemntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1124250079Scarl{ 1125289540Scem uint64_t shift, mask; 1126250079Scarl 1127289540Scem shift = ntb->db_vec_shift; 1128289540Scem mask = (1ull << shift) - 1; 1129289540Scem return (mask << (shift * db_vector)); 1130250079Scarl} 1131250079Scarl 1132250079Scarlstatic void 1133289546Scemntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1134250079Scarl{ 1135289540Scem uint64_t vec_mask; 1136250079Scarl 1137289542Scem ntb->last_ts = ticks; 1138289546Scem vec_mask = ntb_vec_mask(ntb, vec); 1139250079Scarl 1140289542Scem if ((vec_mask & ntb->db_link_mask) != 0) { 1141289546Scem if (ntb_poll_link(ntb)) 1142289546Scem ntb_link_event(ntb); 1143289540Scem } 1144289540Scem 1145289546Scem if ((vec_mask & ntb->db_valid_mask) != 0) 1146289546Scem ntb_db_event(ntb, vec); 1147289546Scem} 1148250079Scarl 1149289546Scemstatic void 1150289546Scemndev_vec_isr(void *arg) 1151289546Scem{ 1152289546Scem struct ntb_vec *nvec = arg; 1153250079Scarl 1154289546Scem ntb_interrupt(nvec->ntb, nvec->num); 1155250079Scarl} 1156250079Scarl 1157250079Scarlstatic void 1158289546Scemndev_irq_isr(void *arg) 1159250079Scarl{ 1160289546Scem /* If we couldn't set up MSI-X, we only have the one vector. */ 1161289546Scem ntb_interrupt(arg, 0); 1162250079Scarl} 1163250079Scarl 1164250079Scarlstatic int 1165289546Scemntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1166250079Scarl{ 1167289342Scem uint32_t i; 1168250079Scarl 1169289546Scem ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1170250079Scarl M_ZERO | M_WAITOK); 1171250079Scarl for (i = 0; i < num_vectors; i++) { 1172289546Scem ntb->msix_vec[i].num = i; 1173289546Scem ntb->msix_vec[i].ntb = ntb; 1174250079Scarl } 1175250079Scarl 1176250079Scarl return (0); 1177250079Scarl} 1178250079Scarl 1179250079Scarlstatic void 1180289546Scemntb_free_msix_vec(struct ntb_softc *ntb) 1181250079Scarl{ 1182250079Scarl 1183289546Scem if (ntb->msix_vec == NULL) 1184289539Scem return; 1185289539Scem 1186289546Scem free(ntb->msix_vec, M_NTB); 1187289546Scem ntb->msix_vec = NULL; 1188250079Scarl} 1189250079Scarl 1190250079Scarlstatic struct ntb_hw_info * 1191250079Scarlntb_get_device_info(uint32_t device_id) 1192250079Scarl{ 1193250079Scarl struct ntb_hw_info *ep = pci_ids; 1194250079Scarl 1195250079Scarl while (ep->device_id) { 1196250079Scarl if (ep->device_id == device_id) 1197250079Scarl return (ep); 1198250079Scarl ++ep; 1199250079Scarl } 1200250079Scarl return (NULL); 1201250079Scarl} 1202250079Scarl 1203289272Scemstatic void 1204289272Scemntb_teardown_xeon(struct ntb_softc *ntb) 1205250079Scarl{ 1206250079Scarl 1207289617Scem if (ntb->reg != NULL) 1208289617Scem ntb_link_disable(ntb); 1209250079Scarl} 1210250079Scarl 1211289397Scemstatic void 1212289397Scemntb_detect_max_mw(struct ntb_softc *ntb) 1213289397Scem{ 1214289397Scem 1215289648Scem if (ntb->type == NTB_ATOM) { 1216289648Scem ntb->mw_count = ATOM_MW_COUNT; 1217289397Scem return; 1218289397Scem } 1219289397Scem 1220289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1221289539Scem ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1222289397Scem else 1223289539Scem ntb->mw_count = XEON_SNB_MW_COUNT; 1224289397Scem} 1225289397Scem 1226250079Scarlstatic int 1227289348Scemntb_detect_xeon(struct ntb_softc *ntb) 1228250079Scarl{ 1229289348Scem uint8_t ppd, conn_type; 1230250079Scarl 1231289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1232289348Scem ntb->ppd = ppd; 1233250079Scarl 1234289348Scem if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1235290681Scem ntb->dev_type = NTB_DEV_DSD; 1236290681Scem else 1237289257Scem ntb->dev_type = NTB_DEV_USD; 1238289257Scem 1239289397Scem if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1240289397Scem ntb->features |= NTB_SPLIT_BAR; 1241289397Scem 1242289542Scem /* SB01BASE_LOCKUP errata is a superset of SDOORBELL errata */ 1243289542Scem if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) 1244289542Scem ntb->features |= NTB_SDOORBELL_LOCKUP; 1245289542Scem 1246289348Scem conn_type = ppd & XEON_PPD_CONN_TYPE; 1247289348Scem switch (conn_type) { 1248289348Scem case NTB_CONN_B2B: 1249289348Scem ntb->conn_type = conn_type; 1250289348Scem break; 1251289348Scem case NTB_CONN_RP: 1252289348Scem case NTB_CONN_TRANSPARENT: 1253289348Scem default: 1254289348Scem device_printf(ntb->device, "Unsupported connection type: %u\n", 1255289348Scem (unsigned)conn_type); 1256289348Scem return (ENXIO); 1257289348Scem } 1258289348Scem return (0); 1259289348Scem} 1260289348Scem 1261289348Scemstatic int 1262289648Scemntb_detect_atom(struct ntb_softc *ntb) 1263289348Scem{ 1264289348Scem uint32_t ppd, conn_type; 1265289348Scem 1266289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1267289348Scem ntb->ppd = ppd; 1268289348Scem 1269289648Scem if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1270289348Scem ntb->dev_type = NTB_DEV_DSD; 1271289348Scem else 1272289348Scem ntb->dev_type = NTB_DEV_USD; 1273289348Scem 1274289648Scem conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1275289348Scem switch (conn_type) { 1276289348Scem case NTB_CONN_B2B: 1277289348Scem ntb->conn_type = conn_type; 1278289348Scem break; 1279289348Scem default: 1280289348Scem device_printf(ntb->device, "Unsupported NTB configuration\n"); 1281289348Scem return (ENXIO); 1282289348Scem } 1283289348Scem return (0); 1284289348Scem} 1285289348Scem 1286289348Scemstatic int 1287289542Scemntb_xeon_init_dev(struct ntb_softc *ntb) 1288289348Scem{ 1289289542Scem int rc; 1290289348Scem 1291289542Scem ntb->spad_count = XEON_SPAD_COUNT; 1292289542Scem ntb->db_count = XEON_DB_COUNT; 1293289542Scem ntb->db_link_mask = XEON_DB_LINK_BIT; 1294289542Scem ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1295289542Scem ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1296289257Scem 1297289542Scem if (ntb->conn_type != NTB_CONN_B2B) { 1298250079Scarl device_printf(ntb->device, "Connection type %d not supported\n", 1299289348Scem ntb->conn_type); 1300250079Scarl return (ENXIO); 1301250079Scarl } 1302250079Scarl 1303289542Scem ntb->reg = &xeon_reg; 1304289607Scem ntb->self_reg = &xeon_pri_reg; 1305289542Scem ntb->peer_reg = &xeon_b2b_reg; 1306289542Scem ntb->xlat_reg = &xeon_sec_xlat; 1307289542Scem 1308289208Scem /* 1309289208Scem * There is a Xeon hardware errata related to writes to SDOORBELL or 1310289208Scem * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1311291263Scem * which may hang the system. To workaround this, use a memory 1312289208Scem * window to access the interrupt and scratch pad registers on the 1313289208Scem * remote system. 1314289208Scem */ 1315291263Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 1316291263Scem ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1317291263Scem ntb->mw_count; 1318291263Scem ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1319291263Scem g_ntb_mw_idx, ntb->b2b_mw_idx); 1320291280Scem rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, VM_MEMATTR_UNCACHEABLE); 1321291263Scem KASSERT(rc == 0, ("shouldn't fail")); 1322291263Scem } else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14)) 1323289208Scem /* 1324289542Scem * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1325289542Scem * mirrored to the remote system. Shrink the number of bits by one, 1326289542Scem * since bit 14 is the last bit. 1327289542Scem * 1328289542Scem * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1329289542Scem * anyway. Nor for non-B2B connection types. 1330289542Scem */ 1331289543Scem ntb->db_count = XEON_DB_COUNT - 1; 1332250079Scarl 1333289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1334250079Scarl 1335289542Scem if (ntb->dev_type == NTB_DEV_USD) 1336289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1337289542Scem &xeon_b2b_usd_addr); 1338289542Scem else 1339289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1340289542Scem &xeon_b2b_dsd_addr); 1341289542Scem if (rc != 0) 1342289542Scem return (rc); 1343289271Scem 1344250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1345290682Scem ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1346289542Scem PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1347255279Scarl 1348290682Scem /* 1349290682Scem * Mask all doorbell interrupts. 1350290682Scem */ 1351290682Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 1352250079Scarl 1353290682Scem rc = ntb_init_isr(ntb); 1354290682Scem return (rc); 1355250079Scarl} 1356250079Scarl 1357250079Scarlstatic int 1358289648Scemntb_atom_init_dev(struct ntb_softc *ntb) 1359250079Scarl{ 1360290682Scem int error; 1361250079Scarl 1362289348Scem KASSERT(ntb->conn_type == NTB_CONN_B2B, 1363289348Scem ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1364250079Scarl 1365289648Scem ntb->spad_count = ATOM_SPAD_COUNT; 1366289648Scem ntb->db_count = ATOM_DB_COUNT; 1367289648Scem ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1368289648Scem ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1369289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1370250079Scarl 1371289648Scem ntb->reg = &atom_reg; 1372289648Scem ntb->self_reg = &atom_pri_reg; 1373289648Scem ntb->peer_reg = &atom_b2b_reg; 1374289648Scem ntb->xlat_reg = &atom_sec_xlat; 1375289542Scem 1376250079Scarl /* 1377289648Scem * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1378250079Scarl * resolved. Mask transaction layer internal parity errors. 1379250079Scarl */ 1380250079Scarl pci_write_config(ntb->device, 0xFC, 0x4, 4); 1381250079Scarl 1382289648Scem configure_atom_secondary_side_bars(ntb); 1383250079Scarl 1384250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1385290682Scem ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1386250079Scarl PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1387289209Scem 1388290682Scem error = ntb_init_isr(ntb); 1389290682Scem if (error != 0) 1390290682Scem return (error); 1391290682Scem 1392289542Scem /* Initiate PCI-E link training */ 1393289546Scem ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1394250079Scarl 1395289648Scem callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1396289542Scem 1397250079Scarl return (0); 1398250079Scarl} 1399250079Scarl 1400289648Scem/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1401255279Scarlstatic void 1402289648Scemconfigure_atom_secondary_side_bars(struct ntb_softc *ntb) 1403255279Scarl{ 1404255279Scarl 1405255279Scarl if (ntb->dev_type == NTB_DEV_USD) { 1406289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1407290725Scem XEON_B2B_BAR2_ADDR64); 1408289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1409290725Scem XEON_B2B_BAR4_ADDR64); 1410290725Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1411290725Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1412255279Scarl } else { 1413289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1414290725Scem XEON_B2B_BAR2_ADDR64); 1415289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1416290725Scem XEON_B2B_BAR4_ADDR64); 1417290725Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1418290725Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1419255279Scarl } 1420255279Scarl} 1421255279Scarl 1422289543Scem 1423289543Scem/* 1424289543Scem * When working around Xeon SDOORBELL errata by remapping remote registers in a 1425289543Scem * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1426289543Scem * remains for use by a higher layer. 1427289543Scem * 1428289543Scem * Will only be used if working around SDOORBELL errata and the BIOS-configured 1429289543Scem * MW size is sufficiently large. 1430289543Scem */ 1431289543Scemstatic unsigned int ntb_b2b_mw_share; 1432289543ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1433289543Scem 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1434289543Scem "MW with higher level consumers. Both sides of the NTB MUST set the same " 1435289543Scem "value here."); 1436289543Scem 1437289543Scemstatic void 1438289543Scemxeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1439289543Scem enum ntb_bar regbar) 1440289543Scem{ 1441289543Scem struct ntb_pci_bar_info *bar; 1442289543Scem uint8_t bar_sz; 1443289543Scem 1444289543Scem if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1445289543Scem return; 1446289543Scem 1447289543Scem bar = &ntb->bar_info[idx]; 1448289543Scem bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1449289543Scem if (idx == regbar) { 1450289543Scem if (ntb->b2b_off != 0) 1451289543Scem bar_sz--; 1452289543Scem else 1453289543Scem bar_sz = 0; 1454289543Scem } 1455289543Scem pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1456289543Scem bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1457289543Scem (void)bar_sz; 1458289543Scem} 1459289543Scem 1460289543Scemstatic void 1461289546Scemxeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1462289543Scem enum ntb_bar idx, enum ntb_bar regbar) 1463289543Scem{ 1464289546Scem uint64_t reg_val; 1465289546Scem uint32_t base_reg, lmt_reg; 1466289543Scem 1467289546Scem bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1468289546Scem if (idx == regbar) 1469289546Scem bar_addr += ntb->b2b_off; 1470289543Scem 1471289546Scem if (!bar_is_64bit(ntb, idx)) { 1472289546Scem ntb_reg_write(4, base_reg, bar_addr); 1473289546Scem reg_val = ntb_reg_read(4, base_reg); 1474289546Scem (void)reg_val; 1475289546Scem 1476289546Scem ntb_reg_write(4, lmt_reg, bar_addr); 1477289546Scem reg_val = ntb_reg_read(4, lmt_reg); 1478289546Scem (void)reg_val; 1479289543Scem } else { 1480289546Scem ntb_reg_write(8, base_reg, bar_addr); 1481289546Scem reg_val = ntb_reg_read(8, base_reg); 1482289546Scem (void)reg_val; 1483289546Scem 1484289546Scem ntb_reg_write(8, lmt_reg, bar_addr); 1485289546Scem reg_val = ntb_reg_read(8, lmt_reg); 1486289546Scem (void)reg_val; 1487289543Scem } 1488289543Scem} 1489289543Scem 1490289543Scemstatic void 1491289543Scemxeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1492289543Scem{ 1493289543Scem struct ntb_pci_bar_info *bar; 1494289543Scem 1495289543Scem bar = &ntb->bar_info[idx]; 1496289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1497289543Scem ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1498289543Scem base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1499289543Scem } else { 1500289543Scem ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1501289543Scem base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1502289543Scem } 1503289543Scem (void)base_addr; 1504289543Scem} 1505289543Scem 1506289542Scemstatic int 1507289542Scemxeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1508289542Scem const struct ntb_b2b_addr *peer_addr) 1509255279Scarl{ 1510289543Scem struct ntb_pci_bar_info *b2b_bar; 1511289543Scem vm_size_t bar_size; 1512289543Scem uint64_t bar_addr; 1513289543Scem enum ntb_bar b2b_bar_num, i; 1514255279Scarl 1515289543Scem if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1516289543Scem b2b_bar = NULL; 1517289543Scem b2b_bar_num = NTB_CONFIG_BAR; 1518289543Scem ntb->b2b_off = 0; 1519289543Scem } else { 1520289543Scem b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1521289543Scem KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1522289543Scem ("invalid b2b mw bar")); 1523289543Scem 1524289543Scem b2b_bar = &ntb->bar_info[b2b_bar_num]; 1525289543Scem bar_size = b2b_bar->size; 1526289543Scem 1527289543Scem if (ntb_b2b_mw_share != 0 && 1528289543Scem (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1529289543Scem ntb->b2b_off = bar_size >> 1; 1530289543Scem else if (bar_size >= XEON_B2B_MIN_SIZE) { 1531289543Scem ntb->b2b_off = 0; 1532289543Scem } else { 1533289543Scem device_printf(ntb->device, 1534289543Scem "B2B bar size is too small!\n"); 1535289543Scem return (EIO); 1536289543Scem } 1537255279Scarl } 1538289542Scem 1539289543Scem /* 1540289543Scem * Reset the secondary bar sizes to match the primary bar sizes. 1541289543Scem * (Except, disable or halve the size of the B2B secondary bar.) 1542289543Scem */ 1543289543Scem for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1544289543Scem xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1545289543Scem 1546289543Scem bar_addr = 0; 1547289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1548289543Scem bar_addr = addr->bar0_addr; 1549289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1550289543Scem bar_addr = addr->bar2_addr64; 1551289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1552289543Scem bar_addr = addr->bar4_addr64; 1553289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1554289543Scem bar_addr = addr->bar4_addr32; 1555289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1556289543Scem bar_addr = addr->bar5_addr32; 1557289543Scem else 1558289543Scem KASSERT(false, ("invalid bar")); 1559289543Scem 1560289543Scem ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1561289543Scem 1562289543Scem /* 1563289543Scem * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1564289543Scem * register BAR. The B2B BAR is either disabled above or configured 1565289543Scem * half-size. It starts at PBAR xlat + offset. 1566289543Scem * 1567289543Scem * Also set up incoming BAR limits == base (zero length window). 1568289543Scem */ 1569289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1570289543Scem b2b_bar_num); 1571289542Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1572289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1573289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1574289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1575289543Scem NTB_B2B_BAR_3, b2b_bar_num); 1576289542Scem } else 1577289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1578289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1579289543Scem 1580289543Scem /* Zero incoming translation addrs */ 1581289543Scem ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1582289543Scem ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1583289543Scem 1584289543Scem /* Zero outgoing translation limits (whole bar size windows) */ 1585289543Scem ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1586289543Scem ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1587289543Scem 1588289543Scem /* Set outgoing translation offsets */ 1589289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1590289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1591289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1592289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1593289543Scem } else 1594289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1595289543Scem 1596289543Scem /* Set the translation offset for B2B registers */ 1597289543Scem bar_addr = 0; 1598289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1599289543Scem bar_addr = peer_addr->bar0_addr; 1600289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1601289543Scem bar_addr = peer_addr->bar2_addr64; 1602289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1603289543Scem bar_addr = peer_addr->bar4_addr64; 1604289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1605289543Scem bar_addr = peer_addr->bar4_addr32; 1606289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1607289543Scem bar_addr = peer_addr->bar5_addr32; 1608289543Scem else 1609289543Scem KASSERT(false, ("invalid bar")); 1610289543Scem 1611289543Scem /* 1612289543Scem * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1613289543Scem * at a time. 1614289543Scem */ 1615289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1616289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1617289542Scem return (0); 1618255279Scarl} 1619255279Scarl 1620289546Scemstatic inline bool 1621289546Scemlink_is_up(struct ntb_softc *ntb) 1622289546Scem{ 1623289546Scem 1624289611Scem if (ntb->type == NTB_XEON) { 1625289611Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1626289611Scem return (true); 1627289546Scem return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1628289611Scem } 1629289546Scem 1630289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1631289648Scem return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1632289546Scem} 1633289546Scem 1634289546Scemstatic inline bool 1635289648Scematom_link_is_err(struct ntb_softc *ntb) 1636289546Scem{ 1637289546Scem uint32_t status; 1638289546Scem 1639289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1640289546Scem 1641289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1642289648Scem if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1643289546Scem return (true); 1644289546Scem 1645289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1646289648Scem return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1647289546Scem} 1648289546Scem 1649289648Scem/* Atom does not have link status interrupt, poll on that platform */ 1650250079Scarlstatic void 1651289648Scematom_link_hb(void *arg) 1652250079Scarl{ 1653250079Scarl struct ntb_softc *ntb = arg; 1654289546Scem sbintime_t timo, poll_ts; 1655250079Scarl 1656289546Scem timo = NTB_HB_TIMEOUT * hz; 1657289546Scem poll_ts = ntb->last_ts + timo; 1658289546Scem 1659289542Scem /* 1660289542Scem * Delay polling the link status if an interrupt was received, unless 1661289542Scem * the cached link status says the link is down. 1662289542Scem */ 1663289546Scem if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1664289546Scem timo = poll_ts - ticks; 1665289542Scem goto out; 1666289546Scem } 1667289542Scem 1668289546Scem if (ntb_poll_link(ntb)) 1669289546Scem ntb_link_event(ntb); 1670289542Scem 1671289648Scem if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1672289546Scem /* Link is down with error, proceed with recovery */ 1673289648Scem callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1674289546Scem return; 1675250079Scarl } 1676250079Scarl 1677289542Scemout: 1678289648Scem callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1679250079Scarl} 1680250079Scarl 1681250079Scarlstatic void 1682289648Scematom_perform_link_restart(struct ntb_softc *ntb) 1683250079Scarl{ 1684250079Scarl uint32_t status; 1685250079Scarl 1686250079Scarl /* Driver resets the NTB ModPhy lanes - magic! */ 1687289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1688289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1689289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1690289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1691250079Scarl 1692250079Scarl /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1693250079Scarl pause("ModPhy", hz / 10); 1694250079Scarl 1695250079Scarl /* Clear AER Errors, write to clear */ 1696289648Scem status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1697250079Scarl status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1698289648Scem ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1699250079Scarl 1700250079Scarl /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1701289648Scem status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1702289648Scem status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1703289648Scem ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1704250079Scarl 1705250079Scarl /* Clear DeSkew Buffer error, write to clear */ 1706289648Scem status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1707289648Scem status |= ATOM_DESKEWSTS_DBERR; 1708289648Scem ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1709250079Scarl 1710289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1711289648Scem status &= ATOM_IBIST_ERR_OFLOW; 1712289648Scem ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1713250079Scarl 1714250079Scarl /* Releases the NTB state machine to allow the link to retrain */ 1715289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1716289648Scem status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1717289648Scem ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1718250079Scarl} 1719250079Scarl 1720289546Scem/* 1721289546Scem * ntb_set_ctx() - associate a driver context with an ntb device 1722289546Scem * @ntb: NTB device context 1723289546Scem * @ctx: Driver context 1724289546Scem * @ctx_ops: Driver context operations 1725289546Scem * 1726289546Scem * Associate a driver context and operations with a ntb device. The context is 1727289546Scem * provided by the client driver, and the driver may associate a different 1728289546Scem * context with each ntb device. 1729289546Scem * 1730289546Scem * Return: Zero if the context is associated, otherwise an error number. 1731289546Scem */ 1732289546Scemint 1733289546Scemntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops) 1734250079Scarl{ 1735250079Scarl 1736289546Scem if (ctx == NULL || ops == NULL) 1737289546Scem return (EINVAL); 1738289546Scem if (ntb->ctx_ops != NULL) 1739289546Scem return (EINVAL); 1740250079Scarl 1741289546Scem CTX_LOCK(ntb); 1742289546Scem if (ntb->ctx_ops != NULL) { 1743289546Scem CTX_UNLOCK(ntb); 1744289546Scem return (EINVAL); 1745250079Scarl } 1746289546Scem ntb->ntb_ctx = ctx; 1747289546Scem ntb->ctx_ops = ops; 1748289546Scem CTX_UNLOCK(ntb); 1749250079Scarl 1750289546Scem return (0); 1751250079Scarl} 1752250079Scarl 1753289546Scem/* 1754289546Scem * It is expected that this will only be used from contexts where the ctx_lock 1755289546Scem * is not needed to protect ntb_ctx lifetime. 1756289546Scem */ 1757289546Scemvoid * 1758289546Scemntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops) 1759289546Scem{ 1760289546Scem 1761289546Scem KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 1762289546Scem if (ops != NULL) 1763289546Scem *ops = ntb->ctx_ops; 1764289546Scem return (ntb->ntb_ctx); 1765289546Scem} 1766289546Scem 1767289546Scem/* 1768289546Scem * ntb_clear_ctx() - disassociate any driver context from an ntb device 1769289546Scem * @ntb: NTB device context 1770289546Scem * 1771289546Scem * Clear any association that may exist between a driver context and the ntb 1772289546Scem * device. 1773289546Scem */ 1774289546Scemvoid 1775289546Scemntb_clear_ctx(struct ntb_softc *ntb) 1776289546Scem{ 1777289546Scem 1778289546Scem CTX_LOCK(ntb); 1779289546Scem ntb->ntb_ctx = NULL; 1780289546Scem ntb->ctx_ops = NULL; 1781289546Scem CTX_UNLOCK(ntb); 1782289546Scem} 1783289546Scem 1784289546Scem/* 1785289546Scem * ntb_link_event() - notify driver context of a change in link status 1786289546Scem * @ntb: NTB device context 1787289546Scem * 1788289546Scem * Notify the driver context that the link status may have changed. The driver 1789289546Scem * should call ntb_link_is_up() to get the current status. 1790289546Scem */ 1791289546Scemvoid 1792289546Scemntb_link_event(struct ntb_softc *ntb) 1793289546Scem{ 1794289546Scem 1795289546Scem CTX_LOCK(ntb); 1796289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 1797289546Scem ntb->ctx_ops->link_event(ntb->ntb_ctx); 1798289546Scem CTX_UNLOCK(ntb); 1799289546Scem} 1800289546Scem 1801289546Scem/* 1802289546Scem * ntb_db_event() - notify driver context of a doorbell event 1803289546Scem * @ntb: NTB device context 1804289546Scem * @vector: Interrupt vector number 1805289546Scem * 1806289546Scem * Notify the driver context of a doorbell event. If hardware supports 1807289546Scem * multiple interrupt vectors for doorbells, the vector number indicates which 1808289546Scem * vector received the interrupt. The vector number is relative to the first 1809289546Scem * vector used for doorbells, starting at zero, and must be less than 1810289546Scem * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 1811289546Scem * doorbell bits need service, and ntb_db_vector_mask() to determine which of 1812289546Scem * those bits are associated with the vector number. 1813289546Scem */ 1814250079Scarlstatic void 1815289546Scemntb_db_event(struct ntb_softc *ntb, uint32_t vec) 1816289272Scem{ 1817289546Scem 1818289546Scem CTX_LOCK(ntb); 1819289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 1820289546Scem ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 1821289546Scem CTX_UNLOCK(ntb); 1822289546Scem} 1823289546Scem 1824289546Scem/* 1825289546Scem * ntb_link_enable() - enable the link on the secondary side of the ntb 1826289546Scem * @ntb: NTB device context 1827289546Scem * @max_speed: The maximum link speed expressed as PCIe generation number[0] 1828289546Scem * @max_width: The maximum link width expressed as the number of PCIe lanes[0] 1829289546Scem * 1830289546Scem * Enable the link on the secondary side of the ntb. This can only be done 1831289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1832289546Scem * should train the link to its maximum speed and width, or the requested speed 1833289546Scem * and width, whichever is smaller, if supported. 1834289546Scem * 1835289546Scem * Return: Zero on success, otherwise an error number. 1836289546Scem * 1837289546Scem * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed 1838289546Scem * and width input will be ignored. 1839289546Scem */ 1840289546Scemint 1841289546Scemntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, 1842289546Scem enum ntb_width w __unused) 1843289546Scem{ 1844289280Scem uint32_t cntl; 1845289272Scem 1846289648Scem if (ntb->type == NTB_ATOM) { 1847289542Scem pci_write_config(ntb->device, NTB_PPD_OFFSET, 1848289648Scem ntb->ppd | ATOM_PPD_INIT_LINK, 4); 1849289546Scem return (0); 1850289542Scem } 1851289542Scem 1852289280Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1853289546Scem ntb_link_event(ntb); 1854289546Scem return (0); 1855289280Scem } 1856289280Scem 1857289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1858289280Scem cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 1859289280Scem cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 1860289397Scem cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 1861289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1862289397Scem cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 1863289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1864289546Scem return (0); 1865289272Scem} 1866289272Scem 1867289546Scem/* 1868289546Scem * ntb_link_disable() - disable the link on the secondary side of the ntb 1869289546Scem * @ntb: NTB device context 1870289546Scem * 1871289546Scem * Disable the link on the secondary side of the ntb. This can only be done 1872289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1873289546Scem * should disable the link. Returning from this call must indicate that a 1874289546Scem * barrier has passed, though with no more writes may pass in either direction 1875289546Scem * across the link, except if this call returns an error number. 1876289546Scem * 1877289546Scem * Return: Zero on success, otherwise an error number. 1878289546Scem */ 1879289546Scemint 1880289542Scemntb_link_disable(struct ntb_softc *ntb) 1881289272Scem{ 1882289272Scem uint32_t cntl; 1883289272Scem 1884289272Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1885289546Scem ntb_link_event(ntb); 1886289546Scem return (0); 1887289272Scem } 1888289272Scem 1889289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1890289280Scem cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 1891289397Scem cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 1892289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1893289397Scem cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 1894289280Scem cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 1895289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1896289546Scem return (0); 1897289272Scem} 1898289272Scem 1899289272Scemstatic void 1900289648Scemrecover_atom_link(void *arg) 1901250079Scarl{ 1902250079Scarl struct ntb_softc *ntb = arg; 1903289608Scem unsigned speed, width, oldspeed, oldwidth; 1904250079Scarl uint32_t status32; 1905250079Scarl 1906289648Scem atom_perform_link_restart(ntb); 1907250079Scarl 1908289232Scem /* 1909289232Scem * There is a potential race between the 2 NTB devices recovering at 1910289232Scem * the same time. If the times are the same, the link will not recover 1911289232Scem * and the driver will be stuck in this loop forever. Add a random 1912289232Scem * interval to the recovery time to prevent this race. 1913289232Scem */ 1914289648Scem status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 1915289648Scem pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 1916289232Scem 1917289648Scem if (atom_link_is_err(ntb)) 1918250079Scarl goto retry; 1919250079Scarl 1920289542Scem status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 1921289648Scem if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 1922289232Scem goto out; 1923289232Scem 1924289542Scem status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 1925289608Scem width = NTB_LNK_STA_WIDTH(status32); 1926289608Scem speed = status32 & NTB_LINK_SPEED_MASK; 1927289608Scem 1928289608Scem oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 1929289608Scem oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 1930289608Scem if (oldwidth != width || oldspeed != speed) 1931250079Scarl goto retry; 1932250079Scarl 1933289232Scemout: 1934289648Scem callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 1935289542Scem ntb); 1936250079Scarl return; 1937250079Scarl 1938250079Scarlretry: 1939289648Scem callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 1940250079Scarl ntb); 1941250079Scarl} 1942250079Scarl 1943289546Scem/* 1944289546Scem * Polls the HW link status register(s); returns true if something has changed. 1945289546Scem */ 1946289546Scemstatic bool 1947289542Scemntb_poll_link(struct ntb_softc *ntb) 1948250079Scarl{ 1949250079Scarl uint32_t ntb_cntl; 1950289546Scem uint16_t reg_val; 1951250079Scarl 1952289648Scem if (ntb->type == NTB_ATOM) { 1953289542Scem ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1954289546Scem if (ntb_cntl == ntb->ntb_ctl) 1955289546Scem return (false); 1956289546Scem 1957289542Scem ntb->ntb_ctl = ntb_cntl; 1958289542Scem ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 1959250079Scarl } else { 1960290678Scem db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 1961250079Scarl 1962289546Scem reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 1963289546Scem if (reg_val == ntb->lnk_sta) 1964289546Scem return (false); 1965250079Scarl 1966289546Scem ntb->lnk_sta = reg_val; 1967289542Scem } 1968289546Scem return (true); 1969289542Scem} 1970289542Scem 1971289546Scemstatic inline enum ntb_speed 1972289546Scemntb_link_sta_speed(struct ntb_softc *ntb) 1973250079Scarl{ 1974250079Scarl 1975289546Scem if (!link_is_up(ntb)) 1976289546Scem return (NTB_SPEED_NONE); 1977289546Scem return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 1978250079Scarl} 1979250079Scarl 1980289546Scemstatic inline enum ntb_width 1981289546Scemntb_link_sta_width(struct ntb_softc *ntb) 1982250079Scarl{ 1983250079Scarl 1984289546Scem if (!link_is_up(ntb)) 1985289546Scem return (NTB_WIDTH_NONE); 1986289546Scem return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 1987250079Scarl} 1988250079Scarl 1989289774ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 1990289774Scem "Driver state, statistics, and HW registers"); 1991289774Scem 1992289774Scem#define NTB_REGSZ_MASK (3ul << 30) 1993289774Scem#define NTB_REG_64 (1ul << 30) 1994289774Scem#define NTB_REG_32 (2ul << 30) 1995289774Scem#define NTB_REG_16 (3ul << 30) 1996289774Scem#define NTB_REG_8 (0ul << 30) 1997289774Scem 1998289774Scem#define NTB_DB_READ (1ul << 29) 1999289774Scem#define NTB_PCI_REG (1ul << 28) 2000289774Scem#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 2001289774Scem 2002289774Scemstatic void 2003289774Scemntb_sysctl_init(struct ntb_softc *ntb) 2004289774Scem{ 2005289774Scem struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; 2006289774Scem struct sysctl_ctx_list *ctx; 2007289774Scem struct sysctl_oid *tree, *tmptree; 2008289774Scem 2009289774Scem ctx = device_get_sysctl_ctx(ntb->device); 2010289774Scem 2011289774Scem tree = SYSCTL_ADD_NODE(ctx, 2012289774Scem SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, 2013289774Scem "debug_info", CTLFLAG_RD, NULL, 2014289774Scem "Driver state, statistics, and HW registers"); 2015289774Scem tree_par = SYSCTL_CHILDREN(tree); 2016289774Scem 2017289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 2018289774Scem &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 2019289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 2020289774Scem &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 2021290687Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 2022290687Scem &ntb->ppd, 0, "Raw PPD register (cached)"); 2023289774Scem 2024289774Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 2025289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 2026289774Scem &ntb->b2b_mw_idx, 0, 2027289774Scem "Index of the MW used for B2B remote register access"); 2028289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 2029289774Scem CTLFLAG_RD, &ntb->b2b_off, 2030289774Scem "If non-zero, offset of B2B register region in shared MW"); 2031289774Scem } 2032289774Scem 2033289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 2034289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 2035289774Scem "Features/errata of this NTB device"); 2036289774Scem 2037289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2038290686Scem __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2039290686Scem "NTB CTL register (cached)"); 2040289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2041290686Scem __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2042290686Scem "LNK STA register (cached)"); 2043289774Scem 2044289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", 2045289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, 2046289774Scem "A", "Link status"); 2047289774Scem 2048289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2049291263Scem &ntb->mw_count, 0, "MW count"); 2050289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2051289774Scem &ntb->spad_count, 0, "Scratchpad count"); 2052289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2053289774Scem &ntb->db_count, 0, "Doorbell count"); 2054289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2055289774Scem &ntb->db_vec_count, 0, "Doorbell vector count"); 2056289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2057289774Scem &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2058289774Scem 2059289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2060289774Scem &ntb->db_valid_mask, "Doorbell valid mask"); 2061289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2062289774Scem &ntb->db_link_mask, "Doorbell link mask"); 2063289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2064289774Scem &ntb->db_mask, "Doorbell mask (cached)"); 2065289774Scem 2066289774Scem tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2067289774Scem CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 2068289774Scem regpar = SYSCTL_CHILDREN(tmptree); 2069289774Scem 2070290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2071290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2072290682Scem ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2073290682Scem "NTB Control register"); 2074290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2075290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2076290682Scem 0x19c, sysctl_handle_register, "IU", 2077290682Scem "NTB Link Capabilities"); 2078290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2079290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2080290682Scem 0x1a0, sysctl_handle_register, "IU", 2081290682Scem "NTB Link Control register"); 2082290682Scem 2083289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2084289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2085289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2086289774Scem sysctl_handle_register, "QU", "Doorbell mask register"); 2087289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2088289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2089289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2090289774Scem sysctl_handle_register, "QU", "Doorbell register"); 2091289774Scem 2092289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2093289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2094289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2095289774Scem sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2096289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2097289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2098289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2099289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2100289774Scem sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2101289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2102289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2103289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2104289774Scem sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2105289774Scem } else { 2106289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2107289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2108289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2109289774Scem sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2110289774Scem } 2111289774Scem 2112289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2113289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2114289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2115289774Scem sysctl_handle_register, "QU", "Incoming LMT23 register"); 2116289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2117289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2118289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2119289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2120289774Scem sysctl_handle_register, "IU", "Incoming LMT4 register"); 2121289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2122289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2123289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2124289774Scem sysctl_handle_register, "IU", "Incoming LMT5 register"); 2125289774Scem } else { 2126289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2127289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2128289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2129289774Scem sysctl_handle_register, "QU", "Incoming LMT45 register"); 2130289774Scem } 2131289774Scem 2132289774Scem if (ntb->type == NTB_ATOM) 2133289774Scem return; 2134289774Scem 2135289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2136289774Scem CTLFLAG_RD, NULL, "Xeon HW statistics"); 2137289774Scem statpar = SYSCTL_CHILDREN(tmptree); 2138289774Scem SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2139289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2140289774Scem NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2141289774Scem sysctl_handle_register, "SU", "Upstream Memory Miss"); 2142289774Scem 2143289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2144289774Scem CTLFLAG_RD, NULL, "Xeon HW errors"); 2145289774Scem errpar = SYSCTL_CHILDREN(tmptree); 2146289774Scem 2147290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2148289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2149290687Scem NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2150290687Scem sysctl_handle_register, "CU", "PPD"); 2151290687Scem 2152290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2153290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2154290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2155290687Scem sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2156290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2157290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2158290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2159290687Scem sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2160290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2161290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2162290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2163290687Scem sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2164290687Scem 2165290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2166290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2167290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2168290687Scem sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2169290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2170290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2171290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2172290687Scem sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2173290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2174290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2175290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2176290687Scem sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2177290687Scem 2178290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2179290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2180289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2181289774Scem sysctl_handle_register, "SU", "DEVSTS"); 2182290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2183289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2184289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2185289774Scem sysctl_handle_register, "SU", "LNKSTS"); 2186290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2187290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2188290687Scem NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2189290687Scem sysctl_handle_register, "SU", "SLNKSTS"); 2190290687Scem 2191289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2192289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2193289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2194289774Scem sysctl_handle_register, "IU", "UNCERRSTS"); 2195289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2196289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2197289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2198289774Scem sysctl_handle_register, "IU", "CORERRSTS"); 2199289774Scem 2200289774Scem if (ntb->conn_type != NTB_CONN_B2B) 2201289774Scem return; 2202289774Scem 2203289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2204289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2205289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2206289774Scem sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2207289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2208289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2209289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2210289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2211289774Scem sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2212289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2213289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2214289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2215289774Scem sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2216289774Scem } else { 2217289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2218289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2219289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2220289774Scem sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2221289774Scem } 2222289774Scem 2223289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2224289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2225289774Scem NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2226289774Scem sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2227289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2228289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2229289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2230289774Scem NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2231289774Scem sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2232289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2233289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2234289774Scem NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2235289774Scem sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2236289774Scem } else { 2237289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2238289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2239289774Scem NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2240289774Scem sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2241289774Scem } 2242289774Scem 2243289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2244289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2245289774Scem NTB_REG_64 | ntb->xlat_reg->bar0_base, 2246289774Scem sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2247289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2248289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2249289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_base, 2250289774Scem sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2251289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2252289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2253289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2254289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_base, 2255289774Scem sysctl_handle_register, "IU", 2256289774Scem "Secondary BAR4 base register"); 2257289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2258289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2259289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_base, 2260289774Scem sysctl_handle_register, "IU", 2261289774Scem "Secondary BAR5 base register"); 2262289774Scem } else { 2263289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2264289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2265289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_base, 2266289774Scem sysctl_handle_register, "QU", 2267289774Scem "Secondary BAR45 base register"); 2268289774Scem } 2269289774Scem} 2270289774Scem 2271289774Scemstatic int 2272289774Scemsysctl_handle_features(SYSCTL_HANDLER_ARGS) 2273289774Scem{ 2274289774Scem struct ntb_softc *ntb; 2275289774Scem struct sbuf sb; 2276289774Scem int error; 2277289774Scem 2278289774Scem error = 0; 2279289774Scem ntb = arg1; 2280289774Scem 2281289774Scem sbuf_new_for_sysctl(&sb, NULL, 256, req); 2282289774Scem 2283289774Scem sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2284289774Scem error = sbuf_finish(&sb); 2285289774Scem sbuf_delete(&sb); 2286289774Scem 2287289774Scem if (error || !req->newptr) 2288289774Scem return (error); 2289289774Scem return (EINVAL); 2290289774Scem} 2291289774Scem 2292289774Scemstatic int 2293289774Scemsysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2294289774Scem{ 2295289774Scem struct ntb_softc *ntb; 2296289774Scem struct sbuf sb; 2297289774Scem enum ntb_speed speed; 2298289774Scem enum ntb_width width; 2299289774Scem int error; 2300289774Scem 2301289774Scem error = 0; 2302289774Scem ntb = arg1; 2303289774Scem 2304289774Scem sbuf_new_for_sysctl(&sb, NULL, 32, req); 2305289774Scem 2306289774Scem if (ntb_link_is_up(ntb, &speed, &width)) 2307289774Scem sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2308289774Scem (unsigned)speed, (unsigned)width); 2309289774Scem else 2310289774Scem sbuf_printf(&sb, "down"); 2311289774Scem 2312289774Scem error = sbuf_finish(&sb); 2313289774Scem sbuf_delete(&sb); 2314289774Scem 2315289774Scem if (error || !req->newptr) 2316289774Scem return (error); 2317289774Scem return (EINVAL); 2318289774Scem} 2319289774Scem 2320289774Scemstatic int 2321289774Scemsysctl_handle_register(SYSCTL_HANDLER_ARGS) 2322289774Scem{ 2323289774Scem struct ntb_softc *ntb; 2324289774Scem const void *outp; 2325289774Scem uintptr_t sz; 2326289774Scem uint64_t umv; 2327289774Scem char be[sizeof(umv)]; 2328289774Scem size_t outsz; 2329289774Scem uint32_t reg; 2330289774Scem bool db, pci; 2331289774Scem int error; 2332289774Scem 2333289774Scem ntb = arg1; 2334289774Scem reg = arg2 & ~NTB_REGFLAGS_MASK; 2335289774Scem sz = arg2 & NTB_REGSZ_MASK; 2336289774Scem db = (arg2 & NTB_DB_READ) != 0; 2337289774Scem pci = (arg2 & NTB_PCI_REG) != 0; 2338289774Scem 2339289774Scem KASSERT(!(db && pci), ("bogus")); 2340289774Scem 2341289774Scem if (db) { 2342289774Scem KASSERT(sz == NTB_REG_64, ("bogus")); 2343289774Scem umv = db_ioread(ntb, reg); 2344289774Scem outsz = sizeof(uint64_t); 2345289774Scem } else { 2346289774Scem switch (sz) { 2347289774Scem case NTB_REG_64: 2348289774Scem if (pci) 2349289774Scem umv = pci_read_config(ntb->device, reg, 8); 2350289774Scem else 2351289774Scem umv = ntb_reg_read(8, reg); 2352289774Scem outsz = sizeof(uint64_t); 2353289774Scem break; 2354289774Scem case NTB_REG_32: 2355289774Scem if (pci) 2356289774Scem umv = pci_read_config(ntb->device, reg, 4); 2357289774Scem else 2358289774Scem umv = ntb_reg_read(4, reg); 2359289774Scem outsz = sizeof(uint32_t); 2360289774Scem break; 2361289774Scem case NTB_REG_16: 2362289774Scem if (pci) 2363289774Scem umv = pci_read_config(ntb->device, reg, 2); 2364289774Scem else 2365289774Scem umv = ntb_reg_read(2, reg); 2366289774Scem outsz = sizeof(uint16_t); 2367289774Scem break; 2368289774Scem case NTB_REG_8: 2369289774Scem if (pci) 2370289774Scem umv = pci_read_config(ntb->device, reg, 1); 2371289774Scem else 2372289774Scem umv = ntb_reg_read(1, reg); 2373289774Scem outsz = sizeof(uint8_t); 2374289774Scem break; 2375289774Scem default: 2376289774Scem panic("bogus"); 2377289774Scem break; 2378289774Scem } 2379289774Scem } 2380289774Scem 2381289774Scem /* Encode bigendian so that sysctl -x is legible. */ 2382289774Scem be64enc(be, umv); 2383289774Scem outp = ((char *)be) + sizeof(umv) - outsz; 2384289774Scem 2385289774Scem error = SYSCTL_OUT(req, outp, outsz); 2386289774Scem if (error || !req->newptr) 2387289774Scem return (error); 2388289774Scem return (EINVAL); 2389289774Scem} 2390289774Scem 2391291263Scemstatic unsigned 2392291263Scemntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2393291263Scem{ 2394291263Scem 2395291263Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2396291263Scem uidx >= ntb->b2b_mw_idx) 2397291263Scem return (uidx + 1); 2398291263Scem return (uidx); 2399291263Scem} 2400291263Scem 2401289546Scem/* 2402289546Scem * Public API to the rest of the OS 2403250079Scarl */ 2404250079Scarl 2405250079Scarl/** 2406250079Scarl * ntb_get_max_spads() - get the total scratch regs usable 2407250079Scarl * @ntb: pointer to ntb_softc instance 2408250079Scarl * 2409250079Scarl * This function returns the max 32bit scratchpad registers usable by the 2410250079Scarl * upper layer. 2411250079Scarl * 2412250079Scarl * RETURNS: total number of scratch pad registers available 2413250079Scarl */ 2414289208Scemuint8_t 2415250079Scarlntb_get_max_spads(struct ntb_softc *ntb) 2416250079Scarl{ 2417250079Scarl 2418289539Scem return (ntb->spad_count); 2419250079Scarl} 2420250079Scarl 2421291263Scem/* 2422291263Scem * ntb_mw_count() - Get the number of memory windows available for KPI 2423291263Scem * consumers. 2424291263Scem * 2425291263Scem * (Excludes any MW wholly reserved for register access.) 2426291263Scem */ 2427289396Scemuint8_t 2428289539Scemntb_mw_count(struct ntb_softc *ntb) 2429289396Scem{ 2430289396Scem 2431291263Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 2432291263Scem return (ntb->mw_count - 1); 2433289539Scem return (ntb->mw_count); 2434289396Scem} 2435289396Scem 2436250079Scarl/** 2437289545Scem * ntb_spad_write() - write to the secondary scratchpad register 2438250079Scarl * @ntb: pointer to ntb_softc instance 2439250079Scarl * @idx: index to the scratchpad register, 0 based 2440250079Scarl * @val: the data value to put into the register 2441250079Scarl * 2442250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2443250079Scarl * register. The register resides on the secondary (external) side. 2444250079Scarl * 2445289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2446250079Scarl */ 2447250079Scarlint 2448289545Scemntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2449250079Scarl{ 2450250079Scarl 2451289539Scem if (idx >= ntb->spad_count) 2452250079Scarl return (EINVAL); 2453250079Scarl 2454289607Scem ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2455250079Scarl 2456250079Scarl return (0); 2457250079Scarl} 2458250079Scarl 2459250079Scarl/** 2460289545Scem * ntb_spad_read() - read from the primary scratchpad register 2461250079Scarl * @ntb: pointer to ntb_softc instance 2462250079Scarl * @idx: index to scratchpad register, 0 based 2463250079Scarl * @val: pointer to 32bit integer for storing the register value 2464250079Scarl * 2465250079Scarl * This function allows reading of the 32bit scratchpad register on 2466250079Scarl * the primary (internal) side. 2467250079Scarl * 2468289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2469250079Scarl */ 2470250079Scarlint 2471289545Scemntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2472250079Scarl{ 2473250079Scarl 2474289539Scem if (idx >= ntb->spad_count) 2475250079Scarl return (EINVAL); 2476250079Scarl 2477289607Scem *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2478250079Scarl 2479250079Scarl return (0); 2480250079Scarl} 2481250079Scarl 2482250079Scarl/** 2483289545Scem * ntb_peer_spad_write() - write to the secondary scratchpad register 2484250079Scarl * @ntb: pointer to ntb_softc instance 2485250079Scarl * @idx: index to the scratchpad register, 0 based 2486250079Scarl * @val: the data value to put into the register 2487250079Scarl * 2488250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2489250079Scarl * register. The register resides on the secondary (external) side. 2490250079Scarl * 2491289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2492250079Scarl */ 2493250079Scarlint 2494289545Scemntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2495250079Scarl{ 2496250079Scarl 2497289539Scem if (idx >= ntb->spad_count) 2498250079Scarl return (EINVAL); 2499250079Scarl 2500289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2501290682Scem ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2502255279Scarl else 2503289542Scem ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2504250079Scarl 2505250079Scarl return (0); 2506250079Scarl} 2507250079Scarl 2508250079Scarl/** 2509289545Scem * ntb_peer_spad_read() - read from the primary scratchpad register 2510250079Scarl * @ntb: pointer to ntb_softc instance 2511250079Scarl * @idx: index to scratchpad register, 0 based 2512250079Scarl * @val: pointer to 32bit integer for storing the register value 2513250079Scarl * 2514250079Scarl * This function allows reading of the 32bit scratchpad register on 2515250079Scarl * the primary (internal) side. 2516250079Scarl * 2517289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2518250079Scarl */ 2519250079Scarlint 2520289545Scemntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2521250079Scarl{ 2522250079Scarl 2523289539Scem if (idx >= ntb->spad_count) 2524250079Scarl return (EINVAL); 2525250079Scarl 2526289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2527290682Scem *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2528255279Scarl else 2529289542Scem *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2530250079Scarl 2531250079Scarl return (0); 2532250079Scarl} 2533250079Scarl 2534289546Scem/* 2535289546Scem * ntb_mw_get_range() - get the range of a memory window 2536289546Scem * @ntb: NTB device context 2537289546Scem * @idx: Memory window number 2538289546Scem * @base: OUT - the base address for mapping the memory window 2539289546Scem * @size: OUT - the size for mapping the memory window 2540289546Scem * @align: OUT - the base alignment for translating the memory window 2541289546Scem * @align_size: OUT - the size alignment for translating the memory window 2542250079Scarl * 2543289546Scem * Get the range of a memory window. NULL may be given for any output 2544289546Scem * parameter if the value is not needed. The base and size may be used for 2545289546Scem * mapping the memory window, to access the peer memory. The alignment and 2546289546Scem * size may be used for translating the memory window, for the peer to access 2547289546Scem * memory on the local system. 2548250079Scarl * 2549289546Scem * Return: Zero on success, otherwise an error number. 2550250079Scarl */ 2551289546Scemint 2552289546Scemntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base, 2553291033Scem caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 2554291033Scem bus_addr_t *plimit) 2555250079Scarl{ 2556289546Scem struct ntb_pci_bar_info *bar; 2557291033Scem bus_addr_t limit; 2558289546Scem size_t bar_b2b_off; 2559291033Scem enum ntb_bar bar_num; 2560250079Scarl 2561289546Scem if (mw_idx >= ntb_mw_count(ntb)) 2562289546Scem return (EINVAL); 2563291263Scem mw_idx = ntb_user_mw_to_idx(ntb, mw_idx); 2564250079Scarl 2565291033Scem bar_num = ntb_mw_to_bar(ntb, mw_idx); 2566291033Scem bar = &ntb->bar_info[bar_num]; 2567289546Scem bar_b2b_off = 0; 2568289546Scem if (mw_idx == ntb->b2b_mw_idx) { 2569289546Scem KASSERT(ntb->b2b_off != 0, 2570289546Scem ("user shouldn't get non-shared b2b mw")); 2571289546Scem bar_b2b_off = ntb->b2b_off; 2572289546Scem } 2573250079Scarl 2574291033Scem if (bar_is_64bit(ntb, bar_num)) 2575291033Scem limit = BUS_SPACE_MAXADDR; 2576291033Scem else 2577291033Scem limit = BUS_SPACE_MAXADDR_32BIT; 2578291033Scem 2579289546Scem if (base != NULL) 2580289546Scem *base = bar->pbase + bar_b2b_off; 2581289546Scem if (vbase != NULL) 2582290679Scem *vbase = bar->vbase + bar_b2b_off; 2583289546Scem if (size != NULL) 2584289546Scem *size = bar->size - bar_b2b_off; 2585289546Scem if (align != NULL) 2586289546Scem *align = bar->size; 2587289546Scem if (align_size != NULL) 2588289546Scem *align_size = 1; 2589291033Scem if (plimit != NULL) 2590291033Scem *plimit = limit; 2591289546Scem return (0); 2592250079Scarl} 2593250079Scarl 2594289546Scem/* 2595289546Scem * ntb_mw_set_trans() - set the translation of a memory window 2596289546Scem * @ntb: NTB device context 2597289546Scem * @idx: Memory window number 2598289546Scem * @addr: The dma address local memory to expose to the peer 2599289546Scem * @size: The size of the local memory to expose to the peer 2600250079Scarl * 2601289546Scem * Set the translation of a memory window. The peer may access local memory 2602289546Scem * through the window starting at the address, up to the size. The address 2603289546Scem * must be aligned to the alignment specified by ntb_mw_get_range(). The size 2604291033Scem * must be aligned to the size alignment specified by ntb_mw_get_range(). The 2605291033Scem * address must be below the plimit specified by ntb_mw_get_range() (i.e. for 2606291033Scem * 32-bit BARs). 2607250079Scarl * 2608289546Scem * Return: Zero on success, otherwise an error number. 2609250079Scarl */ 2610289546Scemint 2611289546Scemntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr, 2612289546Scem size_t size) 2613250079Scarl{ 2614289546Scem struct ntb_pci_bar_info *bar; 2615289546Scem uint64_t base, limit, reg_val; 2616289546Scem size_t bar_size, mw_size; 2617289546Scem uint32_t base_reg, xlat_reg, limit_reg; 2618289546Scem enum ntb_bar bar_num; 2619250079Scarl 2620289546Scem if (idx >= ntb_mw_count(ntb)) 2621289546Scem return (EINVAL); 2622291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2623250079Scarl 2624289546Scem bar_num = ntb_mw_to_bar(ntb, idx); 2625289546Scem bar = &ntb->bar_info[bar_num]; 2626250079Scarl 2627289546Scem bar_size = bar->size; 2628289546Scem if (idx == ntb->b2b_mw_idx) 2629289546Scem mw_size = bar_size - ntb->b2b_off; 2630289546Scem else 2631289546Scem mw_size = bar_size; 2632250079Scarl 2633289546Scem /* Hardware requires that addr is aligned to bar size */ 2634289546Scem if ((addr & (bar_size - 1)) != 0) 2635289546Scem return (EINVAL); 2636250079Scarl 2637289546Scem if (size > mw_size) 2638289546Scem return (EINVAL); 2639289546Scem 2640289546Scem bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2641289546Scem 2642289546Scem limit = 0; 2643289546Scem if (bar_is_64bit(ntb, bar_num)) { 2644291032Scem base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 2645289546Scem 2646289546Scem if (limit_reg != 0 && size != mw_size) 2647289546Scem limit = base + size; 2648289546Scem 2649289546Scem /* Set and verify translation address */ 2650289546Scem ntb_reg_write(8, xlat_reg, addr); 2651291032Scem reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 2652289546Scem if (reg_val != addr) { 2653289546Scem ntb_reg_write(8, xlat_reg, 0); 2654289546Scem return (EIO); 2655289546Scem } 2656289546Scem 2657289546Scem /* Set and verify the limit */ 2658289546Scem ntb_reg_write(8, limit_reg, limit); 2659291032Scem reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 2660289546Scem if (reg_val != limit) { 2661289546Scem ntb_reg_write(8, limit_reg, base); 2662289546Scem ntb_reg_write(8, xlat_reg, 0); 2663289546Scem return (EIO); 2664289546Scem } 2665289546Scem } else { 2666289546Scem /* Configure 32-bit (split) BAR MW */ 2667289546Scem 2668291029Scem if ((addr & UINT32_MAX) != addr) 2669291033Scem return (ERANGE); 2670291029Scem if (((addr + size) & UINT32_MAX) != (addr + size)) 2671291033Scem return (ERANGE); 2672289546Scem 2673291032Scem base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 2674289546Scem 2675289546Scem if (limit_reg != 0 && size != mw_size) 2676289546Scem limit = base + size; 2677289546Scem 2678289546Scem /* Set and verify translation address */ 2679289546Scem ntb_reg_write(4, xlat_reg, addr); 2680291032Scem reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 2681289546Scem if (reg_val != addr) { 2682289546Scem ntb_reg_write(4, xlat_reg, 0); 2683289546Scem return (EIO); 2684289546Scem } 2685289546Scem 2686289546Scem /* Set and verify the limit */ 2687289546Scem ntb_reg_write(4, limit_reg, limit); 2688291032Scem reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 2689289546Scem if (reg_val != limit) { 2690289546Scem ntb_reg_write(4, limit_reg, base); 2691289546Scem ntb_reg_write(4, xlat_reg, 0); 2692289546Scem return (EIO); 2693289546Scem } 2694250079Scarl } 2695289546Scem return (0); 2696250079Scarl} 2697250079Scarl 2698289596Scem/* 2699289596Scem * ntb_mw_clear_trans() - clear the translation of a memory window 2700289596Scem * @ntb: NTB device context 2701289596Scem * @idx: Memory window number 2702289596Scem * 2703289596Scem * Clear the translation of a memory window. The peer may no longer access 2704289596Scem * local memory through the window. 2705289596Scem * 2706289596Scem * Return: Zero on success, otherwise an error number. 2707289596Scem */ 2708289596Scemint 2709289596Scemntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx) 2710289596Scem{ 2711289596Scem 2712289596Scem return (ntb_mw_set_trans(ntb, mw_idx, 0, 0)); 2713289596Scem} 2714289596Scem 2715291031Scem/* 2716291031Scem * ntb_mw_get_wc - Get the write-combine status of a memory window 2717291031Scem * 2718291031Scem * Returns: Zero on success, setting *wc; otherwise an error number (e.g. if 2719291031Scem * idx is an invalid memory window). 2720291280Scem * 2721291280Scem * Mode is a VM_MEMATTR_* type. 2722291031Scem */ 2723291031Scemint 2724291280Scemntb_mw_get_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t *mode) 2725291031Scem{ 2726291031Scem struct ntb_pci_bar_info *bar; 2727291031Scem 2728291031Scem if (idx >= ntb_mw_count(ntb)) 2729291031Scem return (EINVAL); 2730291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2731291031Scem 2732291031Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 2733291280Scem *mode = bar->map_mode; 2734291031Scem return (0); 2735291031Scem} 2736291031Scem 2737291031Scem/* 2738291031Scem * ntb_mw_set_wc - Set the write-combine status of a memory window 2739291031Scem * 2740291280Scem * If 'mode' matches the current status, this does nothing and succeeds. Mode 2741291280Scem * is a VM_MEMATTR_* type. 2742291031Scem * 2743291031Scem * Returns: Zero on success, setting the caching attribute on the virtual 2744291031Scem * mapping of the BAR; otherwise an error number (e.g. if idx is an invalid 2745291031Scem * memory window, or if changing the caching attribute fails). 2746291031Scem */ 2747291031Scemint 2748291280Scemntb_mw_set_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 2749291031Scem{ 2750291263Scem 2751291263Scem if (idx >= ntb_mw_count(ntb)) 2752291263Scem return (EINVAL); 2753291263Scem 2754291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2755291280Scem return (ntb_mw_set_wc_internal(ntb, idx, mode)); 2756291263Scem} 2757291263Scem 2758291263Scemstatic int 2759291280Scemntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 2760291263Scem{ 2761291031Scem struct ntb_pci_bar_info *bar; 2762291031Scem int rc; 2763291031Scem 2764291031Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 2765291280Scem if (bar->map_mode == mode) 2766291031Scem return (0); 2767291031Scem 2768291280Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 2769291031Scem if (rc == 0) 2770291280Scem bar->map_mode = mode; 2771291031Scem 2772291031Scem return (rc); 2773291031Scem} 2774291031Scem 2775250079Scarl/** 2776289545Scem * ntb_peer_db_set() - Set the doorbell on the secondary/external side 2777250079Scarl * @ntb: pointer to ntb_softc instance 2778289545Scem * @bit: doorbell bits to ring 2779250079Scarl * 2780250079Scarl * This function allows triggering of a doorbell on the secondary/external 2781250079Scarl * side that will initiate an interrupt on the remote host 2782250079Scarl */ 2783250079Scarlvoid 2784289545Scemntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit) 2785250079Scarl{ 2786250079Scarl 2787289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2788290682Scem ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 2789289347Scem return; 2790289209Scem } 2791289347Scem 2792289546Scem db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 2793250079Scarl} 2794250079Scarl 2795289542Scem/* 2796289542Scem * ntb_get_peer_db_addr() - Return the address of the remote doorbell register, 2797289542Scem * as well as the size of the register (via *sz_out). 2798289542Scem * 2799289542Scem * This function allows a caller using I/OAT DMA to chain the remote doorbell 2800289542Scem * ring to its memory window write. 2801289542Scem * 2802289542Scem * Note that writing the peer doorbell via a memory window will *not* generate 2803289542Scem * an interrupt on the remote host; that must be done seperately. 2804289542Scem */ 2805289542Scembus_addr_t 2806289542Scemntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out) 2807289542Scem{ 2808289542Scem struct ntb_pci_bar_info *bar; 2809289542Scem uint64_t regoff; 2810289542Scem 2811289542Scem KASSERT(sz_out != NULL, ("must be non-NULL")); 2812289542Scem 2813289542Scem if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2814289542Scem bar = &ntb->bar_info[NTB_CONFIG_BAR]; 2815289542Scem regoff = ntb->peer_reg->db_bell; 2816289542Scem } else { 2817289543Scem KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 2818289543Scem ("invalid b2b idx")); 2819289542Scem 2820289542Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 2821290682Scem regoff = XEON_PDOORBELL_OFFSET; 2822289542Scem } 2823289542Scem KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 2824289542Scem 2825289542Scem *sz_out = ntb->reg->db_size; 2826289542Scem /* HACK: Specific to current x86 bus implementation. */ 2827289542Scem return ((uint64_t)bar->pci_bus_handle + regoff); 2828289542Scem} 2829289542Scem 2830289597Scem/* 2831289597Scem * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb 2832289597Scem * @ntb: NTB device context 2833289597Scem * 2834289597Scem * Hardware may support different number or arrangement of doorbell bits. 2835289597Scem * 2836289597Scem * Return: A mask of doorbell bits supported by the ntb. 2837289597Scem */ 2838289597Scemuint64_t 2839289597Scemntb_db_valid_mask(struct ntb_softc *ntb) 2840289597Scem{ 2841289597Scem 2842289597Scem return (ntb->db_valid_mask); 2843289597Scem} 2844289597Scem 2845289598Scem/* 2846289598Scem * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector 2847289598Scem * @ntb: NTB device context 2848289598Scem * @vector: Doorbell vector number 2849289598Scem * 2850289598Scem * Each interrupt vector may have a different number or arrangement of bits. 2851289598Scem * 2852289598Scem * Return: A mask of doorbell bits serviced by a vector. 2853289598Scem */ 2854289598Scemuint64_t 2855289598Scemntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector) 2856289598Scem{ 2857289598Scem 2858289598Scem if (vector > ntb->db_vec_count) 2859289598Scem return (0); 2860289598Scem return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 2861289598Scem} 2862289598Scem 2863250079Scarl/** 2864289546Scem * ntb_link_is_up() - get the current ntb link state 2865289546Scem * @ntb: NTB device context 2866289546Scem * @speed: OUT - The link speed expressed as PCIe generation number 2867289546Scem * @width: OUT - The link width expressed as the number of PCIe lanes 2868250079Scarl * 2869250079Scarl * RETURNS: true or false based on the hardware link state 2870250079Scarl */ 2871250079Scarlbool 2872289546Scemntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed, 2873289546Scem enum ntb_width *width) 2874250079Scarl{ 2875250079Scarl 2876289546Scem if (speed != NULL) 2877289546Scem *speed = ntb_link_sta_speed(ntb); 2878289546Scem if (width != NULL) 2879289546Scem *width = ntb_link_sta_width(ntb); 2880289546Scem return (link_is_up(ntb)); 2881250079Scarl} 2882250079Scarl 2883255272Scarlstatic void 2884255272Scarlsave_bar_parameters(struct ntb_pci_bar_info *bar) 2885250079Scarl{ 2886255272Scarl 2887289209Scem bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 2888289209Scem bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 2889289209Scem bar->pbase = rman_get_start(bar->pci_resource); 2890289209Scem bar->size = rman_get_size(bar->pci_resource); 2891289209Scem bar->vbase = rman_get_virtual(bar->pci_resource); 2892250079Scarl} 2893255268Scarl 2894289209Scemdevice_t 2895289209Scemntb_get_device(struct ntb_softc *ntb) 2896255268Scarl{ 2897255268Scarl 2898255268Scarl return (ntb->device); 2899255268Scarl} 2900289208Scem 2901289208Scem/* Export HW-specific errata information. */ 2902289208Scembool 2903289774Scemntb_has_feature(struct ntb_softc *ntb, uint32_t feature) 2904289208Scem{ 2905289208Scem 2906289208Scem return (HAS_FEATURE(feature)); 2907289208Scem} 2908