ntb_hw_intel.c revision 291280
1250079Scarl/*- 2250079Scarl * Copyright (C) 2013 Intel Corporation 3289542Scem * Copyright (C) 2015 EMC Corporation 4250079Scarl * All rights reserved. 5250079Scarl * 6250079Scarl * Redistribution and use in source and binary forms, with or without 7250079Scarl * modification, are permitted provided that the following conditions 8250079Scarl * are met: 9250079Scarl * 1. Redistributions of source code must retain the above copyright 10250079Scarl * notice, this list of conditions and the following disclaimer. 11250079Scarl * 2. Redistributions in binary form must reproduce the above copyright 12250079Scarl * notice, this list of conditions and the following disclaimer in the 13250079Scarl * documentation and/or other materials provided with the distribution. 14250079Scarl * 15250079Scarl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16250079Scarl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250079Scarl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250079Scarl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19250079Scarl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20250079Scarl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21250079Scarl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22250079Scarl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23250079Scarl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24250079Scarl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25250079Scarl * SUCH DAMAGE. 26250079Scarl */ 27250079Scarl 28250079Scarl#include <sys/cdefs.h> 29250079Scarl__FBSDID("$FreeBSD: head/sys/dev/ntb/ntb_hw/ntb_hw.c 291280 2015-11-25 01:59:08Z cem $"); 30250079Scarl 31250079Scarl#include <sys/param.h> 32250079Scarl#include <sys/kernel.h> 33250079Scarl#include <sys/systm.h> 34250079Scarl#include <sys/bus.h> 35289774Scem#include <sys/endian.h> 36250079Scarl#include <sys/malloc.h> 37250079Scarl#include <sys/module.h> 38250079Scarl#include <sys/queue.h> 39250079Scarl#include <sys/rman.h> 40289774Scem#include <sys/sbuf.h> 41289207Scem#include <sys/sysctl.h> 42250079Scarl#include <vm/vm.h> 43250079Scarl#include <vm/pmap.h> 44250079Scarl#include <machine/bus.h> 45250079Scarl#include <machine/pmap.h> 46250079Scarl#include <machine/resource.h> 47250079Scarl#include <dev/pci/pcireg.h> 48250079Scarl#include <dev/pci/pcivar.h> 49250079Scarl 50250079Scarl#include "ntb_regs.h" 51250079Scarl#include "ntb_hw.h" 52250079Scarl 53250079Scarl/* 54250079Scarl * The Non-Transparent Bridge (NTB) is a device on some Intel processors that 55250079Scarl * allows you to connect two systems using a PCI-e link. 56250079Scarl * 57250079Scarl * This module contains the hardware abstraction layer for the NTB. It allows 58250079Scarl * you to send and recieve interrupts, map the memory windows and send and 59250079Scarl * receive messages in the scratch-pad registers. 60250079Scarl * 61250079Scarl * NOTE: Much of the code in this module is shared with Linux. Any patches may 62250079Scarl * be picked up and redistributed in Linux with a dual GPL/BSD license. 63250079Scarl */ 64250079Scarl 65289648Scem#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 66250079Scarl 67289539Scem#define NTB_HB_TIMEOUT 1 /* second */ 68289648Scem#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 69291032Scem#define BAR_HIGH_MASK (~((1ull << 12) - 1)) 70250079Scarl 71250079Scarl#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) 72250079Scarl 73250079Scarlenum ntb_device_type { 74250079Scarl NTB_XEON, 75289648Scem NTB_ATOM 76250079Scarl}; 77250079Scarl 78289610Scem/* ntb_conn_type are hardware numbers, cannot change. */ 79289610Scemenum ntb_conn_type { 80289610Scem NTB_CONN_TRANSPARENT = 0, 81289610Scem NTB_CONN_B2B = 1, 82289610Scem NTB_CONN_RP = 2, 83289610Scem}; 84289610Scem 85289610Scemenum ntb_b2b_direction { 86289610Scem NTB_DEV_USD = 0, 87289610Scem NTB_DEV_DSD = 1, 88289610Scem}; 89289610Scem 90289539Scemenum ntb_bar { 91289539Scem NTB_CONFIG_BAR = 0, 92289539Scem NTB_B2B_BAR_1, 93289539Scem NTB_B2B_BAR_2, 94289539Scem NTB_B2B_BAR_3, 95289539Scem NTB_MAX_BARS 96289539Scem}; 97289539Scem 98255274Scarl/* Device features and workarounds */ 99255274Scarl#define HAS_FEATURE(feature) \ 100255274Scarl ((ntb->features & (feature)) != 0) 101255274Scarl 102250079Scarlstruct ntb_hw_info { 103250079Scarl uint32_t device_id; 104255274Scarl const char *desc; 105250079Scarl enum ntb_device_type type; 106289397Scem uint32_t features; 107250079Scarl}; 108250079Scarl 109250079Scarlstruct ntb_pci_bar_info { 110250079Scarl bus_space_tag_t pci_bus_tag; 111250079Scarl bus_space_handle_t pci_bus_handle; 112250079Scarl int pci_resource_id; 113250079Scarl struct resource *pci_resource; 114250079Scarl vm_paddr_t pbase; 115290679Scem caddr_t vbase; 116290679Scem vm_size_t size; 117291280Scem vm_memattr_t map_mode; 118289543Scem 119289543Scem /* Configuration register offsets */ 120289543Scem uint32_t psz_off; 121289543Scem uint32_t ssz_off; 122289543Scem uint32_t pbarxlat_off; 123250079Scarl}; 124250079Scarl 125250079Scarlstruct ntb_int_info { 126250079Scarl struct resource *res; 127250079Scarl int rid; 128250079Scarl void *tag; 129250079Scarl}; 130250079Scarl 131289546Scemstruct ntb_vec { 132250079Scarl struct ntb_softc *ntb; 133289546Scem uint32_t num; 134250079Scarl}; 135250079Scarl 136289542Scemstruct ntb_reg { 137289542Scem uint32_t ntb_ctl; 138289542Scem uint32_t lnk_sta; 139289542Scem uint8_t db_size; 140289542Scem unsigned mw_bar[NTB_MAX_BARS]; 141289542Scem}; 142289542Scem 143289542Scemstruct ntb_alt_reg { 144289542Scem uint32_t db_bell; 145289542Scem uint32_t db_mask; 146289542Scem uint32_t spad; 147289542Scem}; 148289542Scem 149289542Scemstruct ntb_xlat_reg { 150289546Scem uint32_t bar0_base; 151289546Scem uint32_t bar2_base; 152289546Scem uint32_t bar4_base; 153289546Scem uint32_t bar5_base; 154289546Scem 155289546Scem uint32_t bar2_xlat; 156289546Scem uint32_t bar4_xlat; 157289546Scem uint32_t bar5_xlat; 158289546Scem 159289546Scem uint32_t bar2_limit; 160289546Scem uint32_t bar4_limit; 161289546Scem uint32_t bar5_limit; 162289542Scem}; 163289542Scem 164289542Scemstruct ntb_b2b_addr { 165289542Scem uint64_t bar0_addr; 166289542Scem uint64_t bar2_addr64; 167289542Scem uint64_t bar4_addr64; 168289542Scem uint64_t bar4_addr32; 169289542Scem uint64_t bar5_addr32; 170289542Scem}; 171289542Scem 172250079Scarlstruct ntb_softc { 173250079Scarl device_t device; 174250079Scarl enum ntb_device_type type; 175289774Scem uint32_t features; 176250079Scarl 177250079Scarl struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 178250079Scarl struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 179250079Scarl uint32_t allocated_interrupts; 180250079Scarl 181250079Scarl struct callout heartbeat_timer; 182250079Scarl struct callout lr_timer; 183250079Scarl 184289546Scem void *ntb_ctx; 185289546Scem const struct ntb_ctx_ops *ctx_ops; 186289546Scem struct ntb_vec *msix_vec; 187290683Scem#define CTX_LOCK(sc) mtx_lock(&(sc)->ctx_lock) 188290683Scem#define CTX_UNLOCK(sc) mtx_unlock(&(sc)->ctx_lock) 189289546Scem#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f)) 190289546Scem struct mtx ctx_lock; 191250079Scarl 192289610Scem uint32_t ppd; 193289610Scem enum ntb_conn_type conn_type; 194289610Scem enum ntb_b2b_direction dev_type; 195289539Scem 196289542Scem /* Offset of peer bar0 in B2B BAR */ 197289542Scem uint64_t b2b_off; 198289542Scem /* Memory window used to access peer bar0 */ 199289543Scem#define B2B_MW_DISABLED UINT8_MAX 200289542Scem uint8_t b2b_mw_idx; 201289542Scem 202289539Scem uint8_t mw_count; 203289539Scem uint8_t spad_count; 204289539Scem uint8_t db_count; 205289539Scem uint8_t db_vec_count; 206289539Scem uint8_t db_vec_shift; 207289542Scem 208289546Scem /* Protects local db_mask. */ 209289546Scem#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 210289546Scem#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 211289546Scem#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 212289542Scem struct mtx db_mask_lock; 213289542Scem 214290686Scem volatile uint32_t ntb_ctl; 215290686Scem volatile uint32_t lnk_sta; 216289542Scem 217289542Scem uint64_t db_valid_mask; 218289542Scem uint64_t db_link_mask; 219289546Scem uint64_t db_mask; 220289542Scem 221289542Scem int last_ts; /* ticks @ last irq */ 222289542Scem 223289542Scem const struct ntb_reg *reg; 224289542Scem const struct ntb_alt_reg *self_reg; 225289542Scem const struct ntb_alt_reg *peer_reg; 226289542Scem const struct ntb_xlat_reg *xlat_reg; 227250079Scarl}; 228250079Scarl 229289234Scem#ifdef __i386__ 230289234Scemstatic __inline uint64_t 231289234Scembus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 232289234Scem bus_size_t offset) 233289234Scem{ 234289234Scem 235289234Scem return (bus_space_read_4(tag, handle, offset) | 236289234Scem ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 237289234Scem} 238289234Scem 239289234Scemstatic __inline void 240289234Scembus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 241289234Scem bus_size_t offset, uint64_t val) 242289234Scem{ 243289234Scem 244289234Scem bus_space_write_4(tag, handle, offset, val); 245289234Scem bus_space_write_4(tag, handle, offset + 4, val >> 32); 246289234Scem} 247289234Scem#endif 248289234Scem 249255279Scarl#define ntb_bar_read(SIZE, bar, offset) \ 250255279Scarl bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 251255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset)) 252255279Scarl#define ntb_bar_write(SIZE, bar, offset, val) \ 253255279Scarl bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 254255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 255255279Scarl#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 256250079Scarl#define ntb_reg_write(SIZE, offset, val) \ 257255279Scarl ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 258289397Scem#define ntb_mw_read(SIZE, offset) \ 259289542Scem ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 260255279Scarl#define ntb_mw_write(SIZE, offset, val) \ 261289542Scem ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 262289397Scem offset, val) 263250079Scarl 264250079Scarlstatic int ntb_probe(device_t device); 265250079Scarlstatic int ntb_attach(device_t device); 266250079Scarlstatic int ntb_detach(device_t device); 267291263Scemstatic unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 268289539Scemstatic inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 269289546Scemstatic inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 270289546Scemstatic inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 271289546Scem uint32_t *base, uint32_t *xlat, uint32_t *lmt); 272255272Scarlstatic int ntb_map_pci_bars(struct ntb_softc *ntb); 273291280Scemstatic int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 274291280Scem vm_memattr_t); 275289647Scemstatic void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 276289647Scem const char *); 277255272Scarlstatic int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 278255272Scarlstatic int map_memory_window_bar(struct ntb_softc *ntb, 279255272Scarl struct ntb_pci_bar_info *bar); 280250079Scarlstatic void ntb_unmap_pci_bar(struct ntb_softc *ntb); 281289344Scemstatic int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 282289540Scemstatic int ntb_init_isr(struct ntb_softc *ntb); 283289342Scemstatic int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 284289540Scemstatic int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 285250079Scarlstatic void ntb_teardown_interrupts(struct ntb_softc *ntb); 286289540Scemstatic inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 287289546Scemstatic void ntb_interrupt(struct ntb_softc *, uint32_t vec); 288289546Scemstatic void ndev_vec_isr(void *arg); 289289546Scemstatic void ndev_irq_isr(void *arg); 290289546Scemstatic inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 291290678Scemstatic inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 292290678Scemstatic inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 293289546Scemstatic int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 294289546Scemstatic void ntb_free_msix_vec(struct ntb_softc *ntb); 295250079Scarlstatic struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 296289397Scemstatic void ntb_detect_max_mw(struct ntb_softc *ntb); 297289348Scemstatic int ntb_detect_xeon(struct ntb_softc *ntb); 298289648Scemstatic int ntb_detect_atom(struct ntb_softc *ntb); 299289542Scemstatic int ntb_xeon_init_dev(struct ntb_softc *ntb); 300289648Scemstatic int ntb_atom_init_dev(struct ntb_softc *ntb); 301289272Scemstatic void ntb_teardown_xeon(struct ntb_softc *ntb); 302289648Scemstatic void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 303289543Scemstatic void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 304289543Scem enum ntb_bar regbar); 305289543Scemstatic void xeon_set_sbar_base_and_limit(struct ntb_softc *, 306289543Scem uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 307289543Scemstatic void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 308289543Scem enum ntb_bar idx); 309289542Scemstatic int xeon_setup_b2b_mw(struct ntb_softc *, 310289542Scem const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 311289546Scemstatic inline bool link_is_up(struct ntb_softc *ntb); 312289648Scemstatic inline bool atom_link_is_err(struct ntb_softc *ntb); 313289546Scemstatic inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 314289546Scemstatic inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 315289648Scemstatic void atom_link_hb(void *arg); 316289546Scemstatic void ntb_db_event(struct ntb_softc *ntb, uint32_t vec); 317289648Scemstatic void recover_atom_link(void *arg); 318289546Scemstatic bool ntb_poll_link(struct ntb_softc *ntb); 319255274Scarlstatic void save_bar_parameters(struct ntb_pci_bar_info *bar); 320289774Scemstatic void ntb_sysctl_init(struct ntb_softc *); 321289774Scemstatic int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 322289774Scemstatic int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 323289774Scemstatic int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 324250079Scarl 325290685Scemstatic unsigned g_ntb_hw_debug_level; 326290685ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 327290685Scem &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 328290685Scem#define ntb_printf(lvl, ...) do { \ 329290685Scem if ((lvl) <= g_ntb_hw_debug_level) { \ 330290685Scem device_printf(ntb->device, __VA_ARGS__); \ 331290685Scem } \ 332290685Scem} while (0) 333290685Scem 334291030Scemstatic unsigned g_ntb_enable_wc = 1; 335291030ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, enable_writecombine, CTLFLAG_RDTUN, 336291030Scem &g_ntb_enable_wc, 0, "Set to 1 to map memory windows write combining"); 337291030Scem 338291263Scemstatic int g_ntb_mw_idx = -1; 339291263ScemSYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 340291263Scem 0, "Use this memory window to access the peer NTB registers. A " 341291263Scem "non-negative value starts from the first MW index; a negative value " 342291263Scem "starts from the last MW index. The default is -1, i.e., the last " 343291263Scem "available memory window. Both sides of the NTB MUST set the same " 344291263Scem "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 345291263Scem 346250079Scarlstatic struct ntb_hw_info pci_ids[] = { 347289612Scem /* XXX: PS/SS IDs left out until they are supported. */ 348289612Scem { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 349289648Scem NTB_ATOM, 0 }, 350289233Scem 351289233Scem { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 352289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 353289233Scem { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 354289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 355289233Scem { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 356289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 357289538Scem NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 358289233Scem { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 359289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 360289538Scem NTB_SB01BASE_LOCKUP }, 361289233Scem { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 362289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 363289538Scem NTB_SB01BASE_LOCKUP }, 364289233Scem 365289648Scem { 0x00000000, NULL, NTB_ATOM, 0 } 366250079Scarl}; 367250079Scarl 368289648Scemstatic const struct ntb_reg atom_reg = { 369289648Scem .ntb_ctl = ATOM_NTBCNTL_OFFSET, 370289648Scem .lnk_sta = ATOM_LINK_STATUS_OFFSET, 371289542Scem .db_size = sizeof(uint64_t), 372289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 373289542Scem}; 374289542Scem 375289648Scemstatic const struct ntb_alt_reg atom_pri_reg = { 376289648Scem .db_bell = ATOM_PDOORBELL_OFFSET, 377289648Scem .db_mask = ATOM_PDBMSK_OFFSET, 378289648Scem .spad = ATOM_SPAD_OFFSET, 379289607Scem}; 380289607Scem 381289648Scemstatic const struct ntb_alt_reg atom_b2b_reg = { 382289648Scem .db_bell = ATOM_B2B_DOORBELL_OFFSET, 383289648Scem .spad = ATOM_B2B_SPAD_OFFSET, 384289542Scem}; 385289542Scem 386289648Scemstatic const struct ntb_xlat_reg atom_sec_xlat = { 387289542Scem#if 0 388289542Scem /* "FIXME" says the Linux driver. */ 389289648Scem .bar0_base = ATOM_SBAR0BASE_OFFSET, 390289648Scem .bar2_base = ATOM_SBAR2BASE_OFFSET, 391289648Scem .bar4_base = ATOM_SBAR4BASE_OFFSET, 392289546Scem 393289648Scem .bar2_limit = ATOM_SBAR2LMT_OFFSET, 394289648Scem .bar4_limit = ATOM_SBAR4LMT_OFFSET, 395289542Scem#endif 396289546Scem 397289648Scem .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 398289648Scem .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 399289542Scem}; 400289542Scem 401289542Scemstatic const struct ntb_reg xeon_reg = { 402289542Scem .ntb_ctl = XEON_NTBCNTL_OFFSET, 403289542Scem .lnk_sta = XEON_LINK_STATUS_OFFSET, 404289542Scem .db_size = sizeof(uint16_t), 405289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 406289542Scem}; 407289542Scem 408289607Scemstatic const struct ntb_alt_reg xeon_pri_reg = { 409289607Scem .db_bell = XEON_PDOORBELL_OFFSET, 410289607Scem .db_mask = XEON_PDBMSK_OFFSET, 411289607Scem .spad = XEON_SPAD_OFFSET, 412289607Scem}; 413289607Scem 414289542Scemstatic const struct ntb_alt_reg xeon_b2b_reg = { 415289542Scem .db_bell = XEON_B2B_DOORBELL_OFFSET, 416289542Scem .spad = XEON_B2B_SPAD_OFFSET, 417289542Scem}; 418289542Scem 419289542Scemstatic const struct ntb_xlat_reg xeon_sec_xlat = { 420289542Scem .bar0_base = XEON_SBAR0BASE_OFFSET, 421289546Scem .bar2_base = XEON_SBAR2BASE_OFFSET, 422289546Scem .bar4_base = XEON_SBAR4BASE_OFFSET, 423289546Scem .bar5_base = XEON_SBAR5BASE_OFFSET, 424289546Scem 425289542Scem .bar2_limit = XEON_SBAR2LMT_OFFSET, 426289546Scem .bar4_limit = XEON_SBAR4LMT_OFFSET, 427289546Scem .bar5_limit = XEON_SBAR5LMT_OFFSET, 428289546Scem 429289542Scem .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 430289546Scem .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 431289546Scem .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 432289542Scem}; 433289542Scem 434289614Scemstatic struct ntb_b2b_addr xeon_b2b_usd_addr = { 435290725Scem .bar0_addr = XEON_B2B_BAR0_ADDR, 436290725Scem .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 437290725Scem .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 438290725Scem .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 439290725Scem .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 440289542Scem}; 441289542Scem 442289614Scemstatic struct ntb_b2b_addr xeon_b2b_dsd_addr = { 443290725Scem .bar0_addr = XEON_B2B_BAR0_ADDR, 444290725Scem .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 445290725Scem .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 446290725Scem .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 447290725Scem .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 448289542Scem}; 449289542Scem 450289614ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 451289614Scem "B2B MW segment overrides -- MUST be the same on both sides"); 452289614Scem 453289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 454289614Scem &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 455289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 456289614Scem "the window at BAR2, on the upstream side of the link. MUST be the same " 457289614Scem "address on both sides."); 458289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 459289614Scem &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 460289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 461289614Scem &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 462289614Scem "(split-BAR mode)."); 463289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 464289646Scem &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 465289614Scem "(split-BAR mode)."); 466289614Scem 467289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 468289614Scem &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 469289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 470289614Scem "the window at BAR2, on the downstream side of the link. MUST be the same" 471289614Scem " address on both sides."); 472289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 473289614Scem &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 474289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 475289614Scem &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 476289614Scem "(split-BAR mode)."); 477289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 478289646Scem &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 479289614Scem "(split-BAR mode)."); 480289614Scem 481250079Scarl/* 482250079Scarl * OS <-> Driver interface structures 483250079Scarl */ 484250079ScarlMALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 485250079Scarl 486250079Scarlstatic device_method_t ntb_pci_methods[] = { 487250079Scarl /* Device interface */ 488250079Scarl DEVMETHOD(device_probe, ntb_probe), 489250079Scarl DEVMETHOD(device_attach, ntb_attach), 490250079Scarl DEVMETHOD(device_detach, ntb_detach), 491250079Scarl DEVMETHOD_END 492250079Scarl}; 493250079Scarl 494250079Scarlstatic driver_t ntb_pci_driver = { 495250079Scarl "ntb_hw", 496250079Scarl ntb_pci_methods, 497250079Scarl sizeof(struct ntb_softc), 498250079Scarl}; 499250079Scarl 500250079Scarlstatic devclass_t ntb_devclass; 501250079ScarlDRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); 502250079ScarlMODULE_VERSION(ntb_hw, 1); 503250079Scarl 504289207ScemSYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 505289207Scem 506250079Scarl/* 507250079Scarl * OS <-> Driver linkage functions 508250079Scarl */ 509250079Scarlstatic int 510250079Scarlntb_probe(device_t device) 511250079Scarl{ 512289209Scem struct ntb_hw_info *p; 513250079Scarl 514289209Scem p = ntb_get_device_info(pci_get_devid(device)); 515289209Scem if (p == NULL) 516250079Scarl return (ENXIO); 517289209Scem 518289209Scem device_set_desc(device, p->desc); 519289209Scem return (0); 520250079Scarl} 521250079Scarl 522250079Scarlstatic int 523250079Scarlntb_attach(device_t device) 524250079Scarl{ 525289209Scem struct ntb_softc *ntb; 526289209Scem struct ntb_hw_info *p; 527250079Scarl int error; 528250079Scarl 529289209Scem ntb = DEVICE2SOFTC(device); 530289209Scem p = ntb_get_device_info(pci_get_devid(device)); 531289209Scem 532250079Scarl ntb->device = device; 533250079Scarl ntb->type = p->type; 534255274Scarl ntb->features = p->features; 535289543Scem ntb->b2b_mw_idx = B2B_MW_DISABLED; 536250079Scarl 537289648Scem /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 538283291Sjkim callout_init(&ntb->heartbeat_timer, 1); 539283291Sjkim callout_init(&ntb->lr_timer, 1); 540289542Scem mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 541290683Scem mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_DEF); 542250079Scarl 543289648Scem if (ntb->type == NTB_ATOM) 544289648Scem error = ntb_detect_atom(ntb); 545289348Scem else 546289348Scem error = ntb_detect_xeon(ntb); 547290682Scem if (error != 0) 548289348Scem goto out; 549289348Scem 550289397Scem ntb_detect_max_mw(ntb); 551289396Scem 552290682Scem pci_enable_busmaster(ntb->device); 553290682Scem 554289209Scem error = ntb_map_pci_bars(ntb); 555290682Scem if (error != 0) 556289209Scem goto out; 557289648Scem if (ntb->type == NTB_ATOM) 558289648Scem error = ntb_atom_init_dev(ntb); 559289272Scem else 560289542Scem error = ntb_xeon_init_dev(ntb); 561290682Scem if (error != 0) 562289209Scem goto out; 563290682Scem 564290682Scem ntb_poll_link(ntb); 565290682Scem 566289774Scem ntb_sysctl_init(ntb); 567250079Scarl 568289209Scemout: 569289209Scem if (error != 0) 570289209Scem ntb_detach(device); 571250079Scarl return (error); 572250079Scarl} 573250079Scarl 574250079Scarlstatic int 575250079Scarlntb_detach(device_t device) 576250079Scarl{ 577289209Scem struct ntb_softc *ntb; 578250079Scarl 579289209Scem ntb = DEVICE2SOFTC(device); 580289542Scem 581289617Scem if (ntb->self_reg != NULL) 582289617Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 583250079Scarl callout_drain(&ntb->heartbeat_timer); 584250079Scarl callout_drain(&ntb->lr_timer); 585290682Scem pci_disable_busmaster(ntb->device); 586289272Scem if (ntb->type == NTB_XEON) 587289272Scem ntb_teardown_xeon(ntb); 588250079Scarl ntb_teardown_interrupts(ntb); 589289397Scem 590289542Scem mtx_destroy(&ntb->db_mask_lock); 591289546Scem mtx_destroy(&ntb->ctx_lock); 592289542Scem 593250079Scarl ntb_unmap_pci_bar(ntb); 594250079Scarl 595250079Scarl return (0); 596250079Scarl} 597250079Scarl 598289542Scem/* 599289542Scem * Driver internal routines 600289542Scem */ 601289539Scemstatic inline enum ntb_bar 602289539Scemntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 603289539Scem{ 604289539Scem 605291263Scem KASSERT(mw < ntb->mw_count, 606289542Scem ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 607289546Scem KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 608289539Scem 609289542Scem return (ntb->reg->mw_bar[mw]); 610289539Scem} 611289539Scem 612289546Scemstatic inline bool 613289546Scembar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 614289546Scem{ 615289546Scem /* XXX This assertion could be stronger. */ 616289546Scem KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 617289546Scem return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR)); 618289546Scem} 619289546Scem 620289546Scemstatic inline void 621289546Scembar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 622289546Scem uint32_t *xlat, uint32_t *lmt) 623289546Scem{ 624289546Scem uint32_t basev, lmtv, xlatv; 625289546Scem 626289546Scem switch (bar) { 627289546Scem case NTB_B2B_BAR_1: 628289546Scem basev = ntb->xlat_reg->bar2_base; 629289546Scem lmtv = ntb->xlat_reg->bar2_limit; 630289546Scem xlatv = ntb->xlat_reg->bar2_xlat; 631289546Scem break; 632289546Scem case NTB_B2B_BAR_2: 633289546Scem basev = ntb->xlat_reg->bar4_base; 634289546Scem lmtv = ntb->xlat_reg->bar4_limit; 635289546Scem xlatv = ntb->xlat_reg->bar4_xlat; 636289546Scem break; 637289546Scem case NTB_B2B_BAR_3: 638289546Scem basev = ntb->xlat_reg->bar5_base; 639289546Scem lmtv = ntb->xlat_reg->bar5_limit; 640289546Scem xlatv = ntb->xlat_reg->bar5_xlat; 641289546Scem break; 642289546Scem default: 643289546Scem KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 644289546Scem ("bad bar")); 645289546Scem basev = lmtv = xlatv = 0; 646289546Scem break; 647289546Scem } 648289546Scem 649289546Scem if (base != NULL) 650289546Scem *base = basev; 651289546Scem if (xlat != NULL) 652289546Scem *xlat = xlatv; 653289546Scem if (lmt != NULL) 654289546Scem *lmt = lmtv; 655289546Scem} 656289546Scem 657250079Scarlstatic int 658255272Scarlntb_map_pci_bars(struct ntb_softc *ntb) 659250079Scarl{ 660255272Scarl int rc; 661250079Scarl 662250079Scarl ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 663289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 664255272Scarl if (rc != 0) 665289541Scem goto out; 666255272Scarl 667289209Scem ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 668289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 669255272Scarl if (rc != 0) 670289541Scem goto out; 671289543Scem ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 672289543Scem ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 673289543Scem ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 674255272Scarl 675289209Scem ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 676291263Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 677291263Scem if (rc != 0) 678291263Scem goto out; 679289543Scem ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 680289543Scem ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 681289543Scem ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 682289543Scem 683289397Scem if (!HAS_FEATURE(NTB_SPLIT_BAR)) 684289541Scem goto out; 685289397Scem 686289397Scem ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 687291263Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 688289543Scem ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 689289543Scem ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 690289543Scem ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 691250079Scarl 692289541Scemout: 693289209Scem if (rc != 0) 694255272Scarl device_printf(ntb->device, 695255272Scarl "unable to allocate pci resource\n"); 696255272Scarl return (rc); 697255272Scarl} 698255272Scarl 699289541Scemstatic void 700289647Scemprint_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 701289647Scem const char *kind) 702289541Scem{ 703289541Scem 704289647Scem device_printf(ntb->device, 705289647Scem "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 706289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 707289647Scem (char *)bar->vbase + bar->size - 1, 708289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 709289647Scem (uintmax_t)bar->size, kind); 710289541Scem} 711289541Scem 712255272Scarlstatic int 713255272Scarlmap_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 714255272Scarl{ 715255272Scarl 716255275Scarl bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 717289209Scem &bar->pci_resource_id, RF_ACTIVE); 718255272Scarl if (bar->pci_resource == NULL) 719255272Scarl return (ENXIO); 720289209Scem 721289209Scem save_bar_parameters(bar); 722291280Scem bar->map_mode = VM_MEMATTR_UNCACHEABLE; 723289647Scem print_map_success(ntb, bar, "mmr"); 724289209Scem return (0); 725255272Scarl} 726255272Scarl 727255272Scarlstatic int 728255272Scarlmap_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 729255272Scarl{ 730255272Scarl int rc; 731291280Scem vm_memattr_t mapmode; 732255276Scarl uint8_t bar_size_bits = 0; 733255272Scarl 734289209Scem bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 735289209Scem &bar->pci_resource_id, RF_ACTIVE); 736250079Scarl 737255272Scarl if (bar->pci_resource == NULL) 738255272Scarl return (ENXIO); 739255276Scarl 740289209Scem save_bar_parameters(bar); 741289209Scem /* 742289209Scem * Ivytown NTB BAR sizes are misreported by the hardware due to a 743289209Scem * hardware issue. To work around this, query the size it should be 744289209Scem * configured to by the device and modify the resource to correspond to 745289209Scem * this new size. The BIOS on systems with this problem is required to 746289209Scem * provide enough address space to allow the driver to make this change 747289209Scem * safely. 748289209Scem * 749289209Scem * Ideally I could have just specified the size when I allocated the 750289209Scem * resource like: 751289209Scem * bus_alloc_resource(ntb->device, 752289209Scem * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 753289209Scem * 1ul << bar_size_bits, RF_ACTIVE); 754289209Scem * but the PCI driver does not honor the size in this call, so we have 755289209Scem * to modify it after the fact. 756289209Scem */ 757289209Scem if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { 758289209Scem if (bar->pci_resource_id == PCIR_BAR(2)) 759289209Scem bar_size_bits = pci_read_config(ntb->device, 760289209Scem XEON_PBAR23SZ_OFFSET, 1); 761289209Scem else 762289209Scem bar_size_bits = pci_read_config(ntb->device, 763289209Scem XEON_PBAR45SZ_OFFSET, 1); 764289209Scem 765289209Scem rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 766289209Scem bar->pci_resource, bar->pbase, 767289209Scem bar->pbase + (1ul << bar_size_bits) - 1); 768255272Scarl if (rc != 0) { 769289209Scem device_printf(ntb->device, 770289209Scem "unable to resize bar\n"); 771255272Scarl return (rc); 772250079Scarl } 773289209Scem 774289209Scem save_bar_parameters(bar); 775250079Scarl } 776289209Scem 777291280Scem bar->map_mode = VM_MEMATTR_UNCACHEABLE; 778291030Scem print_map_success(ntb, bar, "mw"); 779291280Scem 780291280Scem /* Mark bar region as write combining to improve performance. */ 781291280Scem mapmode = VM_MEMATTR_WRITE_COMBINING; 782291030Scem if (g_ntb_enable_wc == 0) 783291280Scem mapmode = VM_MEMATTR_WRITE_BACK; 784291030Scem 785291280Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 786291031Scem if (rc == 0) { 787291280Scem bar->map_mode = mapmode; 788289209Scem device_printf(ntb->device, 789289647Scem "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 790291280Scem "%s.\n", 791289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 792289647Scem (char *)bar->vbase + bar->size - 1, 793291280Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 794291280Scem (mapmode == VM_MEMATTR_WRITE_COMBINING) ? "WRITE_COMBINING" 795291280Scem : "WRITE_BACK"); 796291031Scem } else 797289647Scem device_printf(ntb->device, 798289647Scem "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 799291280Scem "%s: %d\n", 800289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 801289647Scem (char *)bar->vbase + bar->size - 1, 802289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 803291280Scem (mapmode == VM_MEMATTR_WRITE_COMBINING) ? "WRITE_COMBINING" 804291280Scem : "WRITE_BACK", rc); 805289647Scem /* Proceed anyway */ 806250079Scarl return (0); 807250079Scarl} 808250079Scarl 809250079Scarlstatic void 810250079Scarlntb_unmap_pci_bar(struct ntb_softc *ntb) 811250079Scarl{ 812250079Scarl struct ntb_pci_bar_info *current_bar; 813250079Scarl int i; 814250079Scarl 815289397Scem for (i = 0; i < NTB_MAX_BARS; i++) { 816250079Scarl current_bar = &ntb->bar_info[i]; 817250079Scarl if (current_bar->pci_resource != NULL) 818250079Scarl bus_release_resource(ntb->device, SYS_RES_MEMORY, 819250079Scarl current_bar->pci_resource_id, 820250079Scarl current_bar->pci_resource); 821250079Scarl } 822250079Scarl} 823250079Scarl 824250079Scarlstatic int 825289540Scemntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 826250079Scarl{ 827289342Scem uint32_t i; 828289342Scem int rc; 829289342Scem 830289342Scem for (i = 0; i < num_vectors; i++) { 831289342Scem ntb->int_info[i].rid = i + 1; 832289342Scem ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 833289342Scem SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 834289342Scem if (ntb->int_info[i].res == NULL) { 835289342Scem device_printf(ntb->device, 836289342Scem "bus_alloc_resource failed\n"); 837289342Scem return (ENOMEM); 838289342Scem } 839289342Scem ntb->int_info[i].tag = NULL; 840289342Scem ntb->allocated_interrupts++; 841289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 842289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 843289546Scem &ntb->msix_vec[i], &ntb->int_info[i].tag); 844289342Scem if (rc != 0) { 845289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 846289342Scem return (ENXIO); 847289342Scem } 848289342Scem } 849289342Scem return (0); 850289342Scem} 851289342Scem 852289344Scem/* 853289344Scem * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 854289344Scem * cannot be allocated for each MSI-X message. JHB seems to think remapping 855289344Scem * should be okay. This tunable should enable us to test that hypothesis 856289344Scem * when someone gets their hands on some Xeon hardware. 857289344Scem */ 858289344Scemstatic int ntb_force_remap_mode; 859289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 860289344Scem &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 861289344Scem " to a smaller number of ithreads, even if the desired number are " 862289344Scem "available"); 863289344Scem 864289344Scem/* 865289344Scem * In case it is NOT ok, give consumers an abort button. 866289344Scem */ 867289344Scemstatic int ntb_prefer_intx; 868289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 869289344Scem &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 870289344Scem "than remapping MSI-X messages over available slots (match Linux driver " 871289344Scem "behavior)"); 872289344Scem 873289344Scem/* 874289344Scem * Remap the desired number of MSI-X messages to available ithreads in a simple 875289344Scem * round-robin fashion. 876289344Scem */ 877289342Scemstatic int 878289344Scemntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 879289344Scem{ 880289344Scem u_int *vectors; 881289344Scem uint32_t i; 882289344Scem int rc; 883289344Scem 884289344Scem if (ntb_prefer_intx != 0) 885289344Scem return (ENXIO); 886289344Scem 887289344Scem vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 888289344Scem 889289344Scem for (i = 0; i < desired; i++) 890289344Scem vectors[i] = (i % avail) + 1; 891289344Scem 892289344Scem rc = pci_remap_msix(dev, desired, vectors); 893289344Scem free(vectors, M_NTB); 894289344Scem return (rc); 895289344Scem} 896289344Scem 897289344Scemstatic int 898289540Scemntb_init_isr(struct ntb_softc *ntb) 899289342Scem{ 900289344Scem uint32_t desired_vectors, num_vectors; 901289342Scem int rc; 902250079Scarl 903250079Scarl ntb->allocated_interrupts = 0; 904289542Scem ntb->last_ts = ticks; 905289347Scem 906250079Scarl /* 907289546Scem * Mask all doorbell interrupts. 908250079Scarl */ 909289546Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 910250079Scarl 911289344Scem num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 912289539Scem ntb->db_count); 913289344Scem if (desired_vectors >= 1) { 914289344Scem rc = pci_alloc_msix(ntb->device, &num_vectors); 915250079Scarl 916289344Scem if (ntb_force_remap_mode != 0 && rc == 0 && 917289344Scem num_vectors == desired_vectors) 918289344Scem num_vectors--; 919289344Scem 920289344Scem if (rc == 0 && num_vectors < desired_vectors) { 921289344Scem rc = ntb_remap_msix(ntb->device, desired_vectors, 922289344Scem num_vectors); 923289344Scem if (rc == 0) 924289344Scem num_vectors = desired_vectors; 925289344Scem else 926289344Scem pci_release_msi(ntb->device); 927289344Scem } 928289344Scem if (rc != 0) 929289344Scem num_vectors = 1; 930289344Scem } else 931289344Scem num_vectors = 1; 932289344Scem 933289539Scem if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 934289539Scem ntb->db_vec_count = 1; 935290680Scem ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 936289539Scem rc = ntb_setup_legacy_interrupt(ntb); 937289539Scem } else { 938289546Scem ntb_create_msix_vec(ntb, num_vectors); 939289540Scem rc = ntb_setup_msix(ntb, num_vectors); 940289539Scem } 941289539Scem if (rc != 0) { 942289539Scem device_printf(ntb->device, 943289539Scem "Error allocating interrupts: %d\n", rc); 944289546Scem ntb_free_msix_vec(ntb); 945289396Scem } 946289396Scem 947289342Scem return (rc); 948289342Scem} 949289342Scem 950289342Scemstatic int 951289342Scemntb_setup_legacy_interrupt(struct ntb_softc *ntb) 952289342Scem{ 953289342Scem int rc; 954289342Scem 955289342Scem ntb->int_info[0].rid = 0; 956289342Scem ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 957289342Scem &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 958289342Scem if (ntb->int_info[0].res == NULL) { 959289342Scem device_printf(ntb->device, "bus_alloc_resource failed\n"); 960289342Scem return (ENOMEM); 961250079Scarl } 962250079Scarl 963289342Scem ntb->int_info[0].tag = NULL; 964289342Scem ntb->allocated_interrupts = 1; 965289342Scem 966289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 967289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 968289342Scem ntb, &ntb->int_info[0].tag); 969289342Scem if (rc != 0) { 970289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 971289342Scem return (ENXIO); 972289342Scem } 973289342Scem 974250079Scarl return (0); 975250079Scarl} 976250079Scarl 977250079Scarlstatic void 978250079Scarlntb_teardown_interrupts(struct ntb_softc *ntb) 979250079Scarl{ 980250079Scarl struct ntb_int_info *current_int; 981250079Scarl int i; 982250079Scarl 983289209Scem for (i = 0; i < ntb->allocated_interrupts; i++) { 984250079Scarl current_int = &ntb->int_info[i]; 985250079Scarl if (current_int->tag != NULL) 986250079Scarl bus_teardown_intr(ntb->device, current_int->res, 987250079Scarl current_int->tag); 988250079Scarl 989250079Scarl if (current_int->res != NULL) 990250079Scarl bus_release_resource(ntb->device, SYS_RES_IRQ, 991250079Scarl rman_get_rid(current_int->res), current_int->res); 992250079Scarl } 993250079Scarl 994289546Scem ntb_free_msix_vec(ntb); 995250079Scarl pci_release_msi(ntb->device); 996250079Scarl} 997250079Scarl 998289347Scem/* 999289648Scem * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 1000289347Scem * out to make code clearer. 1001289347Scem */ 1002289539Scemstatic inline uint64_t 1003289546Scemdb_ioread(struct ntb_softc *ntb, uint64_t regoff) 1004289347Scem{ 1005289347Scem 1006289648Scem if (ntb->type == NTB_ATOM) 1007289347Scem return (ntb_reg_read(8, regoff)); 1008289347Scem 1009289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1010289347Scem 1011289347Scem return (ntb_reg_read(2, regoff)); 1012289347Scem} 1013289347Scem 1014289539Scemstatic inline void 1015289546Scemdb_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1016289347Scem{ 1017289347Scem 1018289542Scem KASSERT((val & ~ntb->db_valid_mask) == 0, 1019289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1020289542Scem (uintmax_t)(val & ~ntb->db_valid_mask), 1021289542Scem (uintmax_t)ntb->db_valid_mask)); 1022289542Scem 1023289607Scem if (regoff == ntb->self_reg->db_mask) 1024289546Scem DB_MASK_ASSERT(ntb, MA_OWNED); 1025290678Scem db_iowrite_raw(ntb, regoff, val); 1026290678Scem} 1027289542Scem 1028290678Scemstatic inline void 1029290678Scemdb_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1030290678Scem{ 1031290678Scem 1032289648Scem if (ntb->type == NTB_ATOM) { 1033289347Scem ntb_reg_write(8, regoff, val); 1034289347Scem return; 1035289347Scem } 1036289347Scem 1037289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1038289347Scem ntb_reg_write(2, regoff, (uint16_t)val); 1039289347Scem} 1040289347Scem 1041289546Scemvoid 1042289542Scemntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits) 1043289542Scem{ 1044289542Scem 1045289546Scem DB_MASK_LOCK(ntb); 1046289542Scem ntb->db_mask |= bits; 1047289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1048289546Scem DB_MASK_UNLOCK(ntb); 1049289542Scem} 1050289542Scem 1051289546Scemvoid 1052289542Scemntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits) 1053289542Scem{ 1054289542Scem 1055289542Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1056289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1057289542Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1058289542Scem (uintmax_t)ntb->db_valid_mask)); 1059289542Scem 1060289546Scem DB_MASK_LOCK(ntb); 1061289542Scem ntb->db_mask &= ~bits; 1062289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1063289546Scem DB_MASK_UNLOCK(ntb); 1064289542Scem} 1065289542Scem 1066289546Scemuint64_t 1067289546Scemntb_db_read(struct ntb_softc *ntb) 1068289281Scem{ 1069289281Scem 1070289607Scem return (db_ioread(ntb, ntb->self_reg->db_bell)); 1071289281Scem} 1072289281Scem 1073289546Scemvoid 1074289546Scemntb_db_clear(struct ntb_softc *ntb, uint64_t bits) 1075289281Scem{ 1076289281Scem 1077289546Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1078289546Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1079289546Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1080289546Scem (uintmax_t)ntb->db_valid_mask)); 1081289546Scem 1082289607Scem db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1083289281Scem} 1084289281Scem 1085289540Scemstatic inline uint64_t 1086289540Scemntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1087250079Scarl{ 1088289540Scem uint64_t shift, mask; 1089250079Scarl 1090289540Scem shift = ntb->db_vec_shift; 1091289540Scem mask = (1ull << shift) - 1; 1092289540Scem return (mask << (shift * db_vector)); 1093250079Scarl} 1094250079Scarl 1095250079Scarlstatic void 1096289546Scemntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1097250079Scarl{ 1098289540Scem uint64_t vec_mask; 1099250079Scarl 1100289542Scem ntb->last_ts = ticks; 1101289546Scem vec_mask = ntb_vec_mask(ntb, vec); 1102250079Scarl 1103289542Scem if ((vec_mask & ntb->db_link_mask) != 0) { 1104289546Scem if (ntb_poll_link(ntb)) 1105289546Scem ntb_link_event(ntb); 1106289540Scem } 1107289540Scem 1108289546Scem if ((vec_mask & ntb->db_valid_mask) != 0) 1109289546Scem ntb_db_event(ntb, vec); 1110289546Scem} 1111250079Scarl 1112289546Scemstatic void 1113289546Scemndev_vec_isr(void *arg) 1114289546Scem{ 1115289546Scem struct ntb_vec *nvec = arg; 1116250079Scarl 1117289546Scem ntb_interrupt(nvec->ntb, nvec->num); 1118250079Scarl} 1119250079Scarl 1120250079Scarlstatic void 1121289546Scemndev_irq_isr(void *arg) 1122250079Scarl{ 1123289546Scem /* If we couldn't set up MSI-X, we only have the one vector. */ 1124289546Scem ntb_interrupt(arg, 0); 1125250079Scarl} 1126250079Scarl 1127250079Scarlstatic int 1128289546Scemntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1129250079Scarl{ 1130289342Scem uint32_t i; 1131250079Scarl 1132289546Scem ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1133250079Scarl M_ZERO | M_WAITOK); 1134250079Scarl for (i = 0; i < num_vectors; i++) { 1135289546Scem ntb->msix_vec[i].num = i; 1136289546Scem ntb->msix_vec[i].ntb = ntb; 1137250079Scarl } 1138250079Scarl 1139250079Scarl return (0); 1140250079Scarl} 1141250079Scarl 1142250079Scarlstatic void 1143289546Scemntb_free_msix_vec(struct ntb_softc *ntb) 1144250079Scarl{ 1145250079Scarl 1146289546Scem if (ntb->msix_vec == NULL) 1147289539Scem return; 1148289539Scem 1149289546Scem free(ntb->msix_vec, M_NTB); 1150289546Scem ntb->msix_vec = NULL; 1151250079Scarl} 1152250079Scarl 1153250079Scarlstatic struct ntb_hw_info * 1154250079Scarlntb_get_device_info(uint32_t device_id) 1155250079Scarl{ 1156250079Scarl struct ntb_hw_info *ep = pci_ids; 1157250079Scarl 1158250079Scarl while (ep->device_id) { 1159250079Scarl if (ep->device_id == device_id) 1160250079Scarl return (ep); 1161250079Scarl ++ep; 1162250079Scarl } 1163250079Scarl return (NULL); 1164250079Scarl} 1165250079Scarl 1166289272Scemstatic void 1167289272Scemntb_teardown_xeon(struct ntb_softc *ntb) 1168250079Scarl{ 1169250079Scarl 1170289617Scem if (ntb->reg != NULL) 1171289617Scem ntb_link_disable(ntb); 1172250079Scarl} 1173250079Scarl 1174289397Scemstatic void 1175289397Scemntb_detect_max_mw(struct ntb_softc *ntb) 1176289397Scem{ 1177289397Scem 1178289648Scem if (ntb->type == NTB_ATOM) { 1179289648Scem ntb->mw_count = ATOM_MW_COUNT; 1180289397Scem return; 1181289397Scem } 1182289397Scem 1183289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1184289539Scem ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1185289397Scem else 1186289539Scem ntb->mw_count = XEON_SNB_MW_COUNT; 1187289397Scem} 1188289397Scem 1189250079Scarlstatic int 1190289348Scemntb_detect_xeon(struct ntb_softc *ntb) 1191250079Scarl{ 1192289348Scem uint8_t ppd, conn_type; 1193250079Scarl 1194289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1195289348Scem ntb->ppd = ppd; 1196250079Scarl 1197289348Scem if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1198290681Scem ntb->dev_type = NTB_DEV_DSD; 1199290681Scem else 1200289257Scem ntb->dev_type = NTB_DEV_USD; 1201289257Scem 1202289397Scem if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1203289397Scem ntb->features |= NTB_SPLIT_BAR; 1204289397Scem 1205289542Scem /* SB01BASE_LOCKUP errata is a superset of SDOORBELL errata */ 1206289542Scem if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) 1207289542Scem ntb->features |= NTB_SDOORBELL_LOCKUP; 1208289542Scem 1209289348Scem conn_type = ppd & XEON_PPD_CONN_TYPE; 1210289348Scem switch (conn_type) { 1211289348Scem case NTB_CONN_B2B: 1212289348Scem ntb->conn_type = conn_type; 1213289348Scem break; 1214289348Scem case NTB_CONN_RP: 1215289348Scem case NTB_CONN_TRANSPARENT: 1216289348Scem default: 1217289348Scem device_printf(ntb->device, "Unsupported connection type: %u\n", 1218289348Scem (unsigned)conn_type); 1219289348Scem return (ENXIO); 1220289348Scem } 1221289348Scem return (0); 1222289348Scem} 1223289348Scem 1224289348Scemstatic int 1225289648Scemntb_detect_atom(struct ntb_softc *ntb) 1226289348Scem{ 1227289348Scem uint32_t ppd, conn_type; 1228289348Scem 1229289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1230289348Scem ntb->ppd = ppd; 1231289348Scem 1232289648Scem if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1233289348Scem ntb->dev_type = NTB_DEV_DSD; 1234289348Scem else 1235289348Scem ntb->dev_type = NTB_DEV_USD; 1236289348Scem 1237289648Scem conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1238289348Scem switch (conn_type) { 1239289348Scem case NTB_CONN_B2B: 1240289348Scem ntb->conn_type = conn_type; 1241289348Scem break; 1242289348Scem default: 1243289348Scem device_printf(ntb->device, "Unsupported NTB configuration\n"); 1244289348Scem return (ENXIO); 1245289348Scem } 1246289348Scem return (0); 1247289348Scem} 1248289348Scem 1249289348Scemstatic int 1250289542Scemntb_xeon_init_dev(struct ntb_softc *ntb) 1251289348Scem{ 1252289542Scem int rc; 1253289348Scem 1254289542Scem ntb->spad_count = XEON_SPAD_COUNT; 1255289542Scem ntb->db_count = XEON_DB_COUNT; 1256289542Scem ntb->db_link_mask = XEON_DB_LINK_BIT; 1257289542Scem ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1258289542Scem ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1259289257Scem 1260289542Scem if (ntb->conn_type != NTB_CONN_B2B) { 1261250079Scarl device_printf(ntb->device, "Connection type %d not supported\n", 1262289348Scem ntb->conn_type); 1263250079Scarl return (ENXIO); 1264250079Scarl } 1265250079Scarl 1266289542Scem ntb->reg = &xeon_reg; 1267289607Scem ntb->self_reg = &xeon_pri_reg; 1268289542Scem ntb->peer_reg = &xeon_b2b_reg; 1269289542Scem ntb->xlat_reg = &xeon_sec_xlat; 1270289542Scem 1271289208Scem /* 1272289208Scem * There is a Xeon hardware errata related to writes to SDOORBELL or 1273289208Scem * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1274291263Scem * which may hang the system. To workaround this, use a memory 1275289208Scem * window to access the interrupt and scratch pad registers on the 1276289208Scem * remote system. 1277289208Scem */ 1278291263Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 1279291263Scem ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1280291263Scem ntb->mw_count; 1281291263Scem ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1282291263Scem g_ntb_mw_idx, ntb->b2b_mw_idx); 1283291280Scem rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, VM_MEMATTR_UNCACHEABLE); 1284291263Scem KASSERT(rc == 0, ("shouldn't fail")); 1285291263Scem } else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14)) 1286289208Scem /* 1287289542Scem * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1288289542Scem * mirrored to the remote system. Shrink the number of bits by one, 1289289542Scem * since bit 14 is the last bit. 1290289542Scem * 1291289542Scem * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1292289542Scem * anyway. Nor for non-B2B connection types. 1293289542Scem */ 1294289543Scem ntb->db_count = XEON_DB_COUNT - 1; 1295250079Scarl 1296289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1297250079Scarl 1298289542Scem if (ntb->dev_type == NTB_DEV_USD) 1299289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1300289542Scem &xeon_b2b_usd_addr); 1301289542Scem else 1302289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1303289542Scem &xeon_b2b_dsd_addr); 1304289542Scem if (rc != 0) 1305289542Scem return (rc); 1306289271Scem 1307250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1308290682Scem ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1309289542Scem PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1310255279Scarl 1311290682Scem /* 1312290682Scem * Mask all doorbell interrupts. 1313290682Scem */ 1314290682Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 1315250079Scarl 1316290682Scem rc = ntb_init_isr(ntb); 1317290682Scem return (rc); 1318250079Scarl} 1319250079Scarl 1320250079Scarlstatic int 1321289648Scemntb_atom_init_dev(struct ntb_softc *ntb) 1322250079Scarl{ 1323290682Scem int error; 1324250079Scarl 1325289348Scem KASSERT(ntb->conn_type == NTB_CONN_B2B, 1326289348Scem ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1327250079Scarl 1328289648Scem ntb->spad_count = ATOM_SPAD_COUNT; 1329289648Scem ntb->db_count = ATOM_DB_COUNT; 1330289648Scem ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1331289648Scem ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1332289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1333250079Scarl 1334289648Scem ntb->reg = &atom_reg; 1335289648Scem ntb->self_reg = &atom_pri_reg; 1336289648Scem ntb->peer_reg = &atom_b2b_reg; 1337289648Scem ntb->xlat_reg = &atom_sec_xlat; 1338289542Scem 1339250079Scarl /* 1340289648Scem * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1341250079Scarl * resolved. Mask transaction layer internal parity errors. 1342250079Scarl */ 1343250079Scarl pci_write_config(ntb->device, 0xFC, 0x4, 4); 1344250079Scarl 1345289648Scem configure_atom_secondary_side_bars(ntb); 1346250079Scarl 1347250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1348290682Scem ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1349250079Scarl PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1350289209Scem 1351290682Scem error = ntb_init_isr(ntb); 1352290682Scem if (error != 0) 1353290682Scem return (error); 1354290682Scem 1355289542Scem /* Initiate PCI-E link training */ 1356289546Scem ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1357250079Scarl 1358289648Scem callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1359289542Scem 1360250079Scarl return (0); 1361250079Scarl} 1362250079Scarl 1363289648Scem/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1364255279Scarlstatic void 1365289648Scemconfigure_atom_secondary_side_bars(struct ntb_softc *ntb) 1366255279Scarl{ 1367255279Scarl 1368255279Scarl if (ntb->dev_type == NTB_DEV_USD) { 1369289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1370290725Scem XEON_B2B_BAR2_ADDR64); 1371289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1372290725Scem XEON_B2B_BAR4_ADDR64); 1373290725Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1374290725Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1375255279Scarl } else { 1376289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1377290725Scem XEON_B2B_BAR2_ADDR64); 1378289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1379290725Scem XEON_B2B_BAR4_ADDR64); 1380290725Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1381290725Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1382255279Scarl } 1383255279Scarl} 1384255279Scarl 1385289543Scem 1386289543Scem/* 1387289543Scem * When working around Xeon SDOORBELL errata by remapping remote registers in a 1388289543Scem * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1389289543Scem * remains for use by a higher layer. 1390289543Scem * 1391289543Scem * Will only be used if working around SDOORBELL errata and the BIOS-configured 1392289543Scem * MW size is sufficiently large. 1393289543Scem */ 1394289543Scemstatic unsigned int ntb_b2b_mw_share; 1395289543ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1396289543Scem 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1397289543Scem "MW with higher level consumers. Both sides of the NTB MUST set the same " 1398289543Scem "value here."); 1399289543Scem 1400289543Scemstatic void 1401289543Scemxeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1402289543Scem enum ntb_bar regbar) 1403289543Scem{ 1404289543Scem struct ntb_pci_bar_info *bar; 1405289543Scem uint8_t bar_sz; 1406289543Scem 1407289543Scem if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1408289543Scem return; 1409289543Scem 1410289543Scem bar = &ntb->bar_info[idx]; 1411289543Scem bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1412289543Scem if (idx == regbar) { 1413289543Scem if (ntb->b2b_off != 0) 1414289543Scem bar_sz--; 1415289543Scem else 1416289543Scem bar_sz = 0; 1417289543Scem } 1418289543Scem pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1419289543Scem bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1420289543Scem (void)bar_sz; 1421289543Scem} 1422289543Scem 1423289543Scemstatic void 1424289546Scemxeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1425289543Scem enum ntb_bar idx, enum ntb_bar regbar) 1426289543Scem{ 1427289546Scem uint64_t reg_val; 1428289546Scem uint32_t base_reg, lmt_reg; 1429289543Scem 1430289546Scem bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1431289546Scem if (idx == regbar) 1432289546Scem bar_addr += ntb->b2b_off; 1433289543Scem 1434289546Scem if (!bar_is_64bit(ntb, idx)) { 1435289546Scem ntb_reg_write(4, base_reg, bar_addr); 1436289546Scem reg_val = ntb_reg_read(4, base_reg); 1437289546Scem (void)reg_val; 1438289546Scem 1439289546Scem ntb_reg_write(4, lmt_reg, bar_addr); 1440289546Scem reg_val = ntb_reg_read(4, lmt_reg); 1441289546Scem (void)reg_val; 1442289543Scem } else { 1443289546Scem ntb_reg_write(8, base_reg, bar_addr); 1444289546Scem reg_val = ntb_reg_read(8, base_reg); 1445289546Scem (void)reg_val; 1446289546Scem 1447289546Scem ntb_reg_write(8, lmt_reg, bar_addr); 1448289546Scem reg_val = ntb_reg_read(8, lmt_reg); 1449289546Scem (void)reg_val; 1450289543Scem } 1451289543Scem} 1452289543Scem 1453289543Scemstatic void 1454289543Scemxeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1455289543Scem{ 1456289543Scem struct ntb_pci_bar_info *bar; 1457289543Scem 1458289543Scem bar = &ntb->bar_info[idx]; 1459289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1460289543Scem ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1461289543Scem base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1462289543Scem } else { 1463289543Scem ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1464289543Scem base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1465289543Scem } 1466289543Scem (void)base_addr; 1467289543Scem} 1468289543Scem 1469289542Scemstatic int 1470289542Scemxeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1471289542Scem const struct ntb_b2b_addr *peer_addr) 1472255279Scarl{ 1473289543Scem struct ntb_pci_bar_info *b2b_bar; 1474289543Scem vm_size_t bar_size; 1475289543Scem uint64_t bar_addr; 1476289543Scem enum ntb_bar b2b_bar_num, i; 1477255279Scarl 1478289543Scem if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1479289543Scem b2b_bar = NULL; 1480289543Scem b2b_bar_num = NTB_CONFIG_BAR; 1481289543Scem ntb->b2b_off = 0; 1482289543Scem } else { 1483289543Scem b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1484289543Scem KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1485289543Scem ("invalid b2b mw bar")); 1486289543Scem 1487289543Scem b2b_bar = &ntb->bar_info[b2b_bar_num]; 1488289543Scem bar_size = b2b_bar->size; 1489289543Scem 1490289543Scem if (ntb_b2b_mw_share != 0 && 1491289543Scem (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1492289543Scem ntb->b2b_off = bar_size >> 1; 1493289543Scem else if (bar_size >= XEON_B2B_MIN_SIZE) { 1494289543Scem ntb->b2b_off = 0; 1495289543Scem } else { 1496289543Scem device_printf(ntb->device, 1497289543Scem "B2B bar size is too small!\n"); 1498289543Scem return (EIO); 1499289543Scem } 1500255279Scarl } 1501289542Scem 1502289543Scem /* 1503289543Scem * Reset the secondary bar sizes to match the primary bar sizes. 1504289543Scem * (Except, disable or halve the size of the B2B secondary bar.) 1505289543Scem */ 1506289543Scem for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1507289543Scem xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1508289543Scem 1509289543Scem bar_addr = 0; 1510289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1511289543Scem bar_addr = addr->bar0_addr; 1512289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1513289543Scem bar_addr = addr->bar2_addr64; 1514289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1515289543Scem bar_addr = addr->bar4_addr64; 1516289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1517289543Scem bar_addr = addr->bar4_addr32; 1518289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1519289543Scem bar_addr = addr->bar5_addr32; 1520289543Scem else 1521289543Scem KASSERT(false, ("invalid bar")); 1522289543Scem 1523289543Scem ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1524289543Scem 1525289543Scem /* 1526289543Scem * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1527289543Scem * register BAR. The B2B BAR is either disabled above or configured 1528289543Scem * half-size. It starts at PBAR xlat + offset. 1529289543Scem * 1530289543Scem * Also set up incoming BAR limits == base (zero length window). 1531289543Scem */ 1532289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1533289543Scem b2b_bar_num); 1534289542Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1535289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1536289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1537289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1538289543Scem NTB_B2B_BAR_3, b2b_bar_num); 1539289542Scem } else 1540289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1541289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1542289543Scem 1543289543Scem /* Zero incoming translation addrs */ 1544289543Scem ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1545289543Scem ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1546289543Scem 1547289543Scem /* Zero outgoing translation limits (whole bar size windows) */ 1548289543Scem ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1549289543Scem ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1550289543Scem 1551289543Scem /* Set outgoing translation offsets */ 1552289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1553289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1554289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1555289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1556289543Scem } else 1557289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1558289543Scem 1559289543Scem /* Set the translation offset for B2B registers */ 1560289543Scem bar_addr = 0; 1561289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1562289543Scem bar_addr = peer_addr->bar0_addr; 1563289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1564289543Scem bar_addr = peer_addr->bar2_addr64; 1565289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1566289543Scem bar_addr = peer_addr->bar4_addr64; 1567289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1568289543Scem bar_addr = peer_addr->bar4_addr32; 1569289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1570289543Scem bar_addr = peer_addr->bar5_addr32; 1571289543Scem else 1572289543Scem KASSERT(false, ("invalid bar")); 1573289543Scem 1574289543Scem /* 1575289543Scem * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1576289543Scem * at a time. 1577289543Scem */ 1578289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1579289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1580289542Scem return (0); 1581255279Scarl} 1582255279Scarl 1583289546Scemstatic inline bool 1584289546Scemlink_is_up(struct ntb_softc *ntb) 1585289546Scem{ 1586289546Scem 1587289611Scem if (ntb->type == NTB_XEON) { 1588289611Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1589289611Scem return (true); 1590289546Scem return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1591289611Scem } 1592289546Scem 1593289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1594289648Scem return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1595289546Scem} 1596289546Scem 1597289546Scemstatic inline bool 1598289648Scematom_link_is_err(struct ntb_softc *ntb) 1599289546Scem{ 1600289546Scem uint32_t status; 1601289546Scem 1602289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1603289546Scem 1604289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1605289648Scem if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1606289546Scem return (true); 1607289546Scem 1608289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1609289648Scem return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1610289546Scem} 1611289546Scem 1612289648Scem/* Atom does not have link status interrupt, poll on that platform */ 1613250079Scarlstatic void 1614289648Scematom_link_hb(void *arg) 1615250079Scarl{ 1616250079Scarl struct ntb_softc *ntb = arg; 1617289546Scem sbintime_t timo, poll_ts; 1618250079Scarl 1619289546Scem timo = NTB_HB_TIMEOUT * hz; 1620289546Scem poll_ts = ntb->last_ts + timo; 1621289546Scem 1622289542Scem /* 1623289542Scem * Delay polling the link status if an interrupt was received, unless 1624289542Scem * the cached link status says the link is down. 1625289542Scem */ 1626289546Scem if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1627289546Scem timo = poll_ts - ticks; 1628289542Scem goto out; 1629289546Scem } 1630289542Scem 1631289546Scem if (ntb_poll_link(ntb)) 1632289546Scem ntb_link_event(ntb); 1633289542Scem 1634289648Scem if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1635289546Scem /* Link is down with error, proceed with recovery */ 1636289648Scem callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1637289546Scem return; 1638250079Scarl } 1639250079Scarl 1640289542Scemout: 1641289648Scem callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1642250079Scarl} 1643250079Scarl 1644250079Scarlstatic void 1645289648Scematom_perform_link_restart(struct ntb_softc *ntb) 1646250079Scarl{ 1647250079Scarl uint32_t status; 1648250079Scarl 1649250079Scarl /* Driver resets the NTB ModPhy lanes - magic! */ 1650289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1651289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1652289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1653289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1654250079Scarl 1655250079Scarl /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1656250079Scarl pause("ModPhy", hz / 10); 1657250079Scarl 1658250079Scarl /* Clear AER Errors, write to clear */ 1659289648Scem status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1660250079Scarl status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1661289648Scem ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1662250079Scarl 1663250079Scarl /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1664289648Scem status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1665289648Scem status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1666289648Scem ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1667250079Scarl 1668250079Scarl /* Clear DeSkew Buffer error, write to clear */ 1669289648Scem status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1670289648Scem status |= ATOM_DESKEWSTS_DBERR; 1671289648Scem ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1672250079Scarl 1673289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1674289648Scem status &= ATOM_IBIST_ERR_OFLOW; 1675289648Scem ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1676250079Scarl 1677250079Scarl /* Releases the NTB state machine to allow the link to retrain */ 1678289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1679289648Scem status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1680289648Scem ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1681250079Scarl} 1682250079Scarl 1683289546Scem/* 1684289546Scem * ntb_set_ctx() - associate a driver context with an ntb device 1685289546Scem * @ntb: NTB device context 1686289546Scem * @ctx: Driver context 1687289546Scem * @ctx_ops: Driver context operations 1688289546Scem * 1689289546Scem * Associate a driver context and operations with a ntb device. The context is 1690289546Scem * provided by the client driver, and the driver may associate a different 1691289546Scem * context with each ntb device. 1692289546Scem * 1693289546Scem * Return: Zero if the context is associated, otherwise an error number. 1694289546Scem */ 1695289546Scemint 1696289546Scemntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops) 1697250079Scarl{ 1698250079Scarl 1699289546Scem if (ctx == NULL || ops == NULL) 1700289546Scem return (EINVAL); 1701289546Scem if (ntb->ctx_ops != NULL) 1702289546Scem return (EINVAL); 1703250079Scarl 1704289546Scem CTX_LOCK(ntb); 1705289546Scem if (ntb->ctx_ops != NULL) { 1706289546Scem CTX_UNLOCK(ntb); 1707289546Scem return (EINVAL); 1708250079Scarl } 1709289546Scem ntb->ntb_ctx = ctx; 1710289546Scem ntb->ctx_ops = ops; 1711289546Scem CTX_UNLOCK(ntb); 1712250079Scarl 1713289546Scem return (0); 1714250079Scarl} 1715250079Scarl 1716289546Scem/* 1717289546Scem * It is expected that this will only be used from contexts where the ctx_lock 1718289546Scem * is not needed to protect ntb_ctx lifetime. 1719289546Scem */ 1720289546Scemvoid * 1721289546Scemntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops) 1722289546Scem{ 1723289546Scem 1724289546Scem KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 1725289546Scem if (ops != NULL) 1726289546Scem *ops = ntb->ctx_ops; 1727289546Scem return (ntb->ntb_ctx); 1728289546Scem} 1729289546Scem 1730289546Scem/* 1731289546Scem * ntb_clear_ctx() - disassociate any driver context from an ntb device 1732289546Scem * @ntb: NTB device context 1733289546Scem * 1734289546Scem * Clear any association that may exist between a driver context and the ntb 1735289546Scem * device. 1736289546Scem */ 1737289546Scemvoid 1738289546Scemntb_clear_ctx(struct ntb_softc *ntb) 1739289546Scem{ 1740289546Scem 1741289546Scem CTX_LOCK(ntb); 1742289546Scem ntb->ntb_ctx = NULL; 1743289546Scem ntb->ctx_ops = NULL; 1744289546Scem CTX_UNLOCK(ntb); 1745289546Scem} 1746289546Scem 1747289546Scem/* 1748289546Scem * ntb_link_event() - notify driver context of a change in link status 1749289546Scem * @ntb: NTB device context 1750289546Scem * 1751289546Scem * Notify the driver context that the link status may have changed. The driver 1752289546Scem * should call ntb_link_is_up() to get the current status. 1753289546Scem */ 1754289546Scemvoid 1755289546Scemntb_link_event(struct ntb_softc *ntb) 1756289546Scem{ 1757289546Scem 1758289546Scem CTX_LOCK(ntb); 1759289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 1760289546Scem ntb->ctx_ops->link_event(ntb->ntb_ctx); 1761289546Scem CTX_UNLOCK(ntb); 1762289546Scem} 1763289546Scem 1764289546Scem/* 1765289546Scem * ntb_db_event() - notify driver context of a doorbell event 1766289546Scem * @ntb: NTB device context 1767289546Scem * @vector: Interrupt vector number 1768289546Scem * 1769289546Scem * Notify the driver context of a doorbell event. If hardware supports 1770289546Scem * multiple interrupt vectors for doorbells, the vector number indicates which 1771289546Scem * vector received the interrupt. The vector number is relative to the first 1772289546Scem * vector used for doorbells, starting at zero, and must be less than 1773289546Scem * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 1774289546Scem * doorbell bits need service, and ntb_db_vector_mask() to determine which of 1775289546Scem * those bits are associated with the vector number. 1776289546Scem */ 1777250079Scarlstatic void 1778289546Scemntb_db_event(struct ntb_softc *ntb, uint32_t vec) 1779289272Scem{ 1780289546Scem 1781289546Scem CTX_LOCK(ntb); 1782289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 1783289546Scem ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 1784289546Scem CTX_UNLOCK(ntb); 1785289546Scem} 1786289546Scem 1787289546Scem/* 1788289546Scem * ntb_link_enable() - enable the link on the secondary side of the ntb 1789289546Scem * @ntb: NTB device context 1790289546Scem * @max_speed: The maximum link speed expressed as PCIe generation number[0] 1791289546Scem * @max_width: The maximum link width expressed as the number of PCIe lanes[0] 1792289546Scem * 1793289546Scem * Enable the link on the secondary side of the ntb. This can only be done 1794289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1795289546Scem * should train the link to its maximum speed and width, or the requested speed 1796289546Scem * and width, whichever is smaller, if supported. 1797289546Scem * 1798289546Scem * Return: Zero on success, otherwise an error number. 1799289546Scem * 1800289546Scem * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed 1801289546Scem * and width input will be ignored. 1802289546Scem */ 1803289546Scemint 1804289546Scemntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, 1805289546Scem enum ntb_width w __unused) 1806289546Scem{ 1807289280Scem uint32_t cntl; 1808289272Scem 1809289648Scem if (ntb->type == NTB_ATOM) { 1810289542Scem pci_write_config(ntb->device, NTB_PPD_OFFSET, 1811289648Scem ntb->ppd | ATOM_PPD_INIT_LINK, 4); 1812289546Scem return (0); 1813289542Scem } 1814289542Scem 1815289280Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1816289546Scem ntb_link_event(ntb); 1817289546Scem return (0); 1818289280Scem } 1819289280Scem 1820289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1821289280Scem cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 1822289280Scem cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 1823289397Scem cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 1824289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1825289397Scem cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 1826289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1827289546Scem return (0); 1828289272Scem} 1829289272Scem 1830289546Scem/* 1831289546Scem * ntb_link_disable() - disable the link on the secondary side of the ntb 1832289546Scem * @ntb: NTB device context 1833289546Scem * 1834289546Scem * Disable the link on the secondary side of the ntb. This can only be done 1835289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1836289546Scem * should disable the link. Returning from this call must indicate that a 1837289546Scem * barrier has passed, though with no more writes may pass in either direction 1838289546Scem * across the link, except if this call returns an error number. 1839289546Scem * 1840289546Scem * Return: Zero on success, otherwise an error number. 1841289546Scem */ 1842289546Scemint 1843289542Scemntb_link_disable(struct ntb_softc *ntb) 1844289272Scem{ 1845289272Scem uint32_t cntl; 1846289272Scem 1847289272Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1848289546Scem ntb_link_event(ntb); 1849289546Scem return (0); 1850289272Scem } 1851289272Scem 1852289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1853289280Scem cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 1854289397Scem cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 1855289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1856289397Scem cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 1857289280Scem cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 1858289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1859289546Scem return (0); 1860289272Scem} 1861289272Scem 1862289272Scemstatic void 1863289648Scemrecover_atom_link(void *arg) 1864250079Scarl{ 1865250079Scarl struct ntb_softc *ntb = arg; 1866289608Scem unsigned speed, width, oldspeed, oldwidth; 1867250079Scarl uint32_t status32; 1868250079Scarl 1869289648Scem atom_perform_link_restart(ntb); 1870250079Scarl 1871289232Scem /* 1872289232Scem * There is a potential race between the 2 NTB devices recovering at 1873289232Scem * the same time. If the times are the same, the link will not recover 1874289232Scem * and the driver will be stuck in this loop forever. Add a random 1875289232Scem * interval to the recovery time to prevent this race. 1876289232Scem */ 1877289648Scem status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 1878289648Scem pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 1879289232Scem 1880289648Scem if (atom_link_is_err(ntb)) 1881250079Scarl goto retry; 1882250079Scarl 1883289542Scem status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 1884289648Scem if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 1885289232Scem goto out; 1886289232Scem 1887289542Scem status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 1888289608Scem width = NTB_LNK_STA_WIDTH(status32); 1889289608Scem speed = status32 & NTB_LINK_SPEED_MASK; 1890289608Scem 1891289608Scem oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 1892289608Scem oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 1893289608Scem if (oldwidth != width || oldspeed != speed) 1894250079Scarl goto retry; 1895250079Scarl 1896289232Scemout: 1897289648Scem callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 1898289542Scem ntb); 1899250079Scarl return; 1900250079Scarl 1901250079Scarlretry: 1902289648Scem callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 1903250079Scarl ntb); 1904250079Scarl} 1905250079Scarl 1906289546Scem/* 1907289546Scem * Polls the HW link status register(s); returns true if something has changed. 1908289546Scem */ 1909289546Scemstatic bool 1910289542Scemntb_poll_link(struct ntb_softc *ntb) 1911250079Scarl{ 1912250079Scarl uint32_t ntb_cntl; 1913289546Scem uint16_t reg_val; 1914250079Scarl 1915289648Scem if (ntb->type == NTB_ATOM) { 1916289542Scem ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1917289546Scem if (ntb_cntl == ntb->ntb_ctl) 1918289546Scem return (false); 1919289546Scem 1920289542Scem ntb->ntb_ctl = ntb_cntl; 1921289542Scem ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 1922250079Scarl } else { 1923290678Scem db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 1924250079Scarl 1925289546Scem reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 1926289546Scem if (reg_val == ntb->lnk_sta) 1927289546Scem return (false); 1928250079Scarl 1929289546Scem ntb->lnk_sta = reg_val; 1930289542Scem } 1931289546Scem return (true); 1932289542Scem} 1933289542Scem 1934289546Scemstatic inline enum ntb_speed 1935289546Scemntb_link_sta_speed(struct ntb_softc *ntb) 1936250079Scarl{ 1937250079Scarl 1938289546Scem if (!link_is_up(ntb)) 1939289546Scem return (NTB_SPEED_NONE); 1940289546Scem return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 1941250079Scarl} 1942250079Scarl 1943289546Scemstatic inline enum ntb_width 1944289546Scemntb_link_sta_width(struct ntb_softc *ntb) 1945250079Scarl{ 1946250079Scarl 1947289546Scem if (!link_is_up(ntb)) 1948289546Scem return (NTB_WIDTH_NONE); 1949289546Scem return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 1950250079Scarl} 1951250079Scarl 1952289774ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 1953289774Scem "Driver state, statistics, and HW registers"); 1954289774Scem 1955289774Scem#define NTB_REGSZ_MASK (3ul << 30) 1956289774Scem#define NTB_REG_64 (1ul << 30) 1957289774Scem#define NTB_REG_32 (2ul << 30) 1958289774Scem#define NTB_REG_16 (3ul << 30) 1959289774Scem#define NTB_REG_8 (0ul << 30) 1960289774Scem 1961289774Scem#define NTB_DB_READ (1ul << 29) 1962289774Scem#define NTB_PCI_REG (1ul << 28) 1963289774Scem#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 1964289774Scem 1965289774Scemstatic void 1966289774Scemntb_sysctl_init(struct ntb_softc *ntb) 1967289774Scem{ 1968289774Scem struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; 1969289774Scem struct sysctl_ctx_list *ctx; 1970289774Scem struct sysctl_oid *tree, *tmptree; 1971289774Scem 1972289774Scem ctx = device_get_sysctl_ctx(ntb->device); 1973289774Scem 1974289774Scem tree = SYSCTL_ADD_NODE(ctx, 1975289774Scem SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, 1976289774Scem "debug_info", CTLFLAG_RD, NULL, 1977289774Scem "Driver state, statistics, and HW registers"); 1978289774Scem tree_par = SYSCTL_CHILDREN(tree); 1979289774Scem 1980289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 1981289774Scem &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 1982289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 1983289774Scem &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 1984290687Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 1985290687Scem &ntb->ppd, 0, "Raw PPD register (cached)"); 1986289774Scem 1987289774Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 1988289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 1989289774Scem &ntb->b2b_mw_idx, 0, 1990289774Scem "Index of the MW used for B2B remote register access"); 1991289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 1992289774Scem CTLFLAG_RD, &ntb->b2b_off, 1993289774Scem "If non-zero, offset of B2B register region in shared MW"); 1994289774Scem } 1995289774Scem 1996289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 1997289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 1998289774Scem "Features/errata of this NTB device"); 1999289774Scem 2000289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2001290686Scem __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2002290686Scem "NTB CTL register (cached)"); 2003289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2004290686Scem __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2005290686Scem "LNK STA register (cached)"); 2006289774Scem 2007289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", 2008289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, 2009289774Scem "A", "Link status"); 2010289774Scem 2011289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2012291263Scem &ntb->mw_count, 0, "MW count"); 2013289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2014289774Scem &ntb->spad_count, 0, "Scratchpad count"); 2015289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2016289774Scem &ntb->db_count, 0, "Doorbell count"); 2017289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2018289774Scem &ntb->db_vec_count, 0, "Doorbell vector count"); 2019289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2020289774Scem &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2021289774Scem 2022289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2023289774Scem &ntb->db_valid_mask, "Doorbell valid mask"); 2024289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2025289774Scem &ntb->db_link_mask, "Doorbell link mask"); 2026289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2027289774Scem &ntb->db_mask, "Doorbell mask (cached)"); 2028289774Scem 2029289774Scem tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2030289774Scem CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 2031289774Scem regpar = SYSCTL_CHILDREN(tmptree); 2032289774Scem 2033290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2034290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2035290682Scem ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2036290682Scem "NTB Control register"); 2037290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2038290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2039290682Scem 0x19c, sysctl_handle_register, "IU", 2040290682Scem "NTB Link Capabilities"); 2041290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2042290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2043290682Scem 0x1a0, sysctl_handle_register, "IU", 2044290682Scem "NTB Link Control register"); 2045290682Scem 2046289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2047289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2048289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2049289774Scem sysctl_handle_register, "QU", "Doorbell mask register"); 2050289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2051289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2052289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2053289774Scem sysctl_handle_register, "QU", "Doorbell register"); 2054289774Scem 2055289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2056289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2057289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2058289774Scem sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2059289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2060289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2061289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2062289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2063289774Scem sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2064289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2065289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2066289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2067289774Scem sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2068289774Scem } else { 2069289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2070289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2071289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2072289774Scem sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2073289774Scem } 2074289774Scem 2075289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2076289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2077289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2078289774Scem sysctl_handle_register, "QU", "Incoming LMT23 register"); 2079289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2080289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2081289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2082289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2083289774Scem sysctl_handle_register, "IU", "Incoming LMT4 register"); 2084289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2085289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2086289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2087289774Scem sysctl_handle_register, "IU", "Incoming LMT5 register"); 2088289774Scem } else { 2089289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2090289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2091289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2092289774Scem sysctl_handle_register, "QU", "Incoming LMT45 register"); 2093289774Scem } 2094289774Scem 2095289774Scem if (ntb->type == NTB_ATOM) 2096289774Scem return; 2097289774Scem 2098289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2099289774Scem CTLFLAG_RD, NULL, "Xeon HW statistics"); 2100289774Scem statpar = SYSCTL_CHILDREN(tmptree); 2101289774Scem SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2102289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2103289774Scem NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2104289774Scem sysctl_handle_register, "SU", "Upstream Memory Miss"); 2105289774Scem 2106289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2107289774Scem CTLFLAG_RD, NULL, "Xeon HW errors"); 2108289774Scem errpar = SYSCTL_CHILDREN(tmptree); 2109289774Scem 2110290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2111289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2112290687Scem NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2113290687Scem sysctl_handle_register, "CU", "PPD"); 2114290687Scem 2115290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2116290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2117290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2118290687Scem sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2119290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2120290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2121290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2122290687Scem sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2123290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2124290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2125290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2126290687Scem sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2127290687Scem 2128290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2129290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2130290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2131290687Scem sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2132290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2133290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2134290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2135290687Scem sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2136290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2137290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2138290687Scem NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2139290687Scem sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2140290687Scem 2141290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2142290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2143289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2144289774Scem sysctl_handle_register, "SU", "DEVSTS"); 2145290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2146289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2147289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2148289774Scem sysctl_handle_register, "SU", "LNKSTS"); 2149290687Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2150290687Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2151290687Scem NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2152290687Scem sysctl_handle_register, "SU", "SLNKSTS"); 2153290687Scem 2154289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2155289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2156289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2157289774Scem sysctl_handle_register, "IU", "UNCERRSTS"); 2158289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2159289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2160289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2161289774Scem sysctl_handle_register, "IU", "CORERRSTS"); 2162289774Scem 2163289774Scem if (ntb->conn_type != NTB_CONN_B2B) 2164289774Scem return; 2165289774Scem 2166289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2167289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2168289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2169289774Scem sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2170289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2171289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2172289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2173289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2174289774Scem sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2175289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2176289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2177289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2178289774Scem sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2179289774Scem } else { 2180289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2181289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2182289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2183289774Scem sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2184289774Scem } 2185289774Scem 2186289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2187289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2188289774Scem NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2189289774Scem sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2190289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2191289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2192289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2193289774Scem NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2194289774Scem sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2195289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2196289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2197289774Scem NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2198289774Scem sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2199289774Scem } else { 2200289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2201289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2202289774Scem NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2203289774Scem sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2204289774Scem } 2205289774Scem 2206289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2207289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2208289774Scem NTB_REG_64 | ntb->xlat_reg->bar0_base, 2209289774Scem sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2210289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2211289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2212289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_base, 2213289774Scem sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2214289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2215289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2216289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2217289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_base, 2218289774Scem sysctl_handle_register, "IU", 2219289774Scem "Secondary BAR4 base register"); 2220289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2221289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2222289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_base, 2223289774Scem sysctl_handle_register, "IU", 2224289774Scem "Secondary BAR5 base register"); 2225289774Scem } else { 2226289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2227289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2228289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_base, 2229289774Scem sysctl_handle_register, "QU", 2230289774Scem "Secondary BAR45 base register"); 2231289774Scem } 2232289774Scem} 2233289774Scem 2234289774Scemstatic int 2235289774Scemsysctl_handle_features(SYSCTL_HANDLER_ARGS) 2236289774Scem{ 2237289774Scem struct ntb_softc *ntb; 2238289774Scem struct sbuf sb; 2239289774Scem int error; 2240289774Scem 2241289774Scem error = 0; 2242289774Scem ntb = arg1; 2243289774Scem 2244289774Scem sbuf_new_for_sysctl(&sb, NULL, 256, req); 2245289774Scem 2246289774Scem sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2247289774Scem error = sbuf_finish(&sb); 2248289774Scem sbuf_delete(&sb); 2249289774Scem 2250289774Scem if (error || !req->newptr) 2251289774Scem return (error); 2252289774Scem return (EINVAL); 2253289774Scem} 2254289774Scem 2255289774Scemstatic int 2256289774Scemsysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2257289774Scem{ 2258289774Scem struct ntb_softc *ntb; 2259289774Scem struct sbuf sb; 2260289774Scem enum ntb_speed speed; 2261289774Scem enum ntb_width width; 2262289774Scem int error; 2263289774Scem 2264289774Scem error = 0; 2265289774Scem ntb = arg1; 2266289774Scem 2267289774Scem sbuf_new_for_sysctl(&sb, NULL, 32, req); 2268289774Scem 2269289774Scem if (ntb_link_is_up(ntb, &speed, &width)) 2270289774Scem sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2271289774Scem (unsigned)speed, (unsigned)width); 2272289774Scem else 2273289774Scem sbuf_printf(&sb, "down"); 2274289774Scem 2275289774Scem error = sbuf_finish(&sb); 2276289774Scem sbuf_delete(&sb); 2277289774Scem 2278289774Scem if (error || !req->newptr) 2279289774Scem return (error); 2280289774Scem return (EINVAL); 2281289774Scem} 2282289774Scem 2283289774Scemstatic int 2284289774Scemsysctl_handle_register(SYSCTL_HANDLER_ARGS) 2285289774Scem{ 2286289774Scem struct ntb_softc *ntb; 2287289774Scem const void *outp; 2288289774Scem uintptr_t sz; 2289289774Scem uint64_t umv; 2290289774Scem char be[sizeof(umv)]; 2291289774Scem size_t outsz; 2292289774Scem uint32_t reg; 2293289774Scem bool db, pci; 2294289774Scem int error; 2295289774Scem 2296289774Scem ntb = arg1; 2297289774Scem reg = arg2 & ~NTB_REGFLAGS_MASK; 2298289774Scem sz = arg2 & NTB_REGSZ_MASK; 2299289774Scem db = (arg2 & NTB_DB_READ) != 0; 2300289774Scem pci = (arg2 & NTB_PCI_REG) != 0; 2301289774Scem 2302289774Scem KASSERT(!(db && pci), ("bogus")); 2303289774Scem 2304289774Scem if (db) { 2305289774Scem KASSERT(sz == NTB_REG_64, ("bogus")); 2306289774Scem umv = db_ioread(ntb, reg); 2307289774Scem outsz = sizeof(uint64_t); 2308289774Scem } else { 2309289774Scem switch (sz) { 2310289774Scem case NTB_REG_64: 2311289774Scem if (pci) 2312289774Scem umv = pci_read_config(ntb->device, reg, 8); 2313289774Scem else 2314289774Scem umv = ntb_reg_read(8, reg); 2315289774Scem outsz = sizeof(uint64_t); 2316289774Scem break; 2317289774Scem case NTB_REG_32: 2318289774Scem if (pci) 2319289774Scem umv = pci_read_config(ntb->device, reg, 4); 2320289774Scem else 2321289774Scem umv = ntb_reg_read(4, reg); 2322289774Scem outsz = sizeof(uint32_t); 2323289774Scem break; 2324289774Scem case NTB_REG_16: 2325289774Scem if (pci) 2326289774Scem umv = pci_read_config(ntb->device, reg, 2); 2327289774Scem else 2328289774Scem umv = ntb_reg_read(2, reg); 2329289774Scem outsz = sizeof(uint16_t); 2330289774Scem break; 2331289774Scem case NTB_REG_8: 2332289774Scem if (pci) 2333289774Scem umv = pci_read_config(ntb->device, reg, 1); 2334289774Scem else 2335289774Scem umv = ntb_reg_read(1, reg); 2336289774Scem outsz = sizeof(uint8_t); 2337289774Scem break; 2338289774Scem default: 2339289774Scem panic("bogus"); 2340289774Scem break; 2341289774Scem } 2342289774Scem } 2343289774Scem 2344289774Scem /* Encode bigendian so that sysctl -x is legible. */ 2345289774Scem be64enc(be, umv); 2346289774Scem outp = ((char *)be) + sizeof(umv) - outsz; 2347289774Scem 2348289774Scem error = SYSCTL_OUT(req, outp, outsz); 2349289774Scem if (error || !req->newptr) 2350289774Scem return (error); 2351289774Scem return (EINVAL); 2352289774Scem} 2353289774Scem 2354291263Scemstatic unsigned 2355291263Scemntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2356291263Scem{ 2357291263Scem 2358291263Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2359291263Scem uidx >= ntb->b2b_mw_idx) 2360291263Scem return (uidx + 1); 2361291263Scem return (uidx); 2362291263Scem} 2363291263Scem 2364289546Scem/* 2365289546Scem * Public API to the rest of the OS 2366250079Scarl */ 2367250079Scarl 2368250079Scarl/** 2369250079Scarl * ntb_get_max_spads() - get the total scratch regs usable 2370250079Scarl * @ntb: pointer to ntb_softc instance 2371250079Scarl * 2372250079Scarl * This function returns the max 32bit scratchpad registers usable by the 2373250079Scarl * upper layer. 2374250079Scarl * 2375250079Scarl * RETURNS: total number of scratch pad registers available 2376250079Scarl */ 2377289208Scemuint8_t 2378250079Scarlntb_get_max_spads(struct ntb_softc *ntb) 2379250079Scarl{ 2380250079Scarl 2381289539Scem return (ntb->spad_count); 2382250079Scarl} 2383250079Scarl 2384291263Scem/* 2385291263Scem * ntb_mw_count() - Get the number of memory windows available for KPI 2386291263Scem * consumers. 2387291263Scem * 2388291263Scem * (Excludes any MW wholly reserved for register access.) 2389291263Scem */ 2390289396Scemuint8_t 2391289539Scemntb_mw_count(struct ntb_softc *ntb) 2392289396Scem{ 2393289396Scem 2394291263Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 2395291263Scem return (ntb->mw_count - 1); 2396289539Scem return (ntb->mw_count); 2397289396Scem} 2398289396Scem 2399250079Scarl/** 2400289545Scem * ntb_spad_write() - write to the secondary scratchpad register 2401250079Scarl * @ntb: pointer to ntb_softc instance 2402250079Scarl * @idx: index to the scratchpad register, 0 based 2403250079Scarl * @val: the data value to put into the register 2404250079Scarl * 2405250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2406250079Scarl * register. The register resides on the secondary (external) side. 2407250079Scarl * 2408289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2409250079Scarl */ 2410250079Scarlint 2411289545Scemntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2412250079Scarl{ 2413250079Scarl 2414289539Scem if (idx >= ntb->spad_count) 2415250079Scarl return (EINVAL); 2416250079Scarl 2417289607Scem ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2418250079Scarl 2419250079Scarl return (0); 2420250079Scarl} 2421250079Scarl 2422250079Scarl/** 2423289545Scem * ntb_spad_read() - read from the primary scratchpad register 2424250079Scarl * @ntb: pointer to ntb_softc instance 2425250079Scarl * @idx: index to scratchpad register, 0 based 2426250079Scarl * @val: pointer to 32bit integer for storing the register value 2427250079Scarl * 2428250079Scarl * This function allows reading of the 32bit scratchpad register on 2429250079Scarl * the primary (internal) side. 2430250079Scarl * 2431289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2432250079Scarl */ 2433250079Scarlint 2434289545Scemntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2435250079Scarl{ 2436250079Scarl 2437289539Scem if (idx >= ntb->spad_count) 2438250079Scarl return (EINVAL); 2439250079Scarl 2440289607Scem *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2441250079Scarl 2442250079Scarl return (0); 2443250079Scarl} 2444250079Scarl 2445250079Scarl/** 2446289545Scem * ntb_peer_spad_write() - write to the secondary scratchpad register 2447250079Scarl * @ntb: pointer to ntb_softc instance 2448250079Scarl * @idx: index to the scratchpad register, 0 based 2449250079Scarl * @val: the data value to put into the register 2450250079Scarl * 2451250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2452250079Scarl * register. The register resides on the secondary (external) side. 2453250079Scarl * 2454289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2455250079Scarl */ 2456250079Scarlint 2457289545Scemntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2458250079Scarl{ 2459250079Scarl 2460289539Scem if (idx >= ntb->spad_count) 2461250079Scarl return (EINVAL); 2462250079Scarl 2463289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2464290682Scem ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2465255279Scarl else 2466289542Scem ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2467250079Scarl 2468250079Scarl return (0); 2469250079Scarl} 2470250079Scarl 2471250079Scarl/** 2472289545Scem * ntb_peer_spad_read() - read from the primary scratchpad register 2473250079Scarl * @ntb: pointer to ntb_softc instance 2474250079Scarl * @idx: index to scratchpad register, 0 based 2475250079Scarl * @val: pointer to 32bit integer for storing the register value 2476250079Scarl * 2477250079Scarl * This function allows reading of the 32bit scratchpad register on 2478250079Scarl * the primary (internal) side. 2479250079Scarl * 2480289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2481250079Scarl */ 2482250079Scarlint 2483289545Scemntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2484250079Scarl{ 2485250079Scarl 2486289539Scem if (idx >= ntb->spad_count) 2487250079Scarl return (EINVAL); 2488250079Scarl 2489289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2490290682Scem *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2491255279Scarl else 2492289542Scem *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2493250079Scarl 2494250079Scarl return (0); 2495250079Scarl} 2496250079Scarl 2497289546Scem/* 2498289546Scem * ntb_mw_get_range() - get the range of a memory window 2499289546Scem * @ntb: NTB device context 2500289546Scem * @idx: Memory window number 2501289546Scem * @base: OUT - the base address for mapping the memory window 2502289546Scem * @size: OUT - the size for mapping the memory window 2503289546Scem * @align: OUT - the base alignment for translating the memory window 2504289546Scem * @align_size: OUT - the size alignment for translating the memory window 2505250079Scarl * 2506289546Scem * Get the range of a memory window. NULL may be given for any output 2507289546Scem * parameter if the value is not needed. The base and size may be used for 2508289546Scem * mapping the memory window, to access the peer memory. The alignment and 2509289546Scem * size may be used for translating the memory window, for the peer to access 2510289546Scem * memory on the local system. 2511250079Scarl * 2512289546Scem * Return: Zero on success, otherwise an error number. 2513250079Scarl */ 2514289546Scemint 2515289546Scemntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base, 2516291033Scem caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 2517291033Scem bus_addr_t *plimit) 2518250079Scarl{ 2519289546Scem struct ntb_pci_bar_info *bar; 2520291033Scem bus_addr_t limit; 2521289546Scem size_t bar_b2b_off; 2522291033Scem enum ntb_bar bar_num; 2523250079Scarl 2524289546Scem if (mw_idx >= ntb_mw_count(ntb)) 2525289546Scem return (EINVAL); 2526291263Scem mw_idx = ntb_user_mw_to_idx(ntb, mw_idx); 2527250079Scarl 2528291033Scem bar_num = ntb_mw_to_bar(ntb, mw_idx); 2529291033Scem bar = &ntb->bar_info[bar_num]; 2530289546Scem bar_b2b_off = 0; 2531289546Scem if (mw_idx == ntb->b2b_mw_idx) { 2532289546Scem KASSERT(ntb->b2b_off != 0, 2533289546Scem ("user shouldn't get non-shared b2b mw")); 2534289546Scem bar_b2b_off = ntb->b2b_off; 2535289546Scem } 2536250079Scarl 2537291033Scem if (bar_is_64bit(ntb, bar_num)) 2538291033Scem limit = BUS_SPACE_MAXADDR; 2539291033Scem else 2540291033Scem limit = BUS_SPACE_MAXADDR_32BIT; 2541291033Scem 2542289546Scem if (base != NULL) 2543289546Scem *base = bar->pbase + bar_b2b_off; 2544289546Scem if (vbase != NULL) 2545290679Scem *vbase = bar->vbase + bar_b2b_off; 2546289546Scem if (size != NULL) 2547289546Scem *size = bar->size - bar_b2b_off; 2548289546Scem if (align != NULL) 2549289546Scem *align = bar->size; 2550289546Scem if (align_size != NULL) 2551289546Scem *align_size = 1; 2552291033Scem if (plimit != NULL) 2553291033Scem *plimit = limit; 2554289546Scem return (0); 2555250079Scarl} 2556250079Scarl 2557289546Scem/* 2558289546Scem * ntb_mw_set_trans() - set the translation of a memory window 2559289546Scem * @ntb: NTB device context 2560289546Scem * @idx: Memory window number 2561289546Scem * @addr: The dma address local memory to expose to the peer 2562289546Scem * @size: The size of the local memory to expose to the peer 2563250079Scarl * 2564289546Scem * Set the translation of a memory window. The peer may access local memory 2565289546Scem * through the window starting at the address, up to the size. The address 2566289546Scem * must be aligned to the alignment specified by ntb_mw_get_range(). The size 2567291033Scem * must be aligned to the size alignment specified by ntb_mw_get_range(). The 2568291033Scem * address must be below the plimit specified by ntb_mw_get_range() (i.e. for 2569291033Scem * 32-bit BARs). 2570250079Scarl * 2571289546Scem * Return: Zero on success, otherwise an error number. 2572250079Scarl */ 2573289546Scemint 2574289546Scemntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr, 2575289546Scem size_t size) 2576250079Scarl{ 2577289546Scem struct ntb_pci_bar_info *bar; 2578289546Scem uint64_t base, limit, reg_val; 2579289546Scem size_t bar_size, mw_size; 2580289546Scem uint32_t base_reg, xlat_reg, limit_reg; 2581289546Scem enum ntb_bar bar_num; 2582250079Scarl 2583289546Scem if (idx >= ntb_mw_count(ntb)) 2584289546Scem return (EINVAL); 2585291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2586250079Scarl 2587289546Scem bar_num = ntb_mw_to_bar(ntb, idx); 2588289546Scem bar = &ntb->bar_info[bar_num]; 2589250079Scarl 2590289546Scem bar_size = bar->size; 2591289546Scem if (idx == ntb->b2b_mw_idx) 2592289546Scem mw_size = bar_size - ntb->b2b_off; 2593289546Scem else 2594289546Scem mw_size = bar_size; 2595250079Scarl 2596289546Scem /* Hardware requires that addr is aligned to bar size */ 2597289546Scem if ((addr & (bar_size - 1)) != 0) 2598289546Scem return (EINVAL); 2599250079Scarl 2600289546Scem if (size > mw_size) 2601289546Scem return (EINVAL); 2602289546Scem 2603289546Scem bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2604289546Scem 2605289546Scem limit = 0; 2606289546Scem if (bar_is_64bit(ntb, bar_num)) { 2607291032Scem base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 2608289546Scem 2609289546Scem if (limit_reg != 0 && size != mw_size) 2610289546Scem limit = base + size; 2611289546Scem 2612289546Scem /* Set and verify translation address */ 2613289546Scem ntb_reg_write(8, xlat_reg, addr); 2614291032Scem reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 2615289546Scem if (reg_val != addr) { 2616289546Scem ntb_reg_write(8, xlat_reg, 0); 2617289546Scem return (EIO); 2618289546Scem } 2619289546Scem 2620289546Scem /* Set and verify the limit */ 2621289546Scem ntb_reg_write(8, limit_reg, limit); 2622291032Scem reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 2623289546Scem if (reg_val != limit) { 2624289546Scem ntb_reg_write(8, limit_reg, base); 2625289546Scem ntb_reg_write(8, xlat_reg, 0); 2626289546Scem return (EIO); 2627289546Scem } 2628289546Scem } else { 2629289546Scem /* Configure 32-bit (split) BAR MW */ 2630289546Scem 2631291029Scem if ((addr & UINT32_MAX) != addr) 2632291033Scem return (ERANGE); 2633291029Scem if (((addr + size) & UINT32_MAX) != (addr + size)) 2634291033Scem return (ERANGE); 2635289546Scem 2636291032Scem base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 2637289546Scem 2638289546Scem if (limit_reg != 0 && size != mw_size) 2639289546Scem limit = base + size; 2640289546Scem 2641289546Scem /* Set and verify translation address */ 2642289546Scem ntb_reg_write(4, xlat_reg, addr); 2643291032Scem reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 2644289546Scem if (reg_val != addr) { 2645289546Scem ntb_reg_write(4, xlat_reg, 0); 2646289546Scem return (EIO); 2647289546Scem } 2648289546Scem 2649289546Scem /* Set and verify the limit */ 2650289546Scem ntb_reg_write(4, limit_reg, limit); 2651291032Scem reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 2652289546Scem if (reg_val != limit) { 2653289546Scem ntb_reg_write(4, limit_reg, base); 2654289546Scem ntb_reg_write(4, xlat_reg, 0); 2655289546Scem return (EIO); 2656289546Scem } 2657250079Scarl } 2658289546Scem return (0); 2659250079Scarl} 2660250079Scarl 2661289596Scem/* 2662289596Scem * ntb_mw_clear_trans() - clear the translation of a memory window 2663289596Scem * @ntb: NTB device context 2664289596Scem * @idx: Memory window number 2665289596Scem * 2666289596Scem * Clear the translation of a memory window. The peer may no longer access 2667289596Scem * local memory through the window. 2668289596Scem * 2669289596Scem * Return: Zero on success, otherwise an error number. 2670289596Scem */ 2671289596Scemint 2672289596Scemntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx) 2673289596Scem{ 2674289596Scem 2675289596Scem return (ntb_mw_set_trans(ntb, mw_idx, 0, 0)); 2676289596Scem} 2677289596Scem 2678291031Scem/* 2679291031Scem * ntb_mw_get_wc - Get the write-combine status of a memory window 2680291031Scem * 2681291031Scem * Returns: Zero on success, setting *wc; otherwise an error number (e.g. if 2682291031Scem * idx is an invalid memory window). 2683291280Scem * 2684291280Scem * Mode is a VM_MEMATTR_* type. 2685291031Scem */ 2686291031Scemint 2687291280Scemntb_mw_get_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t *mode) 2688291031Scem{ 2689291031Scem struct ntb_pci_bar_info *bar; 2690291031Scem 2691291031Scem if (idx >= ntb_mw_count(ntb)) 2692291031Scem return (EINVAL); 2693291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2694291031Scem 2695291031Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 2696291280Scem *mode = bar->map_mode; 2697291031Scem return (0); 2698291031Scem} 2699291031Scem 2700291031Scem/* 2701291031Scem * ntb_mw_set_wc - Set the write-combine status of a memory window 2702291031Scem * 2703291280Scem * If 'mode' matches the current status, this does nothing and succeeds. Mode 2704291280Scem * is a VM_MEMATTR_* type. 2705291031Scem * 2706291031Scem * Returns: Zero on success, setting the caching attribute on the virtual 2707291031Scem * mapping of the BAR; otherwise an error number (e.g. if idx is an invalid 2708291031Scem * memory window, or if changing the caching attribute fails). 2709291031Scem */ 2710291031Scemint 2711291280Scemntb_mw_set_wc(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 2712291031Scem{ 2713291263Scem 2714291263Scem if (idx >= ntb_mw_count(ntb)) 2715291263Scem return (EINVAL); 2716291263Scem 2717291263Scem idx = ntb_user_mw_to_idx(ntb, idx); 2718291280Scem return (ntb_mw_set_wc_internal(ntb, idx, mode)); 2719291263Scem} 2720291263Scem 2721291263Scemstatic int 2722291280Scemntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 2723291263Scem{ 2724291031Scem struct ntb_pci_bar_info *bar; 2725291031Scem int rc; 2726291031Scem 2727291031Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 2728291280Scem if (bar->map_mode == mode) 2729291031Scem return (0); 2730291031Scem 2731291280Scem if (mode != VM_MEMATTR_UNCACHEABLE && mode != VM_MEMATTR_DEFAULT && 2732291280Scem mode != VM_MEMATTR_WRITE_COMBINING) 2733291280Scem return (EINVAL); 2734291031Scem 2735291280Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 2736291031Scem if (rc == 0) 2737291280Scem bar->map_mode = mode; 2738291031Scem 2739291031Scem return (rc); 2740291031Scem} 2741291031Scem 2742250079Scarl/** 2743289545Scem * ntb_peer_db_set() - Set the doorbell on the secondary/external side 2744250079Scarl * @ntb: pointer to ntb_softc instance 2745289545Scem * @bit: doorbell bits to ring 2746250079Scarl * 2747250079Scarl * This function allows triggering of a doorbell on the secondary/external 2748250079Scarl * side that will initiate an interrupt on the remote host 2749250079Scarl */ 2750250079Scarlvoid 2751289545Scemntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit) 2752250079Scarl{ 2753250079Scarl 2754289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2755290682Scem ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 2756289347Scem return; 2757289209Scem } 2758289347Scem 2759289546Scem db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 2760250079Scarl} 2761250079Scarl 2762289542Scem/* 2763289542Scem * ntb_get_peer_db_addr() - Return the address of the remote doorbell register, 2764289542Scem * as well as the size of the register (via *sz_out). 2765289542Scem * 2766289542Scem * This function allows a caller using I/OAT DMA to chain the remote doorbell 2767289542Scem * ring to its memory window write. 2768289542Scem * 2769289542Scem * Note that writing the peer doorbell via a memory window will *not* generate 2770289542Scem * an interrupt on the remote host; that must be done seperately. 2771289542Scem */ 2772289542Scembus_addr_t 2773289542Scemntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out) 2774289542Scem{ 2775289542Scem struct ntb_pci_bar_info *bar; 2776289542Scem uint64_t regoff; 2777289542Scem 2778289542Scem KASSERT(sz_out != NULL, ("must be non-NULL")); 2779289542Scem 2780289542Scem if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2781289542Scem bar = &ntb->bar_info[NTB_CONFIG_BAR]; 2782289542Scem regoff = ntb->peer_reg->db_bell; 2783289542Scem } else { 2784289543Scem KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 2785289543Scem ("invalid b2b idx")); 2786289542Scem 2787289542Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 2788290682Scem regoff = XEON_PDOORBELL_OFFSET; 2789289542Scem } 2790289542Scem KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 2791289542Scem 2792289542Scem *sz_out = ntb->reg->db_size; 2793289542Scem /* HACK: Specific to current x86 bus implementation. */ 2794289542Scem return ((uint64_t)bar->pci_bus_handle + regoff); 2795289542Scem} 2796289542Scem 2797289597Scem/* 2798289597Scem * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb 2799289597Scem * @ntb: NTB device context 2800289597Scem * 2801289597Scem * Hardware may support different number or arrangement of doorbell bits. 2802289597Scem * 2803289597Scem * Return: A mask of doorbell bits supported by the ntb. 2804289597Scem */ 2805289597Scemuint64_t 2806289597Scemntb_db_valid_mask(struct ntb_softc *ntb) 2807289597Scem{ 2808289597Scem 2809289597Scem return (ntb->db_valid_mask); 2810289597Scem} 2811289597Scem 2812289598Scem/* 2813289598Scem * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector 2814289598Scem * @ntb: NTB device context 2815289598Scem * @vector: Doorbell vector number 2816289598Scem * 2817289598Scem * Each interrupt vector may have a different number or arrangement of bits. 2818289598Scem * 2819289598Scem * Return: A mask of doorbell bits serviced by a vector. 2820289598Scem */ 2821289598Scemuint64_t 2822289598Scemntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector) 2823289598Scem{ 2824289598Scem 2825289598Scem if (vector > ntb->db_vec_count) 2826289598Scem return (0); 2827289598Scem return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 2828289598Scem} 2829289598Scem 2830250079Scarl/** 2831289546Scem * ntb_link_is_up() - get the current ntb link state 2832289546Scem * @ntb: NTB device context 2833289546Scem * @speed: OUT - The link speed expressed as PCIe generation number 2834289546Scem * @width: OUT - The link width expressed as the number of PCIe lanes 2835250079Scarl * 2836250079Scarl * RETURNS: true or false based on the hardware link state 2837250079Scarl */ 2838250079Scarlbool 2839289546Scemntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed, 2840289546Scem enum ntb_width *width) 2841250079Scarl{ 2842250079Scarl 2843289546Scem if (speed != NULL) 2844289546Scem *speed = ntb_link_sta_speed(ntb); 2845289546Scem if (width != NULL) 2846289546Scem *width = ntb_link_sta_width(ntb); 2847289546Scem return (link_is_up(ntb)); 2848250079Scarl} 2849250079Scarl 2850255272Scarlstatic void 2851255272Scarlsave_bar_parameters(struct ntb_pci_bar_info *bar) 2852250079Scarl{ 2853255272Scarl 2854289209Scem bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 2855289209Scem bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 2856289209Scem bar->pbase = rman_get_start(bar->pci_resource); 2857289209Scem bar->size = rman_get_size(bar->pci_resource); 2858289209Scem bar->vbase = rman_get_virtual(bar->pci_resource); 2859250079Scarl} 2860255268Scarl 2861289209Scemdevice_t 2862289209Scemntb_get_device(struct ntb_softc *ntb) 2863255268Scarl{ 2864255268Scarl 2865255268Scarl return (ntb->device); 2866255268Scarl} 2867289208Scem 2868289208Scem/* Export HW-specific errata information. */ 2869289208Scembool 2870289774Scemntb_has_feature(struct ntb_softc *ntb, uint32_t feature) 2871289208Scem{ 2872289208Scem 2873289208Scem return (HAS_FEATURE(feature)); 2874289208Scem} 2875