ntb_hw_intel.c revision 290685
1250079Scarl/*- 2250079Scarl * Copyright (C) 2013 Intel Corporation 3289542Scem * Copyright (C) 2015 EMC Corporation 4250079Scarl * All rights reserved. 5250079Scarl * 6250079Scarl * Redistribution and use in source and binary forms, with or without 7250079Scarl * modification, are permitted provided that the following conditions 8250079Scarl * are met: 9250079Scarl * 1. Redistributions of source code must retain the above copyright 10250079Scarl * notice, this list of conditions and the following disclaimer. 11250079Scarl * 2. Redistributions in binary form must reproduce the above copyright 12250079Scarl * notice, this list of conditions and the following disclaimer in the 13250079Scarl * documentation and/or other materials provided with the distribution. 14250079Scarl * 15250079Scarl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16250079Scarl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250079Scarl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250079Scarl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19250079Scarl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20250079Scarl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21250079Scarl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22250079Scarl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23250079Scarl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24250079Scarl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25250079Scarl * SUCH DAMAGE. 26250079Scarl */ 27250079Scarl 28250079Scarl#include <sys/cdefs.h> 29250079Scarl__FBSDID("$FreeBSD: head/sys/dev/ntb/ntb_hw/ntb_hw.c 290685 2015-11-11 18:55:53Z cem $"); 30250079Scarl 31250079Scarl#include <sys/param.h> 32250079Scarl#include <sys/kernel.h> 33250079Scarl#include <sys/systm.h> 34250079Scarl#include <sys/bus.h> 35289774Scem#include <sys/endian.h> 36250079Scarl#include <sys/malloc.h> 37250079Scarl#include <sys/module.h> 38250079Scarl#include <sys/queue.h> 39250079Scarl#include <sys/rman.h> 40289774Scem#include <sys/sbuf.h> 41289207Scem#include <sys/sysctl.h> 42250079Scarl#include <vm/vm.h> 43250079Scarl#include <vm/pmap.h> 44250079Scarl#include <machine/bus.h> 45250079Scarl#include <machine/pmap.h> 46250079Scarl#include <machine/resource.h> 47250079Scarl#include <dev/pci/pcireg.h> 48250079Scarl#include <dev/pci/pcivar.h> 49250079Scarl 50250079Scarl#include "ntb_regs.h" 51250079Scarl#include "ntb_hw.h" 52250079Scarl 53250079Scarl/* 54250079Scarl * The Non-Transparent Bridge (NTB) is a device on some Intel processors that 55250079Scarl * allows you to connect two systems using a PCI-e link. 56250079Scarl * 57250079Scarl * This module contains the hardware abstraction layer for the NTB. It allows 58250079Scarl * you to send and recieve interrupts, map the memory windows and send and 59250079Scarl * receive messages in the scratch-pad registers. 60250079Scarl * 61250079Scarl * NOTE: Much of the code in this module is shared with Linux. Any patches may 62250079Scarl * be picked up and redistributed in Linux with a dual GPL/BSD license. 63250079Scarl */ 64250079Scarl 65289648Scem#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 66250079Scarl 67289539Scem#define NTB_HB_TIMEOUT 1 /* second */ 68289648Scem#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 69250079Scarl 70250079Scarl#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) 71250079Scarl 72250079Scarlenum ntb_device_type { 73250079Scarl NTB_XEON, 74289648Scem NTB_ATOM 75250079Scarl}; 76250079Scarl 77289610Scem/* ntb_conn_type are hardware numbers, cannot change. */ 78289610Scemenum ntb_conn_type { 79289610Scem NTB_CONN_TRANSPARENT = 0, 80289610Scem NTB_CONN_B2B = 1, 81289610Scem NTB_CONN_RP = 2, 82289610Scem}; 83289610Scem 84289610Scemenum ntb_b2b_direction { 85289610Scem NTB_DEV_USD = 0, 86289610Scem NTB_DEV_DSD = 1, 87289610Scem}; 88289610Scem 89289539Scemenum ntb_bar { 90289539Scem NTB_CONFIG_BAR = 0, 91289539Scem NTB_B2B_BAR_1, 92289539Scem NTB_B2B_BAR_2, 93289539Scem NTB_B2B_BAR_3, 94289539Scem NTB_MAX_BARS 95289539Scem}; 96289539Scem 97255274Scarl/* Device features and workarounds */ 98255274Scarl#define HAS_FEATURE(feature) \ 99255274Scarl ((ntb->features & (feature)) != 0) 100255274Scarl 101250079Scarlstruct ntb_hw_info { 102250079Scarl uint32_t device_id; 103255274Scarl const char *desc; 104250079Scarl enum ntb_device_type type; 105289397Scem uint32_t features; 106250079Scarl}; 107250079Scarl 108250079Scarlstruct ntb_pci_bar_info { 109250079Scarl bus_space_tag_t pci_bus_tag; 110250079Scarl bus_space_handle_t pci_bus_handle; 111250079Scarl int pci_resource_id; 112250079Scarl struct resource *pci_resource; 113250079Scarl vm_paddr_t pbase; 114290679Scem caddr_t vbase; 115290679Scem vm_size_t size; 116289543Scem 117289543Scem /* Configuration register offsets */ 118289543Scem uint32_t psz_off; 119289543Scem uint32_t ssz_off; 120289543Scem uint32_t pbarxlat_off; 121250079Scarl}; 122250079Scarl 123250079Scarlstruct ntb_int_info { 124250079Scarl struct resource *res; 125250079Scarl int rid; 126250079Scarl void *tag; 127250079Scarl}; 128250079Scarl 129289546Scemstruct ntb_vec { 130250079Scarl struct ntb_softc *ntb; 131289546Scem uint32_t num; 132250079Scarl}; 133250079Scarl 134289542Scemstruct ntb_reg { 135289542Scem uint32_t ntb_ctl; 136289542Scem uint32_t lnk_sta; 137289542Scem uint8_t db_size; 138289542Scem unsigned mw_bar[NTB_MAX_BARS]; 139289542Scem}; 140289542Scem 141289542Scemstruct ntb_alt_reg { 142289542Scem uint32_t db_bell; 143289542Scem uint32_t db_mask; 144289542Scem uint32_t spad; 145289542Scem}; 146289542Scem 147289542Scemstruct ntb_xlat_reg { 148289546Scem uint32_t bar0_base; 149289546Scem uint32_t bar2_base; 150289546Scem uint32_t bar4_base; 151289546Scem uint32_t bar5_base; 152289546Scem 153289546Scem uint32_t bar2_xlat; 154289546Scem uint32_t bar4_xlat; 155289546Scem uint32_t bar5_xlat; 156289546Scem 157289546Scem uint32_t bar2_limit; 158289546Scem uint32_t bar4_limit; 159289546Scem uint32_t bar5_limit; 160289542Scem}; 161289542Scem 162289542Scemstruct ntb_b2b_addr { 163289542Scem uint64_t bar0_addr; 164289542Scem uint64_t bar2_addr64; 165289542Scem uint64_t bar4_addr64; 166289542Scem uint64_t bar4_addr32; 167289542Scem uint64_t bar5_addr32; 168289542Scem}; 169289542Scem 170250079Scarlstruct ntb_softc { 171250079Scarl device_t device; 172250079Scarl enum ntb_device_type type; 173289774Scem uint32_t features; 174250079Scarl 175250079Scarl struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 176250079Scarl struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 177250079Scarl uint32_t allocated_interrupts; 178250079Scarl 179250079Scarl struct callout heartbeat_timer; 180250079Scarl struct callout lr_timer; 181250079Scarl 182289546Scem void *ntb_ctx; 183289546Scem const struct ntb_ctx_ops *ctx_ops; 184289546Scem struct ntb_vec *msix_vec; 185290683Scem#define CTX_LOCK(sc) mtx_lock(&(sc)->ctx_lock) 186290683Scem#define CTX_UNLOCK(sc) mtx_unlock(&(sc)->ctx_lock) 187289546Scem#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f)) 188289546Scem struct mtx ctx_lock; 189250079Scarl 190289610Scem uint32_t ppd; 191289610Scem enum ntb_conn_type conn_type; 192289610Scem enum ntb_b2b_direction dev_type; 193289539Scem 194289542Scem /* Offset of peer bar0 in B2B BAR */ 195289542Scem uint64_t b2b_off; 196289542Scem /* Memory window used to access peer bar0 */ 197289543Scem#define B2B_MW_DISABLED UINT8_MAX 198289542Scem uint8_t b2b_mw_idx; 199289542Scem 200289539Scem uint8_t mw_count; 201289539Scem uint8_t spad_count; 202289539Scem uint8_t db_count; 203289539Scem uint8_t db_vec_count; 204289539Scem uint8_t db_vec_shift; 205289542Scem 206289546Scem /* Protects local db_mask. */ 207289546Scem#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 208289546Scem#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 209289546Scem#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 210289542Scem struct mtx db_mask_lock; 211289542Scem 212289546Scem uint32_t ntb_ctl; 213289546Scem uint32_t lnk_sta; 214289542Scem 215289542Scem uint64_t db_valid_mask; 216289542Scem uint64_t db_link_mask; 217289546Scem uint64_t db_mask; 218289542Scem 219289542Scem int last_ts; /* ticks @ last irq */ 220289542Scem 221289542Scem const struct ntb_reg *reg; 222289542Scem const struct ntb_alt_reg *self_reg; 223289542Scem const struct ntb_alt_reg *peer_reg; 224289542Scem const struct ntb_xlat_reg *xlat_reg; 225250079Scarl}; 226250079Scarl 227289234Scem#ifdef __i386__ 228289234Scemstatic __inline uint64_t 229289234Scembus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 230289234Scem bus_size_t offset) 231289234Scem{ 232289234Scem 233289234Scem return (bus_space_read_4(tag, handle, offset) | 234289234Scem ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 235289234Scem} 236289234Scem 237289234Scemstatic __inline void 238289234Scembus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 239289234Scem bus_size_t offset, uint64_t val) 240289234Scem{ 241289234Scem 242289234Scem bus_space_write_4(tag, handle, offset, val); 243289234Scem bus_space_write_4(tag, handle, offset + 4, val >> 32); 244289234Scem} 245289234Scem#endif 246289234Scem 247255279Scarl#define ntb_bar_read(SIZE, bar, offset) \ 248255279Scarl bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 249255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset)) 250255279Scarl#define ntb_bar_write(SIZE, bar, offset, val) \ 251255279Scarl bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 252255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 253255279Scarl#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 254250079Scarl#define ntb_reg_write(SIZE, offset, val) \ 255255279Scarl ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 256289397Scem#define ntb_mw_read(SIZE, offset) \ 257289542Scem ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 258255279Scarl#define ntb_mw_write(SIZE, offset, val) \ 259289542Scem ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 260289397Scem offset, val) 261250079Scarl 262250079Scarlstatic int ntb_probe(device_t device); 263250079Scarlstatic int ntb_attach(device_t device); 264250079Scarlstatic int ntb_detach(device_t device); 265289539Scemstatic inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 266289546Scemstatic inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 267289546Scemstatic inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 268289546Scem uint32_t *base, uint32_t *xlat, uint32_t *lmt); 269255272Scarlstatic int ntb_map_pci_bars(struct ntb_softc *ntb); 270289647Scemstatic void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 271289647Scem const char *); 272255272Scarlstatic int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 273255272Scarlstatic int map_memory_window_bar(struct ntb_softc *ntb, 274255272Scarl struct ntb_pci_bar_info *bar); 275250079Scarlstatic void ntb_unmap_pci_bar(struct ntb_softc *ntb); 276289344Scemstatic int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 277289540Scemstatic int ntb_init_isr(struct ntb_softc *ntb); 278289342Scemstatic int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 279289540Scemstatic int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 280250079Scarlstatic void ntb_teardown_interrupts(struct ntb_softc *ntb); 281289540Scemstatic inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 282289546Scemstatic void ntb_interrupt(struct ntb_softc *, uint32_t vec); 283289546Scemstatic void ndev_vec_isr(void *arg); 284289546Scemstatic void ndev_irq_isr(void *arg); 285289546Scemstatic inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 286290678Scemstatic inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 287290678Scemstatic inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 288289546Scemstatic int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 289289546Scemstatic void ntb_free_msix_vec(struct ntb_softc *ntb); 290250079Scarlstatic struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 291289397Scemstatic void ntb_detect_max_mw(struct ntb_softc *ntb); 292289348Scemstatic int ntb_detect_xeon(struct ntb_softc *ntb); 293289648Scemstatic int ntb_detect_atom(struct ntb_softc *ntb); 294289542Scemstatic int ntb_xeon_init_dev(struct ntb_softc *ntb); 295289648Scemstatic int ntb_atom_init_dev(struct ntb_softc *ntb); 296289272Scemstatic void ntb_teardown_xeon(struct ntb_softc *ntb); 297289648Scemstatic void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 298289543Scemstatic void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 299289543Scem enum ntb_bar regbar); 300289543Scemstatic void xeon_set_sbar_base_and_limit(struct ntb_softc *, 301289543Scem uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 302289543Scemstatic void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 303289543Scem enum ntb_bar idx); 304289542Scemstatic int xeon_setup_b2b_mw(struct ntb_softc *, 305289542Scem const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 306289546Scemstatic inline bool link_is_up(struct ntb_softc *ntb); 307289648Scemstatic inline bool atom_link_is_err(struct ntb_softc *ntb); 308289546Scemstatic inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 309289546Scemstatic inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 310289648Scemstatic void atom_link_hb(void *arg); 311289546Scemstatic void ntb_db_event(struct ntb_softc *ntb, uint32_t vec); 312289648Scemstatic void recover_atom_link(void *arg); 313289546Scemstatic bool ntb_poll_link(struct ntb_softc *ntb); 314255274Scarlstatic void save_bar_parameters(struct ntb_pci_bar_info *bar); 315289774Scemstatic void ntb_sysctl_init(struct ntb_softc *); 316289774Scemstatic int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 317289774Scemstatic int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 318289774Scemstatic int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 319250079Scarl 320290685Scemstatic unsigned g_ntb_hw_debug_level; 321290685ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 322290685Scem &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 323290685Scem#define ntb_printf(lvl, ...) do { \ 324290685Scem if ((lvl) <= g_ntb_hw_debug_level) { \ 325290685Scem device_printf(ntb->device, __VA_ARGS__); \ 326290685Scem } \ 327290685Scem} while (0) 328290685Scem 329250079Scarlstatic struct ntb_hw_info pci_ids[] = { 330289612Scem /* XXX: PS/SS IDs left out until they are supported. */ 331289612Scem { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 332289648Scem NTB_ATOM, 0 }, 333289233Scem 334289233Scem { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 335289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 336289233Scem { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 337289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 338289233Scem { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 339289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 340289538Scem NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 341289233Scem { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 342289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 343289538Scem NTB_SB01BASE_LOCKUP }, 344289233Scem { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 345289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 346289538Scem NTB_SB01BASE_LOCKUP }, 347289233Scem 348289648Scem { 0x00000000, NULL, NTB_ATOM, 0 } 349250079Scarl}; 350250079Scarl 351289648Scemstatic const struct ntb_reg atom_reg = { 352289648Scem .ntb_ctl = ATOM_NTBCNTL_OFFSET, 353289648Scem .lnk_sta = ATOM_LINK_STATUS_OFFSET, 354289542Scem .db_size = sizeof(uint64_t), 355289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 356289542Scem}; 357289542Scem 358289648Scemstatic const struct ntb_alt_reg atom_pri_reg = { 359289648Scem .db_bell = ATOM_PDOORBELL_OFFSET, 360289648Scem .db_mask = ATOM_PDBMSK_OFFSET, 361289648Scem .spad = ATOM_SPAD_OFFSET, 362289607Scem}; 363289607Scem 364289648Scemstatic const struct ntb_alt_reg atom_b2b_reg = { 365289648Scem .db_bell = ATOM_B2B_DOORBELL_OFFSET, 366289648Scem .spad = ATOM_B2B_SPAD_OFFSET, 367289542Scem}; 368289542Scem 369289648Scemstatic const struct ntb_xlat_reg atom_sec_xlat = { 370289542Scem#if 0 371289542Scem /* "FIXME" says the Linux driver. */ 372289648Scem .bar0_base = ATOM_SBAR0BASE_OFFSET, 373289648Scem .bar2_base = ATOM_SBAR2BASE_OFFSET, 374289648Scem .bar4_base = ATOM_SBAR4BASE_OFFSET, 375289546Scem 376289648Scem .bar2_limit = ATOM_SBAR2LMT_OFFSET, 377289648Scem .bar4_limit = ATOM_SBAR4LMT_OFFSET, 378289542Scem#endif 379289546Scem 380289648Scem .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 381289648Scem .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 382289542Scem}; 383289542Scem 384289542Scemstatic const struct ntb_reg xeon_reg = { 385289542Scem .ntb_ctl = XEON_NTBCNTL_OFFSET, 386289542Scem .lnk_sta = XEON_LINK_STATUS_OFFSET, 387289542Scem .db_size = sizeof(uint16_t), 388289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 389289542Scem}; 390289542Scem 391289607Scemstatic const struct ntb_alt_reg xeon_pri_reg = { 392289607Scem .db_bell = XEON_PDOORBELL_OFFSET, 393289607Scem .db_mask = XEON_PDBMSK_OFFSET, 394289607Scem .spad = XEON_SPAD_OFFSET, 395289607Scem}; 396289607Scem 397289542Scemstatic const struct ntb_alt_reg xeon_b2b_reg = { 398289542Scem .db_bell = XEON_B2B_DOORBELL_OFFSET, 399289542Scem .spad = XEON_B2B_SPAD_OFFSET, 400289542Scem}; 401289542Scem 402289542Scemstatic const struct ntb_xlat_reg xeon_sec_xlat = { 403289542Scem .bar0_base = XEON_SBAR0BASE_OFFSET, 404289546Scem .bar2_base = XEON_SBAR2BASE_OFFSET, 405289546Scem .bar4_base = XEON_SBAR4BASE_OFFSET, 406289546Scem .bar5_base = XEON_SBAR5BASE_OFFSET, 407289546Scem 408289542Scem .bar2_limit = XEON_SBAR2LMT_OFFSET, 409289546Scem .bar4_limit = XEON_SBAR4LMT_OFFSET, 410289546Scem .bar5_limit = XEON_SBAR5LMT_OFFSET, 411289546Scem 412289542Scem .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 413289546Scem .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 414289546Scem .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 415289542Scem}; 416289542Scem 417289614Scemstatic struct ntb_b2b_addr xeon_b2b_usd_addr = { 418289542Scem .bar0_addr = XEON_B2B_BAR0_USD_ADDR, 419289542Scem .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64, 420289542Scem .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64, 421289542Scem .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32, 422289542Scem .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32, 423289542Scem}; 424289542Scem 425289614Scemstatic struct ntb_b2b_addr xeon_b2b_dsd_addr = { 426289542Scem .bar0_addr = XEON_B2B_BAR0_DSD_ADDR, 427289542Scem .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64, 428289542Scem .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64, 429289542Scem .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32, 430289542Scem .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32, 431289542Scem}; 432289542Scem 433289614ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 434289614Scem "B2B MW segment overrides -- MUST be the same on both sides"); 435289614Scem 436289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 437289614Scem &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 438289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 439289614Scem "the window at BAR2, on the upstream side of the link. MUST be the same " 440289614Scem "address on both sides."); 441289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 442289614Scem &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 443289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 444289614Scem &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 445289614Scem "(split-BAR mode)."); 446289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 447289646Scem &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 448289614Scem "(split-BAR mode)."); 449289614Scem 450289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 451289614Scem &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 452289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 453289614Scem "the window at BAR2, on the downstream side of the link. MUST be the same" 454289614Scem " address on both sides."); 455289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 456289614Scem &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 457289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 458289614Scem &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 459289614Scem "(split-BAR mode)."); 460289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 461289646Scem &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 462289614Scem "(split-BAR mode)."); 463289614Scem 464250079Scarl/* 465250079Scarl * OS <-> Driver interface structures 466250079Scarl */ 467250079ScarlMALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 468250079Scarl 469250079Scarlstatic device_method_t ntb_pci_methods[] = { 470250079Scarl /* Device interface */ 471250079Scarl DEVMETHOD(device_probe, ntb_probe), 472250079Scarl DEVMETHOD(device_attach, ntb_attach), 473250079Scarl DEVMETHOD(device_detach, ntb_detach), 474250079Scarl DEVMETHOD_END 475250079Scarl}; 476250079Scarl 477250079Scarlstatic driver_t ntb_pci_driver = { 478250079Scarl "ntb_hw", 479250079Scarl ntb_pci_methods, 480250079Scarl sizeof(struct ntb_softc), 481250079Scarl}; 482250079Scarl 483250079Scarlstatic devclass_t ntb_devclass; 484250079ScarlDRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); 485250079ScarlMODULE_VERSION(ntb_hw, 1); 486250079Scarl 487289207ScemSYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 488289207Scem 489250079Scarl/* 490250079Scarl * OS <-> Driver linkage functions 491250079Scarl */ 492250079Scarlstatic int 493250079Scarlntb_probe(device_t device) 494250079Scarl{ 495289209Scem struct ntb_hw_info *p; 496250079Scarl 497289209Scem p = ntb_get_device_info(pci_get_devid(device)); 498289209Scem if (p == NULL) 499250079Scarl return (ENXIO); 500289209Scem 501289209Scem device_set_desc(device, p->desc); 502289209Scem return (0); 503250079Scarl} 504250079Scarl 505250079Scarlstatic int 506250079Scarlntb_attach(device_t device) 507250079Scarl{ 508289209Scem struct ntb_softc *ntb; 509289209Scem struct ntb_hw_info *p; 510250079Scarl int error; 511250079Scarl 512289209Scem ntb = DEVICE2SOFTC(device); 513289209Scem p = ntb_get_device_info(pci_get_devid(device)); 514289209Scem 515250079Scarl ntb->device = device; 516250079Scarl ntb->type = p->type; 517255274Scarl ntb->features = p->features; 518289543Scem ntb->b2b_mw_idx = B2B_MW_DISABLED; 519250079Scarl 520289648Scem /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 521283291Sjkim callout_init(&ntb->heartbeat_timer, 1); 522283291Sjkim callout_init(&ntb->lr_timer, 1); 523289542Scem mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 524290683Scem mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_DEF); 525250079Scarl 526289648Scem if (ntb->type == NTB_ATOM) 527289648Scem error = ntb_detect_atom(ntb); 528289348Scem else 529289348Scem error = ntb_detect_xeon(ntb); 530290682Scem if (error != 0) 531289348Scem goto out; 532289348Scem 533289397Scem ntb_detect_max_mw(ntb); 534289396Scem 535290682Scem pci_enable_busmaster(ntb->device); 536290682Scem 537289209Scem error = ntb_map_pci_bars(ntb); 538290682Scem if (error != 0) 539289209Scem goto out; 540289648Scem if (ntb->type == NTB_ATOM) 541289648Scem error = ntb_atom_init_dev(ntb); 542289272Scem else 543289542Scem error = ntb_xeon_init_dev(ntb); 544290682Scem if (error != 0) 545289209Scem goto out; 546290682Scem 547290682Scem ntb_poll_link(ntb); 548290682Scem 549289774Scem ntb_sysctl_init(ntb); 550250079Scarl 551289209Scemout: 552289209Scem if (error != 0) 553289209Scem ntb_detach(device); 554250079Scarl return (error); 555250079Scarl} 556250079Scarl 557250079Scarlstatic int 558250079Scarlntb_detach(device_t device) 559250079Scarl{ 560289209Scem struct ntb_softc *ntb; 561250079Scarl 562289209Scem ntb = DEVICE2SOFTC(device); 563289542Scem 564289617Scem if (ntb->self_reg != NULL) 565289617Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 566250079Scarl callout_drain(&ntb->heartbeat_timer); 567250079Scarl callout_drain(&ntb->lr_timer); 568290682Scem pci_disable_busmaster(ntb->device); 569289272Scem if (ntb->type == NTB_XEON) 570289272Scem ntb_teardown_xeon(ntb); 571250079Scarl ntb_teardown_interrupts(ntb); 572289397Scem 573289542Scem mtx_destroy(&ntb->db_mask_lock); 574289546Scem mtx_destroy(&ntb->ctx_lock); 575289542Scem 576289397Scem /* 577289397Scem * Redetect total MWs so we unmap properly -- in case we lowered the 578289397Scem * maximum to work around Xeon errata. 579289397Scem */ 580289397Scem ntb_detect_max_mw(ntb); 581250079Scarl ntb_unmap_pci_bar(ntb); 582250079Scarl 583250079Scarl return (0); 584250079Scarl} 585250079Scarl 586289542Scem/* 587289542Scem * Driver internal routines 588289542Scem */ 589289539Scemstatic inline enum ntb_bar 590289539Scemntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 591289539Scem{ 592289539Scem 593289543Scem KASSERT(mw < ntb->mw_count || 594289543Scem (mw != B2B_MW_DISABLED && mw == ntb->b2b_mw_idx), 595289542Scem ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 596289546Scem KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 597289539Scem 598289542Scem return (ntb->reg->mw_bar[mw]); 599289539Scem} 600289539Scem 601289546Scemstatic inline bool 602289546Scembar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 603289546Scem{ 604289546Scem /* XXX This assertion could be stronger. */ 605289546Scem KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 606289546Scem return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR)); 607289546Scem} 608289546Scem 609289546Scemstatic inline void 610289546Scembar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 611289546Scem uint32_t *xlat, uint32_t *lmt) 612289546Scem{ 613289546Scem uint32_t basev, lmtv, xlatv; 614289546Scem 615289546Scem switch (bar) { 616289546Scem case NTB_B2B_BAR_1: 617289546Scem basev = ntb->xlat_reg->bar2_base; 618289546Scem lmtv = ntb->xlat_reg->bar2_limit; 619289546Scem xlatv = ntb->xlat_reg->bar2_xlat; 620289546Scem break; 621289546Scem case NTB_B2B_BAR_2: 622289546Scem basev = ntb->xlat_reg->bar4_base; 623289546Scem lmtv = ntb->xlat_reg->bar4_limit; 624289546Scem xlatv = ntb->xlat_reg->bar4_xlat; 625289546Scem break; 626289546Scem case NTB_B2B_BAR_3: 627289546Scem basev = ntb->xlat_reg->bar5_base; 628289546Scem lmtv = ntb->xlat_reg->bar5_limit; 629289546Scem xlatv = ntb->xlat_reg->bar5_xlat; 630289546Scem break; 631289546Scem default: 632289546Scem KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 633289546Scem ("bad bar")); 634289546Scem basev = lmtv = xlatv = 0; 635289546Scem break; 636289546Scem } 637289546Scem 638289546Scem if (base != NULL) 639289546Scem *base = basev; 640289546Scem if (xlat != NULL) 641289546Scem *xlat = xlatv; 642289546Scem if (lmt != NULL) 643289546Scem *lmt = lmtv; 644289546Scem} 645289546Scem 646250079Scarlstatic int 647255272Scarlntb_map_pci_bars(struct ntb_softc *ntb) 648250079Scarl{ 649255272Scarl int rc; 650250079Scarl 651250079Scarl ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 652289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 653255272Scarl if (rc != 0) 654289541Scem goto out; 655255272Scarl 656289209Scem ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 657289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 658255272Scarl if (rc != 0) 659289541Scem goto out; 660289543Scem ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 661289543Scem ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 662289543Scem ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 663255272Scarl 664289209Scem ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 665289543Scem /* XXX Are shared MW B2Bs write-combining? */ 666289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP) && !HAS_FEATURE(NTB_SPLIT_BAR)) 667289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 668255279Scarl else 669289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 670289543Scem ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 671289543Scem ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 672289543Scem ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 673289543Scem 674289397Scem if (!HAS_FEATURE(NTB_SPLIT_BAR)) 675289541Scem goto out; 676289397Scem 677289397Scem ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 678289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 679289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 680289397Scem else 681289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 682289543Scem ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 683289543Scem ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 684289543Scem ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 685250079Scarl 686289541Scemout: 687289209Scem if (rc != 0) 688255272Scarl device_printf(ntb->device, 689255272Scarl "unable to allocate pci resource\n"); 690255272Scarl return (rc); 691255272Scarl} 692255272Scarl 693289541Scemstatic void 694289647Scemprint_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 695289647Scem const char *kind) 696289541Scem{ 697289541Scem 698289647Scem device_printf(ntb->device, 699289647Scem "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 700289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 701289647Scem (char *)bar->vbase + bar->size - 1, 702289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 703289647Scem (uintmax_t)bar->size, kind); 704289541Scem} 705289541Scem 706255272Scarlstatic int 707255272Scarlmap_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 708255272Scarl{ 709255272Scarl 710255275Scarl bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 711289209Scem &bar->pci_resource_id, RF_ACTIVE); 712255272Scarl if (bar->pci_resource == NULL) 713255272Scarl return (ENXIO); 714289209Scem 715289209Scem save_bar_parameters(bar); 716289647Scem print_map_success(ntb, bar, "mmr"); 717289209Scem return (0); 718255272Scarl} 719255272Scarl 720255272Scarlstatic int 721255272Scarlmap_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 722255272Scarl{ 723255272Scarl int rc; 724255276Scarl uint8_t bar_size_bits = 0; 725255272Scarl 726289209Scem bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 727289209Scem &bar->pci_resource_id, RF_ACTIVE); 728250079Scarl 729255272Scarl if (bar->pci_resource == NULL) 730255272Scarl return (ENXIO); 731255276Scarl 732289209Scem save_bar_parameters(bar); 733289209Scem /* 734289209Scem * Ivytown NTB BAR sizes are misreported by the hardware due to a 735289209Scem * hardware issue. To work around this, query the size it should be 736289209Scem * configured to by the device and modify the resource to correspond to 737289209Scem * this new size. The BIOS on systems with this problem is required to 738289209Scem * provide enough address space to allow the driver to make this change 739289209Scem * safely. 740289209Scem * 741289209Scem * Ideally I could have just specified the size when I allocated the 742289209Scem * resource like: 743289209Scem * bus_alloc_resource(ntb->device, 744289209Scem * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 745289209Scem * 1ul << bar_size_bits, RF_ACTIVE); 746289209Scem * but the PCI driver does not honor the size in this call, so we have 747289209Scem * to modify it after the fact. 748289209Scem */ 749289209Scem if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { 750289209Scem if (bar->pci_resource_id == PCIR_BAR(2)) 751289209Scem bar_size_bits = pci_read_config(ntb->device, 752289209Scem XEON_PBAR23SZ_OFFSET, 1); 753289209Scem else 754289209Scem bar_size_bits = pci_read_config(ntb->device, 755289209Scem XEON_PBAR45SZ_OFFSET, 1); 756289209Scem 757289209Scem rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 758289209Scem bar->pci_resource, bar->pbase, 759289209Scem bar->pbase + (1ul << bar_size_bits) - 1); 760255272Scarl if (rc != 0) { 761289209Scem device_printf(ntb->device, 762289209Scem "unable to resize bar\n"); 763255272Scarl return (rc); 764250079Scarl } 765289209Scem 766289209Scem save_bar_parameters(bar); 767250079Scarl } 768289209Scem 769289209Scem /* Mark bar region as write combining to improve performance. */ 770289209Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, 771289209Scem VM_MEMATTR_WRITE_COMBINING); 772289647Scem print_map_success(ntb, bar, "mw"); 773289647Scem if (rc == 0) 774289209Scem device_printf(ntb->device, 775289647Scem "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 776289647Scem "WRITE_COMBINING.\n", 777289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 778289647Scem (char *)bar->vbase + bar->size - 1, 779289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1)); 780289647Scem else 781289647Scem device_printf(ntb->device, 782289647Scem "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 783289647Scem "WRITE_COMBINING: %d\n", 784289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 785289647Scem (char *)bar->vbase + bar->size - 1, 786289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 787289647Scem rc); 788289647Scem /* Proceed anyway */ 789250079Scarl return (0); 790250079Scarl} 791250079Scarl 792250079Scarlstatic void 793250079Scarlntb_unmap_pci_bar(struct ntb_softc *ntb) 794250079Scarl{ 795250079Scarl struct ntb_pci_bar_info *current_bar; 796250079Scarl int i; 797250079Scarl 798289397Scem for (i = 0; i < NTB_MAX_BARS; i++) { 799250079Scarl current_bar = &ntb->bar_info[i]; 800250079Scarl if (current_bar->pci_resource != NULL) 801250079Scarl bus_release_resource(ntb->device, SYS_RES_MEMORY, 802250079Scarl current_bar->pci_resource_id, 803250079Scarl current_bar->pci_resource); 804250079Scarl } 805250079Scarl} 806250079Scarl 807250079Scarlstatic int 808289540Scemntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 809250079Scarl{ 810289342Scem uint32_t i; 811289342Scem int rc; 812289342Scem 813289342Scem for (i = 0; i < num_vectors; i++) { 814289342Scem ntb->int_info[i].rid = i + 1; 815289342Scem ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 816289342Scem SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 817289342Scem if (ntb->int_info[i].res == NULL) { 818289342Scem device_printf(ntb->device, 819289342Scem "bus_alloc_resource failed\n"); 820289342Scem return (ENOMEM); 821289342Scem } 822289342Scem ntb->int_info[i].tag = NULL; 823289342Scem ntb->allocated_interrupts++; 824289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 825289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 826289546Scem &ntb->msix_vec[i], &ntb->int_info[i].tag); 827289342Scem if (rc != 0) { 828289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 829289342Scem return (ENXIO); 830289342Scem } 831289342Scem } 832289342Scem return (0); 833289342Scem} 834289342Scem 835289344Scem/* 836289344Scem * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 837289344Scem * cannot be allocated for each MSI-X message. JHB seems to think remapping 838289344Scem * should be okay. This tunable should enable us to test that hypothesis 839289344Scem * when someone gets their hands on some Xeon hardware. 840289344Scem */ 841289344Scemstatic int ntb_force_remap_mode; 842289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 843289344Scem &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 844289344Scem " to a smaller number of ithreads, even if the desired number are " 845289344Scem "available"); 846289344Scem 847289344Scem/* 848289344Scem * In case it is NOT ok, give consumers an abort button. 849289344Scem */ 850289344Scemstatic int ntb_prefer_intx; 851289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 852289344Scem &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 853289344Scem "than remapping MSI-X messages over available slots (match Linux driver " 854289344Scem "behavior)"); 855289344Scem 856289344Scem/* 857289344Scem * Remap the desired number of MSI-X messages to available ithreads in a simple 858289344Scem * round-robin fashion. 859289344Scem */ 860289342Scemstatic int 861289344Scemntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 862289344Scem{ 863289344Scem u_int *vectors; 864289344Scem uint32_t i; 865289344Scem int rc; 866289344Scem 867289344Scem if (ntb_prefer_intx != 0) 868289344Scem return (ENXIO); 869289344Scem 870289344Scem vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 871289344Scem 872289344Scem for (i = 0; i < desired; i++) 873289344Scem vectors[i] = (i % avail) + 1; 874289344Scem 875289344Scem rc = pci_remap_msix(dev, desired, vectors); 876289344Scem free(vectors, M_NTB); 877289344Scem return (rc); 878289344Scem} 879289344Scem 880289344Scemstatic int 881289540Scemntb_init_isr(struct ntb_softc *ntb) 882289342Scem{ 883289344Scem uint32_t desired_vectors, num_vectors; 884289342Scem int rc; 885250079Scarl 886250079Scarl ntb->allocated_interrupts = 0; 887289542Scem ntb->last_ts = ticks; 888289347Scem 889250079Scarl /* 890289546Scem * Mask all doorbell interrupts. 891250079Scarl */ 892289546Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 893250079Scarl 894289344Scem num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 895289539Scem ntb->db_count); 896289344Scem if (desired_vectors >= 1) { 897289344Scem rc = pci_alloc_msix(ntb->device, &num_vectors); 898250079Scarl 899289344Scem if (ntb_force_remap_mode != 0 && rc == 0 && 900289344Scem num_vectors == desired_vectors) 901289344Scem num_vectors--; 902289344Scem 903289344Scem if (rc == 0 && num_vectors < desired_vectors) { 904289344Scem rc = ntb_remap_msix(ntb->device, desired_vectors, 905289344Scem num_vectors); 906289344Scem if (rc == 0) 907289344Scem num_vectors = desired_vectors; 908289344Scem else 909289344Scem pci_release_msi(ntb->device); 910289344Scem } 911289344Scem if (rc != 0) 912289344Scem num_vectors = 1; 913289344Scem } else 914289344Scem num_vectors = 1; 915289344Scem 916289539Scem if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 917289539Scem ntb->db_vec_count = 1; 918290680Scem ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 919289539Scem rc = ntb_setup_legacy_interrupt(ntb); 920289539Scem } else { 921289546Scem ntb_create_msix_vec(ntb, num_vectors); 922289540Scem rc = ntb_setup_msix(ntb, num_vectors); 923289539Scem } 924289539Scem if (rc != 0) { 925289539Scem device_printf(ntb->device, 926289539Scem "Error allocating interrupts: %d\n", rc); 927289546Scem ntb_free_msix_vec(ntb); 928289396Scem } 929289396Scem 930289342Scem return (rc); 931289342Scem} 932289342Scem 933289342Scemstatic int 934289342Scemntb_setup_legacy_interrupt(struct ntb_softc *ntb) 935289342Scem{ 936289342Scem int rc; 937289342Scem 938289342Scem ntb->int_info[0].rid = 0; 939289342Scem ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 940289342Scem &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 941289342Scem if (ntb->int_info[0].res == NULL) { 942289342Scem device_printf(ntb->device, "bus_alloc_resource failed\n"); 943289342Scem return (ENOMEM); 944250079Scarl } 945250079Scarl 946289342Scem ntb->int_info[0].tag = NULL; 947289342Scem ntb->allocated_interrupts = 1; 948289342Scem 949289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 950289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 951289342Scem ntb, &ntb->int_info[0].tag); 952289342Scem if (rc != 0) { 953289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 954289342Scem return (ENXIO); 955289342Scem } 956289342Scem 957250079Scarl return (0); 958250079Scarl} 959250079Scarl 960250079Scarlstatic void 961250079Scarlntb_teardown_interrupts(struct ntb_softc *ntb) 962250079Scarl{ 963250079Scarl struct ntb_int_info *current_int; 964250079Scarl int i; 965250079Scarl 966289209Scem for (i = 0; i < ntb->allocated_interrupts; i++) { 967250079Scarl current_int = &ntb->int_info[i]; 968250079Scarl if (current_int->tag != NULL) 969250079Scarl bus_teardown_intr(ntb->device, current_int->res, 970250079Scarl current_int->tag); 971250079Scarl 972250079Scarl if (current_int->res != NULL) 973250079Scarl bus_release_resource(ntb->device, SYS_RES_IRQ, 974250079Scarl rman_get_rid(current_int->res), current_int->res); 975250079Scarl } 976250079Scarl 977289546Scem ntb_free_msix_vec(ntb); 978250079Scarl pci_release_msi(ntb->device); 979250079Scarl} 980250079Scarl 981289347Scem/* 982289648Scem * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 983289347Scem * out to make code clearer. 984289347Scem */ 985289539Scemstatic inline uint64_t 986289546Scemdb_ioread(struct ntb_softc *ntb, uint64_t regoff) 987289347Scem{ 988289347Scem 989289648Scem if (ntb->type == NTB_ATOM) 990289347Scem return (ntb_reg_read(8, regoff)); 991289347Scem 992289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 993289347Scem 994289347Scem return (ntb_reg_read(2, regoff)); 995289347Scem} 996289347Scem 997289539Scemstatic inline void 998289546Scemdb_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 999289347Scem{ 1000289347Scem 1001289542Scem KASSERT((val & ~ntb->db_valid_mask) == 0, 1002289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1003289542Scem (uintmax_t)(val & ~ntb->db_valid_mask), 1004289542Scem (uintmax_t)ntb->db_valid_mask)); 1005289542Scem 1006289607Scem if (regoff == ntb->self_reg->db_mask) 1007289546Scem DB_MASK_ASSERT(ntb, MA_OWNED); 1008290678Scem db_iowrite_raw(ntb, regoff, val); 1009290678Scem} 1010289542Scem 1011290678Scemstatic inline void 1012290678Scemdb_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1013290678Scem{ 1014290678Scem 1015289648Scem if (ntb->type == NTB_ATOM) { 1016289347Scem ntb_reg_write(8, regoff, val); 1017289347Scem return; 1018289347Scem } 1019289347Scem 1020289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1021289347Scem ntb_reg_write(2, regoff, (uint16_t)val); 1022289347Scem} 1023289347Scem 1024289546Scemvoid 1025289542Scemntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits) 1026289542Scem{ 1027289542Scem 1028289546Scem DB_MASK_LOCK(ntb); 1029289542Scem ntb->db_mask |= bits; 1030289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1031289546Scem DB_MASK_UNLOCK(ntb); 1032289542Scem} 1033289542Scem 1034289546Scemvoid 1035289542Scemntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits) 1036289542Scem{ 1037289542Scem 1038289542Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1039289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1040289542Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1041289542Scem (uintmax_t)ntb->db_valid_mask)); 1042289542Scem 1043289546Scem DB_MASK_LOCK(ntb); 1044289542Scem ntb->db_mask &= ~bits; 1045289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1046289546Scem DB_MASK_UNLOCK(ntb); 1047289542Scem} 1048289542Scem 1049289546Scemuint64_t 1050289546Scemntb_db_read(struct ntb_softc *ntb) 1051289281Scem{ 1052289281Scem 1053289607Scem return (db_ioread(ntb, ntb->self_reg->db_bell)); 1054289281Scem} 1055289281Scem 1056289546Scemvoid 1057289546Scemntb_db_clear(struct ntb_softc *ntb, uint64_t bits) 1058289281Scem{ 1059289281Scem 1060289546Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1061289546Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1062289546Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1063289546Scem (uintmax_t)ntb->db_valid_mask)); 1064289546Scem 1065289607Scem db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1066289281Scem} 1067289281Scem 1068289540Scemstatic inline uint64_t 1069289540Scemntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1070250079Scarl{ 1071289540Scem uint64_t shift, mask; 1072250079Scarl 1073289540Scem shift = ntb->db_vec_shift; 1074289540Scem mask = (1ull << shift) - 1; 1075289540Scem return (mask << (shift * db_vector)); 1076250079Scarl} 1077250079Scarl 1078250079Scarlstatic void 1079289546Scemntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1080250079Scarl{ 1081289540Scem uint64_t vec_mask; 1082250079Scarl 1083289542Scem ntb->last_ts = ticks; 1084289546Scem vec_mask = ntb_vec_mask(ntb, vec); 1085250079Scarl 1086289542Scem if ((vec_mask & ntb->db_link_mask) != 0) { 1087289546Scem if (ntb_poll_link(ntb)) 1088289546Scem ntb_link_event(ntb); 1089289540Scem } 1090289540Scem 1091289546Scem if ((vec_mask & ntb->db_valid_mask) != 0) 1092289546Scem ntb_db_event(ntb, vec); 1093289546Scem} 1094250079Scarl 1095289546Scemstatic void 1096289546Scemndev_vec_isr(void *arg) 1097289546Scem{ 1098289546Scem struct ntb_vec *nvec = arg; 1099250079Scarl 1100289546Scem ntb_interrupt(nvec->ntb, nvec->num); 1101250079Scarl} 1102250079Scarl 1103250079Scarlstatic void 1104289546Scemndev_irq_isr(void *arg) 1105250079Scarl{ 1106289546Scem /* If we couldn't set up MSI-X, we only have the one vector. */ 1107289546Scem ntb_interrupt(arg, 0); 1108250079Scarl} 1109250079Scarl 1110250079Scarlstatic int 1111289546Scemntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1112250079Scarl{ 1113289342Scem uint32_t i; 1114250079Scarl 1115289546Scem ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1116250079Scarl M_ZERO | M_WAITOK); 1117250079Scarl for (i = 0; i < num_vectors; i++) { 1118289546Scem ntb->msix_vec[i].num = i; 1119289546Scem ntb->msix_vec[i].ntb = ntb; 1120250079Scarl } 1121250079Scarl 1122250079Scarl return (0); 1123250079Scarl} 1124250079Scarl 1125250079Scarlstatic void 1126289546Scemntb_free_msix_vec(struct ntb_softc *ntb) 1127250079Scarl{ 1128250079Scarl 1129289546Scem if (ntb->msix_vec == NULL) 1130289539Scem return; 1131289539Scem 1132289546Scem free(ntb->msix_vec, M_NTB); 1133289546Scem ntb->msix_vec = NULL; 1134250079Scarl} 1135250079Scarl 1136250079Scarlstatic struct ntb_hw_info * 1137250079Scarlntb_get_device_info(uint32_t device_id) 1138250079Scarl{ 1139250079Scarl struct ntb_hw_info *ep = pci_ids; 1140250079Scarl 1141250079Scarl while (ep->device_id) { 1142250079Scarl if (ep->device_id == device_id) 1143250079Scarl return (ep); 1144250079Scarl ++ep; 1145250079Scarl } 1146250079Scarl return (NULL); 1147250079Scarl} 1148250079Scarl 1149289272Scemstatic void 1150289272Scemntb_teardown_xeon(struct ntb_softc *ntb) 1151250079Scarl{ 1152250079Scarl 1153289617Scem if (ntb->reg != NULL) 1154289617Scem ntb_link_disable(ntb); 1155250079Scarl} 1156250079Scarl 1157289397Scemstatic void 1158289397Scemntb_detect_max_mw(struct ntb_softc *ntb) 1159289397Scem{ 1160289397Scem 1161289648Scem if (ntb->type == NTB_ATOM) { 1162289648Scem ntb->mw_count = ATOM_MW_COUNT; 1163289397Scem return; 1164289397Scem } 1165289397Scem 1166289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1167289539Scem ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1168289397Scem else 1169289539Scem ntb->mw_count = XEON_SNB_MW_COUNT; 1170289397Scem} 1171289397Scem 1172250079Scarlstatic int 1173289348Scemntb_detect_xeon(struct ntb_softc *ntb) 1174250079Scarl{ 1175289348Scem uint8_t ppd, conn_type; 1176250079Scarl 1177289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1178289348Scem ntb->ppd = ppd; 1179250079Scarl 1180289348Scem if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1181290681Scem ntb->dev_type = NTB_DEV_DSD; 1182290681Scem else 1183289257Scem ntb->dev_type = NTB_DEV_USD; 1184289257Scem 1185289397Scem if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1186289397Scem ntb->features |= NTB_SPLIT_BAR; 1187289397Scem 1188289542Scem /* SB01BASE_LOCKUP errata is a superset of SDOORBELL errata */ 1189289542Scem if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) 1190289542Scem ntb->features |= NTB_SDOORBELL_LOCKUP; 1191289542Scem 1192289348Scem conn_type = ppd & XEON_PPD_CONN_TYPE; 1193289348Scem switch (conn_type) { 1194289348Scem case NTB_CONN_B2B: 1195289348Scem ntb->conn_type = conn_type; 1196289348Scem break; 1197289348Scem case NTB_CONN_RP: 1198289348Scem case NTB_CONN_TRANSPARENT: 1199289348Scem default: 1200289348Scem device_printf(ntb->device, "Unsupported connection type: %u\n", 1201289348Scem (unsigned)conn_type); 1202289348Scem return (ENXIO); 1203289348Scem } 1204289348Scem return (0); 1205289348Scem} 1206289348Scem 1207289348Scemstatic int 1208289648Scemntb_detect_atom(struct ntb_softc *ntb) 1209289348Scem{ 1210289348Scem uint32_t ppd, conn_type; 1211289348Scem 1212289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1213289348Scem ntb->ppd = ppd; 1214289348Scem 1215289648Scem if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1216289348Scem ntb->dev_type = NTB_DEV_DSD; 1217289348Scem else 1218289348Scem ntb->dev_type = NTB_DEV_USD; 1219289348Scem 1220289648Scem conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1221289348Scem switch (conn_type) { 1222289348Scem case NTB_CONN_B2B: 1223289348Scem ntb->conn_type = conn_type; 1224289348Scem break; 1225289348Scem default: 1226289348Scem device_printf(ntb->device, "Unsupported NTB configuration\n"); 1227289348Scem return (ENXIO); 1228289348Scem } 1229289348Scem return (0); 1230289348Scem} 1231289348Scem 1232289348Scemstatic int 1233289542Scemntb_xeon_init_dev(struct ntb_softc *ntb) 1234289348Scem{ 1235289542Scem int rc; 1236289348Scem 1237289542Scem ntb->spad_count = XEON_SPAD_COUNT; 1238289542Scem ntb->db_count = XEON_DB_COUNT; 1239289542Scem ntb->db_link_mask = XEON_DB_LINK_BIT; 1240289542Scem ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1241289542Scem ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1242289257Scem 1243289542Scem if (ntb->conn_type != NTB_CONN_B2B) { 1244250079Scarl device_printf(ntb->device, "Connection type %d not supported\n", 1245289348Scem ntb->conn_type); 1246250079Scarl return (ENXIO); 1247250079Scarl } 1248250079Scarl 1249289542Scem ntb->reg = &xeon_reg; 1250289607Scem ntb->self_reg = &xeon_pri_reg; 1251289542Scem ntb->peer_reg = &xeon_b2b_reg; 1252289542Scem ntb->xlat_reg = &xeon_sec_xlat; 1253289542Scem 1254289208Scem /* 1255289208Scem * There is a Xeon hardware errata related to writes to SDOORBELL or 1256289208Scem * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1257289208Scem * which may hang the system. To workaround this use the second memory 1258289208Scem * window to access the interrupt and scratch pad registers on the 1259289208Scem * remote system. 1260289208Scem */ 1261289543Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 1262289543Scem /* Use the last MW for mapping remote spad */ 1263289542Scem ntb->b2b_mw_idx = ntb->mw_count - 1; 1264289543Scem else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14)) 1265289208Scem /* 1266289542Scem * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1267289542Scem * mirrored to the remote system. Shrink the number of bits by one, 1268289542Scem * since bit 14 is the last bit. 1269289542Scem * 1270289542Scem * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1271289542Scem * anyway. Nor for non-B2B connection types. 1272289542Scem */ 1273289543Scem ntb->db_count = XEON_DB_COUNT - 1; 1274250079Scarl 1275289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1276250079Scarl 1277289542Scem if (ntb->dev_type == NTB_DEV_USD) 1278289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1279289542Scem &xeon_b2b_usd_addr); 1280289542Scem else 1281289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1282289542Scem &xeon_b2b_dsd_addr); 1283289542Scem if (rc != 0) 1284289542Scem return (rc); 1285289271Scem 1286250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1287290682Scem ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1288289542Scem PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1289255279Scarl 1290290682Scem /* 1291290682Scem * Mask all doorbell interrupts. 1292290682Scem */ 1293290682Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 1294250079Scarl 1295290682Scem rc = ntb_init_isr(ntb); 1296290682Scem return (rc); 1297250079Scarl} 1298250079Scarl 1299250079Scarlstatic int 1300289648Scemntb_atom_init_dev(struct ntb_softc *ntb) 1301250079Scarl{ 1302290682Scem int error; 1303250079Scarl 1304289348Scem KASSERT(ntb->conn_type == NTB_CONN_B2B, 1305289348Scem ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1306250079Scarl 1307289648Scem ntb->spad_count = ATOM_SPAD_COUNT; 1308289648Scem ntb->db_count = ATOM_DB_COUNT; 1309289648Scem ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1310289648Scem ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1311289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1312250079Scarl 1313289648Scem ntb->reg = &atom_reg; 1314289648Scem ntb->self_reg = &atom_pri_reg; 1315289648Scem ntb->peer_reg = &atom_b2b_reg; 1316289648Scem ntb->xlat_reg = &atom_sec_xlat; 1317289542Scem 1318250079Scarl /* 1319289648Scem * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1320250079Scarl * resolved. Mask transaction layer internal parity errors. 1321250079Scarl */ 1322250079Scarl pci_write_config(ntb->device, 0xFC, 0x4, 4); 1323250079Scarl 1324289648Scem configure_atom_secondary_side_bars(ntb); 1325250079Scarl 1326250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1327290682Scem ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1328250079Scarl PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1329289209Scem 1330290682Scem error = ntb_init_isr(ntb); 1331290682Scem if (error != 0) 1332290682Scem return (error); 1333290682Scem 1334289542Scem /* Initiate PCI-E link training */ 1335289546Scem ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1336250079Scarl 1337289648Scem callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1338289542Scem 1339250079Scarl return (0); 1340250079Scarl} 1341250079Scarl 1342289648Scem/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1343255279Scarlstatic void 1344289648Scemconfigure_atom_secondary_side_bars(struct ntb_softc *ntb) 1345255279Scarl{ 1346255279Scarl 1347255279Scarl if (ntb->dev_type == NTB_DEV_USD) { 1348289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1349289542Scem XEON_B2B_BAR2_DSD_ADDR64); 1350289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1351289542Scem XEON_B2B_BAR4_DSD_ADDR64); 1352289648Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64); 1353289648Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64); 1354255279Scarl } else { 1355289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1356289542Scem XEON_B2B_BAR2_USD_ADDR64); 1357289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1358289542Scem XEON_B2B_BAR4_USD_ADDR64); 1359289648Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64); 1360289648Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64); 1361255279Scarl } 1362255279Scarl} 1363255279Scarl 1364289543Scem 1365289543Scem/* 1366289543Scem * When working around Xeon SDOORBELL errata by remapping remote registers in a 1367289543Scem * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1368289543Scem * remains for use by a higher layer. 1369289543Scem * 1370289543Scem * Will only be used if working around SDOORBELL errata and the BIOS-configured 1371289543Scem * MW size is sufficiently large. 1372289543Scem */ 1373289543Scemstatic unsigned int ntb_b2b_mw_share; 1374289543ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1375289543Scem 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1376289543Scem "MW with higher level consumers. Both sides of the NTB MUST set the same " 1377289543Scem "value here."); 1378289543Scem 1379289543Scemstatic void 1380289543Scemxeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1381289543Scem enum ntb_bar regbar) 1382289543Scem{ 1383289543Scem struct ntb_pci_bar_info *bar; 1384289543Scem uint8_t bar_sz; 1385289543Scem 1386289543Scem if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1387289543Scem return; 1388289543Scem 1389289543Scem bar = &ntb->bar_info[idx]; 1390289543Scem bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1391289543Scem if (idx == regbar) { 1392289543Scem if (ntb->b2b_off != 0) 1393289543Scem bar_sz--; 1394289543Scem else 1395289543Scem bar_sz = 0; 1396289543Scem } 1397289543Scem pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1398289543Scem bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1399289543Scem (void)bar_sz; 1400289543Scem} 1401289543Scem 1402289543Scemstatic void 1403289546Scemxeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1404289543Scem enum ntb_bar idx, enum ntb_bar regbar) 1405289543Scem{ 1406289546Scem uint64_t reg_val; 1407289546Scem uint32_t base_reg, lmt_reg; 1408289543Scem 1409289546Scem bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1410289546Scem if (idx == regbar) 1411289546Scem bar_addr += ntb->b2b_off; 1412289543Scem 1413289546Scem if (!bar_is_64bit(ntb, idx)) { 1414289546Scem ntb_reg_write(4, base_reg, bar_addr); 1415289546Scem reg_val = ntb_reg_read(4, base_reg); 1416289546Scem (void)reg_val; 1417289546Scem 1418289546Scem ntb_reg_write(4, lmt_reg, bar_addr); 1419289546Scem reg_val = ntb_reg_read(4, lmt_reg); 1420289546Scem (void)reg_val; 1421289543Scem } else { 1422289546Scem ntb_reg_write(8, base_reg, bar_addr); 1423289546Scem reg_val = ntb_reg_read(8, base_reg); 1424289546Scem (void)reg_val; 1425289546Scem 1426289546Scem ntb_reg_write(8, lmt_reg, bar_addr); 1427289546Scem reg_val = ntb_reg_read(8, lmt_reg); 1428289546Scem (void)reg_val; 1429289543Scem } 1430289543Scem} 1431289543Scem 1432289543Scemstatic void 1433289543Scemxeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1434289543Scem{ 1435289543Scem struct ntb_pci_bar_info *bar; 1436289543Scem 1437289543Scem bar = &ntb->bar_info[idx]; 1438289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1439289543Scem ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1440289543Scem base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1441289543Scem } else { 1442289543Scem ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1443289543Scem base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1444289543Scem } 1445289543Scem (void)base_addr; 1446289543Scem} 1447289543Scem 1448289542Scemstatic int 1449289542Scemxeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1450289542Scem const struct ntb_b2b_addr *peer_addr) 1451255279Scarl{ 1452289543Scem struct ntb_pci_bar_info *b2b_bar; 1453289543Scem vm_size_t bar_size; 1454289543Scem uint64_t bar_addr; 1455289543Scem enum ntb_bar b2b_bar_num, i; 1456255279Scarl 1457289543Scem if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1458289543Scem b2b_bar = NULL; 1459289543Scem b2b_bar_num = NTB_CONFIG_BAR; 1460289543Scem ntb->b2b_off = 0; 1461289543Scem } else { 1462289543Scem b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1463289543Scem KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1464289543Scem ("invalid b2b mw bar")); 1465289543Scem 1466289543Scem b2b_bar = &ntb->bar_info[b2b_bar_num]; 1467289543Scem bar_size = b2b_bar->size; 1468289543Scem 1469289543Scem if (ntb_b2b_mw_share != 0 && 1470289543Scem (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1471289543Scem ntb->b2b_off = bar_size >> 1; 1472289543Scem else if (bar_size >= XEON_B2B_MIN_SIZE) { 1473289543Scem ntb->b2b_off = 0; 1474289543Scem ntb->mw_count--; 1475289543Scem } else { 1476289543Scem device_printf(ntb->device, 1477289543Scem "B2B bar size is too small!\n"); 1478289543Scem return (EIO); 1479289543Scem } 1480255279Scarl } 1481289542Scem 1482289543Scem /* 1483289543Scem * Reset the secondary bar sizes to match the primary bar sizes. 1484289543Scem * (Except, disable or halve the size of the B2B secondary bar.) 1485289543Scem */ 1486289543Scem for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1487289543Scem xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1488289543Scem 1489289543Scem bar_addr = 0; 1490289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1491289543Scem bar_addr = addr->bar0_addr; 1492289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1493289543Scem bar_addr = addr->bar2_addr64; 1494289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1495289543Scem bar_addr = addr->bar4_addr64; 1496289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1497289543Scem bar_addr = addr->bar4_addr32; 1498289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1499289543Scem bar_addr = addr->bar5_addr32; 1500289543Scem else 1501289543Scem KASSERT(false, ("invalid bar")); 1502289543Scem 1503289543Scem ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1504289543Scem 1505289543Scem /* 1506289543Scem * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1507289543Scem * register BAR. The B2B BAR is either disabled above or configured 1508289543Scem * half-size. It starts at PBAR xlat + offset. 1509289543Scem * 1510289543Scem * Also set up incoming BAR limits == base (zero length window). 1511289543Scem */ 1512289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1513289543Scem b2b_bar_num); 1514289542Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1515289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1516289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1517289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1518289543Scem NTB_B2B_BAR_3, b2b_bar_num); 1519289542Scem } else 1520289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1521289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1522289543Scem 1523289543Scem /* Zero incoming translation addrs */ 1524289543Scem ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1525289543Scem ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1526289543Scem 1527289543Scem /* Zero outgoing translation limits (whole bar size windows) */ 1528289543Scem ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1529289543Scem ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1530289543Scem 1531289543Scem /* Set outgoing translation offsets */ 1532289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1533289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1534289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1535289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1536289543Scem } else 1537289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1538289543Scem 1539289543Scem /* Set the translation offset for B2B registers */ 1540289543Scem bar_addr = 0; 1541289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1542289543Scem bar_addr = peer_addr->bar0_addr; 1543289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1544289543Scem bar_addr = peer_addr->bar2_addr64; 1545289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1546289543Scem bar_addr = peer_addr->bar4_addr64; 1547289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1548289543Scem bar_addr = peer_addr->bar4_addr32; 1549289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1550289543Scem bar_addr = peer_addr->bar5_addr32; 1551289543Scem else 1552289543Scem KASSERT(false, ("invalid bar")); 1553289543Scem 1554289543Scem /* 1555289543Scem * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1556289543Scem * at a time. 1557289543Scem */ 1558289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1559289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1560289542Scem return (0); 1561255279Scarl} 1562255279Scarl 1563289546Scemstatic inline bool 1564289546Scemlink_is_up(struct ntb_softc *ntb) 1565289546Scem{ 1566289546Scem 1567289611Scem if (ntb->type == NTB_XEON) { 1568289611Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1569289611Scem return (true); 1570289546Scem return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1571289611Scem } 1572289546Scem 1573289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1574289648Scem return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1575289546Scem} 1576289546Scem 1577289546Scemstatic inline bool 1578289648Scematom_link_is_err(struct ntb_softc *ntb) 1579289546Scem{ 1580289546Scem uint32_t status; 1581289546Scem 1582289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1583289546Scem 1584289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1585289648Scem if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1586289546Scem return (true); 1587289546Scem 1588289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1589289648Scem return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1590289546Scem} 1591289546Scem 1592289648Scem/* Atom does not have link status interrupt, poll on that platform */ 1593250079Scarlstatic void 1594289648Scematom_link_hb(void *arg) 1595250079Scarl{ 1596250079Scarl struct ntb_softc *ntb = arg; 1597289546Scem sbintime_t timo, poll_ts; 1598250079Scarl 1599289546Scem timo = NTB_HB_TIMEOUT * hz; 1600289546Scem poll_ts = ntb->last_ts + timo; 1601289546Scem 1602289542Scem /* 1603289542Scem * Delay polling the link status if an interrupt was received, unless 1604289542Scem * the cached link status says the link is down. 1605289542Scem */ 1606289546Scem if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1607289546Scem timo = poll_ts - ticks; 1608289542Scem goto out; 1609289546Scem } 1610289542Scem 1611289546Scem if (ntb_poll_link(ntb)) 1612289546Scem ntb_link_event(ntb); 1613289542Scem 1614289648Scem if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1615289546Scem /* Link is down with error, proceed with recovery */ 1616289648Scem callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1617289546Scem return; 1618250079Scarl } 1619250079Scarl 1620289542Scemout: 1621289648Scem callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1622250079Scarl} 1623250079Scarl 1624250079Scarlstatic void 1625289648Scematom_perform_link_restart(struct ntb_softc *ntb) 1626250079Scarl{ 1627250079Scarl uint32_t status; 1628250079Scarl 1629250079Scarl /* Driver resets the NTB ModPhy lanes - magic! */ 1630289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1631289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1632289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1633289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1634250079Scarl 1635250079Scarl /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1636250079Scarl pause("ModPhy", hz / 10); 1637250079Scarl 1638250079Scarl /* Clear AER Errors, write to clear */ 1639289648Scem status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1640250079Scarl status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1641289648Scem ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1642250079Scarl 1643250079Scarl /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1644289648Scem status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1645289648Scem status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1646289648Scem ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1647250079Scarl 1648250079Scarl /* Clear DeSkew Buffer error, write to clear */ 1649289648Scem status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1650289648Scem status |= ATOM_DESKEWSTS_DBERR; 1651289648Scem ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1652250079Scarl 1653289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1654289648Scem status &= ATOM_IBIST_ERR_OFLOW; 1655289648Scem ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1656250079Scarl 1657250079Scarl /* Releases the NTB state machine to allow the link to retrain */ 1658289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1659289648Scem status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1660289648Scem ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1661250079Scarl} 1662250079Scarl 1663289546Scem/* 1664289546Scem * ntb_set_ctx() - associate a driver context with an ntb device 1665289546Scem * @ntb: NTB device context 1666289546Scem * @ctx: Driver context 1667289546Scem * @ctx_ops: Driver context operations 1668289546Scem * 1669289546Scem * Associate a driver context and operations with a ntb device. The context is 1670289546Scem * provided by the client driver, and the driver may associate a different 1671289546Scem * context with each ntb device. 1672289546Scem * 1673289546Scem * Return: Zero if the context is associated, otherwise an error number. 1674289546Scem */ 1675289546Scemint 1676289546Scemntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops) 1677250079Scarl{ 1678250079Scarl 1679289546Scem if (ctx == NULL || ops == NULL) 1680289546Scem return (EINVAL); 1681289546Scem if (ntb->ctx_ops != NULL) 1682289546Scem return (EINVAL); 1683250079Scarl 1684289546Scem CTX_LOCK(ntb); 1685289546Scem if (ntb->ctx_ops != NULL) { 1686289546Scem CTX_UNLOCK(ntb); 1687289546Scem return (EINVAL); 1688250079Scarl } 1689289546Scem ntb->ntb_ctx = ctx; 1690289546Scem ntb->ctx_ops = ops; 1691289546Scem CTX_UNLOCK(ntb); 1692250079Scarl 1693289546Scem return (0); 1694250079Scarl} 1695250079Scarl 1696289546Scem/* 1697289546Scem * It is expected that this will only be used from contexts where the ctx_lock 1698289546Scem * is not needed to protect ntb_ctx lifetime. 1699289546Scem */ 1700289546Scemvoid * 1701289546Scemntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops) 1702289546Scem{ 1703289546Scem 1704289546Scem KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 1705289546Scem if (ops != NULL) 1706289546Scem *ops = ntb->ctx_ops; 1707289546Scem return (ntb->ntb_ctx); 1708289546Scem} 1709289546Scem 1710289546Scem/* 1711289546Scem * ntb_clear_ctx() - disassociate any driver context from an ntb device 1712289546Scem * @ntb: NTB device context 1713289546Scem * 1714289546Scem * Clear any association that may exist between a driver context and the ntb 1715289546Scem * device. 1716289546Scem */ 1717289546Scemvoid 1718289546Scemntb_clear_ctx(struct ntb_softc *ntb) 1719289546Scem{ 1720289546Scem 1721289546Scem CTX_LOCK(ntb); 1722289546Scem ntb->ntb_ctx = NULL; 1723289546Scem ntb->ctx_ops = NULL; 1724289546Scem CTX_UNLOCK(ntb); 1725289546Scem} 1726289546Scem 1727289546Scem/* 1728289546Scem * ntb_link_event() - notify driver context of a change in link status 1729289546Scem * @ntb: NTB device context 1730289546Scem * 1731289546Scem * Notify the driver context that the link status may have changed. The driver 1732289546Scem * should call ntb_link_is_up() to get the current status. 1733289546Scem */ 1734289546Scemvoid 1735289546Scemntb_link_event(struct ntb_softc *ntb) 1736289546Scem{ 1737289546Scem 1738289546Scem CTX_LOCK(ntb); 1739289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 1740289546Scem ntb->ctx_ops->link_event(ntb->ntb_ctx); 1741289546Scem CTX_UNLOCK(ntb); 1742289546Scem} 1743289546Scem 1744289546Scem/* 1745289546Scem * ntb_db_event() - notify driver context of a doorbell event 1746289546Scem * @ntb: NTB device context 1747289546Scem * @vector: Interrupt vector number 1748289546Scem * 1749289546Scem * Notify the driver context of a doorbell event. If hardware supports 1750289546Scem * multiple interrupt vectors for doorbells, the vector number indicates which 1751289546Scem * vector received the interrupt. The vector number is relative to the first 1752289546Scem * vector used for doorbells, starting at zero, and must be less than 1753289546Scem * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 1754289546Scem * doorbell bits need service, and ntb_db_vector_mask() to determine which of 1755289546Scem * those bits are associated with the vector number. 1756289546Scem */ 1757250079Scarlstatic void 1758289546Scemntb_db_event(struct ntb_softc *ntb, uint32_t vec) 1759289272Scem{ 1760289546Scem 1761289546Scem CTX_LOCK(ntb); 1762289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 1763289546Scem ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 1764289546Scem CTX_UNLOCK(ntb); 1765289546Scem} 1766289546Scem 1767289546Scem/* 1768289546Scem * ntb_link_enable() - enable the link on the secondary side of the ntb 1769289546Scem * @ntb: NTB device context 1770289546Scem * @max_speed: The maximum link speed expressed as PCIe generation number[0] 1771289546Scem * @max_width: The maximum link width expressed as the number of PCIe lanes[0] 1772289546Scem * 1773289546Scem * Enable the link on the secondary side of the ntb. This can only be done 1774289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1775289546Scem * should train the link to its maximum speed and width, or the requested speed 1776289546Scem * and width, whichever is smaller, if supported. 1777289546Scem * 1778289546Scem * Return: Zero on success, otherwise an error number. 1779289546Scem * 1780289546Scem * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed 1781289546Scem * and width input will be ignored. 1782289546Scem */ 1783289546Scemint 1784289546Scemntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, 1785289546Scem enum ntb_width w __unused) 1786289546Scem{ 1787289280Scem uint32_t cntl; 1788289272Scem 1789289648Scem if (ntb->type == NTB_ATOM) { 1790289542Scem pci_write_config(ntb->device, NTB_PPD_OFFSET, 1791289648Scem ntb->ppd | ATOM_PPD_INIT_LINK, 4); 1792289546Scem return (0); 1793289542Scem } 1794289542Scem 1795289280Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1796289546Scem ntb_link_event(ntb); 1797289546Scem return (0); 1798289280Scem } 1799289280Scem 1800289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1801289280Scem cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 1802289280Scem cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 1803289397Scem cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 1804289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1805289397Scem cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 1806289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1807289546Scem return (0); 1808289272Scem} 1809289272Scem 1810289546Scem/* 1811289546Scem * ntb_link_disable() - disable the link on the secondary side of the ntb 1812289546Scem * @ntb: NTB device context 1813289546Scem * 1814289546Scem * Disable the link on the secondary side of the ntb. This can only be done 1815289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1816289546Scem * should disable the link. Returning from this call must indicate that a 1817289546Scem * barrier has passed, though with no more writes may pass in either direction 1818289546Scem * across the link, except if this call returns an error number. 1819289546Scem * 1820289546Scem * Return: Zero on success, otherwise an error number. 1821289546Scem */ 1822289546Scemint 1823289542Scemntb_link_disable(struct ntb_softc *ntb) 1824289272Scem{ 1825289272Scem uint32_t cntl; 1826289272Scem 1827289272Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1828289546Scem ntb_link_event(ntb); 1829289546Scem return (0); 1830289272Scem } 1831289272Scem 1832289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1833289280Scem cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 1834289397Scem cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 1835289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1836289397Scem cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 1837289280Scem cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 1838289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1839289546Scem return (0); 1840289272Scem} 1841289272Scem 1842289272Scemstatic void 1843289648Scemrecover_atom_link(void *arg) 1844250079Scarl{ 1845250079Scarl struct ntb_softc *ntb = arg; 1846289608Scem unsigned speed, width, oldspeed, oldwidth; 1847250079Scarl uint32_t status32; 1848250079Scarl 1849289648Scem atom_perform_link_restart(ntb); 1850250079Scarl 1851289232Scem /* 1852289232Scem * There is a potential race between the 2 NTB devices recovering at 1853289232Scem * the same time. If the times are the same, the link will not recover 1854289232Scem * and the driver will be stuck in this loop forever. Add a random 1855289232Scem * interval to the recovery time to prevent this race. 1856289232Scem */ 1857289648Scem status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 1858289648Scem pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 1859289232Scem 1860289648Scem if (atom_link_is_err(ntb)) 1861250079Scarl goto retry; 1862250079Scarl 1863289542Scem status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 1864289648Scem if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 1865289232Scem goto out; 1866289232Scem 1867289542Scem status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 1868289608Scem width = NTB_LNK_STA_WIDTH(status32); 1869289608Scem speed = status32 & NTB_LINK_SPEED_MASK; 1870289608Scem 1871289608Scem oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 1872289608Scem oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 1873289608Scem if (oldwidth != width || oldspeed != speed) 1874250079Scarl goto retry; 1875250079Scarl 1876289232Scemout: 1877289648Scem callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 1878289542Scem ntb); 1879250079Scarl return; 1880250079Scarl 1881250079Scarlretry: 1882289648Scem callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 1883250079Scarl ntb); 1884250079Scarl} 1885250079Scarl 1886289546Scem/* 1887289546Scem * Polls the HW link status register(s); returns true if something has changed. 1888289546Scem */ 1889289546Scemstatic bool 1890289542Scemntb_poll_link(struct ntb_softc *ntb) 1891250079Scarl{ 1892250079Scarl uint32_t ntb_cntl; 1893289546Scem uint16_t reg_val; 1894250079Scarl 1895289648Scem if (ntb->type == NTB_ATOM) { 1896289542Scem ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1897289546Scem if (ntb_cntl == ntb->ntb_ctl) 1898289546Scem return (false); 1899289546Scem 1900289542Scem ntb->ntb_ctl = ntb_cntl; 1901289542Scem ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 1902250079Scarl } else { 1903290678Scem db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 1904250079Scarl 1905289546Scem reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 1906289546Scem if (reg_val == ntb->lnk_sta) 1907289546Scem return (false); 1908250079Scarl 1909289546Scem ntb->lnk_sta = reg_val; 1910289542Scem } 1911289546Scem return (true); 1912289542Scem} 1913289542Scem 1914289546Scemstatic inline enum ntb_speed 1915289546Scemntb_link_sta_speed(struct ntb_softc *ntb) 1916250079Scarl{ 1917250079Scarl 1918289546Scem if (!link_is_up(ntb)) 1919289546Scem return (NTB_SPEED_NONE); 1920289546Scem return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 1921250079Scarl} 1922250079Scarl 1923289546Scemstatic inline enum ntb_width 1924289546Scemntb_link_sta_width(struct ntb_softc *ntb) 1925250079Scarl{ 1926250079Scarl 1927289546Scem if (!link_is_up(ntb)) 1928289546Scem return (NTB_WIDTH_NONE); 1929289546Scem return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 1930250079Scarl} 1931250079Scarl 1932289774ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 1933289774Scem "Driver state, statistics, and HW registers"); 1934289774Scem 1935289774Scem#define NTB_REGSZ_MASK (3ul << 30) 1936289774Scem#define NTB_REG_64 (1ul << 30) 1937289774Scem#define NTB_REG_32 (2ul << 30) 1938289774Scem#define NTB_REG_16 (3ul << 30) 1939289774Scem#define NTB_REG_8 (0ul << 30) 1940289774Scem 1941289774Scem#define NTB_DB_READ (1ul << 29) 1942289774Scem#define NTB_PCI_REG (1ul << 28) 1943289774Scem#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 1944289774Scem 1945289774Scemstatic void 1946289774Scemntb_sysctl_init(struct ntb_softc *ntb) 1947289774Scem{ 1948289774Scem struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; 1949289774Scem struct sysctl_ctx_list *ctx; 1950289774Scem struct sysctl_oid *tree, *tmptree; 1951289774Scem 1952289774Scem ctx = device_get_sysctl_ctx(ntb->device); 1953289774Scem 1954289774Scem tree = SYSCTL_ADD_NODE(ctx, 1955289774Scem SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, 1956289774Scem "debug_info", CTLFLAG_RD, NULL, 1957289774Scem "Driver state, statistics, and HW registers"); 1958289774Scem tree_par = SYSCTL_CHILDREN(tree); 1959289774Scem 1960289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 1961289774Scem &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 1962289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 1963289774Scem &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 1964289774Scem 1965289774Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 1966289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 1967289774Scem &ntb->b2b_mw_idx, 0, 1968289774Scem "Index of the MW used for B2B remote register access"); 1969289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 1970289774Scem CTLFLAG_RD, &ntb->b2b_off, 1971289774Scem "If non-zero, offset of B2B register region in shared MW"); 1972289774Scem } 1973289774Scem 1974289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 1975289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 1976289774Scem "Features/errata of this NTB device"); 1977289774Scem 1978289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 1979289774Scem &ntb->ntb_ctl, 0, "NTB CTL register (cached)"); 1980289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 1981289774Scem &ntb->lnk_sta, 0, "LNK STA register (cached)"); 1982289774Scem 1983289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", 1984289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, 1985289774Scem "A", "Link status"); 1986289774Scem 1987289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 1988289774Scem &ntb->mw_count, 0, "MW count (excl. non-shared B2B register BAR)"); 1989289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 1990289774Scem &ntb->spad_count, 0, "Scratchpad count"); 1991289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 1992289774Scem &ntb->db_count, 0, "Doorbell count"); 1993289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 1994289774Scem &ntb->db_vec_count, 0, "Doorbell vector count"); 1995289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 1996289774Scem &ntb->db_vec_shift, 0, "Doorbell vector shift"); 1997289774Scem 1998289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 1999289774Scem &ntb->db_valid_mask, "Doorbell valid mask"); 2000289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2001289774Scem &ntb->db_link_mask, "Doorbell link mask"); 2002289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2003289774Scem &ntb->db_mask, "Doorbell mask (cached)"); 2004289774Scem 2005289774Scem tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2006289774Scem CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 2007289774Scem regpar = SYSCTL_CHILDREN(tmptree); 2008289774Scem 2009290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2010290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2011290682Scem ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2012290682Scem "NTB Control register"); 2013290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2014290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2015290682Scem 0x19c, sysctl_handle_register, "IU", 2016290682Scem "NTB Link Capabilities"); 2017290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2018290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2019290682Scem 0x1a0, sysctl_handle_register, "IU", 2020290682Scem "NTB Link Control register"); 2021290682Scem 2022289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2023289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2024289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2025289774Scem sysctl_handle_register, "QU", "Doorbell mask register"); 2026289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2027289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2028289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2029289774Scem sysctl_handle_register, "QU", "Doorbell register"); 2030289774Scem 2031289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2032289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2033289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2034289774Scem sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2035289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2036289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2037289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2038289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2039289774Scem sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2040289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2041289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2042289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2043289774Scem sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2044289774Scem } else { 2045289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2046289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2047289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2048289774Scem sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2049289774Scem } 2050289774Scem 2051289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2052289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2053289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2054289774Scem sysctl_handle_register, "QU", "Incoming LMT23 register"); 2055289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2056289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2057289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2058289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2059289774Scem sysctl_handle_register, "IU", "Incoming LMT4 register"); 2060289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2061289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2062289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2063289774Scem sysctl_handle_register, "IU", "Incoming LMT5 register"); 2064289774Scem } else { 2065289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2066289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2067289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2068289774Scem sysctl_handle_register, "QU", "Incoming LMT45 register"); 2069289774Scem } 2070289774Scem 2071289774Scem if (ntb->type == NTB_ATOM) 2072289774Scem return; 2073289774Scem 2074289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2075289774Scem CTLFLAG_RD, NULL, "Xeon HW statistics"); 2076289774Scem statpar = SYSCTL_CHILDREN(tmptree); 2077289774Scem SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2078289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2079289774Scem NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2080289774Scem sysctl_handle_register, "SU", "Upstream Memory Miss"); 2081289774Scem 2082289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2083289774Scem CTLFLAG_RD, NULL, "Xeon HW errors"); 2084289774Scem errpar = SYSCTL_CHILDREN(tmptree); 2085289774Scem 2086289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "devsts", 2087289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2088289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2089289774Scem sysctl_handle_register, "SU", "DEVSTS"); 2090289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "lnksts", 2091289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2092289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2093289774Scem sysctl_handle_register, "SU", "LNKSTS"); 2094289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2095289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2096289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2097289774Scem sysctl_handle_register, "IU", "UNCERRSTS"); 2098289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2099289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2100289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2101289774Scem sysctl_handle_register, "IU", "CORERRSTS"); 2102289774Scem 2103289774Scem if (ntb->conn_type != NTB_CONN_B2B) 2104289774Scem return; 2105289774Scem 2106289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2107289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2108289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2109289774Scem sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2110289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2111289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2112289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2113289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2114289774Scem sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2115289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2116289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2117289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2118289774Scem sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2119289774Scem } else { 2120289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2121289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2122289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2123289774Scem sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2124289774Scem } 2125289774Scem 2126289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2127289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2128289774Scem NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2129289774Scem sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2130289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2131289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2132289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2133289774Scem NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2134289774Scem sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2135289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2136289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2137289774Scem NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2138289774Scem sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2139289774Scem } else { 2140289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2141289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2142289774Scem NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2143289774Scem sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2144289774Scem } 2145289774Scem 2146289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2147289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2148289774Scem NTB_REG_64 | ntb->xlat_reg->bar0_base, 2149289774Scem sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2150289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2151289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2152289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_base, 2153289774Scem sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2154289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2155289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2156289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2157289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_base, 2158289774Scem sysctl_handle_register, "IU", 2159289774Scem "Secondary BAR4 base register"); 2160289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2161289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2162289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_base, 2163289774Scem sysctl_handle_register, "IU", 2164289774Scem "Secondary BAR5 base register"); 2165289774Scem } else { 2166289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2167289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2168289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_base, 2169289774Scem sysctl_handle_register, "QU", 2170289774Scem "Secondary BAR45 base register"); 2171289774Scem } 2172289774Scem} 2173289774Scem 2174289774Scemstatic int 2175289774Scemsysctl_handle_features(SYSCTL_HANDLER_ARGS) 2176289774Scem{ 2177289774Scem struct ntb_softc *ntb; 2178289774Scem struct sbuf sb; 2179289774Scem int error; 2180289774Scem 2181289774Scem error = 0; 2182289774Scem ntb = arg1; 2183289774Scem 2184289774Scem sbuf_new_for_sysctl(&sb, NULL, 256, req); 2185289774Scem 2186289774Scem sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2187289774Scem error = sbuf_finish(&sb); 2188289774Scem sbuf_delete(&sb); 2189289774Scem 2190289774Scem if (error || !req->newptr) 2191289774Scem return (error); 2192289774Scem return (EINVAL); 2193289774Scem} 2194289774Scem 2195289774Scemstatic int 2196289774Scemsysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2197289774Scem{ 2198289774Scem struct ntb_softc *ntb; 2199289774Scem struct sbuf sb; 2200289774Scem enum ntb_speed speed; 2201289774Scem enum ntb_width width; 2202289774Scem int error; 2203289774Scem 2204289774Scem error = 0; 2205289774Scem ntb = arg1; 2206289774Scem 2207289774Scem sbuf_new_for_sysctl(&sb, NULL, 32, req); 2208289774Scem 2209289774Scem if (ntb_link_is_up(ntb, &speed, &width)) 2210289774Scem sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2211289774Scem (unsigned)speed, (unsigned)width); 2212289774Scem else 2213289774Scem sbuf_printf(&sb, "down"); 2214289774Scem 2215289774Scem error = sbuf_finish(&sb); 2216289774Scem sbuf_delete(&sb); 2217289774Scem 2218289774Scem if (error || !req->newptr) 2219289774Scem return (error); 2220289774Scem return (EINVAL); 2221289774Scem} 2222289774Scem 2223289774Scemstatic int 2224289774Scemsysctl_handle_register(SYSCTL_HANDLER_ARGS) 2225289774Scem{ 2226289774Scem struct ntb_softc *ntb; 2227289774Scem const void *outp; 2228289774Scem uintptr_t sz; 2229289774Scem uint64_t umv; 2230289774Scem char be[sizeof(umv)]; 2231289774Scem size_t outsz; 2232289774Scem uint32_t reg; 2233289774Scem bool db, pci; 2234289774Scem int error; 2235289774Scem 2236289774Scem ntb = arg1; 2237289774Scem reg = arg2 & ~NTB_REGFLAGS_MASK; 2238289774Scem sz = arg2 & NTB_REGSZ_MASK; 2239289774Scem db = (arg2 & NTB_DB_READ) != 0; 2240289774Scem pci = (arg2 & NTB_PCI_REG) != 0; 2241289774Scem 2242289774Scem KASSERT(!(db && pci), ("bogus")); 2243289774Scem 2244289774Scem if (db) { 2245289774Scem KASSERT(sz == NTB_REG_64, ("bogus")); 2246289774Scem umv = db_ioread(ntb, reg); 2247289774Scem outsz = sizeof(uint64_t); 2248289774Scem } else { 2249289774Scem switch (sz) { 2250289774Scem case NTB_REG_64: 2251289774Scem if (pci) 2252289774Scem umv = pci_read_config(ntb->device, reg, 8); 2253289774Scem else 2254289774Scem umv = ntb_reg_read(8, reg); 2255289774Scem outsz = sizeof(uint64_t); 2256289774Scem break; 2257289774Scem case NTB_REG_32: 2258289774Scem if (pci) 2259289774Scem umv = pci_read_config(ntb->device, reg, 4); 2260289774Scem else 2261289774Scem umv = ntb_reg_read(4, reg); 2262289774Scem outsz = sizeof(uint32_t); 2263289774Scem break; 2264289774Scem case NTB_REG_16: 2265289774Scem if (pci) 2266289774Scem umv = pci_read_config(ntb->device, reg, 2); 2267289774Scem else 2268289774Scem umv = ntb_reg_read(2, reg); 2269289774Scem outsz = sizeof(uint16_t); 2270289774Scem break; 2271289774Scem case NTB_REG_8: 2272289774Scem if (pci) 2273289774Scem umv = pci_read_config(ntb->device, reg, 1); 2274289774Scem else 2275289774Scem umv = ntb_reg_read(1, reg); 2276289774Scem outsz = sizeof(uint8_t); 2277289774Scem break; 2278289774Scem default: 2279289774Scem panic("bogus"); 2280289774Scem break; 2281289774Scem } 2282289774Scem } 2283289774Scem 2284289774Scem /* Encode bigendian so that sysctl -x is legible. */ 2285289774Scem be64enc(be, umv); 2286289774Scem outp = ((char *)be) + sizeof(umv) - outsz; 2287289774Scem 2288289774Scem error = SYSCTL_OUT(req, outp, outsz); 2289289774Scem if (error || !req->newptr) 2290289774Scem return (error); 2291289774Scem return (EINVAL); 2292289774Scem} 2293289774Scem 2294289546Scem/* 2295289546Scem * Public API to the rest of the OS 2296250079Scarl */ 2297250079Scarl 2298250079Scarl/** 2299250079Scarl * ntb_get_max_spads() - get the total scratch regs usable 2300250079Scarl * @ntb: pointer to ntb_softc instance 2301250079Scarl * 2302250079Scarl * This function returns the max 32bit scratchpad registers usable by the 2303250079Scarl * upper layer. 2304250079Scarl * 2305250079Scarl * RETURNS: total number of scratch pad registers available 2306250079Scarl */ 2307289208Scemuint8_t 2308250079Scarlntb_get_max_spads(struct ntb_softc *ntb) 2309250079Scarl{ 2310250079Scarl 2311289539Scem return (ntb->spad_count); 2312250079Scarl} 2313250079Scarl 2314289396Scemuint8_t 2315289539Scemntb_mw_count(struct ntb_softc *ntb) 2316289396Scem{ 2317289396Scem 2318289539Scem return (ntb->mw_count); 2319289396Scem} 2320289396Scem 2321250079Scarl/** 2322289545Scem * ntb_spad_write() - write to the secondary scratchpad register 2323250079Scarl * @ntb: pointer to ntb_softc instance 2324250079Scarl * @idx: index to the scratchpad register, 0 based 2325250079Scarl * @val: the data value to put into the register 2326250079Scarl * 2327250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2328250079Scarl * register. The register resides on the secondary (external) side. 2329250079Scarl * 2330289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2331250079Scarl */ 2332250079Scarlint 2333289545Scemntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2334250079Scarl{ 2335250079Scarl 2336289539Scem if (idx >= ntb->spad_count) 2337250079Scarl return (EINVAL); 2338250079Scarl 2339289607Scem ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2340250079Scarl 2341250079Scarl return (0); 2342250079Scarl} 2343250079Scarl 2344250079Scarl/** 2345289545Scem * ntb_spad_read() - read from the primary scratchpad register 2346250079Scarl * @ntb: pointer to ntb_softc instance 2347250079Scarl * @idx: index to scratchpad register, 0 based 2348250079Scarl * @val: pointer to 32bit integer for storing the register value 2349250079Scarl * 2350250079Scarl * This function allows reading of the 32bit scratchpad register on 2351250079Scarl * the primary (internal) side. 2352250079Scarl * 2353289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2354250079Scarl */ 2355250079Scarlint 2356289545Scemntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2357250079Scarl{ 2358250079Scarl 2359289539Scem if (idx >= ntb->spad_count) 2360250079Scarl return (EINVAL); 2361250079Scarl 2362289607Scem *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2363250079Scarl 2364250079Scarl return (0); 2365250079Scarl} 2366250079Scarl 2367250079Scarl/** 2368289545Scem * ntb_peer_spad_write() - write to the secondary scratchpad register 2369250079Scarl * @ntb: pointer to ntb_softc instance 2370250079Scarl * @idx: index to the scratchpad register, 0 based 2371250079Scarl * @val: the data value to put into the register 2372250079Scarl * 2373250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2374250079Scarl * register. The register resides on the secondary (external) side. 2375250079Scarl * 2376289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2377250079Scarl */ 2378250079Scarlint 2379289545Scemntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2380250079Scarl{ 2381250079Scarl 2382289539Scem if (idx >= ntb->spad_count) 2383250079Scarl return (EINVAL); 2384250079Scarl 2385289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2386290682Scem ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2387255279Scarl else 2388289542Scem ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2389250079Scarl 2390250079Scarl return (0); 2391250079Scarl} 2392250079Scarl 2393250079Scarl/** 2394289545Scem * ntb_peer_spad_read() - read from the primary scratchpad register 2395250079Scarl * @ntb: pointer to ntb_softc instance 2396250079Scarl * @idx: index to scratchpad register, 0 based 2397250079Scarl * @val: pointer to 32bit integer for storing the register value 2398250079Scarl * 2399250079Scarl * This function allows reading of the 32bit scratchpad register on 2400250079Scarl * the primary (internal) side. 2401250079Scarl * 2402289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2403250079Scarl */ 2404250079Scarlint 2405289545Scemntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2406250079Scarl{ 2407250079Scarl 2408289539Scem if (idx >= ntb->spad_count) 2409250079Scarl return (EINVAL); 2410250079Scarl 2411289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2412290682Scem *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2413255279Scarl else 2414289542Scem *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2415250079Scarl 2416250079Scarl return (0); 2417250079Scarl} 2418250079Scarl 2419289546Scem/* 2420289546Scem * ntb_mw_get_range() - get the range of a memory window 2421289546Scem * @ntb: NTB device context 2422289546Scem * @idx: Memory window number 2423289546Scem * @base: OUT - the base address for mapping the memory window 2424289546Scem * @size: OUT - the size for mapping the memory window 2425289546Scem * @align: OUT - the base alignment for translating the memory window 2426289546Scem * @align_size: OUT - the size alignment for translating the memory window 2427250079Scarl * 2428289546Scem * Get the range of a memory window. NULL may be given for any output 2429289546Scem * parameter if the value is not needed. The base and size may be used for 2430289546Scem * mapping the memory window, to access the peer memory. The alignment and 2431289546Scem * size may be used for translating the memory window, for the peer to access 2432289546Scem * memory on the local system. 2433250079Scarl * 2434289546Scem * Return: Zero on success, otherwise an error number. 2435250079Scarl */ 2436289546Scemint 2437289546Scemntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base, 2438290679Scem caddr_t *vbase, size_t *size, size_t *align, size_t *align_size) 2439250079Scarl{ 2440289546Scem struct ntb_pci_bar_info *bar; 2441289546Scem size_t bar_b2b_off; 2442250079Scarl 2443289546Scem if (mw_idx >= ntb_mw_count(ntb)) 2444289546Scem return (EINVAL); 2445250079Scarl 2446289546Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, mw_idx)]; 2447289546Scem bar_b2b_off = 0; 2448289546Scem if (mw_idx == ntb->b2b_mw_idx) { 2449289546Scem KASSERT(ntb->b2b_off != 0, 2450289546Scem ("user shouldn't get non-shared b2b mw")); 2451289546Scem bar_b2b_off = ntb->b2b_off; 2452289546Scem } 2453250079Scarl 2454289546Scem if (base != NULL) 2455289546Scem *base = bar->pbase + bar_b2b_off; 2456289546Scem if (vbase != NULL) 2457290679Scem *vbase = bar->vbase + bar_b2b_off; 2458289546Scem if (size != NULL) 2459289546Scem *size = bar->size - bar_b2b_off; 2460289546Scem if (align != NULL) 2461289546Scem *align = bar->size; 2462289546Scem if (align_size != NULL) 2463289546Scem *align_size = 1; 2464289546Scem return (0); 2465250079Scarl} 2466250079Scarl 2467289546Scem/* 2468289546Scem * ntb_mw_set_trans() - set the translation of a memory window 2469289546Scem * @ntb: NTB device context 2470289546Scem * @idx: Memory window number 2471289546Scem * @addr: The dma address local memory to expose to the peer 2472289546Scem * @size: The size of the local memory to expose to the peer 2473250079Scarl * 2474289546Scem * Set the translation of a memory window. The peer may access local memory 2475289546Scem * through the window starting at the address, up to the size. The address 2476289546Scem * must be aligned to the alignment specified by ntb_mw_get_range(). The size 2477289546Scem * must be aligned to the size alignment specified by ntb_mw_get_range(). 2478250079Scarl * 2479289546Scem * Return: Zero on success, otherwise an error number. 2480250079Scarl */ 2481289546Scemint 2482289546Scemntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr, 2483289546Scem size_t size) 2484250079Scarl{ 2485289546Scem struct ntb_pci_bar_info *bar; 2486289546Scem uint64_t base, limit, reg_val; 2487289546Scem size_t bar_size, mw_size; 2488289546Scem uint32_t base_reg, xlat_reg, limit_reg; 2489289546Scem enum ntb_bar bar_num; 2490250079Scarl 2491289546Scem if (idx >= ntb_mw_count(ntb)) 2492289546Scem return (EINVAL); 2493250079Scarl 2494289546Scem bar_num = ntb_mw_to_bar(ntb, idx); 2495289546Scem bar = &ntb->bar_info[bar_num]; 2496250079Scarl 2497289546Scem bar_size = bar->size; 2498289546Scem if (idx == ntb->b2b_mw_idx) 2499289546Scem mw_size = bar_size - ntb->b2b_off; 2500289546Scem else 2501289546Scem mw_size = bar_size; 2502250079Scarl 2503289546Scem /* Hardware requires that addr is aligned to bar size */ 2504289546Scem if ((addr & (bar_size - 1)) != 0) 2505289546Scem return (EINVAL); 2506250079Scarl 2507289546Scem if (size > mw_size) 2508289546Scem return (EINVAL); 2509289546Scem 2510289546Scem bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2511289546Scem 2512289546Scem limit = 0; 2513289546Scem if (bar_is_64bit(ntb, bar_num)) { 2514289546Scem base = ntb_reg_read(8, base_reg); 2515289546Scem 2516289546Scem if (limit_reg != 0 && size != mw_size) 2517289546Scem limit = base + size; 2518289546Scem 2519289546Scem /* Set and verify translation address */ 2520289546Scem ntb_reg_write(8, xlat_reg, addr); 2521289546Scem reg_val = ntb_reg_read(8, xlat_reg); 2522289546Scem if (reg_val != addr) { 2523289546Scem ntb_reg_write(8, xlat_reg, 0); 2524289546Scem return (EIO); 2525289546Scem } 2526289546Scem 2527289546Scem /* Set and verify the limit */ 2528289546Scem ntb_reg_write(8, limit_reg, limit); 2529289546Scem reg_val = ntb_reg_read(8, limit_reg); 2530289546Scem if (reg_val != limit) { 2531289546Scem ntb_reg_write(8, limit_reg, base); 2532289546Scem ntb_reg_write(8, xlat_reg, 0); 2533289546Scem return (EIO); 2534289546Scem } 2535289546Scem } else { 2536289546Scem /* Configure 32-bit (split) BAR MW */ 2537289546Scem 2538289546Scem if ((addr & ~UINT32_MAX) != 0) 2539289546Scem return (EINVAL); 2540289546Scem if (((addr + size) & ~UINT32_MAX) != 0) 2541289546Scem return (EINVAL); 2542289546Scem 2543289546Scem base = ntb_reg_read(4, base_reg); 2544289546Scem 2545289546Scem if (limit_reg != 0 && size != mw_size) 2546289546Scem limit = base + size; 2547289546Scem 2548289546Scem /* Set and verify translation address */ 2549289546Scem ntb_reg_write(4, xlat_reg, addr); 2550289546Scem reg_val = ntb_reg_read(4, xlat_reg); 2551289546Scem if (reg_val != addr) { 2552289546Scem ntb_reg_write(4, xlat_reg, 0); 2553289546Scem return (EIO); 2554289546Scem } 2555289546Scem 2556289546Scem /* Set and verify the limit */ 2557289546Scem ntb_reg_write(4, limit_reg, limit); 2558289546Scem reg_val = ntb_reg_read(4, limit_reg); 2559289546Scem if (reg_val != limit) { 2560289546Scem ntb_reg_write(4, limit_reg, base); 2561289546Scem ntb_reg_write(4, xlat_reg, 0); 2562289546Scem return (EIO); 2563289546Scem } 2564250079Scarl } 2565289546Scem return (0); 2566250079Scarl} 2567250079Scarl 2568289596Scem/* 2569289596Scem * ntb_mw_clear_trans() - clear the translation of a memory window 2570289596Scem * @ntb: NTB device context 2571289596Scem * @idx: Memory window number 2572289596Scem * 2573289596Scem * Clear the translation of a memory window. The peer may no longer access 2574289596Scem * local memory through the window. 2575289596Scem * 2576289596Scem * Return: Zero on success, otherwise an error number. 2577289596Scem */ 2578289596Scemint 2579289596Scemntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx) 2580289596Scem{ 2581289596Scem 2582289596Scem return (ntb_mw_set_trans(ntb, mw_idx, 0, 0)); 2583289596Scem} 2584289596Scem 2585250079Scarl/** 2586289545Scem * ntb_peer_db_set() - Set the doorbell on the secondary/external side 2587250079Scarl * @ntb: pointer to ntb_softc instance 2588289545Scem * @bit: doorbell bits to ring 2589250079Scarl * 2590250079Scarl * This function allows triggering of a doorbell on the secondary/external 2591250079Scarl * side that will initiate an interrupt on the remote host 2592250079Scarl */ 2593250079Scarlvoid 2594289545Scemntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit) 2595250079Scarl{ 2596250079Scarl 2597289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2598290682Scem ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 2599289347Scem return; 2600289209Scem } 2601289347Scem 2602289546Scem db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 2603250079Scarl} 2604250079Scarl 2605289542Scem/* 2606289542Scem * ntb_get_peer_db_addr() - Return the address of the remote doorbell register, 2607289542Scem * as well as the size of the register (via *sz_out). 2608289542Scem * 2609289542Scem * This function allows a caller using I/OAT DMA to chain the remote doorbell 2610289542Scem * ring to its memory window write. 2611289542Scem * 2612289542Scem * Note that writing the peer doorbell via a memory window will *not* generate 2613289542Scem * an interrupt on the remote host; that must be done seperately. 2614289542Scem */ 2615289542Scembus_addr_t 2616289542Scemntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out) 2617289542Scem{ 2618289542Scem struct ntb_pci_bar_info *bar; 2619289542Scem uint64_t regoff; 2620289542Scem 2621289542Scem KASSERT(sz_out != NULL, ("must be non-NULL")); 2622289542Scem 2623289542Scem if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2624289542Scem bar = &ntb->bar_info[NTB_CONFIG_BAR]; 2625289542Scem regoff = ntb->peer_reg->db_bell; 2626289542Scem } else { 2627289542Scem KASSERT((HAS_FEATURE(NTB_SPLIT_BAR) && ntb->mw_count == 2) || 2628289542Scem (!HAS_FEATURE(NTB_SPLIT_BAR) && ntb->mw_count == 1), 2629289542Scem ("mw_count invalid after setup")); 2630289543Scem KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 2631289543Scem ("invalid b2b idx")); 2632289542Scem 2633289542Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 2634290682Scem regoff = XEON_PDOORBELL_OFFSET; 2635289542Scem } 2636289542Scem KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 2637289542Scem 2638289542Scem *sz_out = ntb->reg->db_size; 2639289542Scem /* HACK: Specific to current x86 bus implementation. */ 2640289542Scem return ((uint64_t)bar->pci_bus_handle + regoff); 2641289542Scem} 2642289542Scem 2643289597Scem/* 2644289597Scem * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb 2645289597Scem * @ntb: NTB device context 2646289597Scem * 2647289597Scem * Hardware may support different number or arrangement of doorbell bits. 2648289597Scem * 2649289597Scem * Return: A mask of doorbell bits supported by the ntb. 2650289597Scem */ 2651289597Scemuint64_t 2652289597Scemntb_db_valid_mask(struct ntb_softc *ntb) 2653289597Scem{ 2654289597Scem 2655289597Scem return (ntb->db_valid_mask); 2656289597Scem} 2657289597Scem 2658289598Scem/* 2659289598Scem * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector 2660289598Scem * @ntb: NTB device context 2661289598Scem * @vector: Doorbell vector number 2662289598Scem * 2663289598Scem * Each interrupt vector may have a different number or arrangement of bits. 2664289598Scem * 2665289598Scem * Return: A mask of doorbell bits serviced by a vector. 2666289598Scem */ 2667289598Scemuint64_t 2668289598Scemntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector) 2669289598Scem{ 2670289598Scem 2671289598Scem if (vector > ntb->db_vec_count) 2672289598Scem return (0); 2673289598Scem return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 2674289598Scem} 2675289598Scem 2676250079Scarl/** 2677289546Scem * ntb_link_is_up() - get the current ntb link state 2678289546Scem * @ntb: NTB device context 2679289546Scem * @speed: OUT - The link speed expressed as PCIe generation number 2680289546Scem * @width: OUT - The link width expressed as the number of PCIe lanes 2681250079Scarl * 2682250079Scarl * RETURNS: true or false based on the hardware link state 2683250079Scarl */ 2684250079Scarlbool 2685289546Scemntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed, 2686289546Scem enum ntb_width *width) 2687250079Scarl{ 2688250079Scarl 2689289546Scem if (speed != NULL) 2690289546Scem *speed = ntb_link_sta_speed(ntb); 2691289546Scem if (width != NULL) 2692289546Scem *width = ntb_link_sta_width(ntb); 2693289546Scem return (link_is_up(ntb)); 2694250079Scarl} 2695250079Scarl 2696255272Scarlstatic void 2697255272Scarlsave_bar_parameters(struct ntb_pci_bar_info *bar) 2698250079Scarl{ 2699255272Scarl 2700289209Scem bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 2701289209Scem bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 2702289209Scem bar->pbase = rman_get_start(bar->pci_resource); 2703289209Scem bar->size = rman_get_size(bar->pci_resource); 2704289209Scem bar->vbase = rman_get_virtual(bar->pci_resource); 2705250079Scarl} 2706255268Scarl 2707289209Scemdevice_t 2708289209Scemntb_get_device(struct ntb_softc *ntb) 2709255268Scarl{ 2710255268Scarl 2711255268Scarl return (ntb->device); 2712255268Scarl} 2713289208Scem 2714289208Scem/* Export HW-specific errata information. */ 2715289208Scembool 2716289774Scemntb_has_feature(struct ntb_softc *ntb, uint32_t feature) 2717289208Scem{ 2718289208Scem 2719289208Scem return (HAS_FEATURE(feature)); 2720289208Scem} 2721