ntb_hw_intel.c revision 290682
1250079Scarl/*- 2250079Scarl * Copyright (C) 2013 Intel Corporation 3289542Scem * Copyright (C) 2015 EMC Corporation 4250079Scarl * All rights reserved. 5250079Scarl * 6250079Scarl * Redistribution and use in source and binary forms, with or without 7250079Scarl * modification, are permitted provided that the following conditions 8250079Scarl * are met: 9250079Scarl * 1. Redistributions of source code must retain the above copyright 10250079Scarl * notice, this list of conditions and the following disclaimer. 11250079Scarl * 2. Redistributions in binary form must reproduce the above copyright 12250079Scarl * notice, this list of conditions and the following disclaimer in the 13250079Scarl * documentation and/or other materials provided with the distribution. 14250079Scarl * 15250079Scarl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16250079Scarl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250079Scarl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250079Scarl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19250079Scarl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20250079Scarl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21250079Scarl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22250079Scarl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23250079Scarl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24250079Scarl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25250079Scarl * SUCH DAMAGE. 26250079Scarl */ 27250079Scarl 28250079Scarl#include <sys/cdefs.h> 29250079Scarl__FBSDID("$FreeBSD: head/sys/dev/ntb/ntb_hw/ntb_hw.c 290682 2015-11-11 18:55:25Z cem $"); 30250079Scarl 31250079Scarl#include <sys/param.h> 32250079Scarl#include <sys/kernel.h> 33250079Scarl#include <sys/systm.h> 34250079Scarl#include <sys/bus.h> 35289774Scem#include <sys/endian.h> 36250079Scarl#include <sys/malloc.h> 37250079Scarl#include <sys/module.h> 38250079Scarl#include <sys/queue.h> 39250079Scarl#include <sys/rman.h> 40289774Scem#include <sys/sbuf.h> 41289207Scem#include <sys/sysctl.h> 42250079Scarl#include <vm/vm.h> 43250079Scarl#include <vm/pmap.h> 44250079Scarl#include <machine/bus.h> 45250079Scarl#include <machine/pmap.h> 46250079Scarl#include <machine/resource.h> 47250079Scarl#include <dev/pci/pcireg.h> 48250079Scarl#include <dev/pci/pcivar.h> 49250079Scarl 50250079Scarl#include "ntb_regs.h" 51250079Scarl#include "ntb_hw.h" 52250079Scarl 53250079Scarl/* 54250079Scarl * The Non-Transparent Bridge (NTB) is a device on some Intel processors that 55250079Scarl * allows you to connect two systems using a PCI-e link. 56250079Scarl * 57250079Scarl * This module contains the hardware abstraction layer for the NTB. It allows 58250079Scarl * you to send and recieve interrupts, map the memory windows and send and 59250079Scarl * receive messages in the scratch-pad registers. 60250079Scarl * 61250079Scarl * NOTE: Much of the code in this module is shared with Linux. Any patches may 62250079Scarl * be picked up and redistributed in Linux with a dual GPL/BSD license. 63250079Scarl */ 64250079Scarl 65289648Scem#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 66250079Scarl 67289539Scem#define NTB_HB_TIMEOUT 1 /* second */ 68289648Scem#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 69250079Scarl 70250079Scarl#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) 71250079Scarl 72250079Scarlenum ntb_device_type { 73250079Scarl NTB_XEON, 74289648Scem NTB_ATOM 75250079Scarl}; 76250079Scarl 77289610Scem/* ntb_conn_type are hardware numbers, cannot change. */ 78289610Scemenum ntb_conn_type { 79289610Scem NTB_CONN_TRANSPARENT = 0, 80289610Scem NTB_CONN_B2B = 1, 81289610Scem NTB_CONN_RP = 2, 82289610Scem}; 83289610Scem 84289610Scemenum ntb_b2b_direction { 85289610Scem NTB_DEV_USD = 0, 86289610Scem NTB_DEV_DSD = 1, 87289610Scem}; 88289610Scem 89289539Scemenum ntb_bar { 90289539Scem NTB_CONFIG_BAR = 0, 91289539Scem NTB_B2B_BAR_1, 92289539Scem NTB_B2B_BAR_2, 93289539Scem NTB_B2B_BAR_3, 94289539Scem NTB_MAX_BARS 95289539Scem}; 96289539Scem 97255274Scarl/* Device features and workarounds */ 98255274Scarl#define HAS_FEATURE(feature) \ 99255274Scarl ((ntb->features & (feature)) != 0) 100255274Scarl 101250079Scarlstruct ntb_hw_info { 102250079Scarl uint32_t device_id; 103255274Scarl const char *desc; 104250079Scarl enum ntb_device_type type; 105289397Scem uint32_t features; 106250079Scarl}; 107250079Scarl 108250079Scarlstruct ntb_pci_bar_info { 109250079Scarl bus_space_tag_t pci_bus_tag; 110250079Scarl bus_space_handle_t pci_bus_handle; 111250079Scarl int pci_resource_id; 112250079Scarl struct resource *pci_resource; 113250079Scarl vm_paddr_t pbase; 114290679Scem caddr_t vbase; 115290679Scem vm_size_t size; 116289543Scem 117289543Scem /* Configuration register offsets */ 118289543Scem uint32_t psz_off; 119289543Scem uint32_t ssz_off; 120289543Scem uint32_t pbarxlat_off; 121250079Scarl}; 122250079Scarl 123250079Scarlstruct ntb_int_info { 124250079Scarl struct resource *res; 125250079Scarl int rid; 126250079Scarl void *tag; 127250079Scarl}; 128250079Scarl 129289546Scemstruct ntb_vec { 130250079Scarl struct ntb_softc *ntb; 131289546Scem uint32_t num; 132250079Scarl}; 133250079Scarl 134289542Scemstruct ntb_reg { 135289542Scem uint32_t ntb_ctl; 136289542Scem uint32_t lnk_sta; 137289542Scem uint8_t db_size; 138289542Scem unsigned mw_bar[NTB_MAX_BARS]; 139289542Scem}; 140289542Scem 141289542Scemstruct ntb_alt_reg { 142289542Scem uint32_t db_bell; 143289542Scem uint32_t db_mask; 144289542Scem uint32_t spad; 145289542Scem}; 146289542Scem 147289542Scemstruct ntb_xlat_reg { 148289546Scem uint32_t bar0_base; 149289546Scem uint32_t bar2_base; 150289546Scem uint32_t bar4_base; 151289546Scem uint32_t bar5_base; 152289546Scem 153289546Scem uint32_t bar2_xlat; 154289546Scem uint32_t bar4_xlat; 155289546Scem uint32_t bar5_xlat; 156289546Scem 157289546Scem uint32_t bar2_limit; 158289546Scem uint32_t bar4_limit; 159289546Scem uint32_t bar5_limit; 160289542Scem}; 161289542Scem 162289542Scemstruct ntb_b2b_addr { 163289542Scem uint64_t bar0_addr; 164289542Scem uint64_t bar2_addr64; 165289542Scem uint64_t bar4_addr64; 166289542Scem uint64_t bar4_addr32; 167289542Scem uint64_t bar5_addr32; 168289542Scem}; 169289542Scem 170250079Scarlstruct ntb_softc { 171250079Scarl device_t device; 172250079Scarl enum ntb_device_type type; 173289774Scem uint32_t features; 174250079Scarl 175250079Scarl struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 176250079Scarl struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 177250079Scarl uint32_t allocated_interrupts; 178250079Scarl 179250079Scarl struct callout heartbeat_timer; 180250079Scarl struct callout lr_timer; 181250079Scarl 182289546Scem void *ntb_ctx; 183289546Scem const struct ntb_ctx_ops *ctx_ops; 184289546Scem struct ntb_vec *msix_vec; 185289546Scem#define CTX_LOCK(sc) mtx_lock_spin(&(sc)->ctx_lock) 186289546Scem#define CTX_UNLOCK(sc) mtx_unlock_spin(&(sc)->ctx_lock) 187289546Scem#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f)) 188289546Scem struct mtx ctx_lock; 189250079Scarl 190289610Scem uint32_t ppd; 191289610Scem enum ntb_conn_type conn_type; 192289610Scem enum ntb_b2b_direction dev_type; 193289539Scem 194289542Scem /* Offset of peer bar0 in B2B BAR */ 195289542Scem uint64_t b2b_off; 196289542Scem /* Memory window used to access peer bar0 */ 197289543Scem#define B2B_MW_DISABLED UINT8_MAX 198289542Scem uint8_t b2b_mw_idx; 199289542Scem 200289539Scem uint8_t mw_count; 201289539Scem uint8_t spad_count; 202289539Scem uint8_t db_count; 203289539Scem uint8_t db_vec_count; 204289539Scem uint8_t db_vec_shift; 205289542Scem 206289546Scem /* Protects local db_mask. */ 207289546Scem#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 208289546Scem#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 209289546Scem#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 210289542Scem struct mtx db_mask_lock; 211289542Scem 212289546Scem uint32_t ntb_ctl; 213289546Scem uint32_t lnk_sta; 214289542Scem 215289542Scem uint64_t db_valid_mask; 216289542Scem uint64_t db_link_mask; 217289546Scem uint64_t db_mask; 218289542Scem 219289542Scem int last_ts; /* ticks @ last irq */ 220289542Scem 221289542Scem const struct ntb_reg *reg; 222289542Scem const struct ntb_alt_reg *self_reg; 223289542Scem const struct ntb_alt_reg *peer_reg; 224289542Scem const struct ntb_xlat_reg *xlat_reg; 225250079Scarl}; 226250079Scarl 227289234Scem#ifdef __i386__ 228289234Scemstatic __inline uint64_t 229289234Scembus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 230289234Scem bus_size_t offset) 231289234Scem{ 232289234Scem 233289234Scem return (bus_space_read_4(tag, handle, offset) | 234289234Scem ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 235289234Scem} 236289234Scem 237289234Scemstatic __inline void 238289234Scembus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 239289234Scem bus_size_t offset, uint64_t val) 240289234Scem{ 241289234Scem 242289234Scem bus_space_write_4(tag, handle, offset, val); 243289234Scem bus_space_write_4(tag, handle, offset + 4, val >> 32); 244289234Scem} 245289234Scem#endif 246289234Scem 247255279Scarl#define ntb_bar_read(SIZE, bar, offset) \ 248255279Scarl bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 249255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset)) 250255279Scarl#define ntb_bar_write(SIZE, bar, offset, val) \ 251255279Scarl bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 252255279Scarl ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 253255279Scarl#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 254250079Scarl#define ntb_reg_write(SIZE, offset, val) \ 255255279Scarl ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 256289397Scem#define ntb_mw_read(SIZE, offset) \ 257289542Scem ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 258255279Scarl#define ntb_mw_write(SIZE, offset, val) \ 259289542Scem ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 260289397Scem offset, val) 261250079Scarl 262250079Scarlstatic int ntb_probe(device_t device); 263250079Scarlstatic int ntb_attach(device_t device); 264250079Scarlstatic int ntb_detach(device_t device); 265289539Scemstatic inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 266289546Scemstatic inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 267289546Scemstatic inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 268289546Scem uint32_t *base, uint32_t *xlat, uint32_t *lmt); 269255272Scarlstatic int ntb_map_pci_bars(struct ntb_softc *ntb); 270289647Scemstatic void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 271289647Scem const char *); 272255272Scarlstatic int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 273255272Scarlstatic int map_memory_window_bar(struct ntb_softc *ntb, 274255272Scarl struct ntb_pci_bar_info *bar); 275250079Scarlstatic void ntb_unmap_pci_bar(struct ntb_softc *ntb); 276289344Scemstatic int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 277289540Scemstatic int ntb_init_isr(struct ntb_softc *ntb); 278289342Scemstatic int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 279289540Scemstatic int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 280250079Scarlstatic void ntb_teardown_interrupts(struct ntb_softc *ntb); 281289540Scemstatic inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 282289546Scemstatic void ntb_interrupt(struct ntb_softc *, uint32_t vec); 283289546Scemstatic void ndev_vec_isr(void *arg); 284289546Scemstatic void ndev_irq_isr(void *arg); 285289546Scemstatic inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 286290678Scemstatic inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 287290678Scemstatic inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 288289546Scemstatic int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 289289546Scemstatic void ntb_free_msix_vec(struct ntb_softc *ntb); 290250079Scarlstatic struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 291289397Scemstatic void ntb_detect_max_mw(struct ntb_softc *ntb); 292289348Scemstatic int ntb_detect_xeon(struct ntb_softc *ntb); 293289648Scemstatic int ntb_detect_atom(struct ntb_softc *ntb); 294289542Scemstatic int ntb_xeon_init_dev(struct ntb_softc *ntb); 295289648Scemstatic int ntb_atom_init_dev(struct ntb_softc *ntb); 296289272Scemstatic void ntb_teardown_xeon(struct ntb_softc *ntb); 297289648Scemstatic void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 298289543Scemstatic void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 299289543Scem enum ntb_bar regbar); 300289543Scemstatic void xeon_set_sbar_base_and_limit(struct ntb_softc *, 301289543Scem uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 302289543Scemstatic void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 303289543Scem enum ntb_bar idx); 304289542Scemstatic int xeon_setup_b2b_mw(struct ntb_softc *, 305289542Scem const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 306289546Scemstatic inline bool link_is_up(struct ntb_softc *ntb); 307289648Scemstatic inline bool atom_link_is_err(struct ntb_softc *ntb); 308289546Scemstatic inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 309289546Scemstatic inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 310289648Scemstatic void atom_link_hb(void *arg); 311289546Scemstatic void ntb_db_event(struct ntb_softc *ntb, uint32_t vec); 312289648Scemstatic void recover_atom_link(void *arg); 313289546Scemstatic bool ntb_poll_link(struct ntb_softc *ntb); 314255274Scarlstatic void save_bar_parameters(struct ntb_pci_bar_info *bar); 315289774Scemstatic void ntb_sysctl_init(struct ntb_softc *); 316289774Scemstatic int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 317289774Scemstatic int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 318289774Scemstatic int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 319250079Scarl 320250079Scarlstatic struct ntb_hw_info pci_ids[] = { 321289612Scem /* XXX: PS/SS IDs left out until they are supported. */ 322289612Scem { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 323289648Scem NTB_ATOM, 0 }, 324289233Scem 325289233Scem { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 326289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 327289233Scem { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 328289538Scem NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 329289233Scem { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 330289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 331289538Scem NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 332289233Scem { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 333289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 334289538Scem NTB_SB01BASE_LOCKUP }, 335289233Scem { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 336289538Scem NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 337289538Scem NTB_SB01BASE_LOCKUP }, 338289233Scem 339289648Scem { 0x00000000, NULL, NTB_ATOM, 0 } 340250079Scarl}; 341250079Scarl 342289648Scemstatic const struct ntb_reg atom_reg = { 343289648Scem .ntb_ctl = ATOM_NTBCNTL_OFFSET, 344289648Scem .lnk_sta = ATOM_LINK_STATUS_OFFSET, 345289542Scem .db_size = sizeof(uint64_t), 346289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 347289542Scem}; 348289542Scem 349289648Scemstatic const struct ntb_alt_reg atom_pri_reg = { 350289648Scem .db_bell = ATOM_PDOORBELL_OFFSET, 351289648Scem .db_mask = ATOM_PDBMSK_OFFSET, 352289648Scem .spad = ATOM_SPAD_OFFSET, 353289607Scem}; 354289607Scem 355289648Scemstatic const struct ntb_alt_reg atom_b2b_reg = { 356289648Scem .db_bell = ATOM_B2B_DOORBELL_OFFSET, 357289648Scem .spad = ATOM_B2B_SPAD_OFFSET, 358289542Scem}; 359289542Scem 360289648Scemstatic const struct ntb_xlat_reg atom_sec_xlat = { 361289542Scem#if 0 362289542Scem /* "FIXME" says the Linux driver. */ 363289648Scem .bar0_base = ATOM_SBAR0BASE_OFFSET, 364289648Scem .bar2_base = ATOM_SBAR2BASE_OFFSET, 365289648Scem .bar4_base = ATOM_SBAR4BASE_OFFSET, 366289546Scem 367289648Scem .bar2_limit = ATOM_SBAR2LMT_OFFSET, 368289648Scem .bar4_limit = ATOM_SBAR4LMT_OFFSET, 369289542Scem#endif 370289546Scem 371289648Scem .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 372289648Scem .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 373289542Scem}; 374289542Scem 375289542Scemstatic const struct ntb_reg xeon_reg = { 376289542Scem .ntb_ctl = XEON_NTBCNTL_OFFSET, 377289542Scem .lnk_sta = XEON_LINK_STATUS_OFFSET, 378289542Scem .db_size = sizeof(uint16_t), 379289542Scem .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 380289542Scem}; 381289542Scem 382289607Scemstatic const struct ntb_alt_reg xeon_pri_reg = { 383289607Scem .db_bell = XEON_PDOORBELL_OFFSET, 384289607Scem .db_mask = XEON_PDBMSK_OFFSET, 385289607Scem .spad = XEON_SPAD_OFFSET, 386289607Scem}; 387289607Scem 388289542Scemstatic const struct ntb_alt_reg xeon_b2b_reg = { 389289542Scem .db_bell = XEON_B2B_DOORBELL_OFFSET, 390289542Scem .spad = XEON_B2B_SPAD_OFFSET, 391289542Scem}; 392289542Scem 393289542Scemstatic const struct ntb_xlat_reg xeon_sec_xlat = { 394289542Scem .bar0_base = XEON_SBAR0BASE_OFFSET, 395289546Scem .bar2_base = XEON_SBAR2BASE_OFFSET, 396289546Scem .bar4_base = XEON_SBAR4BASE_OFFSET, 397289546Scem .bar5_base = XEON_SBAR5BASE_OFFSET, 398289546Scem 399289542Scem .bar2_limit = XEON_SBAR2LMT_OFFSET, 400289546Scem .bar4_limit = XEON_SBAR4LMT_OFFSET, 401289546Scem .bar5_limit = XEON_SBAR5LMT_OFFSET, 402289546Scem 403289542Scem .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 404289546Scem .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 405289546Scem .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 406289542Scem}; 407289542Scem 408289614Scemstatic struct ntb_b2b_addr xeon_b2b_usd_addr = { 409289542Scem .bar0_addr = XEON_B2B_BAR0_USD_ADDR, 410289542Scem .bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64, 411289542Scem .bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64, 412289542Scem .bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32, 413289542Scem .bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32, 414289542Scem}; 415289542Scem 416289614Scemstatic struct ntb_b2b_addr xeon_b2b_dsd_addr = { 417289542Scem .bar0_addr = XEON_B2B_BAR0_DSD_ADDR, 418289542Scem .bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64, 419289542Scem .bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64, 420289542Scem .bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32, 421289542Scem .bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32, 422289542Scem}; 423289542Scem 424289614ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 425289614Scem "B2B MW segment overrides -- MUST be the same on both sides"); 426289614Scem 427289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 428289614Scem &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 429289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 430289614Scem "the window at BAR2, on the upstream side of the link. MUST be the same " 431289614Scem "address on both sides."); 432289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 433289614Scem &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 434289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 435289614Scem &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 436289614Scem "(split-BAR mode)."); 437289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 438289646Scem &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 439289614Scem "(split-BAR mode)."); 440289614Scem 441289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 442289614Scem &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 443289614Scem "hardware, use this 64-bit address on the bus between the NTB devices for " 444289614Scem "the window at BAR2, on the downstream side of the link. MUST be the same" 445289614Scem " address on both sides."); 446289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 447289614Scem &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 448289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 449289614Scem &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 450289614Scem "(split-BAR mode)."); 451289614ScemSYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 452289646Scem &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 453289614Scem "(split-BAR mode)."); 454289614Scem 455250079Scarl/* 456250079Scarl * OS <-> Driver interface structures 457250079Scarl */ 458250079ScarlMALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 459250079Scarl 460250079Scarlstatic device_method_t ntb_pci_methods[] = { 461250079Scarl /* Device interface */ 462250079Scarl DEVMETHOD(device_probe, ntb_probe), 463250079Scarl DEVMETHOD(device_attach, ntb_attach), 464250079Scarl DEVMETHOD(device_detach, ntb_detach), 465250079Scarl DEVMETHOD_END 466250079Scarl}; 467250079Scarl 468250079Scarlstatic driver_t ntb_pci_driver = { 469250079Scarl "ntb_hw", 470250079Scarl ntb_pci_methods, 471250079Scarl sizeof(struct ntb_softc), 472250079Scarl}; 473250079Scarl 474250079Scarlstatic devclass_t ntb_devclass; 475250079ScarlDRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); 476250079ScarlMODULE_VERSION(ntb_hw, 1); 477250079Scarl 478289207ScemSYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 479289207Scem 480250079Scarl/* 481250079Scarl * OS <-> Driver linkage functions 482250079Scarl */ 483250079Scarlstatic int 484250079Scarlntb_probe(device_t device) 485250079Scarl{ 486289209Scem struct ntb_hw_info *p; 487250079Scarl 488289209Scem p = ntb_get_device_info(pci_get_devid(device)); 489289209Scem if (p == NULL) 490250079Scarl return (ENXIO); 491289209Scem 492289209Scem device_set_desc(device, p->desc); 493289209Scem return (0); 494250079Scarl} 495250079Scarl 496250079Scarlstatic int 497250079Scarlntb_attach(device_t device) 498250079Scarl{ 499289209Scem struct ntb_softc *ntb; 500289209Scem struct ntb_hw_info *p; 501250079Scarl int error; 502250079Scarl 503289209Scem ntb = DEVICE2SOFTC(device); 504289209Scem p = ntb_get_device_info(pci_get_devid(device)); 505289209Scem 506250079Scarl ntb->device = device; 507250079Scarl ntb->type = p->type; 508255274Scarl ntb->features = p->features; 509289543Scem ntb->b2b_mw_idx = B2B_MW_DISABLED; 510250079Scarl 511289648Scem /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 512283291Sjkim callout_init(&ntb->heartbeat_timer, 1); 513283291Sjkim callout_init(&ntb->lr_timer, 1); 514289542Scem mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 515289546Scem mtx_init(&ntb->ctx_lock, "ntb ctx", NULL, MTX_SPIN); 516250079Scarl 517289648Scem if (ntb->type == NTB_ATOM) 518289648Scem error = ntb_detect_atom(ntb); 519289348Scem else 520289348Scem error = ntb_detect_xeon(ntb); 521290682Scem if (error != 0) 522289348Scem goto out; 523289348Scem 524289397Scem ntb_detect_max_mw(ntb); 525289396Scem 526290682Scem pci_enable_busmaster(ntb->device); 527290682Scem 528289209Scem error = ntb_map_pci_bars(ntb); 529290682Scem if (error != 0) 530289209Scem goto out; 531289648Scem if (ntb->type == NTB_ATOM) 532289648Scem error = ntb_atom_init_dev(ntb); 533289272Scem else 534289542Scem error = ntb_xeon_init_dev(ntb); 535290682Scem if (error != 0) 536289209Scem goto out; 537290682Scem 538290682Scem ntb_poll_link(ntb); 539290682Scem 540289774Scem ntb_sysctl_init(ntb); 541250079Scarl 542289209Scemout: 543289209Scem if (error != 0) 544289209Scem ntb_detach(device); 545250079Scarl return (error); 546250079Scarl} 547250079Scarl 548250079Scarlstatic int 549250079Scarlntb_detach(device_t device) 550250079Scarl{ 551289209Scem struct ntb_softc *ntb; 552250079Scarl 553289209Scem ntb = DEVICE2SOFTC(device); 554289542Scem 555289617Scem if (ntb->self_reg != NULL) 556289617Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 557250079Scarl callout_drain(&ntb->heartbeat_timer); 558250079Scarl callout_drain(&ntb->lr_timer); 559290682Scem pci_disable_busmaster(ntb->device); 560289272Scem if (ntb->type == NTB_XEON) 561289272Scem ntb_teardown_xeon(ntb); 562250079Scarl ntb_teardown_interrupts(ntb); 563289397Scem 564289542Scem mtx_destroy(&ntb->db_mask_lock); 565289546Scem mtx_destroy(&ntb->ctx_lock); 566289542Scem 567289397Scem /* 568289397Scem * Redetect total MWs so we unmap properly -- in case we lowered the 569289397Scem * maximum to work around Xeon errata. 570289397Scem */ 571289397Scem ntb_detect_max_mw(ntb); 572250079Scarl ntb_unmap_pci_bar(ntb); 573250079Scarl 574250079Scarl return (0); 575250079Scarl} 576250079Scarl 577289542Scem/* 578289542Scem * Driver internal routines 579289542Scem */ 580289539Scemstatic inline enum ntb_bar 581289539Scemntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 582289539Scem{ 583289539Scem 584289543Scem KASSERT(mw < ntb->mw_count || 585289543Scem (mw != B2B_MW_DISABLED && mw == ntb->b2b_mw_idx), 586289542Scem ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 587289546Scem KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 588289539Scem 589289542Scem return (ntb->reg->mw_bar[mw]); 590289539Scem} 591289539Scem 592289546Scemstatic inline bool 593289546Scembar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 594289546Scem{ 595289546Scem /* XXX This assertion could be stronger. */ 596289546Scem KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 597289546Scem return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(NTB_SPLIT_BAR)); 598289546Scem} 599289546Scem 600289546Scemstatic inline void 601289546Scembar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 602289546Scem uint32_t *xlat, uint32_t *lmt) 603289546Scem{ 604289546Scem uint32_t basev, lmtv, xlatv; 605289546Scem 606289546Scem switch (bar) { 607289546Scem case NTB_B2B_BAR_1: 608289546Scem basev = ntb->xlat_reg->bar2_base; 609289546Scem lmtv = ntb->xlat_reg->bar2_limit; 610289546Scem xlatv = ntb->xlat_reg->bar2_xlat; 611289546Scem break; 612289546Scem case NTB_B2B_BAR_2: 613289546Scem basev = ntb->xlat_reg->bar4_base; 614289546Scem lmtv = ntb->xlat_reg->bar4_limit; 615289546Scem xlatv = ntb->xlat_reg->bar4_xlat; 616289546Scem break; 617289546Scem case NTB_B2B_BAR_3: 618289546Scem basev = ntb->xlat_reg->bar5_base; 619289546Scem lmtv = ntb->xlat_reg->bar5_limit; 620289546Scem xlatv = ntb->xlat_reg->bar5_xlat; 621289546Scem break; 622289546Scem default: 623289546Scem KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 624289546Scem ("bad bar")); 625289546Scem basev = lmtv = xlatv = 0; 626289546Scem break; 627289546Scem } 628289546Scem 629289546Scem if (base != NULL) 630289546Scem *base = basev; 631289546Scem if (xlat != NULL) 632289546Scem *xlat = xlatv; 633289546Scem if (lmt != NULL) 634289546Scem *lmt = lmtv; 635289546Scem} 636289546Scem 637250079Scarlstatic int 638255272Scarlntb_map_pci_bars(struct ntb_softc *ntb) 639250079Scarl{ 640255272Scarl int rc; 641250079Scarl 642250079Scarl ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 643289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 644255272Scarl if (rc != 0) 645289541Scem goto out; 646255272Scarl 647289209Scem ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 648289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 649255272Scarl if (rc != 0) 650289541Scem goto out; 651289543Scem ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 652289543Scem ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 653289543Scem ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 654255272Scarl 655289209Scem ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 656289543Scem /* XXX Are shared MW B2Bs write-combining? */ 657289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP) && !HAS_FEATURE(NTB_SPLIT_BAR)) 658289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 659255279Scarl else 660289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 661289543Scem ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 662289543Scem ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 663289543Scem ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 664289543Scem 665289397Scem if (!HAS_FEATURE(NTB_SPLIT_BAR)) 666289541Scem goto out; 667289397Scem 668289397Scem ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 669289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 670289541Scem rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 671289397Scem else 672289541Scem rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 673289543Scem ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 674289543Scem ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 675289543Scem ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 676250079Scarl 677289541Scemout: 678289209Scem if (rc != 0) 679255272Scarl device_printf(ntb->device, 680255272Scarl "unable to allocate pci resource\n"); 681255272Scarl return (rc); 682255272Scarl} 683255272Scarl 684289541Scemstatic void 685289647Scemprint_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 686289647Scem const char *kind) 687289541Scem{ 688289541Scem 689289647Scem device_printf(ntb->device, 690289647Scem "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 691289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 692289647Scem (char *)bar->vbase + bar->size - 1, 693289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 694289647Scem (uintmax_t)bar->size, kind); 695289541Scem} 696289541Scem 697255272Scarlstatic int 698255272Scarlmap_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 699255272Scarl{ 700255272Scarl 701255275Scarl bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 702289209Scem &bar->pci_resource_id, RF_ACTIVE); 703255272Scarl if (bar->pci_resource == NULL) 704255272Scarl return (ENXIO); 705289209Scem 706289209Scem save_bar_parameters(bar); 707289647Scem print_map_success(ntb, bar, "mmr"); 708289209Scem return (0); 709255272Scarl} 710255272Scarl 711255272Scarlstatic int 712255272Scarlmap_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 713255272Scarl{ 714255272Scarl int rc; 715255276Scarl uint8_t bar_size_bits = 0; 716255272Scarl 717289209Scem bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 718289209Scem &bar->pci_resource_id, RF_ACTIVE); 719250079Scarl 720255272Scarl if (bar->pci_resource == NULL) 721255272Scarl return (ENXIO); 722255276Scarl 723289209Scem save_bar_parameters(bar); 724289209Scem /* 725289209Scem * Ivytown NTB BAR sizes are misreported by the hardware due to a 726289209Scem * hardware issue. To work around this, query the size it should be 727289209Scem * configured to by the device and modify the resource to correspond to 728289209Scem * this new size. The BIOS on systems with this problem is required to 729289209Scem * provide enough address space to allow the driver to make this change 730289209Scem * safely. 731289209Scem * 732289209Scem * Ideally I could have just specified the size when I allocated the 733289209Scem * resource like: 734289209Scem * bus_alloc_resource(ntb->device, 735289209Scem * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 736289209Scem * 1ul << bar_size_bits, RF_ACTIVE); 737289209Scem * but the PCI driver does not honor the size in this call, so we have 738289209Scem * to modify it after the fact. 739289209Scem */ 740289209Scem if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { 741289209Scem if (bar->pci_resource_id == PCIR_BAR(2)) 742289209Scem bar_size_bits = pci_read_config(ntb->device, 743289209Scem XEON_PBAR23SZ_OFFSET, 1); 744289209Scem else 745289209Scem bar_size_bits = pci_read_config(ntb->device, 746289209Scem XEON_PBAR45SZ_OFFSET, 1); 747289209Scem 748289209Scem rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 749289209Scem bar->pci_resource, bar->pbase, 750289209Scem bar->pbase + (1ul << bar_size_bits) - 1); 751255272Scarl if (rc != 0) { 752289209Scem device_printf(ntb->device, 753289209Scem "unable to resize bar\n"); 754255272Scarl return (rc); 755250079Scarl } 756289209Scem 757289209Scem save_bar_parameters(bar); 758250079Scarl } 759289209Scem 760289209Scem /* Mark bar region as write combining to improve performance. */ 761289209Scem rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, 762289209Scem VM_MEMATTR_WRITE_COMBINING); 763289647Scem print_map_success(ntb, bar, "mw"); 764289647Scem if (rc == 0) 765289209Scem device_printf(ntb->device, 766289647Scem "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 767289647Scem "WRITE_COMBINING.\n", 768289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 769289647Scem (char *)bar->vbase + bar->size - 1, 770289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1)); 771289647Scem else 772289647Scem device_printf(ntb->device, 773289647Scem "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 774289647Scem "WRITE_COMBINING: %d\n", 775289647Scem PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 776289647Scem (char *)bar->vbase + bar->size - 1, 777289647Scem (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 778289647Scem rc); 779289647Scem /* Proceed anyway */ 780250079Scarl return (0); 781250079Scarl} 782250079Scarl 783250079Scarlstatic void 784250079Scarlntb_unmap_pci_bar(struct ntb_softc *ntb) 785250079Scarl{ 786250079Scarl struct ntb_pci_bar_info *current_bar; 787250079Scarl int i; 788250079Scarl 789289397Scem for (i = 0; i < NTB_MAX_BARS; i++) { 790250079Scarl current_bar = &ntb->bar_info[i]; 791250079Scarl if (current_bar->pci_resource != NULL) 792250079Scarl bus_release_resource(ntb->device, SYS_RES_MEMORY, 793250079Scarl current_bar->pci_resource_id, 794250079Scarl current_bar->pci_resource); 795250079Scarl } 796250079Scarl} 797250079Scarl 798250079Scarlstatic int 799289540Scemntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 800250079Scarl{ 801289342Scem uint32_t i; 802289342Scem int rc; 803289342Scem 804289342Scem for (i = 0; i < num_vectors; i++) { 805289342Scem ntb->int_info[i].rid = i + 1; 806289342Scem ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 807289342Scem SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 808289342Scem if (ntb->int_info[i].res == NULL) { 809289342Scem device_printf(ntb->device, 810289342Scem "bus_alloc_resource failed\n"); 811289342Scem return (ENOMEM); 812289342Scem } 813289342Scem ntb->int_info[i].tag = NULL; 814289342Scem ntb->allocated_interrupts++; 815289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 816289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 817289546Scem &ntb->msix_vec[i], &ntb->int_info[i].tag); 818289342Scem if (rc != 0) { 819289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 820289342Scem return (ENXIO); 821289342Scem } 822289342Scem } 823289342Scem return (0); 824289342Scem} 825289342Scem 826289344Scem/* 827289344Scem * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 828289344Scem * cannot be allocated for each MSI-X message. JHB seems to think remapping 829289344Scem * should be okay. This tunable should enable us to test that hypothesis 830289344Scem * when someone gets their hands on some Xeon hardware. 831289344Scem */ 832289344Scemstatic int ntb_force_remap_mode; 833289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 834289344Scem &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 835289344Scem " to a smaller number of ithreads, even if the desired number are " 836289344Scem "available"); 837289344Scem 838289344Scem/* 839289344Scem * In case it is NOT ok, give consumers an abort button. 840289344Scem */ 841289344Scemstatic int ntb_prefer_intx; 842289344ScemSYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 843289344Scem &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 844289344Scem "than remapping MSI-X messages over available slots (match Linux driver " 845289344Scem "behavior)"); 846289344Scem 847289344Scem/* 848289344Scem * Remap the desired number of MSI-X messages to available ithreads in a simple 849289344Scem * round-robin fashion. 850289344Scem */ 851289342Scemstatic int 852289344Scemntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 853289344Scem{ 854289344Scem u_int *vectors; 855289344Scem uint32_t i; 856289344Scem int rc; 857289344Scem 858289344Scem if (ntb_prefer_intx != 0) 859289344Scem return (ENXIO); 860289344Scem 861289344Scem vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 862289344Scem 863289344Scem for (i = 0; i < desired; i++) 864289344Scem vectors[i] = (i % avail) + 1; 865289344Scem 866289344Scem rc = pci_remap_msix(dev, desired, vectors); 867289344Scem free(vectors, M_NTB); 868289344Scem return (rc); 869289344Scem} 870289344Scem 871289344Scemstatic int 872289540Scemntb_init_isr(struct ntb_softc *ntb) 873289342Scem{ 874289344Scem uint32_t desired_vectors, num_vectors; 875289342Scem int rc; 876250079Scarl 877250079Scarl ntb->allocated_interrupts = 0; 878289542Scem ntb->last_ts = ticks; 879289347Scem 880250079Scarl /* 881289546Scem * Mask all doorbell interrupts. 882250079Scarl */ 883289546Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 884250079Scarl 885289344Scem num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 886289539Scem ntb->db_count); 887289344Scem if (desired_vectors >= 1) { 888289344Scem rc = pci_alloc_msix(ntb->device, &num_vectors); 889250079Scarl 890289344Scem if (ntb_force_remap_mode != 0 && rc == 0 && 891289344Scem num_vectors == desired_vectors) 892289344Scem num_vectors--; 893289344Scem 894289344Scem if (rc == 0 && num_vectors < desired_vectors) { 895289344Scem rc = ntb_remap_msix(ntb->device, desired_vectors, 896289344Scem num_vectors); 897289344Scem if (rc == 0) 898289344Scem num_vectors = desired_vectors; 899289344Scem else 900289344Scem pci_release_msi(ntb->device); 901289344Scem } 902289344Scem if (rc != 0) 903289344Scem num_vectors = 1; 904289344Scem } else 905289344Scem num_vectors = 1; 906289344Scem 907289539Scem if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 908289539Scem ntb->db_vec_count = 1; 909290680Scem ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 910289539Scem rc = ntb_setup_legacy_interrupt(ntb); 911289539Scem } else { 912289546Scem ntb_create_msix_vec(ntb, num_vectors); 913289540Scem rc = ntb_setup_msix(ntb, num_vectors); 914289539Scem } 915289539Scem if (rc != 0) { 916289539Scem device_printf(ntb->device, 917289539Scem "Error allocating interrupts: %d\n", rc); 918289546Scem ntb_free_msix_vec(ntb); 919289396Scem } 920289396Scem 921289342Scem return (rc); 922289342Scem} 923289342Scem 924289342Scemstatic int 925289342Scemntb_setup_legacy_interrupt(struct ntb_softc *ntb) 926289342Scem{ 927289342Scem int rc; 928289342Scem 929289342Scem ntb->int_info[0].rid = 0; 930289342Scem ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 931289342Scem &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 932289342Scem if (ntb->int_info[0].res == NULL) { 933289342Scem device_printf(ntb->device, "bus_alloc_resource failed\n"); 934289342Scem return (ENOMEM); 935250079Scarl } 936250079Scarl 937289342Scem ntb->int_info[0].tag = NULL; 938289342Scem ntb->allocated_interrupts = 1; 939289342Scem 940289342Scem rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 941289546Scem INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 942289342Scem ntb, &ntb->int_info[0].tag); 943289342Scem if (rc != 0) { 944289342Scem device_printf(ntb->device, "bus_setup_intr failed\n"); 945289342Scem return (ENXIO); 946289342Scem } 947289342Scem 948250079Scarl return (0); 949250079Scarl} 950250079Scarl 951250079Scarlstatic void 952250079Scarlntb_teardown_interrupts(struct ntb_softc *ntb) 953250079Scarl{ 954250079Scarl struct ntb_int_info *current_int; 955250079Scarl int i; 956250079Scarl 957289209Scem for (i = 0; i < ntb->allocated_interrupts; i++) { 958250079Scarl current_int = &ntb->int_info[i]; 959250079Scarl if (current_int->tag != NULL) 960250079Scarl bus_teardown_intr(ntb->device, current_int->res, 961250079Scarl current_int->tag); 962250079Scarl 963250079Scarl if (current_int->res != NULL) 964250079Scarl bus_release_resource(ntb->device, SYS_RES_IRQ, 965250079Scarl rman_get_rid(current_int->res), current_int->res); 966250079Scarl } 967250079Scarl 968289546Scem ntb_free_msix_vec(ntb); 969250079Scarl pci_release_msi(ntb->device); 970250079Scarl} 971250079Scarl 972289347Scem/* 973289648Scem * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 974289347Scem * out to make code clearer. 975289347Scem */ 976289539Scemstatic inline uint64_t 977289546Scemdb_ioread(struct ntb_softc *ntb, uint64_t regoff) 978289347Scem{ 979289347Scem 980289648Scem if (ntb->type == NTB_ATOM) 981289347Scem return (ntb_reg_read(8, regoff)); 982289347Scem 983289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 984289347Scem 985289347Scem return (ntb_reg_read(2, regoff)); 986289347Scem} 987289347Scem 988289539Scemstatic inline void 989289546Scemdb_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 990289347Scem{ 991289347Scem 992289542Scem KASSERT((val & ~ntb->db_valid_mask) == 0, 993289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 994289542Scem (uintmax_t)(val & ~ntb->db_valid_mask), 995289542Scem (uintmax_t)ntb->db_valid_mask)); 996289542Scem 997289607Scem if (regoff == ntb->self_reg->db_mask) 998289546Scem DB_MASK_ASSERT(ntb, MA_OWNED); 999290678Scem db_iowrite_raw(ntb, regoff, val); 1000290678Scem} 1001289542Scem 1002290678Scemstatic inline void 1003290678Scemdb_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1004290678Scem{ 1005290678Scem 1006289648Scem if (ntb->type == NTB_ATOM) { 1007289347Scem ntb_reg_write(8, regoff, val); 1008289347Scem return; 1009289347Scem } 1010289347Scem 1011289347Scem KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1012289347Scem ntb_reg_write(2, regoff, (uint16_t)val); 1013289347Scem} 1014289347Scem 1015289546Scemvoid 1016289542Scemntb_db_set_mask(struct ntb_softc *ntb, uint64_t bits) 1017289542Scem{ 1018289542Scem 1019289546Scem DB_MASK_LOCK(ntb); 1020289542Scem ntb->db_mask |= bits; 1021289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1022289546Scem DB_MASK_UNLOCK(ntb); 1023289542Scem} 1024289542Scem 1025289546Scemvoid 1026289542Scemntb_db_clear_mask(struct ntb_softc *ntb, uint64_t bits) 1027289542Scem{ 1028289542Scem 1029289542Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1030289542Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1031289542Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1032289542Scem (uintmax_t)ntb->db_valid_mask)); 1033289542Scem 1034289546Scem DB_MASK_LOCK(ntb); 1035289542Scem ntb->db_mask &= ~bits; 1036289607Scem db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1037289546Scem DB_MASK_UNLOCK(ntb); 1038289542Scem} 1039289542Scem 1040289546Scemuint64_t 1041289546Scemntb_db_read(struct ntb_softc *ntb) 1042289281Scem{ 1043289281Scem 1044289607Scem return (db_ioread(ntb, ntb->self_reg->db_bell)); 1045289281Scem} 1046289281Scem 1047289546Scemvoid 1048289546Scemntb_db_clear(struct ntb_softc *ntb, uint64_t bits) 1049289281Scem{ 1050289281Scem 1051289546Scem KASSERT((bits & ~ntb->db_valid_mask) == 0, 1052289546Scem ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1053289546Scem (uintmax_t)(bits & ~ntb->db_valid_mask), 1054289546Scem (uintmax_t)ntb->db_valid_mask)); 1055289546Scem 1056289607Scem db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1057289281Scem} 1058289281Scem 1059289540Scemstatic inline uint64_t 1060289540Scemntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1061250079Scarl{ 1062289540Scem uint64_t shift, mask; 1063250079Scarl 1064289540Scem shift = ntb->db_vec_shift; 1065289540Scem mask = (1ull << shift) - 1; 1066289540Scem return (mask << (shift * db_vector)); 1067250079Scarl} 1068250079Scarl 1069250079Scarlstatic void 1070289546Scemntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1071250079Scarl{ 1072289540Scem uint64_t vec_mask; 1073250079Scarl 1074289542Scem ntb->last_ts = ticks; 1075289546Scem vec_mask = ntb_vec_mask(ntb, vec); 1076250079Scarl 1077289542Scem if ((vec_mask & ntb->db_link_mask) != 0) { 1078289546Scem if (ntb_poll_link(ntb)) 1079289546Scem ntb_link_event(ntb); 1080289540Scem } 1081289540Scem 1082289546Scem if ((vec_mask & ntb->db_valid_mask) != 0) 1083289546Scem ntb_db_event(ntb, vec); 1084289546Scem} 1085250079Scarl 1086289546Scemstatic void 1087289546Scemndev_vec_isr(void *arg) 1088289546Scem{ 1089289546Scem struct ntb_vec *nvec = arg; 1090250079Scarl 1091289546Scem ntb_interrupt(nvec->ntb, nvec->num); 1092250079Scarl} 1093250079Scarl 1094250079Scarlstatic void 1095289546Scemndev_irq_isr(void *arg) 1096250079Scarl{ 1097289546Scem /* If we couldn't set up MSI-X, we only have the one vector. */ 1098289546Scem ntb_interrupt(arg, 0); 1099250079Scarl} 1100250079Scarl 1101250079Scarlstatic int 1102289546Scemntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1103250079Scarl{ 1104289342Scem uint32_t i; 1105250079Scarl 1106289546Scem ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1107250079Scarl M_ZERO | M_WAITOK); 1108250079Scarl for (i = 0; i < num_vectors; i++) { 1109289546Scem ntb->msix_vec[i].num = i; 1110289546Scem ntb->msix_vec[i].ntb = ntb; 1111250079Scarl } 1112250079Scarl 1113250079Scarl return (0); 1114250079Scarl} 1115250079Scarl 1116250079Scarlstatic void 1117289546Scemntb_free_msix_vec(struct ntb_softc *ntb) 1118250079Scarl{ 1119250079Scarl 1120289546Scem if (ntb->msix_vec == NULL) 1121289539Scem return; 1122289539Scem 1123289546Scem free(ntb->msix_vec, M_NTB); 1124289546Scem ntb->msix_vec = NULL; 1125250079Scarl} 1126250079Scarl 1127250079Scarlstatic struct ntb_hw_info * 1128250079Scarlntb_get_device_info(uint32_t device_id) 1129250079Scarl{ 1130250079Scarl struct ntb_hw_info *ep = pci_ids; 1131250079Scarl 1132250079Scarl while (ep->device_id) { 1133250079Scarl if (ep->device_id == device_id) 1134250079Scarl return (ep); 1135250079Scarl ++ep; 1136250079Scarl } 1137250079Scarl return (NULL); 1138250079Scarl} 1139250079Scarl 1140289272Scemstatic void 1141289272Scemntb_teardown_xeon(struct ntb_softc *ntb) 1142250079Scarl{ 1143250079Scarl 1144289617Scem if (ntb->reg != NULL) 1145289617Scem ntb_link_disable(ntb); 1146250079Scarl} 1147250079Scarl 1148289397Scemstatic void 1149289397Scemntb_detect_max_mw(struct ntb_softc *ntb) 1150289397Scem{ 1151289397Scem 1152289648Scem if (ntb->type == NTB_ATOM) { 1153289648Scem ntb->mw_count = ATOM_MW_COUNT; 1154289397Scem return; 1155289397Scem } 1156289397Scem 1157289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1158289539Scem ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1159289397Scem else 1160289539Scem ntb->mw_count = XEON_SNB_MW_COUNT; 1161289397Scem} 1162289397Scem 1163250079Scarlstatic int 1164289348Scemntb_detect_xeon(struct ntb_softc *ntb) 1165250079Scarl{ 1166289348Scem uint8_t ppd, conn_type; 1167250079Scarl 1168289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1169289348Scem ntb->ppd = ppd; 1170250079Scarl 1171289348Scem if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1172290681Scem ntb->dev_type = NTB_DEV_DSD; 1173290681Scem else 1174289257Scem ntb->dev_type = NTB_DEV_USD; 1175289257Scem 1176289397Scem if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1177289397Scem ntb->features |= NTB_SPLIT_BAR; 1178289397Scem 1179289542Scem /* SB01BASE_LOCKUP errata is a superset of SDOORBELL errata */ 1180289542Scem if (HAS_FEATURE(NTB_SB01BASE_LOCKUP)) 1181289542Scem ntb->features |= NTB_SDOORBELL_LOCKUP; 1182289542Scem 1183289348Scem conn_type = ppd & XEON_PPD_CONN_TYPE; 1184289348Scem switch (conn_type) { 1185289348Scem case NTB_CONN_B2B: 1186289348Scem ntb->conn_type = conn_type; 1187289348Scem break; 1188289348Scem case NTB_CONN_RP: 1189289348Scem case NTB_CONN_TRANSPARENT: 1190289348Scem default: 1191289348Scem device_printf(ntb->device, "Unsupported connection type: %u\n", 1192289348Scem (unsigned)conn_type); 1193289348Scem return (ENXIO); 1194289348Scem } 1195289348Scem return (0); 1196289348Scem} 1197289348Scem 1198289348Scemstatic int 1199289648Scemntb_detect_atom(struct ntb_softc *ntb) 1200289348Scem{ 1201289348Scem uint32_t ppd, conn_type; 1202289348Scem 1203289348Scem ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1204289348Scem ntb->ppd = ppd; 1205289348Scem 1206289648Scem if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1207289348Scem ntb->dev_type = NTB_DEV_DSD; 1208289348Scem else 1209289348Scem ntb->dev_type = NTB_DEV_USD; 1210289348Scem 1211289648Scem conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1212289348Scem switch (conn_type) { 1213289348Scem case NTB_CONN_B2B: 1214289348Scem ntb->conn_type = conn_type; 1215289348Scem break; 1216289348Scem default: 1217289348Scem device_printf(ntb->device, "Unsupported NTB configuration\n"); 1218289348Scem return (ENXIO); 1219289348Scem } 1220289348Scem return (0); 1221289348Scem} 1222289348Scem 1223289348Scemstatic int 1224289542Scemntb_xeon_init_dev(struct ntb_softc *ntb) 1225289348Scem{ 1226289542Scem int rc; 1227289348Scem 1228289542Scem ntb->spad_count = XEON_SPAD_COUNT; 1229289542Scem ntb->db_count = XEON_DB_COUNT; 1230289542Scem ntb->db_link_mask = XEON_DB_LINK_BIT; 1231289542Scem ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1232289542Scem ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1233289257Scem 1234289542Scem if (ntb->conn_type != NTB_CONN_B2B) { 1235250079Scarl device_printf(ntb->device, "Connection type %d not supported\n", 1236289348Scem ntb->conn_type); 1237250079Scarl return (ENXIO); 1238250079Scarl } 1239250079Scarl 1240289542Scem ntb->reg = &xeon_reg; 1241289607Scem ntb->self_reg = &xeon_pri_reg; 1242289542Scem ntb->peer_reg = &xeon_b2b_reg; 1243289542Scem ntb->xlat_reg = &xeon_sec_xlat; 1244289542Scem 1245289208Scem /* 1246289208Scem * There is a Xeon hardware errata related to writes to SDOORBELL or 1247289208Scem * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1248289208Scem * which may hang the system. To workaround this use the second memory 1249289208Scem * window to access the interrupt and scratch pad registers on the 1250289208Scem * remote system. 1251289208Scem */ 1252289543Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 1253289543Scem /* Use the last MW for mapping remote spad */ 1254289542Scem ntb->b2b_mw_idx = ntb->mw_count - 1; 1255289543Scem else if (HAS_FEATURE(NTB_B2BDOORBELL_BIT14)) 1256289208Scem /* 1257289542Scem * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1258289542Scem * mirrored to the remote system. Shrink the number of bits by one, 1259289542Scem * since bit 14 is the last bit. 1260289542Scem * 1261289542Scem * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1262289542Scem * anyway. Nor for non-B2B connection types. 1263289542Scem */ 1264289543Scem ntb->db_count = XEON_DB_COUNT - 1; 1265250079Scarl 1266289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1267250079Scarl 1268289542Scem if (ntb->dev_type == NTB_DEV_USD) 1269289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1270289542Scem &xeon_b2b_usd_addr); 1271289542Scem else 1272289542Scem rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1273289542Scem &xeon_b2b_dsd_addr); 1274289542Scem if (rc != 0) 1275289542Scem return (rc); 1276289271Scem 1277250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1278290682Scem ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1279289542Scem PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1280255279Scarl 1281290682Scem /* 1282290682Scem * Mask all doorbell interrupts. 1283290682Scem */ 1284290682Scem ntb_db_set_mask(ntb, ntb->db_valid_mask); 1285250079Scarl 1286290682Scem rc = ntb_init_isr(ntb); 1287290682Scem return (rc); 1288250079Scarl} 1289250079Scarl 1290250079Scarlstatic int 1291289648Scemntb_atom_init_dev(struct ntb_softc *ntb) 1292250079Scarl{ 1293290682Scem int error; 1294250079Scarl 1295289348Scem KASSERT(ntb->conn_type == NTB_CONN_B2B, 1296289348Scem ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1297250079Scarl 1298289648Scem ntb->spad_count = ATOM_SPAD_COUNT; 1299289648Scem ntb->db_count = ATOM_DB_COUNT; 1300289648Scem ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1301289648Scem ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1302289542Scem ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1303250079Scarl 1304289648Scem ntb->reg = &atom_reg; 1305289648Scem ntb->self_reg = &atom_pri_reg; 1306289648Scem ntb->peer_reg = &atom_b2b_reg; 1307289648Scem ntb->xlat_reg = &atom_sec_xlat; 1308289542Scem 1309250079Scarl /* 1310289648Scem * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1311250079Scarl * resolved. Mask transaction layer internal parity errors. 1312250079Scarl */ 1313250079Scarl pci_write_config(ntb->device, 0xFC, 0x4, 4); 1314250079Scarl 1315289648Scem configure_atom_secondary_side_bars(ntb); 1316250079Scarl 1317250079Scarl /* Enable Bus Master and Memory Space on the secondary side */ 1318290682Scem ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1319250079Scarl PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1320289209Scem 1321290682Scem error = ntb_init_isr(ntb); 1322290682Scem if (error != 0) 1323290682Scem return (error); 1324290682Scem 1325289542Scem /* Initiate PCI-E link training */ 1326289546Scem ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1327250079Scarl 1328289648Scem callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1329289542Scem 1330250079Scarl return (0); 1331250079Scarl} 1332250079Scarl 1333289648Scem/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1334255279Scarlstatic void 1335289648Scemconfigure_atom_secondary_side_bars(struct ntb_softc *ntb) 1336255279Scarl{ 1337255279Scarl 1338255279Scarl if (ntb->dev_type == NTB_DEV_USD) { 1339289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1340289542Scem XEON_B2B_BAR2_DSD_ADDR64); 1341289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1342289542Scem XEON_B2B_BAR4_DSD_ADDR64); 1343289648Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_USD_ADDR64); 1344289648Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_USD_ADDR64); 1345255279Scarl } else { 1346289648Scem ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1347289542Scem XEON_B2B_BAR2_USD_ADDR64); 1348289648Scem ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1349289542Scem XEON_B2B_BAR4_USD_ADDR64); 1350289648Scem ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_DSD_ADDR64); 1351289648Scem ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_DSD_ADDR64); 1352255279Scarl } 1353255279Scarl} 1354255279Scarl 1355289543Scem 1356289543Scem/* 1357289543Scem * When working around Xeon SDOORBELL errata by remapping remote registers in a 1358289543Scem * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1359289543Scem * remains for use by a higher layer. 1360289543Scem * 1361289543Scem * Will only be used if working around SDOORBELL errata and the BIOS-configured 1362289543Scem * MW size is sufficiently large. 1363289543Scem */ 1364289543Scemstatic unsigned int ntb_b2b_mw_share; 1365289543ScemSYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1366289543Scem 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1367289543Scem "MW with higher level consumers. Both sides of the NTB MUST set the same " 1368289543Scem "value here."); 1369289543Scem 1370289543Scemstatic void 1371289543Scemxeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1372289543Scem enum ntb_bar regbar) 1373289543Scem{ 1374289543Scem struct ntb_pci_bar_info *bar; 1375289543Scem uint8_t bar_sz; 1376289543Scem 1377289543Scem if (!HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1378289543Scem return; 1379289543Scem 1380289543Scem bar = &ntb->bar_info[idx]; 1381289543Scem bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1382289543Scem if (idx == regbar) { 1383289543Scem if (ntb->b2b_off != 0) 1384289543Scem bar_sz--; 1385289543Scem else 1386289543Scem bar_sz = 0; 1387289543Scem } 1388289543Scem pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1389289543Scem bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1390289543Scem (void)bar_sz; 1391289543Scem} 1392289543Scem 1393289543Scemstatic void 1394289546Scemxeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1395289543Scem enum ntb_bar idx, enum ntb_bar regbar) 1396289543Scem{ 1397289546Scem uint64_t reg_val; 1398289546Scem uint32_t base_reg, lmt_reg; 1399289543Scem 1400289546Scem bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1401289546Scem if (idx == regbar) 1402289546Scem bar_addr += ntb->b2b_off; 1403289543Scem 1404289546Scem if (!bar_is_64bit(ntb, idx)) { 1405289546Scem ntb_reg_write(4, base_reg, bar_addr); 1406289546Scem reg_val = ntb_reg_read(4, base_reg); 1407289546Scem (void)reg_val; 1408289546Scem 1409289546Scem ntb_reg_write(4, lmt_reg, bar_addr); 1410289546Scem reg_val = ntb_reg_read(4, lmt_reg); 1411289546Scem (void)reg_val; 1412289543Scem } else { 1413289546Scem ntb_reg_write(8, base_reg, bar_addr); 1414289546Scem reg_val = ntb_reg_read(8, base_reg); 1415289546Scem (void)reg_val; 1416289546Scem 1417289546Scem ntb_reg_write(8, lmt_reg, bar_addr); 1418289546Scem reg_val = ntb_reg_read(8, lmt_reg); 1419289546Scem (void)reg_val; 1420289543Scem } 1421289543Scem} 1422289543Scem 1423289543Scemstatic void 1424289543Scemxeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1425289543Scem{ 1426289543Scem struct ntb_pci_bar_info *bar; 1427289543Scem 1428289543Scem bar = &ntb->bar_info[idx]; 1429289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1430289543Scem ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1431289543Scem base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1432289543Scem } else { 1433289543Scem ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1434289543Scem base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1435289543Scem } 1436289543Scem (void)base_addr; 1437289543Scem} 1438289543Scem 1439289542Scemstatic int 1440289542Scemxeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1441289542Scem const struct ntb_b2b_addr *peer_addr) 1442255279Scarl{ 1443289543Scem struct ntb_pci_bar_info *b2b_bar; 1444289543Scem vm_size_t bar_size; 1445289543Scem uint64_t bar_addr; 1446289543Scem enum ntb_bar b2b_bar_num, i; 1447255279Scarl 1448289543Scem if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1449289543Scem b2b_bar = NULL; 1450289543Scem b2b_bar_num = NTB_CONFIG_BAR; 1451289543Scem ntb->b2b_off = 0; 1452289543Scem } else { 1453289543Scem b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1454289543Scem KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1455289543Scem ("invalid b2b mw bar")); 1456289543Scem 1457289543Scem b2b_bar = &ntb->bar_info[b2b_bar_num]; 1458289543Scem bar_size = b2b_bar->size; 1459289543Scem 1460289543Scem if (ntb_b2b_mw_share != 0 && 1461289543Scem (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1462289543Scem ntb->b2b_off = bar_size >> 1; 1463289543Scem else if (bar_size >= XEON_B2B_MIN_SIZE) { 1464289543Scem ntb->b2b_off = 0; 1465289543Scem ntb->mw_count--; 1466289543Scem } else { 1467289543Scem device_printf(ntb->device, 1468289543Scem "B2B bar size is too small!\n"); 1469289543Scem return (EIO); 1470289543Scem } 1471255279Scarl } 1472289542Scem 1473289543Scem /* 1474289543Scem * Reset the secondary bar sizes to match the primary bar sizes. 1475289543Scem * (Except, disable or halve the size of the B2B secondary bar.) 1476289543Scem */ 1477289543Scem for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1478289543Scem xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1479289543Scem 1480289543Scem bar_addr = 0; 1481289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1482289543Scem bar_addr = addr->bar0_addr; 1483289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1484289543Scem bar_addr = addr->bar2_addr64; 1485289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1486289543Scem bar_addr = addr->bar4_addr64; 1487289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1488289543Scem bar_addr = addr->bar4_addr32; 1489289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1490289543Scem bar_addr = addr->bar5_addr32; 1491289543Scem else 1492289543Scem KASSERT(false, ("invalid bar")); 1493289543Scem 1494289543Scem ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1495289543Scem 1496289543Scem /* 1497289543Scem * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1498289543Scem * register BAR. The B2B BAR is either disabled above or configured 1499289543Scem * half-size. It starts at PBAR xlat + offset. 1500289543Scem * 1501289543Scem * Also set up incoming BAR limits == base (zero length window). 1502289543Scem */ 1503289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1504289543Scem b2b_bar_num); 1505289542Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1506289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1507289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1508289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1509289543Scem NTB_B2B_BAR_3, b2b_bar_num); 1510289542Scem } else 1511289543Scem xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1512289543Scem NTB_B2B_BAR_2, b2b_bar_num); 1513289543Scem 1514289543Scem /* Zero incoming translation addrs */ 1515289543Scem ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1516289543Scem ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1517289543Scem 1518289543Scem /* Zero outgoing translation limits (whole bar size windows) */ 1519289543Scem ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1520289543Scem ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1521289543Scem 1522289543Scem /* Set outgoing translation offsets */ 1523289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1524289543Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 1525289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1526289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1527289543Scem } else 1528289543Scem xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1529289543Scem 1530289543Scem /* Set the translation offset for B2B registers */ 1531289543Scem bar_addr = 0; 1532289543Scem if (b2b_bar_num == NTB_CONFIG_BAR) 1533289543Scem bar_addr = peer_addr->bar0_addr; 1534289543Scem else if (b2b_bar_num == NTB_B2B_BAR_1) 1535289543Scem bar_addr = peer_addr->bar2_addr64; 1536289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(NTB_SPLIT_BAR)) 1537289543Scem bar_addr = peer_addr->bar4_addr64; 1538289543Scem else if (b2b_bar_num == NTB_B2B_BAR_2) 1539289543Scem bar_addr = peer_addr->bar4_addr32; 1540289543Scem else if (b2b_bar_num == NTB_B2B_BAR_3) 1541289543Scem bar_addr = peer_addr->bar5_addr32; 1542289543Scem else 1543289543Scem KASSERT(false, ("invalid bar")); 1544289543Scem 1545289543Scem /* 1546289543Scem * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1547289543Scem * at a time. 1548289543Scem */ 1549289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1550289543Scem ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1551289542Scem return (0); 1552255279Scarl} 1553255279Scarl 1554289546Scemstatic inline bool 1555289546Scemlink_is_up(struct ntb_softc *ntb) 1556289546Scem{ 1557289546Scem 1558289611Scem if (ntb->type == NTB_XEON) { 1559289611Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1560289611Scem return (true); 1561289546Scem return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1562289611Scem } 1563289546Scem 1564289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1565289648Scem return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1566289546Scem} 1567289546Scem 1568289546Scemstatic inline bool 1569289648Scematom_link_is_err(struct ntb_softc *ntb) 1570289546Scem{ 1571289546Scem uint32_t status; 1572289546Scem 1573289648Scem KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1574289546Scem 1575289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1576289648Scem if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1577289546Scem return (true); 1578289546Scem 1579289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1580289648Scem return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1581289546Scem} 1582289546Scem 1583289648Scem/* Atom does not have link status interrupt, poll on that platform */ 1584250079Scarlstatic void 1585289648Scematom_link_hb(void *arg) 1586250079Scarl{ 1587250079Scarl struct ntb_softc *ntb = arg; 1588289546Scem sbintime_t timo, poll_ts; 1589250079Scarl 1590289546Scem timo = NTB_HB_TIMEOUT * hz; 1591289546Scem poll_ts = ntb->last_ts + timo; 1592289546Scem 1593289542Scem /* 1594289542Scem * Delay polling the link status if an interrupt was received, unless 1595289542Scem * the cached link status says the link is down. 1596289542Scem */ 1597289546Scem if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1598289546Scem timo = poll_ts - ticks; 1599289542Scem goto out; 1600289546Scem } 1601289542Scem 1602289546Scem if (ntb_poll_link(ntb)) 1603289546Scem ntb_link_event(ntb); 1604289542Scem 1605289648Scem if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1606289546Scem /* Link is down with error, proceed with recovery */ 1607289648Scem callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1608289546Scem return; 1609250079Scarl } 1610250079Scarl 1611289542Scemout: 1612289648Scem callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1613250079Scarl} 1614250079Scarl 1615250079Scarlstatic void 1616289648Scematom_perform_link_restart(struct ntb_softc *ntb) 1617250079Scarl{ 1618250079Scarl uint32_t status; 1619250079Scarl 1620250079Scarl /* Driver resets the NTB ModPhy lanes - magic! */ 1621289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1622289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1623289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1624289648Scem ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1625250079Scarl 1626250079Scarl /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1627250079Scarl pause("ModPhy", hz / 10); 1628250079Scarl 1629250079Scarl /* Clear AER Errors, write to clear */ 1630289648Scem status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1631250079Scarl status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1632289648Scem ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1633250079Scarl 1634250079Scarl /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1635289648Scem status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1636289648Scem status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1637289648Scem ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1638250079Scarl 1639250079Scarl /* Clear DeSkew Buffer error, write to clear */ 1640289648Scem status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1641289648Scem status |= ATOM_DESKEWSTS_DBERR; 1642289648Scem ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1643250079Scarl 1644289648Scem status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1645289648Scem status &= ATOM_IBIST_ERR_OFLOW; 1646289648Scem ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1647250079Scarl 1648250079Scarl /* Releases the NTB state machine to allow the link to retrain */ 1649289648Scem status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1650289648Scem status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1651289648Scem ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1652250079Scarl} 1653250079Scarl 1654289546Scem/* 1655289546Scem * ntb_set_ctx() - associate a driver context with an ntb device 1656289546Scem * @ntb: NTB device context 1657289546Scem * @ctx: Driver context 1658289546Scem * @ctx_ops: Driver context operations 1659289546Scem * 1660289546Scem * Associate a driver context and operations with a ntb device. The context is 1661289546Scem * provided by the client driver, and the driver may associate a different 1662289546Scem * context with each ntb device. 1663289546Scem * 1664289546Scem * Return: Zero if the context is associated, otherwise an error number. 1665289546Scem */ 1666289546Scemint 1667289546Scemntb_set_ctx(struct ntb_softc *ntb, void *ctx, const struct ntb_ctx_ops *ops) 1668250079Scarl{ 1669250079Scarl 1670289546Scem if (ctx == NULL || ops == NULL) 1671289546Scem return (EINVAL); 1672289546Scem if (ntb->ctx_ops != NULL) 1673289546Scem return (EINVAL); 1674250079Scarl 1675289546Scem CTX_LOCK(ntb); 1676289546Scem if (ntb->ctx_ops != NULL) { 1677289546Scem CTX_UNLOCK(ntb); 1678289546Scem return (EINVAL); 1679250079Scarl } 1680289546Scem ntb->ntb_ctx = ctx; 1681289546Scem ntb->ctx_ops = ops; 1682289546Scem CTX_UNLOCK(ntb); 1683250079Scarl 1684289546Scem return (0); 1685250079Scarl} 1686250079Scarl 1687289546Scem/* 1688289546Scem * It is expected that this will only be used from contexts where the ctx_lock 1689289546Scem * is not needed to protect ntb_ctx lifetime. 1690289546Scem */ 1691289546Scemvoid * 1692289546Scemntb_get_ctx(struct ntb_softc *ntb, const struct ntb_ctx_ops **ops) 1693289546Scem{ 1694289546Scem 1695289546Scem KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 1696289546Scem if (ops != NULL) 1697289546Scem *ops = ntb->ctx_ops; 1698289546Scem return (ntb->ntb_ctx); 1699289546Scem} 1700289546Scem 1701289546Scem/* 1702289546Scem * ntb_clear_ctx() - disassociate any driver context from an ntb device 1703289546Scem * @ntb: NTB device context 1704289546Scem * 1705289546Scem * Clear any association that may exist between a driver context and the ntb 1706289546Scem * device. 1707289546Scem */ 1708289546Scemvoid 1709289546Scemntb_clear_ctx(struct ntb_softc *ntb) 1710289546Scem{ 1711289546Scem 1712289546Scem CTX_LOCK(ntb); 1713289546Scem ntb->ntb_ctx = NULL; 1714289546Scem ntb->ctx_ops = NULL; 1715289546Scem CTX_UNLOCK(ntb); 1716289546Scem} 1717289546Scem 1718289546Scem/* 1719289546Scem * ntb_link_event() - notify driver context of a change in link status 1720289546Scem * @ntb: NTB device context 1721289546Scem * 1722289546Scem * Notify the driver context that the link status may have changed. The driver 1723289546Scem * should call ntb_link_is_up() to get the current status. 1724289546Scem */ 1725289546Scemvoid 1726289546Scemntb_link_event(struct ntb_softc *ntb) 1727289546Scem{ 1728289546Scem 1729289546Scem CTX_LOCK(ntb); 1730289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 1731289546Scem ntb->ctx_ops->link_event(ntb->ntb_ctx); 1732289546Scem CTX_UNLOCK(ntb); 1733289546Scem} 1734289546Scem 1735289546Scem/* 1736289546Scem * ntb_db_event() - notify driver context of a doorbell event 1737289546Scem * @ntb: NTB device context 1738289546Scem * @vector: Interrupt vector number 1739289546Scem * 1740289546Scem * Notify the driver context of a doorbell event. If hardware supports 1741289546Scem * multiple interrupt vectors for doorbells, the vector number indicates which 1742289546Scem * vector received the interrupt. The vector number is relative to the first 1743289546Scem * vector used for doorbells, starting at zero, and must be less than 1744289546Scem * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 1745289546Scem * doorbell bits need service, and ntb_db_vector_mask() to determine which of 1746289546Scem * those bits are associated with the vector number. 1747289546Scem */ 1748250079Scarlstatic void 1749289546Scemntb_db_event(struct ntb_softc *ntb, uint32_t vec) 1750289272Scem{ 1751289546Scem 1752289546Scem CTX_LOCK(ntb); 1753289546Scem if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 1754289546Scem ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 1755289546Scem CTX_UNLOCK(ntb); 1756289546Scem} 1757289546Scem 1758289546Scem/* 1759289546Scem * ntb_link_enable() - enable the link on the secondary side of the ntb 1760289546Scem * @ntb: NTB device context 1761289546Scem * @max_speed: The maximum link speed expressed as PCIe generation number[0] 1762289546Scem * @max_width: The maximum link width expressed as the number of PCIe lanes[0] 1763289546Scem * 1764289546Scem * Enable the link on the secondary side of the ntb. This can only be done 1765289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1766289546Scem * should train the link to its maximum speed and width, or the requested speed 1767289546Scem * and width, whichever is smaller, if supported. 1768289546Scem * 1769289546Scem * Return: Zero on success, otherwise an error number. 1770289546Scem * 1771289546Scem * [0]: Only NTB_SPEED_AUTO and NTB_WIDTH_AUTO are valid inputs; other speed 1772289546Scem * and width input will be ignored. 1773289546Scem */ 1774289546Scemint 1775289546Scemntb_link_enable(struct ntb_softc *ntb, enum ntb_speed s __unused, 1776289546Scem enum ntb_width w __unused) 1777289546Scem{ 1778289280Scem uint32_t cntl; 1779289272Scem 1780289648Scem if (ntb->type == NTB_ATOM) { 1781289542Scem pci_write_config(ntb->device, NTB_PPD_OFFSET, 1782289648Scem ntb->ppd | ATOM_PPD_INIT_LINK, 4); 1783289546Scem return (0); 1784289542Scem } 1785289542Scem 1786289280Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1787289546Scem ntb_link_event(ntb); 1788289546Scem return (0); 1789289280Scem } 1790289280Scem 1791289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1792289280Scem cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 1793289280Scem cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 1794289397Scem cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 1795289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1796289397Scem cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 1797289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1798289546Scem return (0); 1799289272Scem} 1800289272Scem 1801289546Scem/* 1802289546Scem * ntb_link_disable() - disable the link on the secondary side of the ntb 1803289546Scem * @ntb: NTB device context 1804289546Scem * 1805289546Scem * Disable the link on the secondary side of the ntb. This can only be done 1806289546Scem * from the primary side of the ntb in primary or b2b topology. The ntb device 1807289546Scem * should disable the link. Returning from this call must indicate that a 1808289546Scem * barrier has passed, though with no more writes may pass in either direction 1809289546Scem * across the link, except if this call returns an error number. 1810289546Scem * 1811289546Scem * Return: Zero on success, otherwise an error number. 1812289546Scem */ 1813289546Scemint 1814289542Scemntb_link_disable(struct ntb_softc *ntb) 1815289272Scem{ 1816289272Scem uint32_t cntl; 1817289272Scem 1818289272Scem if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 1819289546Scem ntb_link_event(ntb); 1820289546Scem return (0); 1821289272Scem } 1822289272Scem 1823289542Scem cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1824289280Scem cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 1825289397Scem cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 1826289397Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) 1827289397Scem cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 1828289280Scem cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 1829289542Scem ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 1830289546Scem return (0); 1831289272Scem} 1832289272Scem 1833289272Scemstatic void 1834289648Scemrecover_atom_link(void *arg) 1835250079Scarl{ 1836250079Scarl struct ntb_softc *ntb = arg; 1837289608Scem unsigned speed, width, oldspeed, oldwidth; 1838250079Scarl uint32_t status32; 1839250079Scarl 1840289648Scem atom_perform_link_restart(ntb); 1841250079Scarl 1842289232Scem /* 1843289232Scem * There is a potential race between the 2 NTB devices recovering at 1844289232Scem * the same time. If the times are the same, the link will not recover 1845289232Scem * and the driver will be stuck in this loop forever. Add a random 1846289232Scem * interval to the recovery time to prevent this race. 1847289232Scem */ 1848289648Scem status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 1849289648Scem pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 1850289232Scem 1851289648Scem if (atom_link_is_err(ntb)) 1852250079Scarl goto retry; 1853250079Scarl 1854289542Scem status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 1855289648Scem if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 1856289232Scem goto out; 1857289232Scem 1858289542Scem status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 1859289608Scem width = NTB_LNK_STA_WIDTH(status32); 1860289608Scem speed = status32 & NTB_LINK_SPEED_MASK; 1861289608Scem 1862289608Scem oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 1863289608Scem oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 1864289608Scem if (oldwidth != width || oldspeed != speed) 1865250079Scarl goto retry; 1866250079Scarl 1867289232Scemout: 1868289648Scem callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 1869289542Scem ntb); 1870250079Scarl return; 1871250079Scarl 1872250079Scarlretry: 1873289648Scem callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 1874250079Scarl ntb); 1875250079Scarl} 1876250079Scarl 1877289546Scem/* 1878289546Scem * Polls the HW link status register(s); returns true if something has changed. 1879289546Scem */ 1880289546Scemstatic bool 1881289542Scemntb_poll_link(struct ntb_softc *ntb) 1882250079Scarl{ 1883250079Scarl uint32_t ntb_cntl; 1884289546Scem uint16_t reg_val; 1885250079Scarl 1886289648Scem if (ntb->type == NTB_ATOM) { 1887289542Scem ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 1888289546Scem if (ntb_cntl == ntb->ntb_ctl) 1889289546Scem return (false); 1890289546Scem 1891289542Scem ntb->ntb_ctl = ntb_cntl; 1892289542Scem ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 1893250079Scarl } else { 1894290678Scem db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 1895250079Scarl 1896289546Scem reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 1897289546Scem if (reg_val == ntb->lnk_sta) 1898289546Scem return (false); 1899250079Scarl 1900289546Scem ntb->lnk_sta = reg_val; 1901289542Scem } 1902289546Scem return (true); 1903289542Scem} 1904289542Scem 1905289546Scemstatic inline enum ntb_speed 1906289546Scemntb_link_sta_speed(struct ntb_softc *ntb) 1907250079Scarl{ 1908250079Scarl 1909289546Scem if (!link_is_up(ntb)) 1910289546Scem return (NTB_SPEED_NONE); 1911289546Scem return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 1912250079Scarl} 1913250079Scarl 1914289546Scemstatic inline enum ntb_width 1915289546Scemntb_link_sta_width(struct ntb_softc *ntb) 1916250079Scarl{ 1917250079Scarl 1918289546Scem if (!link_is_up(ntb)) 1919289546Scem return (NTB_WIDTH_NONE); 1920289546Scem return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 1921250079Scarl} 1922250079Scarl 1923289774ScemSYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 1924289774Scem "Driver state, statistics, and HW registers"); 1925289774Scem 1926289774Scem#define NTB_REGSZ_MASK (3ul << 30) 1927289774Scem#define NTB_REG_64 (1ul << 30) 1928289774Scem#define NTB_REG_32 (2ul << 30) 1929289774Scem#define NTB_REG_16 (3ul << 30) 1930289774Scem#define NTB_REG_8 (0ul << 30) 1931289774Scem 1932289774Scem#define NTB_DB_READ (1ul << 29) 1933289774Scem#define NTB_PCI_REG (1ul << 28) 1934289774Scem#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 1935289774Scem 1936289774Scemstatic void 1937289774Scemntb_sysctl_init(struct ntb_softc *ntb) 1938289774Scem{ 1939289774Scem struct sysctl_oid_list *tree_par, *regpar, *statpar, *errpar; 1940289774Scem struct sysctl_ctx_list *ctx; 1941289774Scem struct sysctl_oid *tree, *tmptree; 1942289774Scem 1943289774Scem ctx = device_get_sysctl_ctx(ntb->device); 1944289774Scem 1945289774Scem tree = SYSCTL_ADD_NODE(ctx, 1946289774Scem SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)), OID_AUTO, 1947289774Scem "debug_info", CTLFLAG_RD, NULL, 1948289774Scem "Driver state, statistics, and HW registers"); 1949289774Scem tree_par = SYSCTL_CHILDREN(tree); 1950289774Scem 1951289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 1952289774Scem &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 1953289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 1954289774Scem &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 1955289774Scem 1956289774Scem if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 1957289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 1958289774Scem &ntb->b2b_mw_idx, 0, 1959289774Scem "Index of the MW used for B2B remote register access"); 1960289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 1961289774Scem CTLFLAG_RD, &ntb->b2b_off, 1962289774Scem "If non-zero, offset of B2B register region in shared MW"); 1963289774Scem } 1964289774Scem 1965289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 1966289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 1967289774Scem "Features/errata of this NTB device"); 1968289774Scem 1969289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 1970289774Scem &ntb->ntb_ctl, 0, "NTB CTL register (cached)"); 1971289774Scem SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 1972289774Scem &ntb->lnk_sta, 0, "LNK STA register (cached)"); 1973289774Scem 1974289774Scem SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "link_status", 1975289774Scem CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_link_status, 1976289774Scem "A", "Link status"); 1977289774Scem 1978289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 1979289774Scem &ntb->mw_count, 0, "MW count (excl. non-shared B2B register BAR)"); 1980289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 1981289774Scem &ntb->spad_count, 0, "Scratchpad count"); 1982289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 1983289774Scem &ntb->db_count, 0, "Doorbell count"); 1984289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 1985289774Scem &ntb->db_vec_count, 0, "Doorbell vector count"); 1986289774Scem SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 1987289774Scem &ntb->db_vec_shift, 0, "Doorbell vector shift"); 1988289774Scem 1989289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 1990289774Scem &ntb->db_valid_mask, "Doorbell valid mask"); 1991289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 1992289774Scem &ntb->db_link_mask, "Doorbell link mask"); 1993289774Scem SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 1994289774Scem &ntb->db_mask, "Doorbell mask (cached)"); 1995289774Scem 1996289774Scem tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 1997289774Scem CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 1998289774Scem regpar = SYSCTL_CHILDREN(tmptree); 1999289774Scem 2000290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2001290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2002290682Scem ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2003290682Scem "NTB Control register"); 2004290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2005290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2006290682Scem 0x19c, sysctl_handle_register, "IU", 2007290682Scem "NTB Link Capabilities"); 2008290682Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2009290682Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2010290682Scem 0x1a0, sysctl_handle_register, "IU", 2011290682Scem "NTB Link Control register"); 2012290682Scem 2013289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2014289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2015289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2016289774Scem sysctl_handle_register, "QU", "Doorbell mask register"); 2017289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2018289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2019289774Scem NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2020289774Scem sysctl_handle_register, "QU", "Doorbell register"); 2021289774Scem 2022289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2023289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2024289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2025289774Scem sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2026289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2027289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2028289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2029289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2030289774Scem sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2031289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2032289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2033289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2034289774Scem sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2035289774Scem } else { 2036289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2037289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2038289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2039289774Scem sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2040289774Scem } 2041289774Scem 2042289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2043289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2044289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2045289774Scem sysctl_handle_register, "QU", "Incoming LMT23 register"); 2046289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2047289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2048289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2049289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2050289774Scem sysctl_handle_register, "IU", "Incoming LMT4 register"); 2051289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2052289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2053289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2054289774Scem sysctl_handle_register, "IU", "Incoming LMT5 register"); 2055289774Scem } else { 2056289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2057289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2058289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2059289774Scem sysctl_handle_register, "QU", "Incoming LMT45 register"); 2060289774Scem } 2061289774Scem 2062289774Scem if (ntb->type == NTB_ATOM) 2063289774Scem return; 2064289774Scem 2065289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2066289774Scem CTLFLAG_RD, NULL, "Xeon HW statistics"); 2067289774Scem statpar = SYSCTL_CHILDREN(tmptree); 2068289774Scem SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2069289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2070289774Scem NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2071289774Scem sysctl_handle_register, "SU", "Upstream Memory Miss"); 2072289774Scem 2073289774Scem tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2074289774Scem CTLFLAG_RD, NULL, "Xeon HW errors"); 2075289774Scem errpar = SYSCTL_CHILDREN(tmptree); 2076289774Scem 2077289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "devsts", 2078289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2079289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2080289774Scem sysctl_handle_register, "SU", "DEVSTS"); 2081289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "lnksts", 2082289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2083289774Scem NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2084289774Scem sysctl_handle_register, "SU", "LNKSTS"); 2085289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2086289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2087289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2088289774Scem sysctl_handle_register, "IU", "UNCERRSTS"); 2089289774Scem SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2090289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2091289774Scem NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2092289774Scem sysctl_handle_register, "IU", "CORERRSTS"); 2093289774Scem 2094289774Scem if (ntb->conn_type != NTB_CONN_B2B) 2095289774Scem return; 2096289774Scem 2097289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2098289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2099289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2100289774Scem sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2101289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2102289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2103289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2104289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2105289774Scem sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2106289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2107289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2108289774Scem NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2109289774Scem sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2110289774Scem } else { 2111289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2112289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2113289774Scem NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2114289774Scem sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2115289774Scem } 2116289774Scem 2117289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2118289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2119289774Scem NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2120289774Scem sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2121289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2122289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2123289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2124289774Scem NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2125289774Scem sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2126289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2127289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2128289774Scem NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2129289774Scem sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2130289774Scem } else { 2131289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2132289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2133289774Scem NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2134289774Scem sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2135289774Scem } 2136289774Scem 2137289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2138289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2139289774Scem NTB_REG_64 | ntb->xlat_reg->bar0_base, 2140289774Scem sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2141289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2142289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2143289774Scem NTB_REG_64 | ntb->xlat_reg->bar2_base, 2144289774Scem sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2145289774Scem if (HAS_FEATURE(NTB_SPLIT_BAR)) { 2146289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2147289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2148289774Scem NTB_REG_32 | ntb->xlat_reg->bar4_base, 2149289774Scem sysctl_handle_register, "IU", 2150289774Scem "Secondary BAR4 base register"); 2151289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2152289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2153289774Scem NTB_REG_32 | ntb->xlat_reg->bar5_base, 2154289774Scem sysctl_handle_register, "IU", 2155289774Scem "Secondary BAR5 base register"); 2156289774Scem } else { 2157289774Scem SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2158289774Scem CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2159289774Scem NTB_REG_64 | ntb->xlat_reg->bar4_base, 2160289774Scem sysctl_handle_register, "QU", 2161289774Scem "Secondary BAR45 base register"); 2162289774Scem } 2163289774Scem} 2164289774Scem 2165289774Scemstatic int 2166289774Scemsysctl_handle_features(SYSCTL_HANDLER_ARGS) 2167289774Scem{ 2168289774Scem struct ntb_softc *ntb; 2169289774Scem struct sbuf sb; 2170289774Scem int error; 2171289774Scem 2172289774Scem error = 0; 2173289774Scem ntb = arg1; 2174289774Scem 2175289774Scem sbuf_new_for_sysctl(&sb, NULL, 256, req); 2176289774Scem 2177289774Scem sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2178289774Scem error = sbuf_finish(&sb); 2179289774Scem sbuf_delete(&sb); 2180289774Scem 2181289774Scem if (error || !req->newptr) 2182289774Scem return (error); 2183289774Scem return (EINVAL); 2184289774Scem} 2185289774Scem 2186289774Scemstatic int 2187289774Scemsysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2188289774Scem{ 2189289774Scem struct ntb_softc *ntb; 2190289774Scem struct sbuf sb; 2191289774Scem enum ntb_speed speed; 2192289774Scem enum ntb_width width; 2193289774Scem int error; 2194289774Scem 2195289774Scem error = 0; 2196289774Scem ntb = arg1; 2197289774Scem 2198289774Scem sbuf_new_for_sysctl(&sb, NULL, 32, req); 2199289774Scem 2200289774Scem if (ntb_link_is_up(ntb, &speed, &width)) 2201289774Scem sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2202289774Scem (unsigned)speed, (unsigned)width); 2203289774Scem else 2204289774Scem sbuf_printf(&sb, "down"); 2205289774Scem 2206289774Scem error = sbuf_finish(&sb); 2207289774Scem sbuf_delete(&sb); 2208289774Scem 2209289774Scem if (error || !req->newptr) 2210289774Scem return (error); 2211289774Scem return (EINVAL); 2212289774Scem} 2213289774Scem 2214289774Scemstatic int 2215289774Scemsysctl_handle_register(SYSCTL_HANDLER_ARGS) 2216289774Scem{ 2217289774Scem struct ntb_softc *ntb; 2218289774Scem const void *outp; 2219289774Scem uintptr_t sz; 2220289774Scem uint64_t umv; 2221289774Scem char be[sizeof(umv)]; 2222289774Scem size_t outsz; 2223289774Scem uint32_t reg; 2224289774Scem bool db, pci; 2225289774Scem int error; 2226289774Scem 2227289774Scem ntb = arg1; 2228289774Scem reg = arg2 & ~NTB_REGFLAGS_MASK; 2229289774Scem sz = arg2 & NTB_REGSZ_MASK; 2230289774Scem db = (arg2 & NTB_DB_READ) != 0; 2231289774Scem pci = (arg2 & NTB_PCI_REG) != 0; 2232289774Scem 2233289774Scem KASSERT(!(db && pci), ("bogus")); 2234289774Scem 2235289774Scem if (db) { 2236289774Scem KASSERT(sz == NTB_REG_64, ("bogus")); 2237289774Scem umv = db_ioread(ntb, reg); 2238289774Scem outsz = sizeof(uint64_t); 2239289774Scem } else { 2240289774Scem switch (sz) { 2241289774Scem case NTB_REG_64: 2242289774Scem if (pci) 2243289774Scem umv = pci_read_config(ntb->device, reg, 8); 2244289774Scem else 2245289774Scem umv = ntb_reg_read(8, reg); 2246289774Scem outsz = sizeof(uint64_t); 2247289774Scem break; 2248289774Scem case NTB_REG_32: 2249289774Scem if (pci) 2250289774Scem umv = pci_read_config(ntb->device, reg, 4); 2251289774Scem else 2252289774Scem umv = ntb_reg_read(4, reg); 2253289774Scem outsz = sizeof(uint32_t); 2254289774Scem break; 2255289774Scem case NTB_REG_16: 2256289774Scem if (pci) 2257289774Scem umv = pci_read_config(ntb->device, reg, 2); 2258289774Scem else 2259289774Scem umv = ntb_reg_read(2, reg); 2260289774Scem outsz = sizeof(uint16_t); 2261289774Scem break; 2262289774Scem case NTB_REG_8: 2263289774Scem if (pci) 2264289774Scem umv = pci_read_config(ntb->device, reg, 1); 2265289774Scem else 2266289774Scem umv = ntb_reg_read(1, reg); 2267289774Scem outsz = sizeof(uint8_t); 2268289774Scem break; 2269289774Scem default: 2270289774Scem panic("bogus"); 2271289774Scem break; 2272289774Scem } 2273289774Scem } 2274289774Scem 2275289774Scem /* Encode bigendian so that sysctl -x is legible. */ 2276289774Scem be64enc(be, umv); 2277289774Scem outp = ((char *)be) + sizeof(umv) - outsz; 2278289774Scem 2279289774Scem error = SYSCTL_OUT(req, outp, outsz); 2280289774Scem if (error || !req->newptr) 2281289774Scem return (error); 2282289774Scem return (EINVAL); 2283289774Scem} 2284289774Scem 2285289546Scem/* 2286289546Scem * Public API to the rest of the OS 2287250079Scarl */ 2288250079Scarl 2289250079Scarl/** 2290250079Scarl * ntb_get_max_spads() - get the total scratch regs usable 2291250079Scarl * @ntb: pointer to ntb_softc instance 2292250079Scarl * 2293250079Scarl * This function returns the max 32bit scratchpad registers usable by the 2294250079Scarl * upper layer. 2295250079Scarl * 2296250079Scarl * RETURNS: total number of scratch pad registers available 2297250079Scarl */ 2298289208Scemuint8_t 2299250079Scarlntb_get_max_spads(struct ntb_softc *ntb) 2300250079Scarl{ 2301250079Scarl 2302289539Scem return (ntb->spad_count); 2303250079Scarl} 2304250079Scarl 2305289396Scemuint8_t 2306289539Scemntb_mw_count(struct ntb_softc *ntb) 2307289396Scem{ 2308289396Scem 2309289539Scem return (ntb->mw_count); 2310289396Scem} 2311289396Scem 2312250079Scarl/** 2313289545Scem * ntb_spad_write() - write to the secondary scratchpad register 2314250079Scarl * @ntb: pointer to ntb_softc instance 2315250079Scarl * @idx: index to the scratchpad register, 0 based 2316250079Scarl * @val: the data value to put into the register 2317250079Scarl * 2318250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2319250079Scarl * register. The register resides on the secondary (external) side. 2320250079Scarl * 2321289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2322250079Scarl */ 2323250079Scarlint 2324289545Scemntb_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2325250079Scarl{ 2326250079Scarl 2327289539Scem if (idx >= ntb->spad_count) 2328250079Scarl return (EINVAL); 2329250079Scarl 2330289607Scem ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2331250079Scarl 2332250079Scarl return (0); 2333250079Scarl} 2334250079Scarl 2335250079Scarl/** 2336289545Scem * ntb_spad_read() - read from the primary scratchpad register 2337250079Scarl * @ntb: pointer to ntb_softc instance 2338250079Scarl * @idx: index to scratchpad register, 0 based 2339250079Scarl * @val: pointer to 32bit integer for storing the register value 2340250079Scarl * 2341250079Scarl * This function allows reading of the 32bit scratchpad register on 2342250079Scarl * the primary (internal) side. 2343250079Scarl * 2344289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2345250079Scarl */ 2346250079Scarlint 2347289545Scemntb_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2348250079Scarl{ 2349250079Scarl 2350289539Scem if (idx >= ntb->spad_count) 2351250079Scarl return (EINVAL); 2352250079Scarl 2353289607Scem *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2354250079Scarl 2355250079Scarl return (0); 2356250079Scarl} 2357250079Scarl 2358250079Scarl/** 2359289545Scem * ntb_peer_spad_write() - write to the secondary scratchpad register 2360250079Scarl * @ntb: pointer to ntb_softc instance 2361250079Scarl * @idx: index to the scratchpad register, 0 based 2362250079Scarl * @val: the data value to put into the register 2363250079Scarl * 2364250079Scarl * This function allows writing of a 32bit value to the indexed scratchpad 2365250079Scarl * register. The register resides on the secondary (external) side. 2366250079Scarl * 2367289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2368250079Scarl */ 2369250079Scarlint 2370289545Scemntb_peer_spad_write(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 2371250079Scarl{ 2372250079Scarl 2373289539Scem if (idx >= ntb->spad_count) 2374250079Scarl return (EINVAL); 2375250079Scarl 2376289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2377290682Scem ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2378255279Scarl else 2379289542Scem ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2380250079Scarl 2381250079Scarl return (0); 2382250079Scarl} 2383250079Scarl 2384250079Scarl/** 2385289545Scem * ntb_peer_spad_read() - read from the primary scratchpad register 2386250079Scarl * @ntb: pointer to ntb_softc instance 2387250079Scarl * @idx: index to scratchpad register, 0 based 2388250079Scarl * @val: pointer to 32bit integer for storing the register value 2389250079Scarl * 2390250079Scarl * This function allows reading of the 32bit scratchpad register on 2391250079Scarl * the primary (internal) side. 2392250079Scarl * 2393289209Scem * RETURNS: An appropriate ERRNO error value on error, or zero for success. 2394250079Scarl */ 2395250079Scarlint 2396289545Scemntb_peer_spad_read(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 2397250079Scarl{ 2398250079Scarl 2399289539Scem if (idx >= ntb->spad_count) 2400250079Scarl return (EINVAL); 2401250079Scarl 2402289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) 2403290682Scem *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2404255279Scarl else 2405289542Scem *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2406250079Scarl 2407250079Scarl return (0); 2408250079Scarl} 2409250079Scarl 2410289546Scem/* 2411289546Scem * ntb_mw_get_range() - get the range of a memory window 2412289546Scem * @ntb: NTB device context 2413289546Scem * @idx: Memory window number 2414289546Scem * @base: OUT - the base address for mapping the memory window 2415289546Scem * @size: OUT - the size for mapping the memory window 2416289546Scem * @align: OUT - the base alignment for translating the memory window 2417289546Scem * @align_size: OUT - the size alignment for translating the memory window 2418250079Scarl * 2419289546Scem * Get the range of a memory window. NULL may be given for any output 2420289546Scem * parameter if the value is not needed. The base and size may be used for 2421289546Scem * mapping the memory window, to access the peer memory. The alignment and 2422289546Scem * size may be used for translating the memory window, for the peer to access 2423289546Scem * memory on the local system. 2424250079Scarl * 2425289546Scem * Return: Zero on success, otherwise an error number. 2426250079Scarl */ 2427289546Scemint 2428289546Scemntb_mw_get_range(struct ntb_softc *ntb, unsigned mw_idx, vm_paddr_t *base, 2429290679Scem caddr_t *vbase, size_t *size, size_t *align, size_t *align_size) 2430250079Scarl{ 2431289546Scem struct ntb_pci_bar_info *bar; 2432289546Scem size_t bar_b2b_off; 2433250079Scarl 2434289546Scem if (mw_idx >= ntb_mw_count(ntb)) 2435289546Scem return (EINVAL); 2436250079Scarl 2437289546Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, mw_idx)]; 2438289546Scem bar_b2b_off = 0; 2439289546Scem if (mw_idx == ntb->b2b_mw_idx) { 2440289546Scem KASSERT(ntb->b2b_off != 0, 2441289546Scem ("user shouldn't get non-shared b2b mw")); 2442289546Scem bar_b2b_off = ntb->b2b_off; 2443289546Scem } 2444250079Scarl 2445289546Scem if (base != NULL) 2446289546Scem *base = bar->pbase + bar_b2b_off; 2447289546Scem if (vbase != NULL) 2448290679Scem *vbase = bar->vbase + bar_b2b_off; 2449289546Scem if (size != NULL) 2450289546Scem *size = bar->size - bar_b2b_off; 2451289546Scem if (align != NULL) 2452289546Scem *align = bar->size; 2453289546Scem if (align_size != NULL) 2454289546Scem *align_size = 1; 2455289546Scem return (0); 2456250079Scarl} 2457250079Scarl 2458289546Scem/* 2459289546Scem * ntb_mw_set_trans() - set the translation of a memory window 2460289546Scem * @ntb: NTB device context 2461289546Scem * @idx: Memory window number 2462289546Scem * @addr: The dma address local memory to expose to the peer 2463289546Scem * @size: The size of the local memory to expose to the peer 2464250079Scarl * 2465289546Scem * Set the translation of a memory window. The peer may access local memory 2466289546Scem * through the window starting at the address, up to the size. The address 2467289546Scem * must be aligned to the alignment specified by ntb_mw_get_range(). The size 2468289546Scem * must be aligned to the size alignment specified by ntb_mw_get_range(). 2469250079Scarl * 2470289546Scem * Return: Zero on success, otherwise an error number. 2471250079Scarl */ 2472289546Scemint 2473289546Scemntb_mw_set_trans(struct ntb_softc *ntb, unsigned idx, bus_addr_t addr, 2474289546Scem size_t size) 2475250079Scarl{ 2476289546Scem struct ntb_pci_bar_info *bar; 2477289546Scem uint64_t base, limit, reg_val; 2478289546Scem size_t bar_size, mw_size; 2479289546Scem uint32_t base_reg, xlat_reg, limit_reg; 2480289546Scem enum ntb_bar bar_num; 2481250079Scarl 2482289546Scem if (idx >= ntb_mw_count(ntb)) 2483289546Scem return (EINVAL); 2484250079Scarl 2485289546Scem bar_num = ntb_mw_to_bar(ntb, idx); 2486289546Scem bar = &ntb->bar_info[bar_num]; 2487250079Scarl 2488289546Scem bar_size = bar->size; 2489289546Scem if (idx == ntb->b2b_mw_idx) 2490289546Scem mw_size = bar_size - ntb->b2b_off; 2491289546Scem else 2492289546Scem mw_size = bar_size; 2493250079Scarl 2494289546Scem /* Hardware requires that addr is aligned to bar size */ 2495289546Scem if ((addr & (bar_size - 1)) != 0) 2496289546Scem return (EINVAL); 2497250079Scarl 2498289546Scem if (size > mw_size) 2499289546Scem return (EINVAL); 2500289546Scem 2501289546Scem bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2502289546Scem 2503289546Scem limit = 0; 2504289546Scem if (bar_is_64bit(ntb, bar_num)) { 2505289546Scem base = ntb_reg_read(8, base_reg); 2506289546Scem 2507289546Scem if (limit_reg != 0 && size != mw_size) 2508289546Scem limit = base + size; 2509289546Scem 2510289546Scem /* Set and verify translation address */ 2511289546Scem ntb_reg_write(8, xlat_reg, addr); 2512289546Scem reg_val = ntb_reg_read(8, xlat_reg); 2513289546Scem if (reg_val != addr) { 2514289546Scem ntb_reg_write(8, xlat_reg, 0); 2515289546Scem return (EIO); 2516289546Scem } 2517289546Scem 2518289546Scem /* Set and verify the limit */ 2519289546Scem ntb_reg_write(8, limit_reg, limit); 2520289546Scem reg_val = ntb_reg_read(8, limit_reg); 2521289546Scem if (reg_val != limit) { 2522289546Scem ntb_reg_write(8, limit_reg, base); 2523289546Scem ntb_reg_write(8, xlat_reg, 0); 2524289546Scem return (EIO); 2525289546Scem } 2526289546Scem } else { 2527289546Scem /* Configure 32-bit (split) BAR MW */ 2528289546Scem 2529289546Scem if ((addr & ~UINT32_MAX) != 0) 2530289546Scem return (EINVAL); 2531289546Scem if (((addr + size) & ~UINT32_MAX) != 0) 2532289546Scem return (EINVAL); 2533289546Scem 2534289546Scem base = ntb_reg_read(4, base_reg); 2535289546Scem 2536289546Scem if (limit_reg != 0 && size != mw_size) 2537289546Scem limit = base + size; 2538289546Scem 2539289546Scem /* Set and verify translation address */ 2540289546Scem ntb_reg_write(4, xlat_reg, addr); 2541289546Scem reg_val = ntb_reg_read(4, xlat_reg); 2542289546Scem if (reg_val != addr) { 2543289546Scem ntb_reg_write(4, xlat_reg, 0); 2544289546Scem return (EIO); 2545289546Scem } 2546289546Scem 2547289546Scem /* Set and verify the limit */ 2548289546Scem ntb_reg_write(4, limit_reg, limit); 2549289546Scem reg_val = ntb_reg_read(4, limit_reg); 2550289546Scem if (reg_val != limit) { 2551289546Scem ntb_reg_write(4, limit_reg, base); 2552289546Scem ntb_reg_write(4, xlat_reg, 0); 2553289546Scem return (EIO); 2554289546Scem } 2555250079Scarl } 2556289546Scem return (0); 2557250079Scarl} 2558250079Scarl 2559289596Scem/* 2560289596Scem * ntb_mw_clear_trans() - clear the translation of a memory window 2561289596Scem * @ntb: NTB device context 2562289596Scem * @idx: Memory window number 2563289596Scem * 2564289596Scem * Clear the translation of a memory window. The peer may no longer access 2565289596Scem * local memory through the window. 2566289596Scem * 2567289596Scem * Return: Zero on success, otherwise an error number. 2568289596Scem */ 2569289596Scemint 2570289596Scemntb_mw_clear_trans(struct ntb_softc *ntb, unsigned mw_idx) 2571289596Scem{ 2572289596Scem 2573289596Scem return (ntb_mw_set_trans(ntb, mw_idx, 0, 0)); 2574289596Scem} 2575289596Scem 2576250079Scarl/** 2577289545Scem * ntb_peer_db_set() - Set the doorbell on the secondary/external side 2578250079Scarl * @ntb: pointer to ntb_softc instance 2579289545Scem * @bit: doorbell bits to ring 2580250079Scarl * 2581250079Scarl * This function allows triggering of a doorbell on the secondary/external 2582250079Scarl * side that will initiate an interrupt on the remote host 2583250079Scarl */ 2584250079Scarlvoid 2585289545Scemntb_peer_db_set(struct ntb_softc *ntb, uint64_t bit) 2586250079Scarl{ 2587250079Scarl 2588289538Scem if (HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2589290682Scem ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 2590289347Scem return; 2591289209Scem } 2592289347Scem 2593289546Scem db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 2594250079Scarl} 2595250079Scarl 2596289542Scem/* 2597289542Scem * ntb_get_peer_db_addr() - Return the address of the remote doorbell register, 2598289542Scem * as well as the size of the register (via *sz_out). 2599289542Scem * 2600289542Scem * This function allows a caller using I/OAT DMA to chain the remote doorbell 2601289542Scem * ring to its memory window write. 2602289542Scem * 2603289542Scem * Note that writing the peer doorbell via a memory window will *not* generate 2604289542Scem * an interrupt on the remote host; that must be done seperately. 2605289542Scem */ 2606289542Scembus_addr_t 2607289542Scemntb_get_peer_db_addr(struct ntb_softc *ntb, vm_size_t *sz_out) 2608289542Scem{ 2609289542Scem struct ntb_pci_bar_info *bar; 2610289542Scem uint64_t regoff; 2611289542Scem 2612289542Scem KASSERT(sz_out != NULL, ("must be non-NULL")); 2613289542Scem 2614289542Scem if (!HAS_FEATURE(NTB_SDOORBELL_LOCKUP)) { 2615289542Scem bar = &ntb->bar_info[NTB_CONFIG_BAR]; 2616289542Scem regoff = ntb->peer_reg->db_bell; 2617289542Scem } else { 2618289542Scem KASSERT((HAS_FEATURE(NTB_SPLIT_BAR) && ntb->mw_count == 2) || 2619289542Scem (!HAS_FEATURE(NTB_SPLIT_BAR) && ntb->mw_count == 1), 2620289542Scem ("mw_count invalid after setup")); 2621289543Scem KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 2622289543Scem ("invalid b2b idx")); 2623289542Scem 2624289542Scem bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 2625290682Scem regoff = XEON_PDOORBELL_OFFSET; 2626289542Scem } 2627289542Scem KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 2628289542Scem 2629289542Scem *sz_out = ntb->reg->db_size; 2630289542Scem /* HACK: Specific to current x86 bus implementation. */ 2631289542Scem return ((uint64_t)bar->pci_bus_handle + regoff); 2632289542Scem} 2633289542Scem 2634289597Scem/* 2635289597Scem * ntb_db_valid_mask() - get a mask of doorbell bits supported by the ntb 2636289597Scem * @ntb: NTB device context 2637289597Scem * 2638289597Scem * Hardware may support different number or arrangement of doorbell bits. 2639289597Scem * 2640289597Scem * Return: A mask of doorbell bits supported by the ntb. 2641289597Scem */ 2642289597Scemuint64_t 2643289597Scemntb_db_valid_mask(struct ntb_softc *ntb) 2644289597Scem{ 2645289597Scem 2646289597Scem return (ntb->db_valid_mask); 2647289597Scem} 2648289597Scem 2649289598Scem/* 2650289598Scem * ntb_db_vector_mask() - get a mask of doorbell bits serviced by a vector 2651289598Scem * @ntb: NTB device context 2652289598Scem * @vector: Doorbell vector number 2653289598Scem * 2654289598Scem * Each interrupt vector may have a different number or arrangement of bits. 2655289598Scem * 2656289598Scem * Return: A mask of doorbell bits serviced by a vector. 2657289598Scem */ 2658289598Scemuint64_t 2659289598Scemntb_db_vector_mask(struct ntb_softc *ntb, uint32_t vector) 2660289598Scem{ 2661289598Scem 2662289598Scem if (vector > ntb->db_vec_count) 2663289598Scem return (0); 2664289598Scem return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 2665289598Scem} 2666289598Scem 2667250079Scarl/** 2668289546Scem * ntb_link_is_up() - get the current ntb link state 2669289546Scem * @ntb: NTB device context 2670289546Scem * @speed: OUT - The link speed expressed as PCIe generation number 2671289546Scem * @width: OUT - The link width expressed as the number of PCIe lanes 2672250079Scarl * 2673250079Scarl * RETURNS: true or false based on the hardware link state 2674250079Scarl */ 2675250079Scarlbool 2676289546Scemntb_link_is_up(struct ntb_softc *ntb, enum ntb_speed *speed, 2677289546Scem enum ntb_width *width) 2678250079Scarl{ 2679250079Scarl 2680289546Scem if (speed != NULL) 2681289546Scem *speed = ntb_link_sta_speed(ntb); 2682289546Scem if (width != NULL) 2683289546Scem *width = ntb_link_sta_width(ntb); 2684289546Scem return (link_is_up(ntb)); 2685250079Scarl} 2686250079Scarl 2687255272Scarlstatic void 2688255272Scarlsave_bar_parameters(struct ntb_pci_bar_info *bar) 2689250079Scarl{ 2690255272Scarl 2691289209Scem bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 2692289209Scem bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 2693289209Scem bar->pbase = rman_get_start(bar->pci_resource); 2694289209Scem bar->size = rman_get_size(bar->pci_resource); 2695289209Scem bar->vbase = rman_get_virtual(bar->pci_resource); 2696250079Scarl} 2697255268Scarl 2698289209Scemdevice_t 2699289209Scemntb_get_device(struct ntb_softc *ntb) 2700255268Scarl{ 2701255268Scarl 2702255268Scarl return (ntb->device); 2703255268Scarl} 2704289208Scem 2705289208Scem/* Export HW-specific errata information. */ 2706289208Scembool 2707289774Scemntb_has_feature(struct ntb_softc *ntb, uint32_t feature) 2708289208Scem{ 2709289208Scem 2710289208Scem return (HAS_FEATURE(feature)); 2711289208Scem} 2712