ntb_hw_intel.c revision 289208
1/*- 2 * Copyright (C) 2013 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ntb/ntb_hw/ntb_hw.c 289208 2015-10-13 03:12:11Z cem $"); 29 30#include <sys/param.h> 31#include <sys/kernel.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36#include <sys/queue.h> 37#include <sys/rman.h> 38#include <sys/sysctl.h> 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#include <machine/bus.h> 42#include <machine/pmap.h> 43#include <machine/resource.h> 44#include <dev/pci/pcireg.h> 45#include <dev/pci/pcivar.h> 46 47#include "ntb_regs.h" 48#include "ntb_hw.h" 49 50/* 51 * The Non-Transparent Bridge (NTB) is a device on some Intel processors that 52 * allows you to connect two systems using a PCI-e link. 53 * 54 * This module contains the hardware abstraction layer for the NTB. It allows 55 * you to send and recieve interrupts, map the memory windows and send and 56 * receive messages in the scratch-pad registers. 57 * 58 * NOTE: Much of the code in this module is shared with Linux. Any patches may 59 * be picked up and redistributed in Linux with a dual GPL/BSD license. 60 */ 61 62#define NTB_CONFIG_BAR 0 63#define NTB_B2B_BAR_1 1 64#define NTB_B2B_BAR_2 2 65#define NTB_MAX_BARS 3 66#define NTB_MW_TO_BAR(mw) ((mw) + 1) 67 68#define MAX_MSIX_INTERRUPTS MAX(XEON_MAX_DB_BITS, SOC_MAX_DB_BITS) 69 70#define NTB_HB_TIMEOUT 1 /* second */ 71#define SOC_LINK_RECOVERY_TIME 500 72 73#define DEVICE2SOFTC(dev) ((struct ntb_softc *) device_get_softc(dev)) 74 75enum ntb_device_type { 76 NTB_XEON, 77 NTB_SOC 78}; 79 80/* Device features and workarounds */ 81#define HAS_FEATURE(feature) \ 82 ((ntb->features & (feature)) != 0) 83 84struct ntb_hw_info { 85 uint32_t device_id; 86 const char *desc; 87 enum ntb_device_type type; 88 uint64_t features; 89}; 90 91struct ntb_pci_bar_info { 92 bus_space_tag_t pci_bus_tag; 93 bus_space_handle_t pci_bus_handle; 94 int pci_resource_id; 95 struct resource *pci_resource; 96 vm_paddr_t pbase; 97 void *vbase; 98 u_long size; 99}; 100 101struct ntb_int_info { 102 struct resource *res; 103 int rid; 104 void *tag; 105}; 106 107struct ntb_db_cb { 108 ntb_db_callback callback; 109 unsigned int db_num; 110 void *data; 111 struct ntb_softc *ntb; 112}; 113 114struct ntb_softc { 115 device_t device; 116 enum ntb_device_type type; 117 uint64_t features; 118 119 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 120 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 121 uint32_t allocated_interrupts; 122 123 struct callout heartbeat_timer; 124 struct callout lr_timer; 125 126 void *ntb_transport; 127 ntb_event_callback event_cb; 128 struct ntb_db_cb *db_cb; 129 130 struct { 131 uint8_t max_spads; 132 uint8_t max_db_bits; 133 uint8_t msix_cnt; 134 } limits; 135 struct { 136 uint32_t pdb; 137 uint32_t pdb_mask; 138 uint32_t sdb; 139 uint32_t sbar2_xlat; 140 uint32_t sbar4_xlat; 141 uint32_t spad_remote; 142 uint32_t spad_local; 143 uint32_t lnk_cntl; 144 uint32_t lnk_stat; 145 uint32_t spci_cmd; 146 } reg_ofs; 147 uint8_t conn_type; 148 uint8_t dev_type; 149 uint8_t bits_per_vector; 150 uint8_t link_status; 151 uint8_t link_width; 152 uint8_t link_speed; 153}; 154 155#define ntb_bar_read(SIZE, bar, offset) \ 156 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 157 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 158#define ntb_bar_write(SIZE, bar, offset, val) \ 159 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 160 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 161#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 162#define ntb_reg_write(SIZE, offset, val) \ 163 ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 164#define ntb_mw_read(SIZE, offset) ntb_bar_read(SIZE, NTB_B2B_BAR_2, offset) 165#define ntb_mw_write(SIZE, offset, val) \ 166 ntb_bar_write(SIZE, NTB_B2B_BAR_2, offset, val) 167 168typedef int (*bar_map_strategy)(struct ntb_softc *ntb, 169 struct ntb_pci_bar_info *bar); 170 171static int ntb_probe(device_t device); 172static int ntb_attach(device_t device); 173static int ntb_detach(device_t device); 174static int ntb_map_pci_bars(struct ntb_softc *ntb); 175static int map_pci_bar(struct ntb_softc *ntb, bar_map_strategy strategy, 176 struct ntb_pci_bar_info *bar); 177static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 178static int map_memory_window_bar(struct ntb_softc *ntb, 179 struct ntb_pci_bar_info *bar); 180static void ntb_unmap_pci_bar(struct ntb_softc *ntb); 181static int ntb_setup_interrupts(struct ntb_softc *ntb); 182static void ntb_teardown_interrupts(struct ntb_softc *ntb); 183static void handle_soc_irq(void *arg); 184static void handle_xeon_irq(void *arg); 185static void handle_xeon_event_irq(void *arg); 186static void ntb_handle_legacy_interrupt(void *arg); 187static int ntb_create_callbacks(struct ntb_softc *ntb, int num_vectors); 188static void ntb_free_callbacks(struct ntb_softc *ntb); 189static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 190static int ntb_initialize_hw(struct ntb_softc *ntb); 191static int ntb_setup_xeon(struct ntb_softc *ntb); 192static int ntb_setup_soc(struct ntb_softc *ntb); 193static void configure_soc_secondary_side_bars(struct ntb_softc *ntb); 194static void configure_xeon_secondary_side_bars(struct ntb_softc *ntb); 195static void ntb_handle_heartbeat(void *arg); 196static void ntb_handle_link_event(struct ntb_softc *ntb, int link_state); 197static void recover_soc_link(void *arg); 198static int ntb_check_link_status(struct ntb_softc *ntb); 199static void save_bar_parameters(struct ntb_pci_bar_info *bar); 200 201static struct ntb_hw_info pci_ids[] = { 202 { 0x3C0D8086, "Xeon E5/Core i7 Non-Transparent Bridge B2B", NTB_XEON, 203 NTB_REGS_THRU_MW }, 204 { 0x0C4E8086, "Atom Processor S1200 NTB Primary B2B", NTB_SOC, 0 }, 205 { 0x0E0D8086, "Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 206 NTB_REGS_THRU_MW | NTB_BAR_SIZE_4K }, 207 { 0x00000000, NULL, NTB_SOC, 0 } 208}; 209 210/* 211 * OS <-> Driver interface structures 212 */ 213MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 214 215static device_method_t ntb_pci_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_probe, ntb_probe), 218 DEVMETHOD(device_attach, ntb_attach), 219 DEVMETHOD(device_detach, ntb_detach), 220 DEVMETHOD_END 221}; 222 223static driver_t ntb_pci_driver = { 224 "ntb_hw", 225 ntb_pci_methods, 226 sizeof(struct ntb_softc), 227}; 228 229static devclass_t ntb_devclass; 230DRIVER_MODULE(ntb_hw, pci, ntb_pci_driver, ntb_devclass, NULL, NULL); 231MODULE_VERSION(ntb_hw, 1); 232 233SYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 234 235/* 236 * OS <-> Driver linkage functions 237 */ 238static int 239ntb_probe(device_t device) 240{ 241 struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device)); 242 243 if (p != NULL) { 244 device_set_desc(device, p->desc); 245 return (0); 246 } else 247 return (ENXIO); 248} 249 250#define DETACH_ON_ERROR(func) \ 251 error = func; \ 252 if (error < 0) { \ 253 ntb_detach(device); \ 254 return (error); \ 255 } 256 257static int 258ntb_attach(device_t device) 259{ 260 struct ntb_softc *ntb = DEVICE2SOFTC(device); 261 struct ntb_hw_info *p = ntb_get_device_info(pci_get_devid(device)); 262 int error; 263 264 ntb->device = device; 265 ntb->type = p->type; 266 ntb->features = p->features; 267 268 /* Heartbeat timer for NTB_SOC since there is no link interrupt */ 269 callout_init(&ntb->heartbeat_timer, 1); 270 callout_init(&ntb->lr_timer, 1); 271 272 DETACH_ON_ERROR(ntb_map_pci_bars(ntb)); 273 DETACH_ON_ERROR(ntb_initialize_hw(ntb)); 274 DETACH_ON_ERROR(ntb_setup_interrupts(ntb)); 275 276 pci_enable_busmaster(ntb->device); 277 278 return (error); 279} 280 281static int 282ntb_detach(device_t device) 283{ 284 struct ntb_softc *ntb = DEVICE2SOFTC(device); 285 286 callout_drain(&ntb->heartbeat_timer); 287 callout_drain(&ntb->lr_timer); 288 ntb_teardown_interrupts(ntb); 289 ntb_unmap_pci_bar(ntb); 290 291 return (0); 292} 293 294static int 295ntb_map_pci_bars(struct ntb_softc *ntb) 296{ 297 int rc; 298 299 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 300 rc = map_pci_bar(ntb, map_mmr_bar, &ntb->bar_info[NTB_CONFIG_BAR]); 301 if (rc != 0) 302 return rc; 303 304 ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 305 rc = map_pci_bar(ntb, map_memory_window_bar, 306 &ntb->bar_info[NTB_B2B_BAR_1]); 307 if (rc != 0) 308 return rc; 309 310 ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 311 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 312 rc = map_pci_bar(ntb, map_mmr_bar, 313 &ntb->bar_info[NTB_B2B_BAR_2]); 314 else 315 rc = map_pci_bar(ntb, map_memory_window_bar, 316 &ntb->bar_info[NTB_B2B_BAR_2]); 317 if (rc != 0) 318 return rc; 319 320 return (0); 321} 322 323static int 324map_pci_bar(struct ntb_softc *ntb, bar_map_strategy strategy, 325 struct ntb_pci_bar_info *bar) 326{ 327 int rc; 328 329 rc = strategy(ntb, bar); 330 if (rc != 0) { 331 device_printf(ntb->device, 332 "unable to allocate pci resource\n"); 333 } else { 334 device_printf(ntb->device, 335 "Bar size = %lx, v %p, p %p\n", 336 bar->size, bar->vbase, 337 (void *)(bar->pbase)); 338 } 339 return (rc); 340} 341 342static int 343map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 344{ 345 346 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 347 &bar->pci_resource_id, RF_ACTIVE); 348 349 if (bar->pci_resource == NULL) 350 return (ENXIO); 351 else { 352 save_bar_parameters(bar); 353 return (0); 354 } 355} 356 357static int 358map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 359{ 360 int rc; 361 uint8_t bar_size_bits = 0; 362 363 bar->pci_resource = bus_alloc_resource_any(ntb->device, 364 SYS_RES_MEMORY, &bar->pci_resource_id, RF_ACTIVE); 365 366 if (bar->pci_resource == NULL) 367 return (ENXIO); 368 else { 369 save_bar_parameters(bar); 370 /* 371 * Ivytown NTB BAR sizes are misreported by the hardware due to 372 * a hardware issue. To work around this, query the size it 373 * should be configured to by the device and modify the resource 374 * to correspond to this new size. The BIOS on systems with this 375 * problem is required to provide enough address space to allow 376 * the driver to make this change safely. 377 * 378 * Ideally I could have just specified the size when I allocated 379 * the resource like: 380 * bus_alloc_resource(ntb->device, 381 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 382 * 1ul << bar_size_bits, RF_ACTIVE); 383 * but the PCI driver does not honor the size in this call, so 384 * we have to modify it after the fact. 385 */ 386 if (HAS_FEATURE(NTB_BAR_SIZE_4K)) { 387 if (bar->pci_resource_id == PCIR_BAR(2)) 388 bar_size_bits = pci_read_config(ntb->device, 389 XEON_PBAR23SZ_OFFSET, 1); 390 else 391 bar_size_bits = pci_read_config(ntb->device, 392 XEON_PBAR45SZ_OFFSET, 1); 393 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 394 bar->pci_resource, bar->pbase, 395 bar->pbase + (1ul << bar_size_bits) - 1); 396 if (rc != 0 ) { 397 device_printf(ntb->device, 398 "unable to resize bar\n"); 399 return (rc); 400 } else 401 save_bar_parameters(bar); 402 } 403 404 /* Mark bar region as write combining to improve performance. */ 405 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, 406 VM_MEMATTR_WRITE_COMBINING); 407 if (rc != 0) { 408 device_printf(ntb->device, "unable to mark bar as" 409 " WRITE_COMBINING\n"); 410 return (rc); 411 } 412 } 413 return (0); 414} 415 416static void 417ntb_unmap_pci_bar(struct ntb_softc *ntb) 418{ 419 struct ntb_pci_bar_info *current_bar; 420 int i; 421 422 for (i = 0; i< NTB_MAX_BARS; i++) { 423 current_bar = &ntb->bar_info[i]; 424 if (current_bar->pci_resource != NULL) 425 bus_release_resource(ntb->device, SYS_RES_MEMORY, 426 current_bar->pci_resource_id, 427 current_bar->pci_resource); 428 } 429} 430 431static int 432ntb_setup_interrupts(struct ntb_softc *ntb) 433{ 434 void (*interrupt_handler)(void *); 435 void *int_arg; 436 bool use_msix = 0; 437 uint32_t num_vectors; 438 int i; 439 440 ntb->allocated_interrupts = 0; 441 /* 442 * On SOC, disable all interrupts. On XEON, disable all but Link 443 * Interrupt. The rest will be unmasked as callbacks are registered. 444 */ 445 if (ntb->type == NTB_SOC) 446 ntb_reg_write(8, ntb->reg_ofs.pdb_mask, ~0); 447 else 448 ntb_reg_write(2, ntb->reg_ofs.pdb_mask, 449 ~(1 << ntb->limits.max_db_bits)); 450 451 num_vectors = MIN(pci_msix_count(ntb->device), 452 ntb->limits.max_db_bits); 453 if (num_vectors >= 1) { 454 pci_alloc_msix(ntb->device, &num_vectors); 455 if (num_vectors >= 4) 456 use_msix = TRUE; 457 } 458 459 ntb_create_callbacks(ntb, num_vectors); 460 if (use_msix == TRUE) { 461 for (i = 0; i < num_vectors; i++) { 462 ntb->int_info[i].rid = i + 1; 463 ntb->int_info[i].res = bus_alloc_resource_any( 464 ntb->device, SYS_RES_IRQ, &ntb->int_info[i].rid, 465 RF_ACTIVE); 466 if (ntb->int_info[i].res == NULL) { 467 device_printf(ntb->device, 468 "bus_alloc_resource failed\n"); 469 return (-1); 470 } 471 ntb->int_info[i].tag = NULL; 472 ntb->allocated_interrupts++; 473 if (ntb->type == NTB_SOC) { 474 interrupt_handler = handle_soc_irq; 475 int_arg = &ntb->db_cb[i]; 476 } else { 477 if (i == num_vectors - 1) { 478 interrupt_handler = 479 handle_xeon_event_irq; 480 int_arg = ntb; 481 } else { 482 interrupt_handler = 483 handle_xeon_irq; 484 int_arg = &ntb->db_cb[i]; 485 } 486 } 487 if (bus_setup_intr(ntb->device, ntb->int_info[i].res, 488 INTR_MPSAFE | INTR_TYPE_MISC, NULL, 489 interrupt_handler, int_arg, 490 &ntb->int_info[i].tag) != 0) { 491 device_printf(ntb->device, 492 "bus_setup_intr failed\n"); 493 return (ENXIO); 494 } 495 } 496 } 497 else { 498 ntb->int_info[0].rid = 0; 499 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, 500 SYS_RES_IRQ, &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 501 interrupt_handler = ntb_handle_legacy_interrupt; 502 if (ntb->int_info[0].res == NULL) { 503 device_printf(ntb->device, 504 "bus_alloc_resource failed\n"); 505 return (-1); 506 } 507 ntb->int_info[0].tag = NULL; 508 ntb->allocated_interrupts = 1; 509 510 if (bus_setup_intr(ntb->device, ntb->int_info[0].res, 511 INTR_MPSAFE | INTR_TYPE_MISC, NULL, 512 interrupt_handler, ntb, &ntb->int_info[0].tag) != 0) { 513 514 device_printf(ntb->device, "bus_setup_intr failed\n"); 515 return (ENXIO); 516 } 517 } 518 519 return (0); 520} 521 522static void 523ntb_teardown_interrupts(struct ntb_softc *ntb) 524{ 525 struct ntb_int_info *current_int; 526 int i; 527 528 for (i=0; i<ntb->allocated_interrupts; i++) { 529 current_int = &ntb->int_info[i]; 530 if (current_int->tag != NULL) 531 bus_teardown_intr(ntb->device, current_int->res, 532 current_int->tag); 533 534 if (current_int->res != NULL) 535 bus_release_resource(ntb->device, SYS_RES_IRQ, 536 rman_get_rid(current_int->res), current_int->res); 537 } 538 539 ntb_free_callbacks(ntb); 540 pci_release_msi(ntb->device); 541} 542 543static void 544handle_soc_irq(void *arg) 545{ 546 struct ntb_db_cb *db_cb = arg; 547 struct ntb_softc *ntb = db_cb->ntb; 548 549 ntb_reg_write(8, ntb->reg_ofs.pdb, (uint64_t) 1 << db_cb->db_num); 550 551 if (db_cb->callback != NULL) 552 db_cb->callback(db_cb->data, db_cb->db_num); 553} 554 555static void 556handle_xeon_irq(void *arg) 557{ 558 struct ntb_db_cb *db_cb = arg; 559 struct ntb_softc *ntb = db_cb->ntb; 560 561 /* 562 * On Xeon, there are 16 bits in the interrupt register 563 * but only 4 vectors. So, 5 bits are assigned to the first 3 564 * vectors, with the 4th having a single bit for link 565 * interrupts. 566 */ 567 ntb_reg_write(2, ntb->reg_ofs.pdb, 568 ((1 << ntb->bits_per_vector) - 1) << 569 (db_cb->db_num * ntb->bits_per_vector)); 570 571 if (db_cb->callback != NULL) 572 db_cb->callback(db_cb->data, db_cb->db_num); 573} 574 575/* Since we do not have a HW doorbell in SOC, this is only used in JF/JT */ 576static void 577handle_xeon_event_irq(void *arg) 578{ 579 struct ntb_softc *ntb = arg; 580 int rc; 581 582 rc = ntb_check_link_status(ntb); 583 if (rc != 0) 584 device_printf(ntb->device, "Error determining link status\n"); 585 586 /* bit 15 is always the link bit */ 587 ntb_reg_write(2, ntb->reg_ofs.pdb, 1 << ntb->limits.max_db_bits); 588} 589 590static void 591ntb_handle_legacy_interrupt(void *arg) 592{ 593 struct ntb_softc *ntb = arg; 594 unsigned int i = 0; 595 uint64_t pdb64; 596 uint16_t pdb16; 597 598 if (ntb->type == NTB_SOC) { 599 pdb64 = ntb_reg_read(8, ntb->reg_ofs.pdb); 600 601 while (pdb64) { 602 i = ffs(pdb64); 603 pdb64 &= pdb64 - 1; 604 handle_soc_irq(&ntb->db_cb[i]); 605 } 606 } else { 607 pdb16 = ntb_reg_read(2, ntb->reg_ofs.pdb); 608 609 if ((pdb16 & XEON_DB_HW_LINK) != 0) { 610 handle_xeon_event_irq(ntb); 611 pdb16 &= ~XEON_DB_HW_LINK; 612 } 613 614 while (pdb16 != 0) { 615 i = ffs(pdb16); 616 pdb16 &= pdb16 - 1; 617 handle_xeon_irq(&ntb->db_cb[i]); 618 } 619 } 620 621} 622 623static int 624ntb_create_callbacks(struct ntb_softc *ntb, int num_vectors) 625{ 626 int i; 627 628 ntb->db_cb = malloc(num_vectors * sizeof(struct ntb_db_cb), M_NTB, 629 M_ZERO | M_WAITOK); 630 for (i = 0; i < num_vectors; i++) { 631 ntb->db_cb[i].db_num = i; 632 ntb->db_cb[i].ntb = ntb; 633 } 634 635 return (0); 636} 637 638static void 639ntb_free_callbacks(struct ntb_softc *ntb) 640{ 641 int i; 642 643 for (i = 0; i < ntb->limits.max_db_bits; i++) 644 ntb_unregister_db_callback(ntb, i); 645 646 free(ntb->db_cb, M_NTB); 647} 648 649static struct ntb_hw_info * 650ntb_get_device_info(uint32_t device_id) 651{ 652 struct ntb_hw_info *ep = pci_ids; 653 654 while (ep->device_id) { 655 if (ep->device_id == device_id) 656 return (ep); 657 ++ep; 658 } 659 return (NULL); 660} 661 662static int 663ntb_initialize_hw(struct ntb_softc *ntb) 664{ 665 666 if (ntb->type == NTB_SOC) 667 return (ntb_setup_soc(ntb)); 668 else 669 return (ntb_setup_xeon(ntb)); 670} 671 672static int 673ntb_setup_xeon(struct ntb_softc *ntb) 674{ 675 uint8_t val, connection_type; 676 677 val = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 678 679 connection_type = val & XEON_PPD_CONN_TYPE; 680 switch (connection_type) { 681 case NTB_CONN_B2B: 682 ntb->conn_type = NTB_CONN_B2B; 683 break; 684 case NTB_CONN_CLASSIC: 685 case NTB_CONN_RP: 686 default: 687 device_printf(ntb->device, "Connection type %d not supported\n", 688 connection_type); 689 return (ENXIO); 690 } 691 692 if ((val & XEON_PPD_DEV_TYPE) != 0) 693 ntb->dev_type = NTB_DEV_USD; 694 else 695 ntb->dev_type = NTB_DEV_DSD; 696 697 ntb->reg_ofs.pdb = XEON_PDOORBELL_OFFSET; 698 ntb->reg_ofs.pdb_mask = XEON_PDBMSK_OFFSET; 699 ntb->reg_ofs.sbar2_xlat = XEON_SBAR2XLAT_OFFSET; 700 ntb->reg_ofs.sbar4_xlat = XEON_SBAR4XLAT_OFFSET; 701 ntb->reg_ofs.lnk_cntl = XEON_NTBCNTL_OFFSET; 702 ntb->reg_ofs.lnk_stat = XEON_LINK_STATUS_OFFSET; 703 ntb->reg_ofs.spad_local = XEON_SPAD_OFFSET; 704 ntb->reg_ofs.spci_cmd = XEON_PCICMD_OFFSET; 705 706 /* 707 * There is a Xeon hardware errata related to writes to SDOORBELL or 708 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 709 * which may hang the system. To workaround this use the second memory 710 * window to access the interrupt and scratch pad registers on the 711 * remote system. 712 */ 713 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 714 /* 715 * Set the Limit register to 4k, the minimum size, to prevent 716 * an illegal access. 717 */ 718 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 719 ntb_get_mw_size(ntb, 1) + 0x1000); 720 else 721 /* 722 * Disable the limit register, just in case it is set to 723 * something silly. 724 */ 725 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 726 727 728 if (ntb->conn_type == NTB_CONN_B2B) { 729 ntb->reg_ofs.sdb = XEON_B2B_DOORBELL_OFFSET; 730 ntb->reg_ofs.spad_remote = XEON_B2B_SPAD_OFFSET; 731 ntb->limits.max_spads = XEON_MAX_SPADS; 732 } else { 733 ntb->reg_ofs.sdb = XEON_SDOORBELL_OFFSET; 734 ntb->reg_ofs.spad_remote = XEON_SPAD_OFFSET; 735 ntb->limits.max_spads = XEON_MAX_COMPAT_SPADS; 736 } 737 738 ntb->limits.max_db_bits = XEON_MAX_DB_BITS; 739 ntb->limits.msix_cnt = XEON_MSIX_CNT; 740 ntb->bits_per_vector = XEON_DB_BITS_PER_VEC; 741 742 configure_xeon_secondary_side_bars(ntb); 743 /* Enable Bus Master and Memory Space on the secondary side */ 744 ntb_reg_write(2, ntb->reg_ofs.spci_cmd, 745 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 746 747 /* Enable link training */ 748 ntb_reg_write(4, ntb->reg_ofs.lnk_cntl, 749 NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP); 750 751 return (0); 752} 753 754static int 755ntb_setup_soc(struct ntb_softc *ntb) 756{ 757 uint32_t val, connection_type; 758 759 val = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 760 761 connection_type = (val & SOC_PPD_CONN_TYPE) >> 8; 762 switch (connection_type) { 763 case NTB_CONN_B2B: 764 ntb->conn_type = NTB_CONN_B2B; 765 break; 766 case NTB_CONN_RP: 767 default: 768 device_printf(ntb->device, "Connection type %d not supported\n", 769 connection_type); 770 return (ENXIO); 771 } 772 773 if ((val & SOC_PPD_DEV_TYPE) != 0) 774 ntb->dev_type = NTB_DEV_DSD; 775 else 776 ntb->dev_type = NTB_DEV_USD; 777 778 /* Initiate PCI-E link training */ 779 pci_write_config(ntb->device, NTB_PPD_OFFSET, val | SOC_PPD_INIT_LINK, 780 4); 781 782 ntb->reg_ofs.pdb = SOC_PDOORBELL_OFFSET; 783 ntb->reg_ofs.pdb_mask = SOC_PDBMSK_OFFSET; 784 ntb->reg_ofs.sbar2_xlat = SOC_SBAR2XLAT_OFFSET; 785 ntb->reg_ofs.sbar4_xlat = SOC_SBAR4XLAT_OFFSET; 786 ntb->reg_ofs.lnk_cntl = SOC_NTBCNTL_OFFSET; 787 ntb->reg_ofs.lnk_stat = SOC_LINK_STATUS_OFFSET; 788 ntb->reg_ofs.spad_local = SOC_SPAD_OFFSET; 789 ntb->reg_ofs.spci_cmd = SOC_PCICMD_OFFSET; 790 791 if (ntb->conn_type == NTB_CONN_B2B) { 792 ntb->reg_ofs.sdb = SOC_B2B_DOORBELL_OFFSET; 793 ntb->reg_ofs.spad_remote = SOC_B2B_SPAD_OFFSET; 794 ntb->limits.max_spads = SOC_MAX_SPADS; 795 } else { 796 ntb->reg_ofs.sdb = SOC_PDOORBELL_OFFSET; 797 ntb->reg_ofs.spad_remote = SOC_SPAD_OFFSET; 798 ntb->limits.max_spads = SOC_MAX_COMPAT_SPADS; 799 } 800 801 ntb->limits.max_db_bits = SOC_MAX_DB_BITS; 802 ntb->limits.msix_cnt = SOC_MSIX_CNT; 803 ntb->bits_per_vector = SOC_DB_BITS_PER_VEC; 804 805 /* 806 * FIXME - MSI-X bug on early SOC HW, remove once internal issue is 807 * resolved. Mask transaction layer internal parity errors. 808 */ 809 pci_write_config(ntb->device, 0xFC, 0x4, 4); 810 811 configure_soc_secondary_side_bars(ntb); 812 813 /* Enable Bus Master and Memory Space on the secondary side */ 814 ntb_reg_write(2, ntb->reg_ofs.spci_cmd, 815 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 816 callout_reset(&ntb->heartbeat_timer, 0, ntb_handle_heartbeat, ntb); 817 818 return (0); 819} 820 821static void 822configure_soc_secondary_side_bars(struct ntb_softc *ntb) 823{ 824 825 if (ntb->dev_type == NTB_DEV_USD) { 826 ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET, PBAR2XLAT_USD_ADDR); 827 ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET, PBAR4XLAT_USD_ADDR); 828 ntb_reg_write(8, SOC_MBAR23_OFFSET, MBAR23_USD_ADDR); 829 ntb_reg_write(8, SOC_MBAR45_OFFSET, MBAR45_USD_ADDR); 830 } else { 831 ntb_reg_write(8, SOC_PBAR2XLAT_OFFSET, PBAR2XLAT_DSD_ADDR); 832 ntb_reg_write(8, SOC_PBAR4XLAT_OFFSET, PBAR4XLAT_DSD_ADDR); 833 ntb_reg_write(8, SOC_MBAR23_OFFSET, MBAR23_DSD_ADDR); 834 ntb_reg_write(8, SOC_MBAR45_OFFSET, MBAR45_DSD_ADDR); 835 } 836} 837 838static void 839configure_xeon_secondary_side_bars(struct ntb_softc *ntb) 840{ 841 842 if (ntb->dev_type == NTB_DEV_USD) { 843 ntb_reg_write(8, XEON_PBAR2XLAT_OFFSET, PBAR2XLAT_USD_ADDR); 844 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 845 ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, 846 MBAR01_DSD_ADDR); 847 else { 848 ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, 849 PBAR4XLAT_USD_ADDR); 850 /* 851 * B2B_XLAT_OFFSET is a 64-bit register but can only be 852 * written 32 bits at a time. 853 */ 854 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, 855 MBAR01_DSD_ADDR & 0xffffffff); 856 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, 857 MBAR01_DSD_ADDR >> 32); 858 } 859 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, MBAR01_USD_ADDR); 860 ntb_reg_write(8, XEON_SBAR2BASE_OFFSET, MBAR23_USD_ADDR); 861 ntb_reg_write(8, XEON_SBAR4BASE_OFFSET, MBAR45_USD_ADDR); 862 } else { 863 ntb_reg_write(8, XEON_PBAR2XLAT_OFFSET, PBAR2XLAT_DSD_ADDR); 864 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 865 ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, 866 MBAR01_USD_ADDR); 867 else { 868 ntb_reg_write(8, XEON_PBAR4XLAT_OFFSET, 869 PBAR4XLAT_DSD_ADDR); 870 /* 871 * B2B_XLAT_OFFSET is a 64-bit register but can only be 872 * written 32 bits at a time. 873 */ 874 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, 875 MBAR01_USD_ADDR & 0xffffffff); 876 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, 877 MBAR01_USD_ADDR >> 32); 878 } 879 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, MBAR01_DSD_ADDR); 880 ntb_reg_write(8, XEON_SBAR2BASE_OFFSET, MBAR23_DSD_ADDR); 881 ntb_reg_write(8, XEON_SBAR4BASE_OFFSET, MBAR45_DSD_ADDR); 882 } 883} 884 885/* SOC does not have link status interrupt, poll on that platform */ 886static void 887ntb_handle_heartbeat(void *arg) 888{ 889 struct ntb_softc *ntb = arg; 890 uint32_t status32; 891 int rc = ntb_check_link_status(ntb); 892 893 if (rc != 0) 894 device_printf(ntb->device, 895 "Error determining link status\n"); 896 /* Check to see if a link error is the cause of the link down */ 897 if (ntb->link_status == NTB_LINK_DOWN) { 898 status32 = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); 899 if ((status32 & SOC_LTSSMSTATEJMP_FORCEDETECT) != 0) { 900 callout_reset(&ntb->lr_timer, 0, recover_soc_link, 901 ntb); 902 return; 903 } 904 } 905 906 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, 907 ntb_handle_heartbeat, ntb); 908} 909 910static void 911soc_perform_link_restart(struct ntb_softc *ntb) 912{ 913 uint32_t status; 914 915 /* Driver resets the NTB ModPhy lanes - magic! */ 916 ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0xe0); 917 ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x40); 918 ntb_reg_write(1, SOC_MODPHY_PCSREG4, 0x60); 919 ntb_reg_write(1, SOC_MODPHY_PCSREG6, 0x60); 920 921 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 922 pause("ModPhy", hz / 10); 923 924 /* Clear AER Errors, write to clear */ 925 status = ntb_reg_read(4, SOC_ERRCORSTS_OFFSET); 926 status &= PCIM_AER_COR_REPLAY_ROLLOVER; 927 ntb_reg_write(4, SOC_ERRCORSTS_OFFSET, status); 928 929 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 930 status = ntb_reg_read(4, SOC_LTSSMERRSTS0_OFFSET); 931 status |= SOC_LTSSMERRSTS0_UNEXPECTEDEI; 932 ntb_reg_write(4, SOC_LTSSMERRSTS0_OFFSET, status); 933 934 /* Clear DeSkew Buffer error, write to clear */ 935 status = ntb_reg_read(4, SOC_DESKEWSTS_OFFSET); 936 status |= SOC_DESKEWSTS_DBERR; 937 ntb_reg_write(4, SOC_DESKEWSTS_OFFSET, status); 938 939 status = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET); 940 status &= SOC_IBIST_ERR_OFLOW; 941 ntb_reg_write(4, SOC_IBSTERRRCRVSTS0_OFFSET, status); 942 943 /* Releases the NTB state machine to allow the link to retrain */ 944 status = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); 945 status &= ~SOC_LTSSMSTATEJMP_FORCEDETECT; 946 ntb_reg_write(4, SOC_LTSSMSTATEJMP_OFFSET, status); 947} 948 949static void 950ntb_handle_link_event(struct ntb_softc *ntb, int link_state) 951{ 952 enum ntb_hw_event event; 953 uint16_t status; 954 955 if (ntb->link_status == link_state) 956 return; 957 958 if (link_state == NTB_LINK_UP) { 959 device_printf(ntb->device, "Link Up\n"); 960 ntb->link_status = NTB_LINK_UP; 961 event = NTB_EVENT_HW_LINK_UP; 962 963 if (ntb->type == NTB_SOC) 964 status = ntb_reg_read(2, ntb->reg_ofs.lnk_stat); 965 else 966 status = pci_read_config(ntb->device, 967 XEON_LINK_STATUS_OFFSET, 2); 968 ntb->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4; 969 ntb->link_speed = (status & NTB_LINK_SPEED_MASK); 970 device_printf(ntb->device, "Link Width %d, Link Speed %d\n", 971 ntb->link_width, ntb->link_speed); 972 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, 973 ntb_handle_heartbeat, ntb); 974 } else { 975 device_printf(ntb->device, "Link Down\n"); 976 ntb->link_status = NTB_LINK_DOWN; 977 event = NTB_EVENT_HW_LINK_DOWN; 978 /* Do not modify link width/speed, we need it in link recovery */ 979 } 980 981 /* notify the upper layer if we have an event change */ 982 if (ntb->event_cb != NULL) 983 ntb->event_cb(ntb->ntb_transport, event); 984} 985 986static void 987recover_soc_link(void *arg) 988{ 989 struct ntb_softc *ntb = arg; 990 uint8_t speed, width; 991 uint32_t status32; 992 uint16_t status16; 993 994 soc_perform_link_restart(ntb); 995 pause("Link", SOC_LINK_RECOVERY_TIME * hz / 1000); 996 997 status32 = ntb_reg_read(4, SOC_LTSSMSTATEJMP_OFFSET); 998 if ((status32 & SOC_LTSSMSTATEJMP_FORCEDETECT) != 0) 999 goto retry; 1000 1001 status32 = ntb_reg_read(4, SOC_IBSTERRRCRVSTS0_OFFSET); 1002 if ((status32 & SOC_IBIST_ERR_OFLOW) != 0) 1003 goto retry; 1004 1005 status16 = ntb_reg_read(2, ntb->reg_ofs.lnk_stat); 1006 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4; 1007 speed = (status16 & NTB_LINK_SPEED_MASK); 1008 if (ntb->link_width != width || ntb->link_speed != speed) 1009 goto retry; 1010 1011 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, 1012 ntb_handle_heartbeat, ntb); 1013 return; 1014 1015retry: 1016 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_soc_link, 1017 ntb); 1018} 1019 1020static int 1021ntb_check_link_status(struct ntb_softc *ntb) 1022{ 1023 int link_state; 1024 uint32_t ntb_cntl; 1025 uint16_t status; 1026 1027 if (ntb->type == NTB_SOC) { 1028 ntb_cntl = ntb_reg_read(4, ntb->reg_ofs.lnk_cntl); 1029 if ((ntb_cntl & SOC_CNTL_LINK_DOWN) != 0) 1030 link_state = NTB_LINK_DOWN; 1031 else 1032 link_state = NTB_LINK_UP; 1033 } else { 1034 status = pci_read_config(ntb->device, XEON_LINK_STATUS_OFFSET, 1035 2); 1036 1037 if ((status & NTB_LINK_STATUS_ACTIVE) != 0) 1038 link_state = NTB_LINK_UP; 1039 else 1040 link_state = NTB_LINK_DOWN; 1041 } 1042 1043 ntb_handle_link_event(ntb, link_state); 1044 1045 return (0); 1046} 1047 1048/** 1049 * ntb_register_event_callback() - register event callback 1050 * @ntb: pointer to ntb_softc instance 1051 * @func: callback function to register 1052 * 1053 * This function registers a callback for any HW driver events such as link 1054 * up/down, power management notices and etc. 1055 * 1056 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1057 */ 1058int 1059ntb_register_event_callback(struct ntb_softc *ntb, ntb_event_callback func) 1060{ 1061 1062 if (ntb->event_cb != NULL) 1063 return (EINVAL); 1064 1065 ntb->event_cb = func; 1066 1067 return (0); 1068} 1069 1070/** 1071 * ntb_unregister_event_callback() - unregisters the event callback 1072 * @ntb: pointer to ntb_softc instance 1073 * 1074 * This function unregisters the existing callback from transport 1075 */ 1076void 1077ntb_unregister_event_callback(struct ntb_softc *ntb) 1078{ 1079 1080 ntb->event_cb = NULL; 1081} 1082 1083/** 1084 * ntb_register_db_callback() - register a callback for doorbell interrupt 1085 * @ntb: pointer to ntb_softc instance 1086 * @idx: doorbell index to register callback, zero based 1087 * @func: callback function to register 1088 * 1089 * This function registers a callback function for the doorbell interrupt 1090 * on the primary side. The function will unmask the doorbell as well to 1091 * allow interrupt. 1092 * 1093 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1094 */ 1095int 1096ntb_register_db_callback(struct ntb_softc *ntb, unsigned int idx, void *data, 1097 ntb_db_callback func) 1098{ 1099 uint16_t mask; 1100 1101 if (idx >= ntb->allocated_interrupts || ntb->db_cb[idx].callback) { 1102 device_printf(ntb->device, "Invalid Index.\n"); 1103 return (EINVAL); 1104 } 1105 1106 ntb->db_cb[idx].callback = func; 1107 ntb->db_cb[idx].data = data; 1108 1109 /* unmask interrupt */ 1110 mask = ntb_reg_read(2, ntb->reg_ofs.pdb_mask); 1111 mask &= ~(1 << (idx * ntb->bits_per_vector)); 1112 ntb_reg_write(2, ntb->reg_ofs.pdb_mask, mask); 1113 1114 return (0); 1115} 1116 1117/** 1118 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt 1119 * @ntb: pointer to ntb_softc instance 1120 * @idx: doorbell index to register callback, zero based 1121 * 1122 * This function unregisters a callback function for the doorbell interrupt 1123 * on the primary side. The function will also mask the said doorbell. 1124 */ 1125void 1126ntb_unregister_db_callback(struct ntb_softc *ntb, unsigned int idx) 1127{ 1128 unsigned long mask; 1129 1130 if (idx >= ntb->allocated_interrupts || !ntb->db_cb[idx].callback) 1131 return; 1132 1133 mask = ntb_reg_read(2, ntb->reg_ofs.pdb_mask); 1134 mask |= 1 << (idx * ntb->bits_per_vector); 1135 ntb_reg_write(2, ntb->reg_ofs.pdb_mask, mask); 1136 1137 ntb->db_cb[idx].callback = NULL; 1138} 1139 1140/** 1141 * ntb_find_transport() - find the transport pointer 1142 * @transport: pointer to pci device 1143 * 1144 * Given the pci device pointer, return the transport pointer passed in when 1145 * the transport attached when it was inited. 1146 * 1147 * RETURNS: pointer to transport. 1148 */ 1149void * 1150ntb_find_transport(struct ntb_softc *ntb) 1151{ 1152 1153 return (ntb->ntb_transport); 1154} 1155 1156/** 1157 * ntb_register_transport() - Register NTB transport with NTB HW driver 1158 * @transport: transport identifier 1159 * 1160 * This function allows a transport to reserve the hardware driver for 1161 * NTB usage. 1162 * 1163 * RETURNS: pointer to ntb_softc, NULL on error. 1164 */ 1165struct ntb_softc * 1166ntb_register_transport(struct ntb_softc *ntb, void *transport) 1167{ 1168 1169 /* 1170 * TODO: when we have more than one transport, we will need to rewrite 1171 * this to prevent race conditions 1172 */ 1173 if (ntb->ntb_transport != NULL) 1174 return (NULL); 1175 1176 ntb->ntb_transport = transport; 1177 return (ntb); 1178} 1179 1180/** 1181 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver 1182 * @ntb - ntb_softc of the transport to be freed 1183 * 1184 * This function unregisters the transport from the HW driver and performs any 1185 * necessary cleanups. 1186 */ 1187void 1188ntb_unregister_transport(struct ntb_softc *ntb) 1189{ 1190 int i; 1191 1192 if (ntb->ntb_transport == NULL) 1193 return; 1194 1195 for (i = 0; i < ntb->allocated_interrupts; i++) 1196 ntb_unregister_db_callback(ntb, i); 1197 1198 ntb_unregister_event_callback(ntb); 1199 ntb->ntb_transport = NULL; 1200} 1201 1202/** 1203 * ntb_get_max_spads() - get the total scratch regs usable 1204 * @ntb: pointer to ntb_softc instance 1205 * 1206 * This function returns the max 32bit scratchpad registers usable by the 1207 * upper layer. 1208 * 1209 * RETURNS: total number of scratch pad registers available 1210 */ 1211uint8_t 1212ntb_get_max_spads(struct ntb_softc *ntb) 1213{ 1214 1215 return (ntb->limits.max_spads); 1216} 1217 1218/** 1219 * ntb_write_local_spad() - write to the secondary scratchpad register 1220 * @ntb: pointer to ntb_softc instance 1221 * @idx: index to the scratchpad register, 0 based 1222 * @val: the data value to put into the register 1223 * 1224 * This function allows writing of a 32bit value to the indexed scratchpad 1225 * register. The register resides on the secondary (external) side. 1226 * 1227 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1228 */ 1229int 1230ntb_write_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 1231{ 1232 1233 if (idx >= ntb->limits.max_spads) 1234 return (EINVAL); 1235 1236 ntb_reg_write(4, ntb->reg_ofs.spad_local + idx * 4, val); 1237 1238 return (0); 1239} 1240 1241/** 1242 * ntb_read_local_spad() - read from the primary scratchpad register 1243 * @ntb: pointer to ntb_softc instance 1244 * @idx: index to scratchpad register, 0 based 1245 * @val: pointer to 32bit integer for storing the register value 1246 * 1247 * This function allows reading of the 32bit scratchpad register on 1248 * the primary (internal) side. 1249 * 1250 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1251 */ 1252int 1253ntb_read_local_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 1254{ 1255 1256 if (idx >= ntb->limits.max_spads) 1257 return (EINVAL); 1258 1259 *val = ntb_reg_read(4, ntb->reg_ofs.spad_local + idx * 4); 1260 1261 return (0); 1262} 1263 1264/** 1265 * ntb_write_remote_spad() - write to the secondary scratchpad register 1266 * @ntb: pointer to ntb_softc instance 1267 * @idx: index to the scratchpad register, 0 based 1268 * @val: the data value to put into the register 1269 * 1270 * This function allows writing of a 32bit value to the indexed scratchpad 1271 * register. The register resides on the secondary (external) side. 1272 * 1273 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1274 */ 1275int 1276ntb_write_remote_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t val) 1277{ 1278 1279 if (idx >= ntb->limits.max_spads) 1280 return (EINVAL); 1281 1282 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 1283 ntb_mw_write(4, XEON_SHADOW_SPAD_OFFSET + idx * 4, val); 1284 else 1285 ntb_reg_write(4, ntb->reg_ofs.spad_remote + idx * 4, val); 1286 1287 return (0); 1288} 1289 1290/** 1291 * ntb_read_remote_spad() - read from the primary scratchpad register 1292 * @ntb: pointer to ntb_softc instance 1293 * @idx: index to scratchpad register, 0 based 1294 * @val: pointer to 32bit integer for storing the register value 1295 * 1296 * This function allows reading of the 32bit scratchpad register on 1297 * the primary (internal) side. 1298 * 1299 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1300 */ 1301int 1302ntb_read_remote_spad(struct ntb_softc *ntb, unsigned int idx, uint32_t *val) 1303{ 1304 1305 if (idx >= ntb->limits.max_spads) 1306 return (EINVAL); 1307 1308 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 1309 *val = ntb_mw_read(4, XEON_SHADOW_SPAD_OFFSET + idx * 4); 1310 else 1311 *val = ntb_reg_read(4, ntb->reg_ofs.spad_remote + idx * 4); 1312 1313 return (0); 1314} 1315 1316/** 1317 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window 1318 * @ntb: pointer to ntb_softc instance 1319 * @mw: memory window number 1320 * 1321 * This function provides the base virtual address of the memory window 1322 * specified. 1323 * 1324 * RETURNS: pointer to virtual address, or NULL on error. 1325 */ 1326void * 1327ntb_get_mw_vbase(struct ntb_softc *ntb, unsigned int mw) 1328{ 1329 1330 if (mw >= NTB_NUM_MW) 1331 return (NULL); 1332 1333 return (ntb->bar_info[NTB_MW_TO_BAR(mw)].vbase); 1334} 1335 1336vm_paddr_t 1337ntb_get_mw_pbase(struct ntb_softc *ntb, unsigned int mw) 1338{ 1339 1340 if (mw >= NTB_NUM_MW) 1341 return (0); 1342 1343 return (ntb->bar_info[NTB_MW_TO_BAR(mw)].pbase); 1344} 1345 1346/** 1347 * ntb_get_mw_size() - return size of NTB memory window 1348 * @ntb: pointer to ntb_softc instance 1349 * @mw: memory window number 1350 * 1351 * This function provides the physical size of the memory window specified 1352 * 1353 * RETURNS: the size of the memory window or zero on error 1354 */ 1355u_long 1356ntb_get_mw_size(struct ntb_softc *ntb, unsigned int mw) 1357{ 1358 1359 if (mw >= NTB_NUM_MW) 1360 return (0); 1361 1362 return (ntb->bar_info[NTB_MW_TO_BAR(mw)].size); 1363} 1364 1365/** 1366 * ntb_set_mw_addr - set the memory window address 1367 * @ntb: pointer to ntb_softc instance 1368 * @mw: memory window number 1369 * @addr: base address for data 1370 * 1371 * This function sets the base physical address of the memory window. This 1372 * memory address is where data from the remote system will be transfered into 1373 * or out of depending on how the transport is configured. 1374 */ 1375void 1376ntb_set_mw_addr(struct ntb_softc *ntb, unsigned int mw, uint64_t addr) 1377{ 1378 1379 if (mw >= NTB_NUM_MW) 1380 return; 1381 1382 switch (NTB_MW_TO_BAR(mw)) { 1383 case NTB_B2B_BAR_1: 1384 ntb_reg_write(8, ntb->reg_ofs.sbar2_xlat, addr); 1385 break; 1386 case NTB_B2B_BAR_2: 1387 ntb_reg_write(8, ntb->reg_ofs.sbar4_xlat, addr); 1388 break; 1389 } 1390} 1391 1392/** 1393 * ntb_ring_sdb() - Set the doorbell on the secondary/external side 1394 * @ntb: pointer to ntb_softc instance 1395 * @db: doorbell to ring 1396 * 1397 * This function allows triggering of a doorbell on the secondary/external 1398 * side that will initiate an interrupt on the remote host 1399 * 1400 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1401 */ 1402void 1403ntb_ring_sdb(struct ntb_softc *ntb, unsigned int db) 1404{ 1405 1406 if (ntb->type == NTB_SOC) 1407 ntb_reg_write(8, ntb->reg_ofs.sdb, (uint64_t) 1 << db); 1408 else 1409 if (HAS_FEATURE(NTB_REGS_THRU_MW)) 1410 ntb_mw_write(2, XEON_SHADOW_PDOORBELL_OFFSET, 1411 ((1 << ntb->bits_per_vector) - 1) << 1412 (db * ntb->bits_per_vector)); 1413 else 1414 ntb_reg_write(2, ntb->reg_ofs.sdb, 1415 ((1 << ntb->bits_per_vector) - 1) << 1416 (db * ntb->bits_per_vector)); 1417} 1418 1419/** 1420 * ntb_query_link_status() - return the hardware link status 1421 * @ndev: pointer to ntb_device instance 1422 * 1423 * Returns true if the hardware is connected to the remote system 1424 * 1425 * RETURNS: true or false based on the hardware link state 1426 */ 1427bool 1428ntb_query_link_status(struct ntb_softc *ntb) 1429{ 1430 1431 return (ntb->link_status == NTB_LINK_UP); 1432} 1433 1434static void 1435save_bar_parameters(struct ntb_pci_bar_info *bar) 1436{ 1437 bar->pci_bus_tag = 1438 rman_get_bustag(bar->pci_resource); 1439 bar->pci_bus_handle = 1440 rman_get_bushandle(bar->pci_resource); 1441 bar->pbase = 1442 rman_get_start(bar->pci_resource); 1443 bar->size = 1444 rman_get_size(bar->pci_resource); 1445 bar->vbase = 1446 rman_get_virtual(bar->pci_resource); 1447 1448} 1449 1450device_t ntb_get_device(struct ntb_softc *ntb) 1451{ 1452 1453 return (ntb->device); 1454} 1455 1456/* Export HW-specific errata information. */ 1457bool 1458ntb_has_feature(struct ntb_softc *ntb, uint64_t feature) 1459{ 1460 1461 return (HAS_FEATURE(feature)); 1462} 1463