if_mxge.c revision 159612
1/****************************************************************************** 2 3Copyright (c) 2006, Myricom Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Myricom Inc, nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/mxge/if_mxge.c 159612 2006-06-14 16:23:17Z gallatin $"); 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/linker.h> 40#include <sys/firmware.h> 41#include <sys/endian.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kdb.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48#include <sys/memrange.h> 49#include <sys/socket.h> 50#include <sys/sysctl.h> 51#include <sys/sx.h> 52 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/ethernet.h> 56#include <net/if_dl.h> 57#include <net/if_media.h> 58 59#include <net/bpf.h> 60 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63#include <net/zlib.h> 64 65#include <netinet/in_systm.h> 66#include <netinet/in.h> 67#include <netinet/ip.h> 68 69#include <machine/bus.h> 70#include <machine/resource.h> 71#include <sys/bus.h> 72#include <sys/rman.h> 73 74#include <dev/pci/pcireg.h> 75#include <dev/pci/pcivar.h> 76 77#include <vm/vm.h> /* for pmap_mapdev() */ 78#include <vm/pmap.h> 79 80#include <dev/mxge/mxge_mcp.h> 81#include <dev/mxge/mcp_gen_header.h> 82#include <dev/mxge/if_mxge_var.h> 83 84/* tunable params */ 85static int mxge_nvidia_ecrc_enable = 1; 86static int mxge_max_intr_slots = 1024; 87static int mxge_intr_coal_delay = 30; 88static int mxge_deassert_wait = 1; 89static int mxge_flow_control = 1; 90static int mxge_verbose = 0; 91static char *mxge_fw_unaligned = "mxge_ethp_z8e"; 92static char *mxge_fw_aligned = "mxge_eth_z8e"; 93 94static int mxge_probe(device_t dev); 95static int mxge_attach(device_t dev); 96static int mxge_detach(device_t dev); 97static int mxge_shutdown(device_t dev); 98static void mxge_intr(void *arg); 99 100static device_method_t mxge_methods[] = 101{ 102 /* Device interface */ 103 DEVMETHOD(device_probe, mxge_probe), 104 DEVMETHOD(device_attach, mxge_attach), 105 DEVMETHOD(device_detach, mxge_detach), 106 DEVMETHOD(device_shutdown, mxge_shutdown), 107 {0, 0} 108}; 109 110static driver_t mxge_driver = 111{ 112 "mxge", 113 mxge_methods, 114 sizeof(mxge_softc_t), 115}; 116 117static devclass_t mxge_devclass; 118 119/* Declare ourselves to be a child of the PCI bus.*/ 120DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, 0, 0); 121MODULE_DEPEND(mxge, firmware, 1, 1, 1); 122 123static int 124mxge_probe(device_t dev) 125{ 126 if ((pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM) && 127 (pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E)) { 128 device_set_desc(dev, "Myri10G-PCIE-8A"); 129 return 0; 130 } 131 return ENXIO; 132} 133 134static void 135mxge_enable_wc(mxge_softc_t *sc) 136{ 137 struct mem_range_desc mrdesc; 138 vm_paddr_t pa; 139 vm_offset_t len; 140 int err, action; 141 142 pa = rman_get_start(sc->mem_res); 143 len = rman_get_size(sc->mem_res); 144 mrdesc.mr_base = pa; 145 mrdesc.mr_len = len; 146 mrdesc.mr_flags = MDF_WRITECOMBINE; 147 action = MEMRANGE_SET_UPDATE; 148 strcpy((char *)&mrdesc.mr_owner, "mxge"); 149 err = mem_range_attr_set(&mrdesc, &action); 150 if (err != 0) { 151 device_printf(sc->dev, 152 "w/c failed for pa 0x%lx, len 0x%lx, err = %d\n", 153 (unsigned long)pa, (unsigned long)len, err); 154 } else { 155 sc->wc = 1; 156 } 157} 158 159 160/* callback to get our DMA address */ 161static void 162mxge_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, 163 int error) 164{ 165 if (error == 0) { 166 *(bus_addr_t *) arg = segs->ds_addr; 167 } 168} 169 170static int 171mxge_dma_alloc(mxge_softc_t *sc, mxge_dma_t *dma, size_t bytes, 172 bus_size_t alignment) 173{ 174 int err; 175 device_t dev = sc->dev; 176 177 /* allocate DMAable memory tags */ 178 err = bus_dma_tag_create(sc->parent_dmat, /* parent */ 179 alignment, /* alignment */ 180 4096, /* boundary */ 181 BUS_SPACE_MAXADDR, /* low */ 182 BUS_SPACE_MAXADDR, /* high */ 183 NULL, NULL, /* filter */ 184 bytes, /* maxsize */ 185 1, /* num segs */ 186 4096, /* maxsegsize */ 187 BUS_DMA_COHERENT, /* flags */ 188 NULL, NULL, /* lock */ 189 &dma->dmat); /* tag */ 190 if (err != 0) { 191 device_printf(dev, "couldn't alloc tag (err = %d)\n", err); 192 return err; 193 } 194 195 /* allocate DMAable memory & map */ 196 err = bus_dmamem_alloc(dma->dmat, &dma->addr, 197 (BUS_DMA_WAITOK | BUS_DMA_COHERENT 198 | BUS_DMA_ZERO), &dma->map); 199 if (err != 0) { 200 device_printf(dev, "couldn't alloc mem (err = %d)\n", err); 201 goto abort_with_dmat; 202 } 203 204 /* load the memory */ 205 err = bus_dmamap_load(dma->dmat, dma->map, dma->addr, bytes, 206 mxge_dmamap_callback, 207 (void *)&dma->bus_addr, 0); 208 if (err != 0) { 209 device_printf(dev, "couldn't load map (err = %d)\n", err); 210 goto abort_with_mem; 211 } 212 return 0; 213 214abort_with_mem: 215 bus_dmamem_free(dma->dmat, dma->addr, dma->map); 216abort_with_dmat: 217 (void)bus_dma_tag_destroy(dma->dmat); 218 return err; 219} 220 221 222static void 223mxge_dma_free(mxge_dma_t *dma) 224{ 225 bus_dmamap_unload(dma->dmat, dma->map); 226 bus_dmamem_free(dma->dmat, dma->addr, dma->map); 227 (void)bus_dma_tag_destroy(dma->dmat); 228} 229 230/* 231 * The eeprom strings on the lanaiX have the format 232 * SN=x\0 233 * MAC=x:x:x:x:x:x\0 234 * PC=text\0 235 */ 236 237static int 238mxge_parse_strings(mxge_softc_t *sc) 239{ 240#define MXGE_NEXT_STRING(p) while(ptr < limit && *ptr++) 241 242 char *ptr, *limit; 243 int i, found_mac; 244 245 ptr = sc->eeprom_strings; 246 limit = sc->eeprom_strings + MXGE_EEPROM_STRINGS_SIZE; 247 found_mac = 0; 248 while (ptr < limit && *ptr != '\0') { 249 if (memcmp(ptr, "MAC=", 4) == 0) { 250 ptr += 1; 251 sc->mac_addr_string = ptr; 252 for (i = 0; i < 6; i++) { 253 ptr += 3; 254 if ((ptr + 2) > limit) 255 goto abort; 256 sc->mac_addr[i] = strtoul(ptr, NULL, 16); 257 found_mac = 1; 258 } 259 } else if (memcmp(ptr, "PC=", 3) == 0) { 260 ptr += 3; 261 strncpy(sc->product_code_string, ptr, 262 sizeof (sc->product_code_string) - 1); 263 } else if (memcmp(ptr, "SN=", 3) == 0) { 264 ptr += 3; 265 strncpy(sc->serial_number_string, ptr, 266 sizeof (sc->serial_number_string) - 1); 267 } 268 MXGE_NEXT_STRING(ptr); 269 } 270 271 if (found_mac) 272 return 0; 273 274 abort: 275 device_printf(sc->dev, "failed to parse eeprom_strings\n"); 276 277 return ENXIO; 278} 279 280#if #cpu(i386) || defined __i386 || defined i386 || defined __i386__ || #cpu(x86_64) || defined __x86_64__ 281static int 282mxge_enable_nvidia_ecrc(mxge_softc_t *sc, device_t pdev) 283{ 284 uint32_t val; 285 unsigned long off; 286 char *va, *cfgptr; 287 uint16_t vendor_id, device_id; 288 uintptr_t bus, slot, func, ivend, idev; 289 uint32_t *ptr32; 290 291 /* XXXX 292 Test below is commented because it is believed that doing 293 config read/write beyond 0xff will access the config space 294 for the next larger function. Uncomment this and remove 295 the hacky pmap_mapdev() way of accessing config space when 296 FreeBSD grows support for extended pcie config space access 297 */ 298#if 0 299 /* See if we can, by some miracle, access the extended 300 config space */ 301 val = pci_read_config(pdev, 0x178, 4); 302 if (val != 0xffffffff) { 303 val |= 0x40; 304 pci_write_config(pdev, 0x178, val, 4); 305 return 0; 306 } 307#endif 308 /* Rather than using normal pci config space writes, we must 309 * map the Nvidia config space ourselves. This is because on 310 * opteron/nvidia class machine the 0xe000000 mapping is 311 * handled by the nvidia chipset, that means the internal PCI 312 * device (the on-chip northbridge), or the amd-8131 bridge 313 * and things behind them are not visible by this method. 314 */ 315 316 BUS_READ_IVAR(device_get_parent(pdev), pdev, 317 PCI_IVAR_BUS, &bus); 318 BUS_READ_IVAR(device_get_parent(pdev), pdev, 319 PCI_IVAR_SLOT, &slot); 320 BUS_READ_IVAR(device_get_parent(pdev), pdev, 321 PCI_IVAR_FUNCTION, &func); 322 BUS_READ_IVAR(device_get_parent(pdev), pdev, 323 PCI_IVAR_VENDOR, &ivend); 324 BUS_READ_IVAR(device_get_parent(pdev), pdev, 325 PCI_IVAR_DEVICE, &idev); 326 327 off = 0xe0000000UL 328 + 0x00100000UL * (unsigned long)bus 329 + 0x00001000UL * (unsigned long)(func 330 + 8 * slot); 331 332 /* map it into the kernel */ 333 va = pmap_mapdev(trunc_page((vm_paddr_t)off), PAGE_SIZE); 334 335 336 if (va == NULL) { 337 device_printf(sc->dev, "pmap_kenter_temporary didn't\n"); 338 return EIO; 339 } 340 /* get a pointer to the config space mapped into the kernel */ 341 cfgptr = va + (off & PAGE_MASK); 342 343 /* make sure that we can really access it */ 344 vendor_id = *(uint16_t *)(cfgptr + PCIR_VENDOR); 345 device_id = *(uint16_t *)(cfgptr + PCIR_DEVICE); 346 if (! (vendor_id == ivend && device_id == idev)) { 347 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n", 348 vendor_id, device_id); 349 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE); 350 return EIO; 351 } 352 353 ptr32 = (uint32_t*)(cfgptr + 0x178); 354 val = *ptr32; 355 356 if (val == 0xffffffff) { 357 device_printf(sc->dev, "extended mapping failed\n"); 358 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE); 359 return EIO; 360 } 361 *ptr32 = val | 0x40; 362 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE); 363 if (mxge_verbose) 364 device_printf(sc->dev, 365 "Enabled ECRC on upstream Nvidia bridge " 366 "at %d:%d:%d\n", 367 (int)bus, (int)slot, (int)func); 368 return 0; 369} 370#else 371static int 372mxge_enable_nvidia_ecrc(mxge_softc_t *sc, device_t pdev) 373{ 374 device_printf(sc->dev, 375 "Nforce 4 chipset on non-x86/amd64!?!?!\n"); 376 return ENXIO; 377} 378#endif 379/* 380 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput 381 * when the PCI-E Completion packets are aligned on an 8-byte 382 * boundary. Some PCI-E chip sets always align Completion packets; on 383 * the ones that do not, the alignment can be enforced by enabling 384 * ECRC generation (if supported). 385 * 386 * When PCI-E Completion packets are not aligned, it is actually more 387 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB. 388 * 389 * If the driver can neither enable ECRC nor verify that it has 390 * already been enabled, then it must use a firmware image which works 391 * around unaligned completion packets (ethp_z8e.dat), and it should 392 * also ensure that it never gives the device a Read-DMA which is 393 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is 394 * enabled, then the driver should use the aligned (eth_z8e.dat) 395 * firmware image, and set tx.boundary to 4KB. 396 */ 397 398static void 399mxge_select_firmware(mxge_softc_t *sc) 400{ 401 int err, aligned = 0; 402 device_t pdev; 403 uint16_t pvend, pdid; 404 405 pdev = device_get_parent(device_get_parent(sc->dev)); 406 if (pdev == NULL) { 407 device_printf(sc->dev, "could not find parent?\n"); 408 goto abort; 409 } 410 pvend = pci_read_config(pdev, PCIR_VENDOR, 2); 411 pdid = pci_read_config(pdev, PCIR_DEVICE, 2); 412 413 /* see if we can enable ECRC's on an upstream 414 Nvidia bridge */ 415 if (mxge_nvidia_ecrc_enable && 416 (pvend == 0x10de && pdid == 0x005d)) { 417 err = mxge_enable_nvidia_ecrc(sc, pdev); 418 if (err == 0) { 419 aligned = 1; 420 if (mxge_verbose) 421 device_printf(sc->dev, 422 "Assuming aligned completions" 423 " (ECRC)\n"); 424 } 425 } 426 /* see if the upstream bridge is known to 427 provided aligned completions */ 428 if (/* HT2000 */ (pvend == 0x1166 && pdid == 0x0132) || 429 /* Ontario */ (pvend == 0x10b5 && pdid == 0x8532)) { 430 if (mxge_verbose) 431 device_printf(sc->dev, 432 "Assuming aligned completions " 433 "(0x%x:0x%x)\n", pvend, pdid); 434 } 435 436abort: 437 if (aligned) { 438 sc->fw_name = mxge_fw_aligned; 439 sc->tx.boundary = 4096; 440 } else { 441 sc->fw_name = mxge_fw_unaligned; 442 sc->tx.boundary = 2048; 443 } 444} 445 446union qualhack 447{ 448 const char *ro_char; 449 char *rw_char; 450}; 451 452 453static int 454mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit) 455{ 456 struct firmware *fw; 457 const mcp_gen_header_t *hdr; 458 unsigned hdr_offset; 459 const char *fw_data; 460 union qualhack hack; 461 int status; 462 463 464 fw = firmware_get(sc->fw_name); 465 466 if (fw == NULL) { 467 device_printf(sc->dev, "Could not find firmware image %s\n", 468 sc->fw_name); 469 return ENOENT; 470 } 471 if (fw->datasize > *limit || 472 fw->datasize < MCP_HEADER_PTR_OFFSET + 4) { 473 device_printf(sc->dev, "Firmware image %s too large (%d/%d)\n", 474 sc->fw_name, (int)fw->datasize, (int) *limit); 475 status = ENOSPC; 476 goto abort_with_fw; 477 } 478 *limit = fw->datasize; 479 480 /* check id */ 481 fw_data = (const char *)fw->data; 482 hdr_offset = htobe32(*(const uint32_t *) 483 (fw_data + MCP_HEADER_PTR_OFFSET)); 484 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->datasize) { 485 device_printf(sc->dev, "Bad firmware file"); 486 status = EIO; 487 goto abort_with_fw; 488 } 489 hdr = (const void*)(fw_data + hdr_offset); 490 if (be32toh(hdr->mcp_type) != MCP_TYPE_ETH) { 491 device_printf(sc->dev, "Bad firmware type: 0x%x\n", 492 be32toh(hdr->mcp_type)); 493 status = EIO; 494 goto abort_with_fw; 495 } 496 497 /* save firmware version for sysctl */ 498 strncpy(sc->fw_version, hdr->version, sizeof (sc->fw_version)); 499 if (mxge_verbose) 500 device_printf(sc->dev, "firmware id: %s\n", hdr->version); 501 502 hack.ro_char = fw_data; 503 /* Copy the inflated firmware to NIC SRAM. */ 504 mxge_pio_copy(&sc->sram[MXGE_FW_OFFSET], hack.rw_char, *limit); 505 506 status = 0; 507abort_with_fw: 508 firmware_put(fw, FIRMWARE_UNLOAD); 509 return status; 510} 511 512/* 513 * Enable or disable periodic RDMAs from the host to make certain 514 * chipsets resend dropped PCIe messages 515 */ 516 517static void 518mxge_dummy_rdma(mxge_softc_t *sc, int enable) 519{ 520 char buf_bytes[72]; 521 volatile uint32_t *confirm; 522 volatile char *submit; 523 uint32_t *buf, dma_low, dma_high; 524 int i; 525 526 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL); 527 528 /* clear confirmation addr */ 529 confirm = (volatile uint32_t *)sc->cmd; 530 *confirm = 0; 531 mb(); 532 533 /* send an rdma command to the PCIe engine, and wait for the 534 response in the confirmation address. The firmware should 535 write a -1 there to indicate it is alive and well 536 */ 537 538 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr); 539 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr); 540 buf[0] = htobe32(dma_high); /* confirm addr MSW */ 541 buf[1] = htobe32(dma_low); /* confirm addr LSW */ 542 buf[2] = htobe32(0xffffffff); /* confirm data */ 543 dma_low = MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr); 544 dma_high = MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr); 545 buf[3] = htobe32(dma_high); /* dummy addr MSW */ 546 buf[4] = htobe32(dma_low); /* dummy addr LSW */ 547 buf[5] = htobe32(enable); /* enable? */ 548 549 550 submit = (volatile char *)(sc->sram + 0xfc01c0); 551 552 mxge_pio_copy(submit, buf, 64); 553 mb(); 554 DELAY(1000); 555 mb(); 556 i = 0; 557 while (*confirm != 0xffffffff && i < 20) { 558 DELAY(1000); 559 i++; 560 } 561 if (*confirm != 0xffffffff) { 562 device_printf(sc->dev, "dummy rdma %s failed (%p = 0x%x)", 563 (enable ? "enable" : "disable"), confirm, 564 *confirm); 565 } 566 return; 567} 568 569static int 570mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data) 571{ 572 mcp_cmd_t *buf; 573 char buf_bytes[sizeof(*buf) + 8]; 574 volatile mcp_cmd_response_t *response = sc->cmd; 575 volatile char *cmd_addr = sc->sram + MXGEFW_CMD_OFFSET; 576 uint32_t dma_low, dma_high; 577 int sleep_total = 0; 578 579 /* ensure buf is aligned to 8 bytes */ 580 buf = (mcp_cmd_t *)((unsigned long)(buf_bytes + 7) & ~7UL); 581 582 buf->data0 = htobe32(data->data0); 583 buf->data1 = htobe32(data->data1); 584 buf->data2 = htobe32(data->data2); 585 buf->cmd = htobe32(cmd); 586 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr); 587 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr); 588 589 buf->response_addr.low = htobe32(dma_low); 590 buf->response_addr.high = htobe32(dma_high); 591 mtx_lock(&sc->cmd_lock); 592 response->result = 0xffffffff; 593 mb(); 594 mxge_pio_copy((volatile void *)cmd_addr, buf, sizeof (*buf)); 595 596 /* wait up to 20ms */ 597 for (sleep_total = 0; sleep_total < 20; sleep_total++) { 598 bus_dmamap_sync(sc->cmd_dma.dmat, 599 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD); 600 mb(); 601 if (response->result != 0xffffffff) { 602 if (response->result == 0) { 603 data->data0 = be32toh(response->data); 604 mtx_unlock(&sc->cmd_lock); 605 return 0; 606 } else { 607 device_printf(sc->dev, 608 "mxge: command %d " 609 "failed, result = %d\n", 610 cmd, be32toh(response->result)); 611 mtx_unlock(&sc->cmd_lock); 612 return ENXIO; 613 } 614 } 615 DELAY(1000); 616 } 617 mtx_unlock(&sc->cmd_lock); 618 device_printf(sc->dev, "mxge: command %d timed out" 619 "result = %d\n", 620 cmd, be32toh(response->result)); 621 return EAGAIN; 622} 623 624 625static int 626mxge_load_firmware(mxge_softc_t *sc) 627{ 628 volatile uint32_t *confirm; 629 volatile char *submit; 630 char buf_bytes[72]; 631 uint32_t *buf, size, dma_low, dma_high; 632 int status, i; 633 634 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL); 635 636 size = sc->sram_size; 637 status = mxge_load_firmware_helper(sc, &size); 638 if (status) { 639 device_printf(sc->dev, "firmware loading failed\n"); 640 return status; 641 } 642 /* clear confirmation addr */ 643 confirm = (volatile uint32_t *)sc->cmd; 644 *confirm = 0; 645 mb(); 646 /* send a reload command to the bootstrap MCP, and wait for the 647 response in the confirmation address. The firmware should 648 write a -1 there to indicate it is alive and well 649 */ 650 651 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.bus_addr); 652 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.bus_addr); 653 654 buf[0] = htobe32(dma_high); /* confirm addr MSW */ 655 buf[1] = htobe32(dma_low); /* confirm addr LSW */ 656 buf[2] = htobe32(0xffffffff); /* confirm data */ 657 658 /* FIX: All newest firmware should un-protect the bottom of 659 the sram before handoff. However, the very first interfaces 660 do not. Therefore the handoff copy must skip the first 8 bytes 661 */ 662 /* where the code starts*/ 663 buf[3] = htobe32(MXGE_FW_OFFSET + 8); 664 buf[4] = htobe32(size - 8); /* length of code */ 665 buf[5] = htobe32(8); /* where to copy to */ 666 buf[6] = htobe32(0); /* where to jump to */ 667 668 submit = (volatile char *)(sc->sram + 0xfc0000); 669 mxge_pio_copy(submit, buf, 64); 670 mb(); 671 DELAY(1000); 672 mb(); 673 i = 0; 674 while (*confirm != 0xffffffff && i < 20) { 675 DELAY(1000*10); 676 i++; 677 bus_dmamap_sync(sc->cmd_dma.dmat, 678 sc->cmd_dma.map, BUS_DMASYNC_POSTREAD); 679 } 680 if (*confirm != 0xffffffff) { 681 device_printf(sc->dev,"handoff failed (%p = 0x%x)", 682 confirm, *confirm); 683 684 return ENXIO; 685 } 686 mxge_dummy_rdma(sc, 1); 687 return 0; 688} 689 690static int 691mxge_update_mac_address(mxge_softc_t *sc) 692{ 693 mxge_cmd_t cmd; 694 uint8_t *addr = sc->mac_addr; 695 int status; 696 697 698 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16) 699 | (addr[2] << 8) | addr[3]); 700 701 cmd.data1 = ((addr[4] << 8) | (addr[5])); 702 703 status = mxge_send_cmd(sc, MXGEFW_SET_MAC_ADDRESS, &cmd); 704 return status; 705} 706 707static int 708mxge_change_pause(mxge_softc_t *sc, int pause) 709{ 710 mxge_cmd_t cmd; 711 int status; 712 713 if (pause) 714 status = mxge_send_cmd(sc, MXGEFW_ENABLE_FLOW_CONTROL, 715 &cmd); 716 else 717 status = mxge_send_cmd(sc, MXGEFW_DISABLE_FLOW_CONTROL, 718 &cmd); 719 720 if (status) { 721 device_printf(sc->dev, "Failed to set flow control mode\n"); 722 return ENXIO; 723 } 724 sc->pause = pause; 725 return 0; 726} 727 728static void 729mxge_change_promisc(mxge_softc_t *sc, int promisc) 730{ 731 mxge_cmd_t cmd; 732 int status; 733 734 if (promisc) 735 status = mxge_send_cmd(sc, MXGEFW_ENABLE_PROMISC, 736 &cmd); 737 else 738 status = mxge_send_cmd(sc, MXGEFW_DISABLE_PROMISC, 739 &cmd); 740 741 if (status) { 742 device_printf(sc->dev, "Failed to set promisc mode\n"); 743 } 744} 745 746static int 747mxge_reset(mxge_softc_t *sc) 748{ 749 750 mxge_cmd_t cmd; 751 mxge_dma_t dmabench_dma; 752 size_t bytes; 753 int status; 754 755 /* try to send a reset command to the card to see if it 756 is alive */ 757 memset(&cmd, 0, sizeof (cmd)); 758 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd); 759 if (status != 0) { 760 device_printf(sc->dev, "failed reset\n"); 761 return ENXIO; 762 } 763 764 /* Now exchange information about interrupts */ 765 bytes = mxge_max_intr_slots * sizeof (*sc->rx_done.entry);\ 766 memset(sc->rx_done.entry, 0, bytes); 767 cmd.data0 = (uint32_t)bytes; 768 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd); 769 cmd.data0 = MXGE_LOWPART_TO_U32(sc->rx_done.dma.bus_addr); 770 cmd.data1 = MXGE_HIGHPART_TO_U32(sc->rx_done.dma.bus_addr); 771 status |= mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_DMA, &cmd); 772 773 status |= mxge_send_cmd(sc, 774 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd); 775 776 777 sc->intr_coal_delay_ptr = (volatile uint32_t *)(sc->sram + cmd.data0); 778 779 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd); 780 sc->irq_claim = (volatile uint32_t *)(sc->sram + cmd.data0); 781 782 783 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 784 &cmd); 785 sc->irq_deassert = (volatile uint32_t *)(sc->sram + cmd.data0); 786 if (status != 0) { 787 device_printf(sc->dev, "failed set interrupt parameters\n"); 788 return status; 789 } 790 791 792 *sc->intr_coal_delay_ptr = htobe32(sc->intr_coal_delay); 793 794 795 /* run a DMA benchmark */ 796 sc->read_dma = sc->write_dma = sc->read_write_dma = 0; 797 status = mxge_dma_alloc(sc, &dmabench_dma, 4096, 4096); 798 if (status) 799 goto dmabench_fail; 800 801 /* Read DMA */ 802 cmd.data0 = MXGE_LOWPART_TO_U32(dmabench_dma.bus_addr); 803 cmd.data1 = MXGE_HIGHPART_TO_U32(dmabench_dma.bus_addr); 804 cmd.data2 = sc->tx.boundary * 0x10000; 805 806 status = mxge_send_cmd(sc, MXGEFW_DMA_TEST, &cmd); 807 if (status != 0) 808 device_printf(sc->dev, "read dma benchmark failed\n"); 809 else 810 sc->read_dma = ((cmd.data0>>16) * sc->tx.boundary * 2) / 811 (cmd.data0 & 0xffff); 812 813 /* Write DMA */ 814 cmd.data0 = MXGE_LOWPART_TO_U32(dmabench_dma.bus_addr); 815 cmd.data1 = MXGE_HIGHPART_TO_U32(dmabench_dma.bus_addr); 816 cmd.data2 = sc->tx.boundary * 0x1; 817 status = mxge_send_cmd(sc, MXGEFW_DMA_TEST, &cmd); 818 if (status != 0) 819 device_printf(sc->dev, "write dma benchmark failed\n"); 820 else 821 sc->write_dma = ((cmd.data0>>16) * sc->tx.boundary * 2) / 822 (cmd.data0 & 0xffff); 823 /* Read/Write DMA */ 824 cmd.data0 = MXGE_LOWPART_TO_U32(dmabench_dma.bus_addr); 825 cmd.data1 = MXGE_HIGHPART_TO_U32(dmabench_dma.bus_addr); 826 cmd.data2 = sc->tx.boundary * 0x10001; 827 status = mxge_send_cmd(sc, MXGEFW_DMA_TEST, &cmd); 828 if (status != 0) 829 device_printf(sc->dev, "read/write dma benchmark failed\n"); 830 else 831 sc->read_write_dma = 832 ((cmd.data0>>16) * sc->tx.boundary * 2 * 2) / 833 (cmd.data0 & 0xffff); 834 835 mxge_dma_free(&dmabench_dma); 836 837dmabench_fail: 838 /* reset mcp/driver shared state back to 0 */ 839 bzero(sc->rx_done.entry, bytes); 840 sc->rx_done.idx = 0; 841 sc->rx_done.cnt = 0; 842 sc->tx.req = 0; 843 sc->tx.done = 0; 844 sc->tx.pkt_done = 0; 845 sc->rx_big.cnt = 0; 846 sc->rx_small.cnt = 0; 847 sc->rdma_tags_available = 15; 848 status = mxge_update_mac_address(sc); 849 mxge_change_promisc(sc, 0); 850 mxge_change_pause(sc, sc->pause); 851 return status; 852} 853 854static int 855mxge_change_intr_coal(SYSCTL_HANDLER_ARGS) 856{ 857 mxge_softc_t *sc; 858 unsigned int intr_coal_delay; 859 int err; 860 861 sc = arg1; 862 intr_coal_delay = sc->intr_coal_delay; 863 err = sysctl_handle_int(oidp, &intr_coal_delay, arg2, req); 864 if (err != 0) { 865 return err; 866 } 867 if (intr_coal_delay == sc->intr_coal_delay) 868 return 0; 869 870 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000) 871 return EINVAL; 872 873 sx_xlock(&sc->driver_lock); 874 *sc->intr_coal_delay_ptr = htobe32(intr_coal_delay); 875 sc->intr_coal_delay = intr_coal_delay; 876 877 sx_xunlock(&sc->driver_lock); 878 return err; 879} 880 881static int 882mxge_change_flow_control(SYSCTL_HANDLER_ARGS) 883{ 884 mxge_softc_t *sc; 885 unsigned int enabled; 886 int err; 887 888 sc = arg1; 889 enabled = sc->pause; 890 err = sysctl_handle_int(oidp, &enabled, arg2, req); 891 if (err != 0) { 892 return err; 893 } 894 if (enabled == sc->pause) 895 return 0; 896 897 sx_xlock(&sc->driver_lock); 898 err = mxge_change_pause(sc, enabled); 899 sx_xunlock(&sc->driver_lock); 900 return err; 901} 902 903static int 904mxge_handle_be32(SYSCTL_HANDLER_ARGS) 905{ 906 int err; 907 908 if (arg1 == NULL) 909 return EFAULT; 910 arg2 = be32toh(*(int *)arg1); 911 arg1 = NULL; 912 err = sysctl_handle_int(oidp, arg1, arg2, req); 913 914 return err; 915} 916 917static void 918mxge_add_sysctls(mxge_softc_t *sc) 919{ 920 struct sysctl_ctx_list *ctx; 921 struct sysctl_oid_list *children; 922 mcp_irq_data_t *fw; 923 924 ctx = device_get_sysctl_ctx(sc->dev); 925 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 926 fw = sc->fw_stats; 927 928 /* random information */ 929 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, 930 "firmware_version", 931 CTLFLAG_RD, &sc->fw_version, 932 0, "firmware version"); 933 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, 934 "serial_number", 935 CTLFLAG_RD, &sc->serial_number_string, 936 0, "serial number"); 937 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, 938 "product_code", 939 CTLFLAG_RD, &sc->product_code_string, 940 0, "product_code"); 941 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 942 "tx_boundary", 943 CTLFLAG_RD, &sc->tx.boundary, 944 0, "tx_boundary"); 945 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 946 "read_dma_MBs", 947 CTLFLAG_RD, &sc->read_dma, 948 0, "DMA Read speed in MB/s"); 949 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 950 "write_dma_MBs", 951 CTLFLAG_RD, &sc->write_dma, 952 0, "DMA Write speed in MB/s"); 953 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 954 "read_write_dma_MBs", 955 CTLFLAG_RD, &sc->read_write_dma, 956 0, "DMA concurrent Read/Write speed in MB/s"); 957 958 959 /* performance related tunables */ 960 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 961 "intr_coal_delay", 962 CTLTYPE_INT|CTLFLAG_RW, sc, 963 0, mxge_change_intr_coal, 964 "I", "interrupt coalescing delay in usecs"); 965 966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 967 "flow_control_enabled", 968 CTLTYPE_INT|CTLFLAG_RW, sc, 969 0, mxge_change_flow_control, 970 "I", "interrupt coalescing delay in usecs"); 971 972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 973 "deassert_wait", 974 CTLFLAG_RW, &mxge_deassert_wait, 975 0, "Wait for IRQ line to go low in ihandler"); 976 977 /* stats block from firmware is in network byte order. 978 Need to swap it */ 979 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 980 "link_up", 981 CTLTYPE_INT|CTLFLAG_RD, &fw->link_up, 982 0, mxge_handle_be32, 983 "I", "link up"); 984 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 985 "rdma_tags_available", 986 CTLTYPE_INT|CTLFLAG_RD, &fw->rdma_tags_available, 987 0, mxge_handle_be32, 988 "I", "rdma_tags_available"); 989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 990 "dropped_link_overflow", 991 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_link_overflow, 992 0, mxge_handle_be32, 993 "I", "dropped_link_overflow"); 994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 995 "dropped_link_error_or_filtered", 996 CTLTYPE_INT|CTLFLAG_RD, 997 &fw->dropped_link_error_or_filtered, 998 0, mxge_handle_be32, 999 "I", "dropped_link_error_or_filtered"); 1000 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 1001 "dropped_runt", 1002 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_runt, 1003 0, mxge_handle_be32, 1004 "I", "dropped_runt"); 1005 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 1006 "dropped_overrun", 1007 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_overrun, 1008 0, mxge_handle_be32, 1009 "I", "dropped_overrun"); 1010 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 1011 "dropped_no_small_buffer", 1012 CTLTYPE_INT|CTLFLAG_RD, 1013 &fw->dropped_no_small_buffer, 1014 0, mxge_handle_be32, 1015 "I", "dropped_no_small_buffer"); 1016 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 1017 "dropped_no_big_buffer", 1018 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_no_big_buffer, 1019 0, mxge_handle_be32, 1020 "I", "dropped_no_big_buffer"); 1021 1022 /* host counters exported for debugging */ 1023 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1024 "rx_small_cnt", 1025 CTLFLAG_RD, &sc->rx_small.cnt, 1026 0, "rx_small_cnt"); 1027 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1028 "rx_big_cnt", 1029 CTLFLAG_RD, &sc->rx_big.cnt, 1030 0, "rx_small_cnt"); 1031 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1032 "tx_req", 1033 CTLFLAG_RD, &sc->tx.req, 1034 0, "tx_req"); 1035 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1036 "tx_done", 1037 CTLFLAG_RD, &sc->tx.done, 1038 0, "tx_done"); 1039 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1040 "tx_pkt_done", 1041 CTLFLAG_RD, &sc->tx.pkt_done, 1042 0, "tx_done"); 1043 1044 /* verbose printing? */ 1045 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 1046 "verbose", 1047 CTLFLAG_RW, &mxge_verbose, 1048 0, "verbose printing"); 1049 1050} 1051 1052/* copy an array of mcp_kreq_ether_send_t's to the mcp. Copy 1053 backwards one at a time and handle ring wraps */ 1054 1055static inline void 1056mxge_submit_req_backwards(mxge_tx_buf_t *tx, 1057 mcp_kreq_ether_send_t *src, int cnt) 1058{ 1059 int idx, starting_slot; 1060 starting_slot = tx->req; 1061 while (cnt > 1) { 1062 cnt--; 1063 idx = (starting_slot + cnt) & tx->mask; 1064 mxge_pio_copy(&tx->lanai[idx], 1065 &src[cnt], sizeof(*src)); 1066 mb(); 1067 } 1068} 1069 1070/* 1071 * copy an array of mcp_kreq_ether_send_t's to the mcp. Copy 1072 * at most 32 bytes at a time, so as to avoid involving the software 1073 * pio handler in the nic. We re-write the first segment's flags 1074 * to mark them valid only after writing the entire chain 1075 */ 1076 1077static inline void 1078mxge_submit_req(mxge_tx_buf_t *tx, mcp_kreq_ether_send_t *src, 1079 int cnt) 1080{ 1081 int idx, i; 1082 uint32_t *src_ints; 1083 volatile uint32_t *dst_ints; 1084 mcp_kreq_ether_send_t *srcp; 1085 volatile mcp_kreq_ether_send_t *dstp, *dst; 1086 uint8_t last_flags; 1087 1088 idx = tx->req & tx->mask; 1089 1090 last_flags = src->flags; 1091 src->flags = 0; 1092 mb(); 1093 dst = dstp = &tx->lanai[idx]; 1094 srcp = src; 1095 1096 if ((idx + cnt) < tx->mask) { 1097 for (i = 0; i < (cnt - 1); i += 2) { 1098 mxge_pio_copy(dstp, srcp, 2 * sizeof(*src)); 1099 mb(); /* force write every 32 bytes */ 1100 srcp += 2; 1101 dstp += 2; 1102 } 1103 } else { 1104 /* submit all but the first request, and ensure 1105 that it is submitted below */ 1106 mxge_submit_req_backwards(tx, src, cnt); 1107 i = 0; 1108 } 1109 if (i < cnt) { 1110 /* submit the first request */ 1111 mxge_pio_copy(dstp, srcp, sizeof(*src)); 1112 mb(); /* barrier before setting valid flag */ 1113 } 1114 1115 /* re-write the last 32-bits with the valid flags */ 1116 src->flags = last_flags; 1117 src_ints = (uint32_t *)src; 1118 src_ints+=3; 1119 dst_ints = (volatile uint32_t *)dst; 1120 dst_ints+=3; 1121 *dst_ints = *src_ints; 1122 tx->req += cnt; 1123 mb(); 1124} 1125 1126static inline void 1127mxge_submit_req_wc(mxge_tx_buf_t *tx, mcp_kreq_ether_send_t *src, int cnt) 1128{ 1129 tx->req += cnt; 1130 mb(); 1131 while (cnt >= 4) { 1132 mxge_pio_copy((volatile char *)tx->wc_fifo, src, 64); 1133 mb(); 1134 src += 4; 1135 cnt -= 4; 1136 } 1137 if (cnt > 0) { 1138 /* pad it to 64 bytes. The src is 64 bytes bigger than it 1139 needs to be so that we don't overrun it */ 1140 mxge_pio_copy(tx->wc_fifo + (cnt<<18), src, 64); 1141 mb(); 1142 } 1143} 1144 1145static void 1146mxge_encap(mxge_softc_t *sc, struct mbuf *m) 1147{ 1148 mcp_kreq_ether_send_t *req; 1149 bus_dma_segment_t seg_list[MXGE_MAX_SEND_DESC]; 1150 bus_dma_segment_t *seg; 1151 struct mbuf *m_tmp; 1152 struct ifnet *ifp; 1153 mxge_tx_buf_t *tx; 1154 struct ether_header *eh; 1155 struct ip *ip; 1156 int cnt, cum_len, err, i, idx; 1157 uint16_t flags, pseudo_hdr_offset; 1158 uint8_t cksum_offset; 1159 1160 1161 1162 ifp = sc->ifp; 1163 tx = &sc->tx; 1164 1165 /* (try to) map the frame for DMA */ 1166 idx = tx->req & tx->mask; 1167 err = bus_dmamap_load_mbuf_sg(tx->dmat, tx->info[idx].map, 1168 m, seg_list, &cnt, 1169 BUS_DMA_NOWAIT); 1170 if (err == EFBIG) { 1171 /* Too many segments in the chain. Try 1172 to defrag */ 1173 m_tmp = m_defrag(m, M_NOWAIT); 1174 if (m_tmp == NULL) { 1175 goto drop; 1176 } 1177 m = m_tmp; 1178 err = bus_dmamap_load_mbuf_sg(tx->dmat, 1179 tx->info[idx].map, 1180 m, seg_list, &cnt, 1181 BUS_DMA_NOWAIT); 1182 } 1183 if (err != 0) { 1184 device_printf(sc->dev, "bus_dmamap_load_mbuf_sg returned %d\n", 1185 err); 1186 goto drop; 1187 } 1188 bus_dmamap_sync(tx->dmat, tx->info[idx].map, 1189 BUS_DMASYNC_PREWRITE); 1190 tx->info[idx].m = m; 1191 1192 req = tx->req_list; 1193 cksum_offset = 0; 1194 pseudo_hdr_offset = 0; 1195 flags = MXGEFW_FLAGS_NO_TSO; 1196 1197 /* checksum offloading? */ 1198 if (m->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 1199 eh = mtod(m, struct ether_header *); 1200 ip = (struct ip *) (eh + 1); 1201 cksum_offset = sizeof(*eh) + (ip->ip_hl << 2); 1202 pseudo_hdr_offset = cksum_offset + m->m_pkthdr.csum_data; 1203 pseudo_hdr_offset = htobe16(pseudo_hdr_offset); 1204 req->cksum_offset = cksum_offset; 1205 flags |= MXGEFW_FLAGS_CKSUM; 1206 } 1207 if (m->m_pkthdr.len < MXGEFW_SEND_SMALL_SIZE) 1208 flags |= MXGEFW_FLAGS_SMALL; 1209 1210 /* convert segments into a request list */ 1211 cum_len = 0; 1212 seg = seg_list; 1213 req->flags = MXGEFW_FLAGS_FIRST; 1214 for (i = 0; i < cnt; i++) { 1215 req->addr_low = 1216 htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr)); 1217 req->addr_high = 1218 htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr)); 1219 req->length = htobe16(seg->ds_len); 1220 req->cksum_offset = cksum_offset; 1221 if (cksum_offset > seg->ds_len) 1222 cksum_offset -= seg->ds_len; 1223 else 1224 cksum_offset = 0; 1225 req->pseudo_hdr_offset = pseudo_hdr_offset; 1226 req->pad = 0; /* complete solid 16-byte block */ 1227 req->rdma_count = 1; 1228 req->flags |= flags | ((cum_len & 1) * MXGEFW_FLAGS_ALIGN_ODD); 1229 cum_len += seg->ds_len; 1230 seg++; 1231 req++; 1232 req->flags = 0; 1233 } 1234 req--; 1235 /* pad runts to 60 bytes */ 1236 if (cum_len < 60) { 1237 req++; 1238 req->addr_low = 1239 htobe32(MXGE_LOWPART_TO_U32(sc->zeropad_dma.bus_addr)); 1240 req->addr_high = 1241 htobe32(MXGE_HIGHPART_TO_U32(sc->zeropad_dma.bus_addr)); 1242 req->length = htobe16(60 - cum_len); 1243 req->cksum_offset = 0; 1244 req->pseudo_hdr_offset = pseudo_hdr_offset; 1245 req->pad = 0; /* complete solid 16-byte block */ 1246 req->rdma_count = 1; 1247 req->flags |= flags | ((cum_len & 1) * MXGEFW_FLAGS_ALIGN_ODD); 1248 cnt++; 1249 } 1250 1251 tx->req_list[0].rdma_count = cnt; 1252#if 0 1253 /* print what the firmware will see */ 1254 for (i = 0; i < cnt; i++) { 1255 printf("%d: addr: 0x%x 0x%x len:%d pso%d," 1256 "cso:%d, flags:0x%x, rdma:%d\n", 1257 i, (int)ntohl(tx->req_list[i].addr_high), 1258 (int)ntohl(tx->req_list[i].addr_low), 1259 (int)ntohs(tx->req_list[i].length), 1260 (int)ntohs(tx->req_list[i].pseudo_hdr_offset), 1261 tx->req_list[i].cksum_offset, tx->req_list[i].flags, 1262 tx->req_list[i].rdma_count); 1263 } 1264 printf("--------------\n"); 1265#endif 1266 tx->info[((cnt - 1) + tx->req) & tx->mask].flag = 1; 1267 if (tx->wc_fifo == NULL) 1268 mxge_submit_req(tx, tx->req_list, cnt); 1269 else 1270 mxge_submit_req_wc(tx, tx->req_list, cnt); 1271 return; 1272 1273drop: 1274 m_freem(m); 1275 ifp->if_oerrors++; 1276 return; 1277} 1278 1279 1280static void 1281mxge_start_locked(mxge_softc_t *sc) 1282{ 1283 int avail; 1284 struct mbuf *m; 1285 struct ifnet *ifp; 1286 1287 1288 ifp = sc->ifp; 1289 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1290 /* dequeue the packet */ 1291 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1292 1293 /* let BPF see it */ 1294 BPF_MTAP(ifp, m); 1295 1296 /* give it to the nic */ 1297 mxge_encap(sc, m); 1298 1299 /* leave an extra slot keep the ring from wrapping */ 1300 avail = sc->tx.mask - (sc->tx.req - sc->tx.done); 1301 if (avail < MXGE_MAX_SEND_DESC) { 1302 sc->ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1303 return; 1304 } 1305 } 1306} 1307 1308static void 1309mxge_start(struct ifnet *ifp) 1310{ 1311 mxge_softc_t *sc = ifp->if_softc; 1312 1313 1314 mtx_lock(&sc->tx_lock); 1315 mxge_start_locked(sc); 1316 mtx_unlock(&sc->tx_lock); 1317} 1318 1319/* 1320 * copy an array of mcp_kreq_ether_recv_t's to the mcp. Copy 1321 * at most 32 bytes at a time, so as to avoid involving the software 1322 * pio handler in the nic. We re-write the first segment's low 1323 * DMA address to mark it valid only after we write the entire chunk 1324 * in a burst 1325 */ 1326static inline void 1327mxge_submit_8rx(volatile mcp_kreq_ether_recv_t *dst, 1328 mcp_kreq_ether_recv_t *src) 1329{ 1330 uint32_t low; 1331 1332 low = src->addr_low; 1333 src->addr_low = 0xffffffff; 1334 mxge_pio_copy(dst, src, 8 * sizeof (*src)); 1335 mb(); 1336 dst->addr_low = low; 1337 mb(); 1338} 1339 1340static int 1341mxge_get_buf_small(mxge_softc_t *sc, bus_dmamap_t map, int idx) 1342{ 1343 bus_dma_segment_t seg; 1344 struct mbuf *m; 1345 mxge_rx_buf_t *rx = &sc->rx_small; 1346 int cnt, err; 1347 1348 m = m_gethdr(M_DONTWAIT, MT_DATA); 1349 if (m == NULL) { 1350 rx->alloc_fail++; 1351 err = ENOBUFS; 1352 goto done; 1353 } 1354 m->m_len = MHLEN; 1355 err = bus_dmamap_load_mbuf_sg(rx->dmat, map, m, 1356 &seg, &cnt, BUS_DMA_NOWAIT); 1357 if (err != 0) { 1358 m_free(m); 1359 goto done; 1360 } 1361 rx->info[idx].m = m; 1362 rx->shadow[idx].addr_low = 1363 htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr)); 1364 rx->shadow[idx].addr_high = 1365 htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr)); 1366 1367done: 1368 if ((idx & 7) == 7) { 1369 if (rx->wc_fifo == NULL) 1370 mxge_submit_8rx(&rx->lanai[idx - 7], 1371 &rx->shadow[idx - 7]); 1372 else { 1373 mb(); 1374 mxge_pio_copy(rx->wc_fifo, &rx->shadow[idx - 7], 64); 1375 } 1376 } 1377 return err; 1378} 1379 1380static int 1381mxge_get_buf_big(mxge_softc_t *sc, bus_dmamap_t map, int idx) 1382{ 1383 bus_dma_segment_t seg; 1384 struct mbuf *m; 1385 mxge_rx_buf_t *rx = &sc->rx_big; 1386 int cnt, err; 1387 1388 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->big_bytes); 1389 if (m == NULL) { 1390 rx->alloc_fail++; 1391 err = ENOBUFS; 1392 goto done; 1393 } 1394 m->m_len = sc->big_bytes; 1395 err = bus_dmamap_load_mbuf_sg(rx->dmat, map, m, 1396 &seg, &cnt, BUS_DMA_NOWAIT); 1397 if (err != 0) { 1398 m_free(m); 1399 goto done; 1400 } 1401 rx->info[idx].m = m; 1402 rx->shadow[idx].addr_low = 1403 htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr)); 1404 rx->shadow[idx].addr_high = 1405 htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr)); 1406 1407done: 1408 if ((idx & 7) == 7) { 1409 if (rx->wc_fifo == NULL) 1410 mxge_submit_8rx(&rx->lanai[idx - 7], 1411 &rx->shadow[idx - 7]); 1412 else { 1413 mb(); 1414 mxge_pio_copy(rx->wc_fifo, &rx->shadow[idx - 7], 64); 1415 } 1416 } 1417 return err; 1418} 1419 1420static inline void 1421mxge_rx_csum(struct mbuf *m, int csum) 1422{ 1423 struct ether_header *eh; 1424 struct ip *ip; 1425 1426 eh = mtod(m, struct ether_header *); 1427 if (__predict_true(eh->ether_type == htons(ETHERTYPE_IP))) { 1428 ip = (struct ip *)(eh + 1); 1429 if (__predict_true(ip->ip_p == IPPROTO_TCP || 1430 ip->ip_p == IPPROTO_UDP)) { 1431 m->m_pkthdr.csum_data = csum; 1432 m->m_pkthdr.csum_flags = CSUM_DATA_VALID; 1433 } 1434 } 1435} 1436 1437static inline void 1438mxge_rx_done_big(mxge_softc_t *sc, int len, int csum) 1439{ 1440 struct ifnet *ifp; 1441 struct mbuf *m = 0; /* -Wunitialized */ 1442 struct mbuf *m_prev = 0; /* -Wunitialized */ 1443 struct mbuf *m_head = 0; 1444 bus_dmamap_t old_map; 1445 mxge_rx_buf_t *rx; 1446 int idx; 1447 1448 1449 rx = &sc->rx_big; 1450 ifp = sc->ifp; 1451 while (len > 0) { 1452 idx = rx->cnt & rx->mask; 1453 rx->cnt++; 1454 /* save a pointer to the received mbuf */ 1455 m = rx->info[idx].m; 1456 /* try to replace the received mbuf */ 1457 if (mxge_get_buf_big(sc, rx->extra_map, idx)) { 1458 goto drop; 1459 } 1460 /* unmap the received buffer */ 1461 old_map = rx->info[idx].map; 1462 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD); 1463 bus_dmamap_unload(rx->dmat, old_map); 1464 1465 /* swap the bus_dmamap_t's */ 1466 rx->info[idx].map = rx->extra_map; 1467 rx->extra_map = old_map; 1468 1469 /* chain multiple segments together */ 1470 if (!m_head) { 1471 m_head = m; 1472 /* mcp implicitly skips 1st bytes so that 1473 * packet is properly aligned */ 1474 m->m_data += MXGEFW_PAD; 1475 m->m_pkthdr.len = len; 1476 m->m_len = sc->big_bytes - MXGEFW_PAD; 1477 } else { 1478 m->m_len = sc->big_bytes; 1479 m->m_flags &= ~M_PKTHDR; 1480 m_prev->m_next = m; 1481 } 1482 len -= m->m_len; 1483 m_prev = m; 1484 } 1485 1486 /* trim trailing garbage from the last mbuf in the chain. If 1487 * there is any garbage, len will be negative */ 1488 m->m_len += len; 1489 1490 /* if the checksum is valid, mark it in the mbuf header */ 1491 if (sc->csum_flag) 1492 mxge_rx_csum(m_head, csum); 1493 1494 /* pass the frame up the stack */ 1495 m_head->m_pkthdr.rcvif = ifp; 1496 ifp->if_ipackets++; 1497 (*ifp->if_input)(ifp, m_head); 1498 return; 1499 1500drop: 1501 /* drop the frame -- the old mbuf(s) are re-cycled by running 1502 every slot through the allocator */ 1503 if (m_head) { 1504 len -= sc->big_bytes; 1505 m_freem(m_head); 1506 } else { 1507 len -= (sc->big_bytes + MXGEFW_PAD); 1508 } 1509 while ((int)len > 0) { 1510 idx = rx->cnt & rx->mask; 1511 rx->cnt++; 1512 m = rx->info[idx].m; 1513 if (0 == (mxge_get_buf_big(sc, rx->extra_map, idx))) { 1514 m_freem(m); 1515 /* unmap the received buffer */ 1516 old_map = rx->info[idx].map; 1517 bus_dmamap_sync(rx->dmat, old_map, 1518 BUS_DMASYNC_POSTREAD); 1519 bus_dmamap_unload(rx->dmat, old_map); 1520 1521 /* swap the bus_dmamap_t's */ 1522 rx->info[idx].map = rx->extra_map; 1523 rx->extra_map = old_map; 1524 } 1525 len -= sc->big_bytes; 1526 } 1527 1528 ifp->if_ierrors++; 1529 1530} 1531 1532static inline void 1533mxge_rx_done_small(mxge_softc_t *sc, uint32_t len, uint32_t csum) 1534{ 1535 struct ifnet *ifp; 1536 struct mbuf *m; 1537 mxge_rx_buf_t *rx; 1538 bus_dmamap_t old_map; 1539 int idx; 1540 1541 ifp = sc->ifp; 1542 rx = &sc->rx_small; 1543 idx = rx->cnt & rx->mask; 1544 rx->cnt++; 1545 /* save a pointer to the received mbuf */ 1546 m = rx->info[idx].m; 1547 /* try to replace the received mbuf */ 1548 if (mxge_get_buf_small(sc, rx->extra_map, idx)) { 1549 /* drop the frame -- the old mbuf is re-cycled */ 1550 ifp->if_ierrors++; 1551 return; 1552 } 1553 1554 /* unmap the received buffer */ 1555 old_map = rx->info[idx].map; 1556 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD); 1557 bus_dmamap_unload(rx->dmat, old_map); 1558 1559 /* swap the bus_dmamap_t's */ 1560 rx->info[idx].map = rx->extra_map; 1561 rx->extra_map = old_map; 1562 1563 /* mcp implicitly skips 1st 2 bytes so that packet is properly 1564 * aligned */ 1565 m->m_data += MXGEFW_PAD; 1566 1567 /* if the checksum is valid, mark it in the mbuf header */ 1568 if (sc->csum_flag) 1569 mxge_rx_csum(m, csum); 1570 1571 /* pass the frame up the stack */ 1572 m->m_pkthdr.rcvif = ifp; 1573 m->m_len = m->m_pkthdr.len = len; 1574 ifp->if_ipackets++; 1575 (*ifp->if_input)(ifp, m); 1576} 1577 1578static inline void 1579mxge_clean_rx_done(mxge_softc_t *sc) 1580{ 1581 mxge_rx_done_t *rx_done = &sc->rx_done; 1582 int limit = 0; 1583 uint16_t length; 1584 uint16_t checksum; 1585 1586 1587 while (rx_done->entry[rx_done->idx].length != 0) { 1588 length = ntohs(rx_done->entry[rx_done->idx].length); 1589 rx_done->entry[rx_done->idx].length = 0; 1590 checksum = ntohs(rx_done->entry[rx_done->idx].checksum); 1591 if (length <= MHLEN) 1592 mxge_rx_done_small(sc, length, checksum); 1593 else 1594 mxge_rx_done_big(sc, length, checksum); 1595 rx_done->cnt++; 1596 rx_done->idx = rx_done->cnt & (mxge_max_intr_slots - 1); 1597 1598 /* limit potential for livelock */ 1599 if (__predict_false(++limit > 2 * mxge_max_intr_slots)) 1600 break; 1601 1602 } 1603} 1604 1605 1606static inline void 1607mxge_tx_done(mxge_softc_t *sc, uint32_t mcp_idx) 1608{ 1609 struct ifnet *ifp; 1610 mxge_tx_buf_t *tx; 1611 struct mbuf *m; 1612 bus_dmamap_t map; 1613 int idx, limit; 1614 1615 limit = 0; 1616 tx = &sc->tx; 1617 ifp = sc->ifp; 1618 while (tx->pkt_done != mcp_idx) { 1619 idx = tx->done & tx->mask; 1620 tx->done++; 1621 m = tx->info[idx].m; 1622 /* mbuf and DMA map only attached to the first 1623 segment per-mbuf */ 1624 if (m != NULL) { 1625 ifp->if_opackets++; 1626 tx->info[idx].m = NULL; 1627 map = tx->info[idx].map; 1628 bus_dmamap_unload(tx->dmat, map); 1629 m_freem(m); 1630 } 1631 if (tx->info[idx].flag) { 1632 tx->info[idx].flag = 0; 1633 tx->pkt_done++; 1634 } 1635 /* limit potential for livelock by only handling 1636 2 full tx rings per call */ 1637 if (__predict_false(++limit > 2 * tx->mask)) 1638 break; 1639 } 1640 1641 /* If we have space, clear IFF_OACTIVE to tell the stack that 1642 its OK to send packets */ 1643 1644 if (ifp->if_drv_flags & IFF_DRV_OACTIVE && 1645 tx->req - tx->done < (tx->mask + 1)/4) { 1646 mtx_lock(&sc->tx_lock); 1647 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1648 mxge_start_locked(sc); 1649 mtx_unlock(&sc->tx_lock); 1650 } 1651} 1652 1653static void 1654mxge_intr(void *arg) 1655{ 1656 mxge_softc_t *sc = arg; 1657 mcp_irq_data_t *stats = sc->fw_stats; 1658 mxge_tx_buf_t *tx = &sc->tx; 1659 mxge_rx_done_t *rx_done = &sc->rx_done; 1660 uint32_t send_done_count; 1661 uint8_t valid; 1662 1663 1664 /* make sure the DMA has finished */ 1665 if (!stats->valid) { 1666 return; 1667 } 1668 valid = stats->valid; 1669 1670 /* lower legacy IRQ */ 1671 *sc->irq_deassert = 0; 1672 mb(); 1673 if (!mxge_deassert_wait) 1674 /* don't wait for conf. that irq is low */ 1675 stats->valid = 0; 1676 do { 1677 /* check for transmit completes and receives */ 1678 send_done_count = be32toh(stats->send_done_count); 1679 while ((send_done_count != tx->pkt_done) || 1680 (rx_done->entry[rx_done->idx].length != 0)) { 1681 mxge_tx_done(sc, (int)send_done_count); 1682 mxge_clean_rx_done(sc); 1683 send_done_count = be32toh(stats->send_done_count); 1684 } 1685 } while (*((volatile uint8_t *) &stats->valid)); 1686 1687 if (__predict_false(stats->stats_updated)) { 1688 if (sc->link_state != stats->link_up) { 1689 sc->link_state = stats->link_up; 1690 if (sc->link_state) { 1691 if_link_state_change(sc->ifp, LINK_STATE_UP); 1692 if (mxge_verbose) 1693 device_printf(sc->dev, "link up\n"); 1694 } else { 1695 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 1696 if (mxge_verbose) 1697 device_printf(sc->dev, "link down\n"); 1698 } 1699 } 1700 if (sc->rdma_tags_available != 1701 be32toh(sc->fw_stats->rdma_tags_available)) { 1702 sc->rdma_tags_available = 1703 be32toh(sc->fw_stats->rdma_tags_available); 1704 device_printf(sc->dev, "RDMA timed out! %d tags " 1705 "left\n", sc->rdma_tags_available); 1706 } 1707 sc->down_cnt += stats->link_down; 1708 } 1709 1710 /* check to see if we have rx token to pass back */ 1711 if (valid & 0x1) 1712 *sc->irq_claim = be32toh(3); 1713 *(sc->irq_claim + 1) = be32toh(3); 1714} 1715 1716static void 1717mxge_watchdog(struct ifnet *ifp) 1718{ 1719 printf("%s called\n", __FUNCTION__); 1720} 1721 1722static void 1723mxge_init(void *arg) 1724{ 1725} 1726 1727 1728 1729static void 1730mxge_free_mbufs(mxge_softc_t *sc) 1731{ 1732 int i; 1733 1734 for (i = 0; i <= sc->rx_big.mask; i++) { 1735 if (sc->rx_big.info[i].m == NULL) 1736 continue; 1737 bus_dmamap_unload(sc->rx_big.dmat, 1738 sc->rx_big.info[i].map); 1739 m_freem(sc->rx_big.info[i].m); 1740 sc->rx_big.info[i].m = NULL; 1741 } 1742 1743 for (i = 0; i <= sc->rx_big.mask; i++) { 1744 if (sc->rx_big.info[i].m == NULL) 1745 continue; 1746 bus_dmamap_unload(sc->rx_big.dmat, 1747 sc->rx_big.info[i].map); 1748 m_freem(sc->rx_big.info[i].m); 1749 sc->rx_big.info[i].m = NULL; 1750 } 1751 1752 for (i = 0; i <= sc->tx.mask; i++) { 1753 if (sc->tx.info[i].m == NULL) 1754 continue; 1755 bus_dmamap_unload(sc->tx.dmat, 1756 sc->tx.info[i].map); 1757 m_freem(sc->tx.info[i].m); 1758 sc->tx.info[i].m = NULL; 1759 } 1760} 1761 1762static void 1763mxge_free_rings(mxge_softc_t *sc) 1764{ 1765 int i; 1766 1767 if (sc->tx.req_bytes != NULL) { 1768 free(sc->tx.req_bytes, M_DEVBUF); 1769 } 1770 if (sc->rx_small.shadow != NULL) 1771 free(sc->rx_small.shadow, M_DEVBUF); 1772 if (sc->rx_big.shadow != NULL) 1773 free(sc->rx_big.shadow, M_DEVBUF); 1774 if (sc->tx.info != NULL) { 1775 for (i = 0; i <= sc->tx.mask; i++) { 1776 if (sc->tx.info[i].map != NULL) 1777 bus_dmamap_destroy(sc->tx.dmat, 1778 sc->tx.info[i].map); 1779 } 1780 free(sc->tx.info, M_DEVBUF); 1781 } 1782 if (sc->rx_small.info != NULL) { 1783 for (i = 0; i <= sc->rx_small.mask; i++) { 1784 if (sc->rx_small.info[i].map != NULL) 1785 bus_dmamap_destroy(sc->rx_small.dmat, 1786 sc->rx_small.info[i].map); 1787 } 1788 free(sc->rx_small.info, M_DEVBUF); 1789 } 1790 if (sc->rx_big.info != NULL) { 1791 for (i = 0; i <= sc->rx_big.mask; i++) { 1792 if (sc->rx_big.info[i].map != NULL) 1793 bus_dmamap_destroy(sc->rx_big.dmat, 1794 sc->rx_big.info[i].map); 1795 } 1796 free(sc->rx_big.info, M_DEVBUF); 1797 } 1798 if (sc->rx_big.extra_map != NULL) 1799 bus_dmamap_destroy(sc->rx_big.dmat, 1800 sc->rx_big.extra_map); 1801 if (sc->rx_small.extra_map != NULL) 1802 bus_dmamap_destroy(sc->rx_small.dmat, 1803 sc->rx_small.extra_map); 1804 if (sc->tx.dmat != NULL) 1805 bus_dma_tag_destroy(sc->tx.dmat); 1806 if (sc->rx_small.dmat != NULL) 1807 bus_dma_tag_destroy(sc->rx_small.dmat); 1808 if (sc->rx_big.dmat != NULL) 1809 bus_dma_tag_destroy(sc->rx_big.dmat); 1810} 1811 1812static int 1813mxge_alloc_rings(mxge_softc_t *sc) 1814{ 1815 mxge_cmd_t cmd; 1816 int tx_ring_size, rx_ring_size; 1817 int tx_ring_entries, rx_ring_entries; 1818 int i, err; 1819 unsigned long bytes; 1820 1821 /* get ring sizes */ 1822 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd); 1823 tx_ring_size = cmd.data0; 1824 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd); 1825 if (err != 0) { 1826 device_printf(sc->dev, "Cannot determine ring sizes\n"); 1827 goto abort_with_nothing; 1828 } 1829 1830 rx_ring_size = cmd.data0; 1831 1832 tx_ring_entries = tx_ring_size / sizeof (mcp_kreq_ether_send_t); 1833 rx_ring_entries = rx_ring_size / sizeof (mcp_dma_addr_t); 1834 sc->ifp->if_snd.ifq_maxlen = tx_ring_entries - 1; 1835 sc->ifp->if_snd.ifq_drv_maxlen = sc->ifp->if_snd.ifq_maxlen; 1836 1837 sc->tx.mask = tx_ring_entries - 1; 1838 sc->rx_small.mask = sc->rx_big.mask = rx_ring_entries - 1; 1839 1840 err = ENOMEM; 1841 1842 /* allocate the tx request copy block */ 1843 bytes = 8 + 1844 sizeof (*sc->tx.req_list) * (MXGE_MAX_SEND_DESC + 4); 1845 sc->tx.req_bytes = malloc(bytes, M_DEVBUF, M_WAITOK); 1846 if (sc->tx.req_bytes == NULL) 1847 goto abort_with_nothing; 1848 /* ensure req_list entries are aligned to 8 bytes */ 1849 sc->tx.req_list = (mcp_kreq_ether_send_t *) 1850 ((unsigned long)(sc->tx.req_bytes + 7) & ~7UL); 1851 1852 /* allocate the rx shadow rings */ 1853 bytes = rx_ring_entries * sizeof (*sc->rx_small.shadow); 1854 sc->rx_small.shadow = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK); 1855 if (sc->rx_small.shadow == NULL) 1856 goto abort_with_alloc; 1857 1858 bytes = rx_ring_entries * sizeof (*sc->rx_big.shadow); 1859 sc->rx_big.shadow = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK); 1860 if (sc->rx_big.shadow == NULL) 1861 goto abort_with_alloc; 1862 1863 /* allocate the host info rings */ 1864 bytes = tx_ring_entries * sizeof (*sc->tx.info); 1865 sc->tx.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK); 1866 if (sc->tx.info == NULL) 1867 goto abort_with_alloc; 1868 1869 bytes = rx_ring_entries * sizeof (*sc->rx_small.info); 1870 sc->rx_small.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK); 1871 if (sc->rx_small.info == NULL) 1872 goto abort_with_alloc; 1873 1874 bytes = rx_ring_entries * sizeof (*sc->rx_big.info); 1875 sc->rx_big.info = malloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK); 1876 if (sc->rx_big.info == NULL) 1877 goto abort_with_alloc; 1878 1879 /* allocate the busdma resources */ 1880 err = bus_dma_tag_create(sc->parent_dmat, /* parent */ 1881 1, /* alignment */ 1882 sc->tx.boundary, /* boundary */ 1883 BUS_SPACE_MAXADDR, /* low */ 1884 BUS_SPACE_MAXADDR, /* high */ 1885 NULL, NULL, /* filter */ 1886 MXGE_MAX_ETHER_MTU, /* maxsize */ 1887 MXGE_MAX_SEND_DESC, /* num segs */ 1888 sc->tx.boundary, /* maxsegsize */ 1889 BUS_DMA_ALLOCNOW, /* flags */ 1890 NULL, NULL, /* lock */ 1891 &sc->tx.dmat); /* tag */ 1892 1893 if (err != 0) { 1894 device_printf(sc->dev, "Err %d allocating tx dmat\n", 1895 err); 1896 goto abort_with_alloc; 1897 } 1898 1899 err = bus_dma_tag_create(sc->parent_dmat, /* parent */ 1900 1, /* alignment */ 1901 4096, /* boundary */ 1902 BUS_SPACE_MAXADDR, /* low */ 1903 BUS_SPACE_MAXADDR, /* high */ 1904 NULL, NULL, /* filter */ 1905 MHLEN, /* maxsize */ 1906 1, /* num segs */ 1907 MHLEN, /* maxsegsize */ 1908 BUS_DMA_ALLOCNOW, /* flags */ 1909 NULL, NULL, /* lock */ 1910 &sc->rx_small.dmat); /* tag */ 1911 if (err != 0) { 1912 device_printf(sc->dev, "Err %d allocating rx_small dmat\n", 1913 err); 1914 goto abort_with_alloc; 1915 } 1916 1917 err = bus_dma_tag_create(sc->parent_dmat, /* parent */ 1918 1, /* alignment */ 1919 4096, /* boundary */ 1920 BUS_SPACE_MAXADDR, /* low */ 1921 BUS_SPACE_MAXADDR, /* high */ 1922 NULL, NULL, /* filter */ 1923 4096, /* maxsize */ 1924 1, /* num segs */ 1925 4096, /* maxsegsize */ 1926 BUS_DMA_ALLOCNOW, /* flags */ 1927 NULL, NULL, /* lock */ 1928 &sc->rx_big.dmat); /* tag */ 1929 if (err != 0) { 1930 device_printf(sc->dev, "Err %d allocating rx_big dmat\n", 1931 err); 1932 goto abort_with_alloc; 1933 } 1934 1935 /* now use these tags to setup dmamaps for each slot 1936 in each ring */ 1937 for (i = 0; i <= sc->tx.mask; i++) { 1938 err = bus_dmamap_create(sc->tx.dmat, 0, 1939 &sc->tx.info[i].map); 1940 if (err != 0) { 1941 device_printf(sc->dev, "Err %d tx dmamap\n", 1942 err); 1943 goto abort_with_alloc; 1944 } 1945 } 1946 for (i = 0; i <= sc->rx_small.mask; i++) { 1947 err = bus_dmamap_create(sc->rx_small.dmat, 0, 1948 &sc->rx_small.info[i].map); 1949 if (err != 0) { 1950 device_printf(sc->dev, "Err %d rx_small dmamap\n", 1951 err); 1952 goto abort_with_alloc; 1953 } 1954 } 1955 err = bus_dmamap_create(sc->rx_small.dmat, 0, 1956 &sc->rx_small.extra_map); 1957 if (err != 0) { 1958 device_printf(sc->dev, "Err %d extra rx_small dmamap\n", 1959 err); 1960 goto abort_with_alloc; 1961 } 1962 1963 for (i = 0; i <= sc->rx_big.mask; i++) { 1964 err = bus_dmamap_create(sc->rx_big.dmat, 0, 1965 &sc->rx_big.info[i].map); 1966 if (err != 0) { 1967 device_printf(sc->dev, "Err %d rx_big dmamap\n", 1968 err); 1969 goto abort_with_alloc; 1970 } 1971 } 1972 err = bus_dmamap_create(sc->rx_big.dmat, 0, 1973 &sc->rx_big.extra_map); 1974 if (err != 0) { 1975 device_printf(sc->dev, "Err %d extra rx_big dmamap\n", 1976 err); 1977 goto abort_with_alloc; 1978 } 1979 return 0; 1980 1981abort_with_alloc: 1982 mxge_free_rings(sc); 1983 1984abort_with_nothing: 1985 return err; 1986} 1987 1988static int 1989mxge_open(mxge_softc_t *sc) 1990{ 1991 mxge_cmd_t cmd; 1992 int i, err; 1993 bus_dmamap_t map; 1994 1995 1996 err = mxge_reset(sc); 1997 if (err != 0) { 1998 device_printf(sc->dev, "failed to reset\n"); 1999 return EIO; 2000 } 2001 2002 if (MCLBYTES >= 2003 sc->ifp->if_mtu + ETHER_HDR_LEN + MXGEFW_PAD) 2004 sc->big_bytes = MCLBYTES; 2005 else 2006 sc->big_bytes = MJUMPAGESIZE; 2007 2008 err = mxge_alloc_rings(sc); 2009 if (err != 0) { 2010 device_printf(sc->dev, "failed to allocate rings\n"); 2011 return err; 2012 } 2013 2014 err = bus_setup_intr(sc->dev, sc->irq_res, 2015 INTR_TYPE_NET | INTR_MPSAFE, 2016 mxge_intr, sc, &sc->ih); 2017 if (err != 0) { 2018 goto abort_with_rings; 2019 } 2020 2021 /* get the lanai pointers to the send and receive rings */ 2022 2023 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_OFFSET, &cmd); 2024 sc->tx.lanai = 2025 (volatile mcp_kreq_ether_send_t *)(sc->sram + cmd.data0); 2026 err |= mxge_send_cmd(sc, 2027 MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd); 2028 sc->rx_small.lanai = 2029 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0); 2030 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd); 2031 sc->rx_big.lanai = 2032 (volatile mcp_kreq_ether_recv_t *)(sc->sram + cmd.data0); 2033 2034 if (err != 0) { 2035 device_printf(sc->dev, 2036 "failed to get ring sizes or locations\n"); 2037 err = EIO; 2038 goto abort_with_irq; 2039 } 2040 2041 if (sc->wc) { 2042 sc->tx.wc_fifo = sc->sram + 0x200000; 2043 sc->rx_small.wc_fifo = sc->sram + 0x300000; 2044 sc->rx_big.wc_fifo = sc->sram + 0x340000; 2045 } else { 2046 sc->tx.wc_fifo = 0; 2047 sc->rx_small.wc_fifo = 0; 2048 sc->rx_big.wc_fifo = 0; 2049 } 2050 2051 2052 /* stock receive rings */ 2053 for (i = 0; i <= sc->rx_small.mask; i++) { 2054 map = sc->rx_small.info[i].map; 2055 err = mxge_get_buf_small(sc, map, i); 2056 if (err) { 2057 device_printf(sc->dev, "alloced %d/%d smalls\n", 2058 i, sc->rx_small.mask + 1); 2059 goto abort; 2060 } 2061 } 2062 for (i = 0; i <= sc->rx_big.mask; i++) { 2063 map = sc->rx_big.info[i].map; 2064 err = mxge_get_buf_big(sc, map, i); 2065 if (err) { 2066 device_printf(sc->dev, "alloced %d/%d bigs\n", 2067 i, sc->rx_big.mask + 1); 2068 goto abort; 2069 } 2070 } 2071 2072 /* Give the firmware the mtu and the big and small buffer 2073 sizes. The firmware wants the big buf size to be a power 2074 of two. Luckily, FreeBSD's clusters are powers of two */ 2075 cmd.data0 = sc->ifp->if_mtu + ETHER_HDR_LEN; 2076 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_MTU, &cmd); 2077 cmd.data0 = MHLEN; 2078 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, 2079 &cmd); 2080 cmd.data0 = sc->big_bytes; 2081 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd); 2082 /* Now give him the pointer to the stats block */ 2083 cmd.data0 = MXGE_LOWPART_TO_U32(sc->fw_stats_dma.bus_addr); 2084 cmd.data1 = MXGE_HIGHPART_TO_U32(sc->fw_stats_dma.bus_addr); 2085 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_STATS_DMA, &cmd); 2086 2087 if (err != 0) { 2088 device_printf(sc->dev, "failed to setup params\n"); 2089 goto abort; 2090 } 2091 2092 /* Finally, start the firmware running */ 2093 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_UP, &cmd); 2094 if (err) { 2095 device_printf(sc->dev, "Couldn't bring up link\n"); 2096 goto abort; 2097 } 2098 sc->ifp->if_drv_flags |= IFF_DRV_RUNNING; 2099 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2100 2101 return 0; 2102 2103 2104abort: 2105 mxge_free_mbufs(sc); 2106abort_with_irq: 2107 bus_teardown_intr(sc->dev, sc->irq_res, sc->ih); 2108abort_with_rings: 2109 mxge_free_rings(sc); 2110 return err; 2111} 2112 2113static int 2114mxge_close(mxge_softc_t *sc) 2115{ 2116 mxge_cmd_t cmd; 2117 int err, old_down_cnt; 2118 2119 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2120 old_down_cnt = sc->down_cnt; 2121 mb(); 2122 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_DOWN, &cmd); 2123 if (err) { 2124 device_printf(sc->dev, "Couldn't bring down link\n"); 2125 } 2126 if (old_down_cnt == sc->down_cnt) { 2127 /* wait for down irq */ 2128 (void)tsleep(&sc->down_cnt, PWAIT, "down mxge", hz); 2129 } 2130 if (old_down_cnt == sc->down_cnt) { 2131 device_printf(sc->dev, "never got down irq\n"); 2132 } 2133 if (sc->ih != NULL) 2134 bus_teardown_intr(sc->dev, sc->irq_res, sc->ih); 2135 mxge_free_mbufs(sc); 2136 mxge_free_rings(sc); 2137 return 0; 2138} 2139 2140 2141static int 2142mxge_media_change(struct ifnet *ifp) 2143{ 2144 return EINVAL; 2145} 2146 2147static int 2148mxge_change_mtu(mxge_softc_t *sc, int mtu) 2149{ 2150 struct ifnet *ifp = sc->ifp; 2151 int real_mtu, old_mtu; 2152 int err = 0; 2153 2154 2155 real_mtu = mtu + ETHER_HDR_LEN; 2156 if ((real_mtu > MXGE_MAX_ETHER_MTU) || 2157 real_mtu < 60) 2158 return EINVAL; 2159 sx_xlock(&sc->driver_lock); 2160 old_mtu = ifp->if_mtu; 2161 ifp->if_mtu = mtu; 2162 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2163 mxge_close(sc); 2164 err = mxge_open(sc); 2165 if (err != 0) { 2166 ifp->if_mtu = old_mtu; 2167 mxge_close(sc); 2168 (void) mxge_open(sc); 2169 } 2170 } 2171 sx_xunlock(&sc->driver_lock); 2172 return err; 2173} 2174 2175static void 2176mxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2177{ 2178 mxge_softc_t *sc = ifp->if_softc; 2179 2180 2181 if (sc == NULL) 2182 return; 2183 ifmr->ifm_status = IFM_AVALID; 2184 ifmr->ifm_status |= sc->fw_stats->link_up ? IFM_ACTIVE : 0; 2185 ifmr->ifm_active = IFM_AUTO | IFM_ETHER; 2186 ifmr->ifm_active |= sc->fw_stats->link_up ? IFM_FDX : 0; 2187} 2188 2189static int 2190mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2191{ 2192 mxge_softc_t *sc = ifp->if_softc; 2193 struct ifreq *ifr = (struct ifreq *)data; 2194 int err, mask; 2195 2196 err = 0; 2197 switch (command) { 2198 case SIOCSIFADDR: 2199 case SIOCGIFADDR: 2200 err = ether_ioctl(ifp, command, data); 2201 break; 2202 2203 case SIOCSIFMTU: 2204 err = mxge_change_mtu(sc, ifr->ifr_mtu); 2205 break; 2206 2207 case SIOCSIFFLAGS: 2208 sx_xlock(&sc->driver_lock); 2209 if (ifp->if_flags & IFF_UP) { 2210 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2211 err = mxge_open(sc); 2212 } else { 2213 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2214 mxge_close(sc); 2215 } 2216 sx_xunlock(&sc->driver_lock); 2217 break; 2218 2219 case SIOCADDMULTI: 2220 case SIOCDELMULTI: 2221 err = 0; 2222 break; 2223 2224 case SIOCSIFCAP: 2225 sx_xlock(&sc->driver_lock); 2226 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2227 if (mask & IFCAP_TXCSUM) { 2228 if (IFCAP_TXCSUM & ifp->if_capenable) { 2229 ifp->if_capenable &= ~IFCAP_TXCSUM; 2230 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP); 2231 } else { 2232 ifp->if_capenable |= IFCAP_TXCSUM; 2233 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 2234 } 2235 } else if (mask & IFCAP_RXCSUM) { 2236 if (IFCAP_RXCSUM & ifp->if_capenable) { 2237 ifp->if_capenable &= ~IFCAP_RXCSUM; 2238 sc->csum_flag = 0; 2239 } else { 2240 ifp->if_capenable |= IFCAP_RXCSUM; 2241 sc->csum_flag = 1; 2242 } 2243 } 2244 sx_xunlock(&sc->driver_lock); 2245 break; 2246 2247 case SIOCGIFMEDIA: 2248 err = ifmedia_ioctl(ifp, (struct ifreq *)data, 2249 &sc->media, command); 2250 break; 2251 2252 default: 2253 err = ENOTTY; 2254 } 2255 return err; 2256} 2257 2258static void 2259mxge_fetch_tunables(mxge_softc_t *sc) 2260{ 2261 2262 TUNABLE_INT_FETCH("hw.mxge.flow_control_enabled", 2263 &mxge_flow_control); 2264 TUNABLE_INT_FETCH("hw.mxge.intr_coal_delay", 2265 &mxge_intr_coal_delay); 2266 TUNABLE_INT_FETCH("hw.mxge.nvidia_ecrc_enable", 2267 &mxge_nvidia_ecrc_enable); 2268 TUNABLE_INT_FETCH("hw.mxge.deassert_wait", 2269 &mxge_deassert_wait); 2270 TUNABLE_INT_FETCH("hw.mxge.verbose", 2271 &mxge_verbose); 2272 2273 if (bootverbose) 2274 mxge_verbose = 1; 2275 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000) 2276 mxge_intr_coal_delay = 30; 2277 sc->pause = mxge_flow_control; 2278} 2279 2280static int 2281mxge_attach(device_t dev) 2282{ 2283 mxge_softc_t *sc = device_get_softc(dev); 2284 struct ifnet *ifp; 2285 size_t bytes; 2286 int rid, err; 2287 uint16_t cmd; 2288 2289 sc->dev = dev; 2290 mxge_fetch_tunables(sc); 2291 2292 err = bus_dma_tag_create(NULL, /* parent */ 2293 1, /* alignment */ 2294 4096, /* boundary */ 2295 BUS_SPACE_MAXADDR, /* low */ 2296 BUS_SPACE_MAXADDR, /* high */ 2297 NULL, NULL, /* filter */ 2298 MXGE_MAX_ETHER_MTU, /* maxsize */ 2299 MXGE_MAX_SEND_DESC, /* num segs */ 2300 4096, /* maxsegsize */ 2301 0, /* flags */ 2302 NULL, NULL, /* lock */ 2303 &sc->parent_dmat); /* tag */ 2304 2305 if (err != 0) { 2306 device_printf(sc->dev, "Err %d allocating parent dmat\n", 2307 err); 2308 goto abort_with_nothing; 2309 } 2310 2311 ifp = sc->ifp = if_alloc(IFT_ETHER); 2312 if (ifp == NULL) { 2313 device_printf(dev, "can not if_alloc()\n"); 2314 err = ENOSPC; 2315 goto abort_with_parent_dmat; 2316 } 2317 mtx_init(&sc->cmd_lock, NULL, 2318 MTX_NETWORK_LOCK, MTX_DEF); 2319 mtx_init(&sc->tx_lock, device_get_nameunit(dev), 2320 MTX_NETWORK_LOCK, MTX_DEF); 2321 sx_init(&sc->driver_lock, device_get_nameunit(dev)); 2322 2323 /* Enable DMA and Memory space access */ 2324 pci_enable_busmaster(dev); 2325 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2326 cmd |= PCIM_CMD_MEMEN; 2327 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2328 2329 /* Map the board into the kernel */ 2330 rid = PCIR_BARS; 2331 sc->mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, 2332 ~0, 1, RF_ACTIVE); 2333 if (sc->mem_res == NULL) { 2334 device_printf(dev, "could not map memory\n"); 2335 err = ENXIO; 2336 goto abort_with_lock; 2337 } 2338 sc->sram = rman_get_virtual(sc->mem_res); 2339 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100; 2340 if (sc->sram_size > rman_get_size(sc->mem_res)) { 2341 device_printf(dev, "impossible memory region size %ld\n", 2342 rman_get_size(sc->mem_res)); 2343 err = ENXIO; 2344 goto abort_with_mem_res; 2345 } 2346 2347 /* make NULL terminated copy of the EEPROM strings section of 2348 lanai SRAM */ 2349 bzero(sc->eeprom_strings, MXGE_EEPROM_STRINGS_SIZE); 2350 bus_space_read_region_1(rman_get_bustag(sc->mem_res), 2351 rman_get_bushandle(sc->mem_res), 2352 sc->sram_size - MXGE_EEPROM_STRINGS_SIZE, 2353 sc->eeprom_strings, 2354 MXGE_EEPROM_STRINGS_SIZE - 2); 2355 err = mxge_parse_strings(sc); 2356 if (err != 0) 2357 goto abort_with_mem_res; 2358 2359 /* Enable write combining for efficient use of PCIe bus */ 2360 mxge_enable_wc(sc); 2361 2362 /* Allocate the out of band dma memory */ 2363 err = mxge_dma_alloc(sc, &sc->cmd_dma, 2364 sizeof (mxge_cmd_t), 64); 2365 if (err != 0) 2366 goto abort_with_mem_res; 2367 sc->cmd = (mcp_cmd_response_t *) sc->cmd_dma.addr; 2368 err = mxge_dma_alloc(sc, &sc->zeropad_dma, 64, 64); 2369 if (err != 0) 2370 goto abort_with_cmd_dma; 2371 2372 err = mxge_dma_alloc(sc, &sc->fw_stats_dma, 2373 sizeof (*sc->fw_stats), 64); 2374 if (err != 0) 2375 goto abort_with_zeropad_dma; 2376 sc->fw_stats = (mcp_irq_data_t *)sc->fw_stats_dma.addr; 2377 2378 2379 /* allocate interrupt queues */ 2380 bytes = mxge_max_intr_slots * sizeof (*sc->rx_done.entry); 2381 err = mxge_dma_alloc(sc, &sc->rx_done.dma, bytes, 4096); 2382 if (err != 0) 2383 goto abort_with_fw_stats; 2384 sc->rx_done.entry = sc->rx_done.dma.addr; 2385 bzero(sc->rx_done.entry, bytes); 2386 /* Add our ithread */ 2387 rid = 0; 2388 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 2389 1, RF_SHAREABLE | RF_ACTIVE); 2390 if (sc->irq_res == NULL) { 2391 device_printf(dev, "could not alloc interrupt\n"); 2392 goto abort_with_rx_done; 2393 } 2394 2395 /* load the firmware */ 2396 mxge_select_firmware(sc); 2397 2398 err = mxge_load_firmware(sc); 2399 if (err != 0) 2400 goto abort_with_irq_res; 2401 sc->intr_coal_delay = mxge_intr_coal_delay; 2402 err = mxge_reset(sc); 2403 if (err != 0) 2404 goto abort_with_irq_res; 2405 2406 /* hook into the network stack */ 2407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2408 ifp->if_baudrate = 100000000; 2409 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM; 2410 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 2411 ifp->if_capenable = ifp->if_capabilities; 2412 sc->csum_flag = 1; 2413 ifp->if_init = mxge_init; 2414 ifp->if_softc = sc; 2415 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2416 ifp->if_ioctl = mxge_ioctl; 2417 ifp->if_start = mxge_start; 2418 ifp->if_watchdog = mxge_watchdog; 2419 ether_ifattach(ifp, sc->mac_addr); 2420 /* ether_ifattach sets mtu to 1500 */ 2421 ifp->if_mtu = MXGE_MAX_ETHER_MTU - ETHER_HDR_LEN; 2422 2423 /* Initialise the ifmedia structure */ 2424 ifmedia_init(&sc->media, 0, mxge_media_change, 2425 mxge_media_status); 2426 ifmedia_add(&sc->media, IFM_ETHER|IFM_AUTO, 0, NULL); 2427 mxge_add_sysctls(sc); 2428 return 0; 2429 2430abort_with_irq_res: 2431 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 2432abort_with_rx_done: 2433 sc->rx_done.entry = NULL; 2434 mxge_dma_free(&sc->rx_done.dma); 2435abort_with_fw_stats: 2436 mxge_dma_free(&sc->fw_stats_dma); 2437abort_with_zeropad_dma: 2438 mxge_dma_free(&sc->zeropad_dma); 2439abort_with_cmd_dma: 2440 mxge_dma_free(&sc->cmd_dma); 2441abort_with_mem_res: 2442 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res); 2443abort_with_lock: 2444 pci_disable_busmaster(dev); 2445 mtx_destroy(&sc->cmd_lock); 2446 mtx_destroy(&sc->tx_lock); 2447 sx_destroy(&sc->driver_lock); 2448 if_free(ifp); 2449abort_with_parent_dmat: 2450 bus_dma_tag_destroy(sc->parent_dmat); 2451 2452abort_with_nothing: 2453 return err; 2454} 2455 2456static int 2457mxge_detach(device_t dev) 2458{ 2459 mxge_softc_t *sc = device_get_softc(dev); 2460 2461 sx_xlock(&sc->driver_lock); 2462 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) 2463 mxge_close(sc); 2464 sx_xunlock(&sc->driver_lock); 2465 ether_ifdetach(sc->ifp); 2466 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 2467 sc->rx_done.entry = NULL; 2468 mxge_dma_free(&sc->rx_done.dma); 2469 mxge_dma_free(&sc->fw_stats_dma); 2470 mxge_dma_free(&sc->zeropad_dma); 2471 mxge_dma_free(&sc->cmd_dma); 2472 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS, sc->mem_res); 2473 pci_disable_busmaster(dev); 2474 mtx_destroy(&sc->cmd_lock); 2475 mtx_destroy(&sc->tx_lock); 2476 sx_destroy(&sc->driver_lock); 2477 if_free(sc->ifp); 2478 bus_dma_tag_destroy(sc->parent_dmat); 2479 return 0; 2480} 2481 2482static int 2483mxge_shutdown(device_t dev) 2484{ 2485 return 0; 2486} 2487 2488/* 2489 This file uses Myri10GE driver indentation. 2490 2491 Local Variables: 2492 c-file-style:"linux" 2493 tab-width:8 2494 End: 2495*/ 2496