if_mskreg.h revision 298955
1289550Szbb/****************************************************************************** 2289550Szbb * 3289550Szbb * Name: skgehw.h 4289550Szbb * Project: Gigabit Ethernet Adapters, Common Modules 5289550Szbb * Version: $Revision: 2.49 $ 6289550Szbb * Date: $Date: 2005/01/20 13:01:35 $ 7289550Szbb * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 8289550Szbb * 9289550Szbb ******************************************************************************/ 10289550Szbb 11289550Szbb/****************************************************************************** 12289550Szbb * 13289550Szbb * LICENSE: 14289550Szbb * Copyright (C) Marvell International Ltd. and/or its affiliates 15289550Szbb * 16289550Szbb * The computer program files contained in this folder ("Files") 17289550Szbb * are provided to you under the BSD-type license terms provided 18289550Szbb * below, and any use of such Files and any derivative works 19289550Szbb * thereof created by you shall be governed by the following terms 20289550Szbb * and conditions: 21289550Szbb * 22289550Szbb * - Redistributions of source code must retain the above copyright 23289550Szbb * notice, this list of conditions and the following disclaimer. 24289550Szbb * - Redistributions in binary form must reproduce the above 25289550Szbb * copyright notice, this list of conditions and the following 26289550Szbb * disclaimer in the documentation and/or other materials provided 27289550Szbb * with the distribution. 28289550Szbb * - Neither the name of Marvell nor the names of its contributors 29289551Szbb * may be used to endorse or promote products derived from this 30289551Szbb * software without specific prior written permission. 31289550Szbb * 32296030Szbb * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33296030Szbb * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34296030Szbb * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35289551Szbb * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36289551Szbb * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37289551Szbb * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38289551Szbb * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39289551Szbb * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40289551Szbb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41289551Szbb * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42289551Szbb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43289551Szbb * OF THE POSSIBILITY OF SUCH DAMAGE. 44289551Szbb * /LICENSE 45289551Szbb * 46289551Szbb ******************************************************************************/ 47289551Szbb 48289551Szbb/*- 49289551Szbb * Copyright (c) 1997, 1998, 1999, 2000 50289551Szbb * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51289551Szbb * 52289551Szbb * Redistribution and use in source and binary forms, with or without 53289551Szbb * modification, are permitted provided that the following conditions 54289551Szbb * are met: 55289551Szbb * 1. Redistributions of source code must retain the above copyright 56289550Szbb * notice, this list of conditions and the following disclaimer. 57289551Szbb * 2. Redistributions in binary form must reproduce the above copyright 58289551Szbb * notice, this list of conditions and the following disclaimer in the 59289551Szbb * documentation and/or other materials provided with the distribution. 60289551Szbb * 3. All advertising materials mentioning features or use of this software 61289551Szbb * must display the following acknowledgement: 62289551Szbb * This product includes software developed by Bill Paul. 63289551Szbb * 4. Neither the name of the author nor the names of any co-contributors 64289551Szbb * may be used to endorse or promote products derived from this software 65289551Szbb * without specific prior written permission. 66289551Szbb * 67297450Szbb * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68297450Szbb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69289551Szbb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70296030Szbb * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71296030Szbb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72296030Szbb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73296030Szbb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74296030Szbb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75296030Szbb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76296030Szbb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77296030Szbb * THE POSSIBILITY OF SUCH DAMAGE. 78296030Szbb */ 79296030Szbb 80289551Szbb/*- 81289551Szbb * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 82289551Szbb * 83289551Szbb * Permission to use, copy, modify, and distribute this software for any 84289550Szbb * purpose with or without fee is hereby granted, provided that the above 85289550Szbb * copyright notice and this permission notice appear in all copies. 86289550Szbb * 87289550Szbb * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 88289550Szbb * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 89289551Szbb * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 90289551Szbb * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 91289551Szbb * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 92289551Szbb * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 93289551Szbb * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 94289551Szbb */ 95289551Szbb 96289551Szbb/*$FreeBSD: head/sys/dev/msk/if_mskreg.h 298955 2016-05-03 03:41:25Z pfg $*/ 97289551Szbb 98289551Szbb/* 99289551Szbb * SysKonnect PCI vendor ID 100289551Szbb */ 101289551Szbb#define VENDORID_SK 0x1148 102289551Szbb 103289551Szbb/* 104289551Szbb * Marvell PCI vendor ID 105289551Szbb */ 106289551Szbb#define VENDORID_MARVELL 0x11AB 107289551Szbb 108289551Szbb/* 109297450Szbb * D-Link PCI vendor ID 110297450Szbb */ 111289551Szbb#define VENDORID_DLINK 0x1186 112289551Szbb 113289551Szbb/* 114289550Szbb * SysKonnect ethernet device IDs 115289551Szbb */ 116289551Szbb#define DEVICEID_SK_YUKON2 0x9000 117289551Szbb#define DEVICEID_SK_YUKON2_EXPR 0x9e00 118289550Szbb 119289550Szbb/* 120289551Szbb * Marvell gigabit ethernet device IDs 121289550Szbb */ 122289550Szbb#define DEVICEID_MRVL_8021CU 0x4340 123289550Szbb#define DEVICEID_MRVL_8022CU 0x4341 124289551Szbb#define DEVICEID_MRVL_8061CU 0x4342 125289550Szbb#define DEVICEID_MRVL_8062CU 0x4343 126289551Szbb#define DEVICEID_MRVL_8021X 0x4344 127289551Szbb#define DEVICEID_MRVL_8022X 0x4345 128289550Szbb#define DEVICEID_MRVL_8061X 0x4346 129289550Szbb#define DEVICEID_MRVL_8062X 0x4347 130289551Szbb#define DEVICEID_MRVL_8035 0x4350 131289550Szbb#define DEVICEID_MRVL_8036 0x4351 132289550Szbb#define DEVICEID_MRVL_8038 0x4352 133289550Szbb#define DEVICEID_MRVL_8039 0x4353 134289550Szbb#define DEVICEID_MRVL_8040 0x4354 135289550Szbb#define DEVICEID_MRVL_8040T 0x4355 136289551Szbb#define DEVICEID_MRVL_8042 0x4357 137289551Szbb#define DEVICEID_MRVL_8048 0x435A 138289551Szbb#define DEVICEID_MRVL_4360 0x4360 139289550Szbb#define DEVICEID_MRVL_4361 0x4361 140289550Szbb#define DEVICEID_MRVL_4362 0x4362 141289551Szbb#define DEVICEID_MRVL_4363 0x4363 142289551Szbb#define DEVICEID_MRVL_4364 0x4364 143289550Szbb#define DEVICEID_MRVL_4365 0x4365 144289550Szbb#define DEVICEID_MRVL_436A 0x436A 145289551Szbb#define DEVICEID_MRVL_436B 0x436B 146289551Szbb#define DEVICEID_MRVL_436C 0x436C 147289551Szbb#define DEVICEID_MRVL_436D 0x436D 148289551Szbb#define DEVICEID_MRVL_4370 0x4370 149289551Szbb#define DEVICEID_MRVL_4380 0x4380 150289551Szbb#define DEVICEID_MRVL_4381 0x4381 151289551Szbb 152289551Szbb/* 153289551Szbb * D-Link gigabit ethernet device ID 154289551Szbb */ 155289551Szbb#define DEVICEID_DLINK_DGE550SX 0x4001 156289550Szbb#define DEVICEID_DLINK_DGE560SX 0x4002 157289551Szbb#define DEVICEID_DLINK_DGE560T 0x4b00 158289551Szbb 159289551Szbb#define BIT_31 (1U << 31) 160289550Szbb#define BIT_30 (1 << 30) 161289551Szbb#define BIT_29 (1 << 29) 162289551Szbb#define BIT_28 (1 << 28) 163289551Szbb#define BIT_27 (1 << 27) 164289551Szbb#define BIT_26 (1 << 26) 165289551Szbb#define BIT_25 (1 << 25) 166289551Szbb#define BIT_24 (1 << 24) 167289551Szbb#define BIT_23 (1 << 23) 168289551Szbb#define BIT_22 (1 << 22) 169289551Szbb#define BIT_21 (1 << 21) 170289551Szbb#define BIT_20 (1 << 20) 171289551Szbb#define BIT_19 (1 << 19) 172289551Szbb#define BIT_18 (1 << 18) 173289551Szbb#define BIT_17 (1 << 17) 174289551Szbb#define BIT_16 (1 << 16) 175289551Szbb#define BIT_15 (1 << 15) 176289551Szbb#define BIT_14 (1 << 14) 177289551Szbb#define BIT_13 (1 << 13) 178289551Szbb#define BIT_12 (1 << 12) 179289551Szbb#define BIT_11 (1 << 11) 180289551Szbb#define BIT_10 (1 << 10) 181289551Szbb#define BIT_9 (1 << 9) 182289551Szbb#define BIT_8 (1 << 8) 183289551Szbb#define BIT_7 (1 << 7) 184289551Szbb#define BIT_6 (1 << 6) 185289551Szbb#define BIT_5 (1 << 5) 186289551Szbb#define BIT_4 (1 << 4) 187289551Szbb#define BIT_3 (1 << 3) 188289551Szbb#define BIT_2 (1 << 2) 189289551Szbb#define BIT_1 (1 << 1) 190289551Szbb#define BIT_0 (1 << 0) 191289551Szbb 192289551Szbb#define SHIFT31(x) ((x) << 31) 193289551Szbb#define SHIFT30(x) ((x) << 30) 194289551Szbb#define SHIFT29(x) ((x) << 29) 195289551Szbb#define SHIFT28(x) ((x) << 28) 196289551Szbb#define SHIFT27(x) ((x) << 27) 197289551Szbb#define SHIFT26(x) ((x) << 26) 198289551Szbb#define SHIFT25(x) ((x) << 25) 199289551Szbb#define SHIFT24(x) ((x) << 24) 200289551Szbb#define SHIFT23(x) ((x) << 23) 201289551Szbb#define SHIFT22(x) ((x) << 22) 202289551Szbb#define SHIFT21(x) ((x) << 21) 203289551Szbb#define SHIFT20(x) ((x) << 20) 204289551Szbb#define SHIFT19(x) ((x) << 19) 205289551Szbb#define SHIFT18(x) ((x) << 18) 206289551Szbb#define SHIFT17(x) ((x) << 17) 207289551Szbb#define SHIFT16(x) ((x) << 16) 208289551Szbb#define SHIFT15(x) ((x) << 15) 209289551Szbb#define SHIFT14(x) ((x) << 14) 210289550Szbb#define SHIFT13(x) ((x) << 13) 211289551Szbb#define SHIFT12(x) ((x) << 12) 212289550Szbb#define SHIFT11(x) ((x) << 11) 213289551Szbb#define SHIFT10(x) ((x) << 10) 214289551Szbb#define SHIFT9(x) ((x) << 9) 215289551Szbb#define SHIFT8(x) ((x) << 8) 216289551Szbb#define SHIFT7(x) ((x) << 7) 217289551Szbb#define SHIFT6(x) ((x) << 6) 218289551Szbb#define SHIFT5(x) ((x) << 5) 219289551Szbb#define SHIFT4(x) ((x) << 4) 220289551Szbb#define SHIFT3(x) ((x) << 3) 221289551Szbb#define SHIFT2(x) ((x) << 2) 222289551Szbb#define SHIFT1(x) ((x) << 1) 223289551Szbb#define SHIFT0(x) ((x) << 0) 224289551Szbb 225289550Szbb/* 226289550Szbb * PCI Configuration Space header 227289550Szbb */ 228289551Szbb#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 229289551Szbb#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 230289550Szbb#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 231289551Szbb#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 232289551Szbb#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 233289551Szbb#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 234289550Szbb#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 235289550Szbb#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 236289551Szbb#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 237289551Szbb#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 238289551Szbb 239289551Szbb/* PCI Express Capability */ 240289551Szbb#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 241289551Szbb#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 242289551Szbb#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 243289551Szbb#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 244289551Szbb#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 245289551Szbb#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 246289551Szbb#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 247289551Szbb#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 248289550Szbb#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 249289550Szbb 250289550Szbb/* PCI Express Extended Capabilities */ 251289551Szbb#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 252289551Szbb#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 253289550Szbb#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 254289550Szbb#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 255289550Szbb#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 256289550Szbb#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 257289551Szbb#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 258289551Szbb#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 259289551Szbb 260289550Szbb/* PCI_OUR_REG_1 32 bit Our Register 1 */ 261289551Szbb#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 262289550Szbb#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 263289551Szbb#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 264289551Szbb#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 265289551Szbb#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 266289550Szbb#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 267289551Szbb#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 268289551Szbb#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 269289551Szbb#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 270289550Szbb /* 1 = Map Flash to memory */ 271289551Szbb /* 0 = Disable addr. dec */ 272289551Szbb#define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 273289551Szbb#define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 274289551Szbb#define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 275289551Szbb#define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 276289551Szbb#define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 277289551Szbb#define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 278289551Szbb#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 279289551Szbb#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 280289551Szbb#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 281289551Szbb#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 282289551Szbb#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 283289551Szbb#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 284289551Szbb#define PCI_BURST_DIS BIT_9 /* Burst Disable */ 285289551Szbb#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 286289550Szbb#define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 287289551Szbb#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 288289551Szbb#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 289289551Szbb 290289551Szbb/* PCI_OUR_REG_2 32 bit Our Register 2 */ 291289551Szbb#define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 292289551Szbb#define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 293289551Szbb#define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 294289551Szbb /* Bit 13..12: reserved */ 295289550Szbb#define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 296289551Szbb#define PCI_PATCH_DIR_3 BIT_11 297289551Szbb#define PCI_PATCH_DIR_2 BIT_10 298289551Szbb#define PCI_PATCH_DIR_1 BIT_9 299289550Szbb#define PCI_PATCH_DIR_0 BIT_8 300289551Szbb#define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 301289550Szbb#define PCI_EXT_PATCH_3 BIT_7 302289551Szbb#define PCI_EXT_PATCH_2 BIT_6 303289550Szbb#define PCI_EXT_PATCH_1 BIT_5 304289550Szbb#define PCI_EXT_PATCH_0 BIT_4 305289551Szbb#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 306289551Szbb#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 307289551Szbb#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 308289550Szbb 309289551Szbb/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 310289550Szbb#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 311289550Szbb#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 312289550Szbb#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 313289551Szbb#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 314289550Szbb#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 315289551Szbb#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 316289551Szbb#define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 317289551Szbb#define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 318289551Szbb 319289551Szbb#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 320289550Szbb/* possible values for the speed field of the register */ 321289551Szbb#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 322289551Szbb#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 323289551Szbb#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 324289551Szbb#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 325289551Szbb 326289550Szbb/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ 327289551Szbb#define PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */ 328289551Szbb 329289550Szbb/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 330289551Szbb#define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 331289550Szbb#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 332289550Szbb#define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 333289550Szbb#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 334289551Szbb#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 335289551Szbb#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 336289551Szbb#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 337289550Szbb#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 338289551Szbb#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 339289551Szbb#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 340289551Szbb 341289550Szbb/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 342289550Szbb /* Bit 31..27: for A3 & later */ 343289550Szbb#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 344289551Szbb#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 345289550Szbb#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 346289551Szbb#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 347289551Szbb#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 348289551Szbb#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 349289551Szbb /* Bit 26..16: Release Clock on Event */ 350289551Szbb#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 351289551Szbb#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 352289550Szbb#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 353289550Szbb#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 354289551Szbb#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 355289551Szbb#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 356289551Szbb#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 357289551Szbb#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 358289551Szbb#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 359289551Szbb#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 360289550Szbb#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 361289551Szbb /* Bit 10.. 0: Mask for Gate Clock */ 362289551Szbb#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 363289550Szbb#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 364289551Szbb#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 365289551Szbb#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 366289551Szbb#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 367289551Szbb#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 368289551Szbb#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 369289551Szbb#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 370289551Szbb#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 371289551Szbb#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 372289551Szbb#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 373289551Szbb 374289551Szbb/* PCI_CFG_REG_1 32 bit Config Register 1 */ 375289551Szbb#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 376289551Szbb /* Bit 23..21: Release Clock on Event */ 377289551Szbb#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 378289551Szbb#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 379289551Szbb#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 380289551Szbb /* Bit 20..18: Gate Clock on Event */ 381289551Szbb#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 382289551Szbb#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 383289551Szbb#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 384289551Szbb#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 385289551Szbb#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 386289551Szbb 387289551Szbb#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 388289551Szbb#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 389289551Szbb#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 390289551Szbb 391289551Szbb/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 392289551Szbb#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 393289551Szbb#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 394289551Szbb#define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 395289551Szbb#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 396289551Szbb#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 397289551Szbb#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 398289551Szbb#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 399289550Szbb#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 400289551Szbb#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 401289551Szbb#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 402289551Szbb#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 403289551Szbb 404289551Szbb#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 405289551Szbb 406289551Szbb/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 407289550Szbb#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 408289551Szbb#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 409289551Szbb#define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 410289551Szbb#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 411289551Szbb#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 412289551Szbb 413289550Szbb/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 414289551Szbb#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 415289550Szbb#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 416289551Szbb#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 417289551Szbb#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 418289551Szbb#define PEX_COMP_TO BIT_14 /* Completion Timeout */ 419289551Szbb#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 420289551Szbb#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 421289551Szbb#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 422289551Szbb 423289551Szbb#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 424289551Szbb 425289551Szbb/* Control Register File (Address Map) */ 426289550Szbb 427289550Szbb/* 428289550Szbb * Bank 0 429289551Szbb */ 430289551Szbb#define B0_RAP 0x0000 /* 8 bit Register Address Port */ 431289550Szbb#define B0_CTST 0x0004 /* 16 bit Control/Status register */ 432289551Szbb#define B0_LED 0x0006 /* 8 Bit LED register */ 433289551Szbb#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 434289550Szbb#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 435289550Szbb#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 436289551Szbb#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 437289551Szbb#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 438289551Szbb#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 439289550Szbb 440289551Szbb/* Special ISR registers (Yukon-2 only) */ 441289550Szbb#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 442289551Szbb#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 443289550Szbb#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 444289550Szbb#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 445289551Szbb#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 446289551Szbb 447289551Szbb/* 448289551Szbb * Bank 1 449289551Szbb * - completely empty (this is the RAP Block window) 450289551Szbb * Note: if RAP = 1 this page is reserved 451289551Szbb */ 452289551Szbb 453289551Szbb/* 454289551Szbb * Bank 2 455289551Szbb */ 456289550Szbb/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 457289551Szbb#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 458289551Szbb#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 459289551Szbb#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 460289551Szbb#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 461289551Szbb#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 462289551Szbb#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 463289551Szbb#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 464289551Szbb#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 465289551Szbb#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 466289551Szbb#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 467289551Szbb#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 468289551Szbb#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 469289551Szbb#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 470289551Szbb#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 471289551Szbb#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 472289551Szbb#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 473289551Szbb#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 474289551Szbb#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 475289551Szbb#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 476289551Szbb#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 477289551Szbb#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 478289551Szbb#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 479289551Szbb#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 480289551Szbb#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 481289551Szbb#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 482289551Szbb#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 483289551Szbb#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 484289551Szbb#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 485289551Szbb#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 486289551Szbb 487289551Szbb#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 488289551Szbb#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 489289551Szbb 490289550Szbb/* 491289551Szbb * Bank 3 492289551Szbb */ 493289551Szbb/* RAM Random Registers */ 494289551Szbb#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 495289551Szbb#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 496289551Szbb#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 497289551Szbb 498289551Szbb#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 499289551Szbb 500289551Szbb/* RAM Interface Registers */ 501289551Szbb/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 502289551Szbb/* 503289551Szbb * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 504289551Szbb * not usable in SW. Please notice these are NOT real timeouts, these are 505289551Szbb * the number of qWords transferred continuously. 506289551Szbb */ 507289551Szbb#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 508289551Szbb#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 509289551Szbb#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 510289551Szbb#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 511289551Szbb#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 512289551Szbb#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 513289551Szbb#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 514289551Szbb#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 515289551Szbb#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 516289550Szbb#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 517289550Szbb#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 518289550Szbb#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 519289550Szbb#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 520289550Szbb#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 521289550Szbb#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 522289551Szbb 523289551Szbb/* 524289550Szbb * Bank 4 - 5 525289551Szbb */ 526289551Szbb/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 527289550Szbb#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 528289551Szbb#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 529289551Szbb#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 530289551Szbb#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 531289550Szbb#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 532289550Szbb#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 533289550Szbb#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 534289551Szbb 535289551Szbb#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 536289551Szbb 537289551Szbb/* RSS key registers for Yukon-2 Family */ 538289550Szbb#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 539289551Szbb/* RSS key register offsets */ 540289551Szbb#define KEY_IDX_0 0 /* offset for location of KEY 0 */ 541289551Szbb#define KEY_IDX_1 4 /* offset for location of KEY 1 */ 542289551Szbb#define KEY_IDX_2 8 /* offset for location of KEY 2 */ 543289551Szbb#define KEY_IDX_3 12 /* offset for location of KEY 3 */ 544289551Szbb /* 0x0280 - 0x0292: MAC 2 */ 545289550Szbb#define RSS_KEY_ADDR(Port, KeyIndex) \ 546289550Szbb ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 547289551Szbb 548289550Szbb/* 549289550Szbb * Bank 8 - 15 550289550Szbb */ 551289550Szbb/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 552289550Szbb#define B8_Q_REGS 0x0400 553289551Szbb 554289551Szbb/* Queue Register Offsets, use Q_ADDR() to access */ 555289551Szbb#define Q_D 0x00 /* 8*32 bit Current Descriptor */ 556289551Szbb#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 557289550Szbb#define Q_DONE 0x24 /* 16 bit Done Index */ 558289550Szbb#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 559289550Szbb#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 560289550Szbb#define Q_BC 0x30 /* 32 bit Current Byte Counter */ 561289550Szbb#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 562289550Szbb#define Q_F 0x38 /* 32 bit Flag Register */ 563289550Szbb#define Q_T1 0x3c /* 32 bit Test Register 1 */ 564289550Szbb#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 565289551Szbb#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 566289551Szbb#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 567289551Szbb#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 568289551Szbb#define Q_WM 0x40 /* 16 bit FIFO Watermark */ 569289550Szbb#define Q_AL 0x42 /* 8 bit FIFO Alignment */ 570289551Szbb#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 571289550Szbb#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 572289551Szbb#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 573289550Szbb#define Q_RL 0x4a /* 8 bit FIFO Read Level */ 574289550Szbb#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 575289550Szbb#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 576289550Szbb#define Q_WL 0x4e /* 8 bit FIFO Write Level */ 577289550Szbb#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 578289551Szbb 579289550Szbb#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 580289550Szbb 581289551Szbb/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 582289551Szbb#define Y2_B8_PREF_REGS 0x0450 583289550Szbb 584289550Szbb#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 585289550Szbb#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 586289550Szbb#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 587289551Szbb#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 588289551Szbb#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 589289551Szbb#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 590289551Szbb#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 591289551Szbb#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 592289551Szbb#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 593289550Szbb#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 594289550Szbb 595289551Szbb#define PREF_UNIT_MASK_IDX 0x0fff 596289551Szbb 597289551Szbb#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 598289551Szbb 599289550Szbb/* 600289550Szbb * Bank 16 - 23 601289551Szbb */ 602289551Szbb/* RAM Buffer Registers */ 603289551Szbb#define B16_RAM_REGS 0x0800 604289550Szbb 605289551Szbb/* RAM Buffer Register Offsets, use RB_ADDR() to access */ 606289551Szbb#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 607289550Szbb#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 608289551Szbb#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 609289551Szbb#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 610289551Szbb#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 611289551Szbb#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 612289551Szbb#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 613289551Szbb#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 614289551Szbb#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 615289550Szbb#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 616289550Szbb#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 617289551Szbb#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 618289551Szbb#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 619289551Szbb 620289550Szbb/* 621289551Szbb * Bank 24 622289551Szbb */ 623289550Szbb/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 624289551Szbb#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 625289551Szbb#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 626289551Szbb#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 627289551Szbb#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 628289551Szbb#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 629289551Szbb#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 630289551Szbb#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ 631289551Szbb#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ 632289551Szbb#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 633289550Szbb#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 634289550Szbb#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 635289550Szbb#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 636289551Szbb#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 637289551Szbb 638289551Szbb/* 639289551Szbb * Bank 25 640289551Szbb */ 641296031Szbb /* 0x0c80 - 0x0cbf: MAC 2 */ 642289551Szbb /* 0x0cc0 - 0x0cff: reserved */ 643289551Szbb 644289551Szbb/* 645289551Szbb * Bank 26 646296031Szbb */ 647289551Szbb/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 648289551Szbb#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 649289551Szbb#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 650289551Szbb#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 651289551Szbb#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 652289551Szbb#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 653289551Szbb#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 654289551Szbb#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 655289551Szbb#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 656289551Szbb#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 657289551Szbb#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 658289551Szbb 659289551Szbb/* 660289551Szbb * Bank 27 661289551Szbb */ 662289551Szbb /* 0x0d80 - 0x0dbf: MAC 2 */ 663289551Szbb /* 0x0daa - 0x0dff: reserved */ 664289551Szbb 665296031Szbb/* 666296031Szbb * Bank 28 667296031Szbb */ 668296031Szbb/* Descriptor Poll Timer Registers */ 669296031Szbb#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 670296031Szbb#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 671296031Szbb#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 672296031Szbb#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 673296031Szbb/* Time Stamp Timer Registers (YUKON only) */ 674296031Szbb#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 675296031Szbb#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 676296031Szbb#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 677296031Szbb/* Polling Unit Registers (Yukon-2 only) */ 678289551Szbb#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 679289551Szbb#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 680289551Szbb#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 681289551Szbb#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 682289551Szbb/* ASF Subsystem Registers (Yukon-2 only) */ 683289551Szbb#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 684289551Szbb#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 685289551Szbb#define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ 686289551Szbb#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 687289551Szbb#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 688289551Szbb#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 689289551Szbb#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 690289551Szbb#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 691289551Szbb#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 692289551Szbb#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 693289551Szbb#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 694289551Szbb 695289551Szbb/* 696289551Szbb * Bank 29 697289551Szbb */ 698289551Szbb 699289551Szbb/* Status BMU Registers (Yukon-2 only)*/ 700289551Szbb#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 701289551Szbb#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 702289551Szbb#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 703289551Szbb#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 704289551Szbb#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 705289551Szbb#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 706289551Szbb#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 707289551Szbb#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 708289551Szbb#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 709289551Szbb#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 710289551Szbb/* FIFO Control/Status Registers (Yukon-2 only)*/ 711289551Szbb#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 712289551Szbb#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 713289551Szbb#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 714289551Szbb#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 715289551Szbb#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 716289551Szbb#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 717289551Szbb#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 718289551Szbb/* Level and ISR Timer Registers (Yukon-2 only)*/ 719289551Szbb#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 720289551Szbb#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 721289551Szbb#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 722289551Szbb#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 723289551Szbb#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 724289551Szbb#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 725289551Szbb#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 726289551Szbb#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 727296602Szbb#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 728289551Szbb#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 729289551Szbb#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 730289551Szbb#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 731289551Szbb 732289551Szbb#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 733289551Szbb#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 734289551Szbb#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 735289551Szbb#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 736289551Szbb 737289551Szbb/* 738289551Szbb * Bank 30 739289551Szbb */ 740289551Szbb/* GMAC and GPHY Control Registers (YUKON only) */ 741289551Szbb#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 742289551Szbb#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 743289551Szbb#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 744289551Szbb#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 745297450Szbb#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 746296031Szbb 747289551Szbb/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 748296031Szbb 749296031Szbb#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 750289551Szbb 751289551Szbb#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 752289551Szbb#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 753289551Szbb#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 754289551Szbb#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 755289551Szbb#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 756289551Szbb#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 757289551Szbb#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 758289551Szbb#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 759289551Szbb 760289551Szbb/* WOL Pattern Length Registers (YUKON only) */ 761289551Szbb 762289551Szbb#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 763289551Szbb#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 764289551Szbb 765289551Szbb/* WOL Pattern Counter Registers (YUKON only) */ 766289551Szbb 767289551Szbb#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 768289551Szbb#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 769289551Szbb 770289551Szbb/* 771289551Szbb * Bank 32 - 33 772296032Szbb */ 773296032Szbb#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 774289551Szbb#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 775289551Szbb 776289551Szbb/* offset to configuration space on Yukon-2 */ 777289551Szbb#define Y2_CFG_SPC 0x1c00 778289551Szbb#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 779289551Szbb#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 780289551Szbb 781289551Szbb/* 782289551Szbb * Control Register Bit Definitions: 783289551Szbb */ 784289551Szbb/* B0_CTST 24 bit Control/Status register */ 785289551Szbb#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 786289551Szbb#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 787289551Szbb#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 788289551Szbb#define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 789289551Szbb#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 790289551Szbb#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 791289551Szbb#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 792289551Szbb#define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 793289551Szbb#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 794289551Szbb#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 795289551Szbb#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 796289551Szbb#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 797289551Szbb#define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 798289551Szbb#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 799289551Szbb#define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 800289551Szbb#define CS_MRST_SET BIT_2 /* Set Master Reset */ 801289551Szbb#define CS_RST_CLR BIT_1 /* Clear Software Reset */ 802289551Szbb#define CS_RST_SET BIT_0 /* Set Software Reset */ 803289551Szbb 804289551Szbb#define LED_STAT_ON BIT_1 /* Status LED On */ 805289551Szbb#define LED_STAT_OFF BIT_0 /* Status LED Off */ 806289551Szbb 807289551Szbb/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 808289551Szbb#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 809289551Szbb#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 810289551Szbb#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 811289551Szbb#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 812289551Szbb#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 813289551Szbb#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 814289551Szbb#define PC_VCC_ON BIT_1 /* Switch VCC On */ 815289551Szbb#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 816289551Szbb 817289551Szbb/* B0_ISRC 32 bit Interrupt Source Register */ 818289551Szbb/* B0_IMSK 32 bit Interrupt Mask Register */ 819289551Szbb/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 820289551Szbb/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 821289551Szbb/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 822289551Szbb/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 823289551Szbb/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 824297450Szbb/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 825289551Szbb#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 826289551Szbb#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 827296031Szbb#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 828296031Szbb#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 829296031Szbb#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 830296031Szbb#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 831296031Szbb#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 832296031Szbb#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 833297482Ssephe#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 834296031Szbb#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 835289551Szbb#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 836289551Szbb#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 837289551Szbb#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 838289551Szbb#define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ 839289551Szbb#define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ 840289551Szbb#define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ 841289551Szbb#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 842289551Szbb#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 843289551Szbb#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 844289551Szbb#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 845289551Szbb#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 846289551Szbb 847289551Szbb#define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 848289551Szbb 849289551Szbb#define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 850289551Szbb 851289551Szbb#define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 852289551Szbb 853289551Szbb#define Y2_IS_PORT_A \ 854289551Szbb (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 855289551Szbb#define Y2_IS_PORT_B \ 856289551Szbb (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 857289551Szbb 858289551Szbb/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 859289551Szbb/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 860289551Szbb/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 861289551Szbb#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 862289551Szbb#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 863289551Szbb#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 864289551Szbb#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 865289551Szbb#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 866289551Szbb#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 867289551Szbb#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 868289551Szbb#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 869289551Szbb#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 870289551Szbb#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 871289551Szbb#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 872289551Szbb#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 873289551Szbb#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 874289551Szbb#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 875289551Szbb#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 876289551Szbb#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 877289551Szbb#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 878289551Szbb#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 879289551Szbb 880289551Szbb#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 881289551Szbb Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 882289551Szbb#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 883289551Szbb Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 884289551Szbb 885289551Szbb#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 886289551Szbb Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 887289551Szbb Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 888289551Szbb 889289551Szbb/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 890289551Szbb#define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 891289551Szbb#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 892289551Szbb#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 893289551Szbb 894289551Szbb/* B2_CHIP_ID 8 bit Chip Identification Number */ 895289551Szbb#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 896289551Szbb#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 897289551Szbb#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 898289551Szbb#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 899289551Szbb#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 900289551Szbb#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 901289551Szbb#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 902289551Szbb#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 903289551Szbb#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 904289551Szbb#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 905289551Szbb#define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 906289551Szbb#define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 907289551Szbb#define CHIP_ID_YUKON_UNKNOWN 0xbb 908289551Szbb#define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ 909289551Szbb 910296601Szbb#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 911289551Szbb#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 912289551Szbb#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 913289551Szbb#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 914289551Szbb 915289551Szbb#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 916289550Szbb#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 917289551Szbb#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 918289551Szbb 919289551Szbb#define CHIP_REV_YU_EC_U_A0 1 920289550Szbb#define CHIP_REV_YU_EC_U_A1 2 921289550Szbb 922289550Szbb#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 923289551Szbb 924289551Szbb#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 925289551Szbb#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 926289551Szbb 927289551Szbb#define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */ 928289550Szbb#define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */ 929289550Szbb#define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */ 930289550Szbb 931289551Szbb/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 932289551Szbb#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 933289551Szbb#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 934289551Szbb#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 935289551Szbb#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 936289551Szbb#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 937289550Szbb#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 938296038Szbb#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 939289551Szbb#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 940289551Szbb 941289550Szbb/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 942289550Szbb#define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 943289551Szbb#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 944289551Szbb#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 945289551Szbb 946289551Szbb#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 947289551Szbb#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 948289551Szbb 949289551Szbb/* B2_E_3 8 bit lower 4 bits used for HW self test result */ 950289551Szbb#define B2_E3_RES_MASK 0x0f 951289551Szbb 952289551Szbb/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 953289551Szbb/* Yukon-EC/FE */ 954289550Szbb#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 955289550Szbb#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 956289551Szbb/* Yukon-2 */ 957289551Szbb#define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 958289550Szbb#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 959289551Szbb#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 960289551Szbb#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 961289550Szbb#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 962289551Szbb#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 963289551Szbb 964289551Szbb/* B2_TI_CTRL 8 bit Timer control */ 965289551Szbb/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 966289551Szbb#define TIM_START BIT_2 /* Start Timer */ 967289551Szbb#define TIM_STOP BIT_1 /* Stop Timer */ 968289551Szbb#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 969289550Szbb 970289551Szbb/* B2_TI_TEST 8 Bit Timer Test */ 971289551Szbb/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 972289551Szbb/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 973289551Szbb#define TIM_T_ON BIT_2 /* Test mode on */ 974289551Szbb#define TIM_T_OFF BIT_1 /* Test mode off */ 975289551Szbb#define TIM_T_STEP BIT_0 /* Test step */ 976289551Szbb 977289551Szbb/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 978289551Szbb/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 979289551Szbb#define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 980289551Szbb 981289551Szbb/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 982289551Szbb#define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 983289551Szbb#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 984289551Szbb 985289551Szbb/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 986289551Szbb#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 987289551Szbb#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 988289550Szbb#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 989289551Szbb#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 990289551Szbb#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 991289551Szbb#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 992289551Szbb#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 993289550Szbb#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 994289550Szbb 995297450Szbb/* B2_GP_IO */ 996297450Szbb#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 997297450Szbb#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 998297450Szbb 999297450Szbb#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 1000297450Szbb#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 1001297450Szbb#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 1002297450Szbb#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 1003297450Szbb#define GLB_GPIO_TEST_SEL_BASE BIT_11 1004297450Szbb#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 1005297450Szbb#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 1006297450Szbb 1007297450Szbb/* B2_I2C_CTRL 32 bit I2C HW Control Register */ 1008297450Szbb#define I2C_FLAG BIT_31 /* Start read/write if WR */ 1009297450Szbb#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 1010297450Szbb#define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 1011297450Szbb#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 1012297450Szbb#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 1013297450Szbb#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 1014297450Szbb#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 1015297450Szbb#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 1016297450Szbb#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 1017297450Szbb#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 1018297450Szbb#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 1019297450Szbb#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 1020297450Szbb#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 1021297450Szbb#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 1022297450Szbb 1023297450Szbb/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 1024297450Szbb#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 1025297450Szbb 1026289551Szbb/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 1027289551Szbb#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 1028289551Szbb#define I2C_DATA BIT_1 /* I2C Data Port */ 1029289551Szbb#define I2C_CLK BIT_0 /* I2C Clock Port */ 1030297450Szbb 1031297450Szbb/* I2C Address */ 1032297450Szbb#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 1033289551Szbb 1034297450Szbb 1035297450Szbb/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 1036297450Szbb#define BSC_START BIT_1 /* Start Blink Source Counter */ 1037297450Szbb#define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 1038297450Szbb 1039297450Szbb/* B2_BSC_STAT 8 bit Blink Source Counter Status */ 1040297450Szbb#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 1041297450Szbb 1042297450Szbb/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 1043297450Szbb#define BSC_T_ON BIT_2 /* Test mode on */ 1044297450Szbb#define BSC_T_OFF BIT_1 /* Test mode off */ 1045289551Szbb#define BSC_T_STEP BIT_0 /* Test step */ 1046297450Szbb 1047289551Szbb/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 1048297450Szbb#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 1049297450Szbb#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 1050297450Szbb 1051289551Szbb/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 1052289551Szbb#define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 1053289550Szbb 1054289551Szbb/* RAM Interface Registers */ 1055289551Szbb/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 1056289551Szbb#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 1057289550Szbb#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 1058289551Szbb#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 1059289550Szbb#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 1060289550Szbb 1061289551Szbb#define MSK_RI_TO_53 36 /* RAM interface timeout */ 1062289551Szbb 1063289551Szbb/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 1064289551Szbb/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 1065289551Szbb/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 1066289551Szbb/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 1067289551Szbb/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 1068289551Szbb#define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 1069289551Szbb 1070289551Szbb/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 1071289551Szbb#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 1072289551Szbb#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 1073289551Szbb#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 1074289551Szbb#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 1075289551Szbb#define TXA_START_RC BIT_3 /* Start sync Rate Control */ 1076289551Szbb#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 1077289551Szbb#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 1078289550Szbb#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 1079289550Szbb 1080289551Szbb/* TXA_TEST 8 bit Tx Arbiter Test Register */ 1081289551Szbb#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 1082289551Szbb#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 1083289551Szbb#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 1084289551Szbb#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 1085289550Szbb#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 1086289550Szbb#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 1087289551Szbb 1088297388Szbb/* TXA_STAT 8 bit Tx Arbiter Status Register */ 1089289550Szbb#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 1090289551Szbb 1091289551Szbb/* Q_BC 32 bit Current Byte Counter */ 1092289550Szbb#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 1093289551Szbb 1094289551Szbb/* Rx BMU Control / Status Registers (Yukon-2) */ 1095289551Szbb#define BMU_IDLE BIT_31 /* BMU Idle State */ 1096289550Szbb#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 1097289551Szbb#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 1098289551Szbb#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 1099289551Szbb#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 1100289551Szbb#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1101289551Szbb#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1102289551Szbb#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1103289551Szbb#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 1104289551Szbb#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 1105296039Szbb#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 1106296039Szbb#define BMU_START BIT_8 /* Start Rx/Tx Queue */ 1107289551Szbb#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1108289551Szbb#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 1109289551Szbb#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 1110289551Szbb#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 1111289551Szbb#define BMU_OP_ON BIT_3 /* BMU Operational On */ 1112289551Szbb#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 1113289551Szbb#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 1114289551Szbb#define BMU_RST_SET BIT_0 /* Set BMU Reset */ 1115289551Szbb 1116289551Szbb#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 1117289551Szbb#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 1118289551Szbb BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1119289551Szbb 1120289551Szbb/* Tx BMU Control / Status Registers (Yukon-2) */ 1121289551Szbb /* Bit 31: same as for Rx */ 1122289551Szbb#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 1123289551Szbb#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 1124289551Szbb#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 1125289551Szbb /* Bit 10..0: same as for Rx */ 1126289551Szbb 1127289551Szbb/* Q_F 32 bit Flag Register */ 1128289551Szbb#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 1129289551Szbb#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1130289551Szbb#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 1131289551Szbb#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 1132289551Szbb#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1133289551Szbb#define F_WM_REACHED BIT_25 /* Watermark reached */ 1134289551Szbb#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1135289551Szbb#define F_FIFO_LEVEL (0x1f<<16) 1136289551Szbb /* Bit 23..16: # of Qwords in FIFO */ 1137289551Szbb#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 1138289551Szbb 1139289551Szbb/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1140289551Szbb/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1141289551Szbb#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1142289551Szbb#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1143289551Szbb#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1144289551Szbb#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1145289551Szbb 1146289551Szbb/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1147289551Szbb/* RB_START 32 bit RAM Buffer Start Address */ 1148289551Szbb/* RB_END 32 bit RAM Buffer End Address */ 1149289551Szbb/* RB_WP 32 bit RAM Buffer Write Pointer */ 1150289551Szbb/* RB_RP 32 bit RAM Buffer Read Pointer */ 1151289550Szbb/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 1152289550Szbb/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1153289551Szbb/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1154289551Szbb/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1155289550Szbb/* RB_PC 32 bit RAM Buffer Packet Counter */ 1156289551Szbb/* RB_LEV 32 bit RAM Buffer Level Register */ 1157289551Szbb#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1158289551Szbb 1159289551Szbb/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 1160289551Szbb#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1161289550Szbb#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 1162289550Szbb#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1163289551Szbb#define RB_PC_INC BIT_0 /* Packet Counter Increment */ 1164289551Szbb 1165289551Szbb/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1166289551Szbb#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1167289550Szbb#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1168289551Szbb#define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1169289551Szbb#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1170289551Szbb#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1171289551Szbb#define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1172289551Szbb 1173289551Szbb/* RB_CTRL 8 bit RAM Buffer Control Register */ 1174289551Szbb#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1175289551Szbb#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1176289551Szbb#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 1177289551Szbb#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1178289551Szbb#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1179289551Szbb#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1180289551Szbb 1181289551Szbb/* RAM Buffer High Pause Threshold values */ 1182289551Szbb#define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 1183289551Szbb#define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1184289551Szbb#define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1185289551Szbb 1186289551Szbb/* Threshold values for Yukon-EC Ultra */ 1187289551Szbb#define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1188289551Szbb#define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1189289551Szbb#define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 1190289551Szbb#define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1191289551Szbb#define MSK_ECU_JUMBO_WM 0x01 1192289551Szbb 1193289551Szbb#define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1194289551Szbb#define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1195289551Szbb/* performance sensitive drivers should set this define to 0x80 */ 1196289551Szbb#define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 1197289551Szbb 1198289551Szbb/* Receive and Transmit Queues */ 1199289551Szbb#define Q_R1 0x0000 /* Receive Queue 1 */ 1200289551Szbb#define Q_R2 0x0080 /* Receive Queue 2 */ 1201289551Szbb#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1202289551Szbb#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1203289551Szbb#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1204289551Szbb#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 1205289551Szbb 1206289551Szbb#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1207289551Szbb#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 1208289551Szbb#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1209289551Szbb#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 1210289551Szbb 1211289551Szbb#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1212289550Szbb 1213289550Szbb/* Minimum RAM Buffer Rx Queue Size */ 1214289551Szbb#define MSK_MIN_RXQ_SIZE 10 1215289551Szbb/* Minimum RAM Buffer Tx Queue Size */ 1216289550Szbb#define MSK_MIN_TXQ_SIZE 10 1217289551Szbb/* Percentage of queue size from whole memory. 80 % for receive */ 1218289550Szbb#define MSK_RAM_QUOTA_RX 80 1219289550Szbb 1220289550Szbb/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1221289550Szbb#define WOL_CTL_LINK_CHG_OCC BIT_15 1222289550Szbb#define WOL_CTL_MAGIC_PKT_OCC BIT_14 1223289550Szbb#define WOL_CTL_PATTERN_OCC BIT_13 1224289550Szbb#define WOL_CTL_CLEAR_RESULT BIT_12 1225289550Szbb#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1226289550Szbb#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 1227289551Szbb#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 1228289551Szbb#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 1229289550Szbb#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 1230289550Szbb#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 1231289550Szbb#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 1232289550Szbb#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 1233289550Szbb#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1234289550Szbb#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1235289550Szbb#define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1236289550Szbb#define WOL_CTL_DIS_PATTERN_UNIT BIT_0 1237289551Szbb 1238289551Szbb#define WOL_CTL_DEFAULT \ 1239289550Szbb (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1240289551Szbb WOL_CTL_DIS_PME_ON_PATTERN | \ 1241289550Szbb WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1242289550Szbb WOL_CTL_DIS_LINK_CHG_UNIT | \ 1243289550Szbb WOL_CTL_DIS_PATTERN_UNIT | \ 1244289550Szbb WOL_CTL_DIS_MAGIC_PKT_UNIT) 1245289550Szbb 1246289550Szbb/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1247289550Szbb#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 1248289550Szbb 1249289551Szbb/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 1250289551Szbb#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 1251289550Szbb#define WOL_PATT_MATCH_PME_ALL 0x7f 1252289551Szbb 1253289550Szbb 1254289550Szbb/* 1255289550Szbb * Marvel-PHY Registers, indirect addressed over GMAC 1256289551Szbb */ 1257289551Szbb#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 1258289551Szbb#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 1259289551Szbb#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1260289550Szbb#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1261289551Szbb#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 1262289551Szbb#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 1263289550Szbb#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 1264289550Szbb#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 1265289550Szbb#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 1266289551Szbb /* Marvel-specific registers */ 1267289550Szbb#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1268289551Szbb#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1269289551Szbb /* 0x0b - 0x0e: reserved */ 1270289550Szbb#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1271289550Szbb#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1272289550Szbb#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1273289550Szbb#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1274289550Szbb#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1275289550Szbb#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1276289550Szbb#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1277289551Szbb#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1278289550Szbb#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1279289550Szbb#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1280289551Szbb#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 1281289551Szbb#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1282289550Szbb#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1283289550Szbb#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 1284289551Szbb#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 1285289551Szbb#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 1286289550Szbb 1287289550Szbb/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1288289550Szbb#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 1289289551Szbb#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 1290289551Szbb#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 1291289550Szbb#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 1292289550Szbb#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 1293289550Szbb 1294289550Szbb#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 1295289550Szbb#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 1296289550Szbb#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 1297289550Szbb#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 1298289550Szbb#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1299289550Szbb#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 1300289551Szbb#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 1301289551Szbb#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 1302289551Szbb#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1303289550Szbb#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 1304289550Szbb 1305289550Szbb#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 1306289550Szbb#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 1307296031Szbb#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 1308296031Szbb 1309289550Szbb#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1310296031Szbb#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 1311296031Szbb#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1312289550Szbb#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */ 1313289550Szbb#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 1314289550Szbb#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 1315296031Szbb#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 1316296031Szbb#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1317289550Szbb 1318289550Szbb#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1319289550Szbb#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1320289550Szbb#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1321289550Szbb 1322296031Szbb/* different Marvell PHY Ids */ 1323296031Szbb#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1324296031Szbb 1325289550Szbb#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1326289550Szbb#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1327289550Szbb#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 1328296031Szbb#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 1329296031Szbb#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1330296031Szbb#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 1331296031Szbb 1332296031Szbb/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1333296031Szbb#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1334296031Szbb#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1335296031Szbb#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1336296031Szbb#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 1337296031Szbb#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1338296031Szbb#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1339296031Szbb#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1340289550Szbb 1341289550Szbb/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1342289550Szbb/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1343289550Szbb#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1344289550Szbb#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1345289550Szbb#define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1346289550Szbb#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1347289550Szbb#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1348289550Szbb#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 1349289550Szbb#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1350289550Szbb#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1351289550Szbb#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1352289550Szbb#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1353289550Szbb#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1354289551Szbb 1355289551Szbb/* special defines for FIBER (88E1011S only) */ 1356289551Szbb#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1357289550Szbb#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1358289550Szbb#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1359289550Szbb#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1360289551Szbb 1361289550Szbb/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1362289550Szbb#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1363289551Szbb#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1364289551Szbb#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1365289550Szbb#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1366289550Szbb 1367289550Szbb/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1368289551Szbb#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1369289550Szbb#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1370289550Szbb#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1371289550Szbb#define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1372289550Szbb#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1373289550Szbb#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1374289550Szbb 1375289550Szbb/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1376289551Szbb#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1377289551Szbb#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1378289550Szbb#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 1379289550Szbb#define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 1380289550Szbb#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1381289551Szbb#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 1382289551Szbb#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1383289551Szbb#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 1384289550Szbb#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1385289550Szbb#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 1386289550Szbb#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 1387289550Szbb#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 1388289550Szbb 1389289550Szbb#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1390289550Szbb#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1391289550Szbb 1392289550Szbb#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 1393289550Szbb 1394289550Szbb#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1395289550Szbb#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1396289550Szbb#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1397289550Szbb 1398289550Szbb/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1399289550Szbb#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 1400289551Szbb#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 1401289551Szbb#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 1402289550Szbb /* !!! Errata in spec. (1 = disable) */ 1403289550Szbb 1404289550Szbb#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 1405289550Szbb /* 000=1x; 001=2x; 010=3x; 011=4x */ 1406289550Szbb /* 100=5x; 101=6x; 110=7x; 111=8x */ 1407289550Szbb 1408289550Szbb/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1409289551Szbb#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1410289550Szbb#define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 1411289550Szbb#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 1412289550Szbb#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 1413289551Szbb#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 1414289551Szbb#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1415289550Szbb#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 1416289550Szbb#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 1417289550Szbb#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 1418289551Szbb 1419289551Szbb/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1420289551Szbb#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1421289550Szbb#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 1422289550Szbb#define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 1423289550Szbb#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1424289550Szbb#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 1425289550Szbb#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 1426289550Szbb#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 1427289550Szbb#define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 1428289550Szbb#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 1429289550Szbb#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 1430289550Szbb#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 1431289550Szbb#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 1432289550Szbb#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 1433289550Szbb#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 1434289550Szbb#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 1435289550Szbb#define PHY_M_PS_JABBER BIT_0 /* Jabber */ 1436289550Szbb 1437289550Szbb#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1438289550Szbb 1439289550Szbb/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1440289550Szbb#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 1441289550Szbb#define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1442289550Szbb 1443289550Szbb/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1444289550Szbb/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1445289550Szbb#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 1446289550Szbb#define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 1447289550Szbb#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 1448289550Szbb#define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 1449289551Szbb#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1450289551Szbb#define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 1451289550Szbb#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 1452289550Szbb#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 1453289550Szbb#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 1454289550Szbb#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 1455289550Szbb#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 1456289550Szbb#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 1457289550Szbb#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 1458289551Szbb#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 1459289550Szbb#define PHY_M_IS_JABBER BIT_0 /* Jabber */ 1460289550Szbb 1461289550Szbb#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1462289550Szbb PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1463289550Szbb 1464289550Szbb/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1465289551Szbb#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1466289551Szbb#define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 1467289551Szbb#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 1468289550Szbb#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 1469289550Szbb /* (88E1011 only) */ 1470289550Szbb#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 1471289550Szbb /* (88E1011 only) */ 1472289550Szbb#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 1473289550Szbb /* (88E1111 only) */ 1474289550Szbb#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 1475289550Szbb /* !!! Errata in spec. (1 = disable) */ 1476289550Szbb#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 1477289550Szbb#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1478289551Szbb#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 1479289551Szbb#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 1480289550Szbb#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 1481289550Szbb#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 1482289550Szbb 1483289550Szbb#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1484289550Szbb /* 00=1x; 01=2x; 10=3x; 11=4x */ 1485289550Szbb#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 1486289550Szbb /* 00=dis; 01=1x; 10=2x; 11=3x */ 1487289550Szbb#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1488289550Szbb /* 01X=0; 110=2.5; 111=25 (MHz) */ 1489289551Szbb 1490289551Szbb#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 1491289550Szbb /* 000=1x; 001=2x; 010=3x; 011=4x */ 1492289550Szbb /* 100=5x; 101=6x; 110=7x; 111=8x */ 1493289551Szbb#define MAC_TX_CLK_0_MHZ 2 1494289551Szbb#define MAC_TX_CLK_2_5_MHZ 6 1495289550Szbb#define MAC_TX_CLK_25_MHZ 7 1496289550Szbb 1497289551Szbb/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1498289551Szbb#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 1499289550Szbb#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1500289550Szbb#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1501289550Szbb#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1502289551Szbb#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 1503289551Szbb#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 1504289550Szbb#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 1505289550Szbb /* (88E1111 only) */ 1506289551Szbb#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1507289550Szbb /* (88E1011 only) */ 1508289550Szbb#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1509289551Szbb#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 1510289551Szbb#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 1511289551Szbb#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 1512289551Szbb#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 1513289550Szbb 1514289550Szbb#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 1515289550Szbb 1516289550Szbb#define PULS_NO_STR 0 /* no pulse stretching */ 1517289550Szbb#define PULS_21MS 1 /* 21 ms to 42 ms */ 1518289550Szbb#define PULS_42MS 2 /* 42 ms to 84 ms */ 1519289550Szbb#define PULS_84MS 3 /* 84 ms to 170 ms */ 1520289550Szbb#define PULS_170MS 4 /* 170 ms to 340 ms */ 1521289550Szbb#define PULS_340MS 5 /* 340 ms to 670 ms */ 1522289550Szbb#define PULS_670MS 6 /* 670 ms to 1.3 s */ 1523289550Szbb#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1524289550Szbb 1525289550Szbb#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 1526289550Szbb 1527289550Szbb#define BLINK_42MS 0 /* 42 ms */ 1528289550Szbb#define BLINK_84MS 1 /* 84 ms */ 1529289550Szbb#define BLINK_170MS 2 /* 170 ms */ 1530289550Szbb#define BLINK_340MS 3 /* 340 ms */ 1531289550Szbb#define BLINK_670MS 4 /* 670 ms */ 1532289551Szbb 1533289551Szbb/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1534289550Szbb#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 1535289550Szbb#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1536289551Szbb#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1537289550Szbb#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1538289551Szbb#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1539289551Szbb#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1540289551Szbb#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1541289551Szbb 1542289551Szbb#define MO_LED_NORM 0 1543289551Szbb#define MO_LED_BLINK 1 1544289551Szbb#define MO_LED_OFF 2 1545289551Szbb#define MO_LED_ON 3 1546289551Szbb 1547289551Szbb/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1548289551Szbb#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 1549289551Szbb#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1550289551Szbb#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 1551289551Szbb#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 1552289551Szbb#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1553289550Szbb 1554289550Szbb/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1555289550Szbb#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 1556289550Szbb#define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1557289550Szbb#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 1558289550Szbb#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1559289550Szbb#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 1560289550Szbb#define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 1561289550Szbb#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 1562289550Szbb /* (88E1111 only) */ 1563289550Szbb#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 1564289550Szbb#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 1565289550Szbb#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1566289551Szbb 1567289551Szbb/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1568289550Szbb#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 1569289551Szbb#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 1570289550Szbb /* (88E1111 only) */ 1571289550Szbb#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1572289550Szbb#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 1573289550Szbb /* (88E1111 only) */ 1574289550Szbb#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 1575289551Szbb 1576289550Szbb/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1577289550Szbb#define CABD_STAT_NORMAL 0 1578289550Szbb#define CABD_STAT_SHORT 1 1579289550Szbb#define CABD_STAT_OPEN 2 1580289550Szbb#define CABD_STAT_FAIL 3 1581289551Szbb 1582289550Szbb/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1583289550Szbb/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1584289550Szbb#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 1585289550Szbb#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 1586289550Szbb#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 1587289551Szbb 1588289550Szbb#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1589289550Szbb#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 1590289550Szbb#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 1591289551Szbb 1592289551Szbb#define LED_PAR_CTRL_COLX 0x00 1593289551Szbb#define LED_PAR_CTRL_ERROR 0x01 1594289551Szbb#define LED_PAR_CTRL_DUPLEX 0x02 1595289551Szbb#define LED_PAR_CTRL_DP_COL 0x03 1596289551Szbb#define LED_PAR_CTRL_SPEED 0x04 1597289551Szbb#define LED_PAR_CTRL_LINK 0x05 1598289551Szbb#define LED_PAR_CTRL_TX 0x06 1599289550Szbb#define LED_PAR_CTRL_RX 0x07 1600289550Szbb#define LED_PAR_CTRL_ACT 0x08 1601289551Szbb#define LED_PAR_CTRL_LNK_RX 0x09 1602289550Szbb#define LED_PAR_CTRL_LNK_AC 0x0a 1603289550Szbb#define LED_PAR_CTRL_ACT_BL 0x0b 1604289551Szbb#define LED_PAR_CTRL_TX_BL 0x0c 1605289551Szbb#define LED_PAR_CTRL_RX_BL 0x0d 1606289550Szbb#define LED_PAR_CTRL_COL_BL 0x0e 1607289550Szbb#define LED_PAR_CTRL_INACT 0x0f 1608289550Szbb 1609289551Szbb/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1610289550Szbb#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1611289550Szbb#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1612289550Szbb#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1613289550Szbb 1614289551Szbb/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1615289550Szbb/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1616289551Szbb#define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1617289550Szbb#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1618289550Szbb#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1619289550Szbb 1620289550Szbb/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1621289550Szbb#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1622289550Szbb#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1623289550Szbb#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1624289550Szbb#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1625289550Szbb#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1626289550Szbb 1627289550Szbb/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1628289551Szbb#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 1629289550Szbb#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1630289550Szbb#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1631289551Szbb#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1632289551Szbb 1633289550Szbb#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1634289551Szbb#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 1635289551Szbb#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 1636289550Szbb#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 1637289550Szbb 1638289551Szbb/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1639289551Szbb#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1640289551Szbb#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1641289550Szbb#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1642289550Szbb#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1643289551Szbb#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1644289551Szbb#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1645289550Szbb 1646289550Szbb#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1647289550Szbb#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1648289550Szbb#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1649289550Szbb#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1650289550Szbb#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1651289550Szbb#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1652289550Szbb 1653289550Szbb/* 1654289550Szbb * GMAC registers 1655289550Szbb * 1656289550Szbb * The GMAC registers are 16 or 32 bits wide. 1657289550Szbb * The GMACs host processor interface is 16 bits wide, 1658289550Szbb * therefore ALL registers will be addressed with 16 bit accesses. 1659289550Szbb * 1660289550Szbb * Note: NA reg = Network Address e.g DA, SA etc. 1661289550Szbb */ 1662289550Szbb 1663289550Szbb/* Port Registers */ 1664289550Szbb#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1665289550Szbb#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1666289550Szbb#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1667289551Szbb#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1668289550Szbb#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1669289550Szbb#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1670289551Szbb#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1671289551Szbb 1672289550Szbb/* Source Address Registers */ 1673289550Szbb#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1674289551Szbb#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1675289551Szbb#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1676289550Szbb#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1677289550Szbb#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1678289550Szbb#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1679289550Szbb 1680297388Szbb/* Multicast Address Hash Registers */ 1681289550Szbb#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1682289550Szbb#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1683289550Szbb#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1684289551Szbb#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1685289550Szbb 1686289550Szbb/* Interrupt Source Registers */ 1687289550Szbb#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1688289551Szbb#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1689289551Szbb#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1690289550Szbb 1691289551Szbb/* Interrupt Mask Registers */ 1692297388Szbb#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1693289550Szbb#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1694289550Szbb#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1695289550Szbb 1696289550Szbb/* Serial Management Interface (SMI) Registers */ 1697289551Szbb#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1698289551Szbb#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1699289550Szbb#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1700289550Szbb 1701289550Szbb/* MIB Counters */ 1702289551Szbb#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1703289550Szbb#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1704289550Szbb 1705289551Szbb/* 1706289551Szbb * MIB Counters base address definitions (low word) - 1707289550Szbb * use offset 4 for access to high word (32 bit r/o) 1708289551Szbb */ 1709289550Szbb#define GM_RXF_UC_OK \ 1710289550Szbb (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1711289550Szbb#define GM_RXF_BC_OK \ 1712289550Szbb (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1713289550Szbb#define GM_RXF_MPAUSE \ 1714289550Szbb (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1715289550Szbb#define GM_RXF_MC_OK \ 1716289550Szbb (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1717289551Szbb#define GM_RXF_FCS_ERR \ 1718289551Szbb (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1719289550Szbb#define GM_RXF_SPARE1 \ 1720289551Szbb (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 1721289550Szbb#define GM_RXO_OK_LO \ 1722289550Szbb (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1723289550Szbb#define GM_RXO_OK_HI \ 1724289550Szbb (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1725289550Szbb#define GM_RXO_ERR_LO \ 1726289550Szbb (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1727289551Szbb#define GM_RXO_ERR_HI \ 1728289551Szbb (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1729289550Szbb#define GM_RXF_SHT \ 1730289551Szbb (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1731289551Szbb#define GM_RXE_FRAG \ 1732289550Szbb (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1733289550Szbb#define GM_RXF_64B \ 1734289551Szbb (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1735289550Szbb#define GM_RXF_127B \ 1736289550Szbb (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1737289550Szbb#define GM_RXF_255B \ 1738289550Szbb (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1739289550Szbb#define GM_RXF_511B \ 1740289550Szbb (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1741289550Szbb#define GM_RXF_1023B \ 1742289550Szbb (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1743289551Szbb#define GM_RXF_1518B \ 1744289551Szbb (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1745289551Szbb#define GM_RXF_MAX_SZ \ 1746289551Szbb (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1747289551Szbb#define GM_RXF_LNG_ERR \ 1748289551Szbb (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1749289550Szbb#define GM_RXF_JAB_PKT \ 1750289550Szbb (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1751289551Szbb#define GM_RXF_SPARE2 \ 1752289550Szbb (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 1753289550Szbb#define GM_RXE_FIFO_OV \ 1754289551Szbb (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1755289551Szbb#define GM_RXF_SPARE3 \ 1756289550Szbb (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 1757289550Szbb#define GM_TXF_UC_OK \ 1758296030Szbb (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1759289550Szbb#define GM_TXF_BC_OK \ 1760289551Szbb (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1761289550Szbb#define GM_TXF_MPAUSE \ 1762296039Szbb (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1763289550Szbb#define GM_TXF_MC_OK \ 1764296030Szbb (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1765296030Szbb#define GM_TXO_OK_LO \ 1766296030Szbb (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1767296039Szbb#define GM_TXO_OK_HI \ 1768296030Szbb (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1769296030Szbb#define GM_TXF_64B \ 1770296030Szbb (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1771289550Szbb#define GM_TXF_127B \ 1772296039Szbb (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1773296039Szbb#define GM_TXF_255B \ 1774289550Szbb (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1775289551Szbb#define GM_TXF_511B \ 1776289550Szbb (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1777289550Szbb#define GM_TXF_1023B \ 1778289550Szbb (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1779289550Szbb#define GM_TXF_1518B \ 1780289550Szbb (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1781289550Szbb#define GM_TXF_MAX_SZ \ 1782289550Szbb (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1783289550Szbb#define GM_TXF_SPARE1 \ 1784289550Szbb (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 1785296039Szbb#define GM_TXF_COL \ 1786296039Szbb (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1787296039Szbb#define GM_TXF_LAT_COL \ 1788296039Szbb (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1789296039Szbb#define GM_TXF_ABO_COL \ 1790296039Szbb (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1791296039Szbb#define GM_TXF_MUL_COL \ 1792296039Szbb (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1793296030Szbb#define GM_TXF_SNG_COL \ 1794296039Szbb (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1795296039Szbb#define GM_TXE_FIFO_UR \ 1796296039Szbb (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1797296039Szbb 1798296039Szbb/*----------------------------------------------------------------------------*/ 1799296039Szbb/* 1800296039Szbb * GMAC Bit Definitions 1801296039Szbb * 1802296039Szbb * If the bit access behaviour differs from the register access behaviour 1803296039Szbb * (r/w, r/o) this is documented after the bit number. 1804296030Szbb * The following bit access behaviours are used: 1805296030Szbb * (sc) self clearing 1806296030Szbb * (r/o) read only 1807296030Szbb */ 1808296030Szbb 1809296030Szbb/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1810296030Szbb#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1811296039Szbb#define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1812296039Szbb#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1813296039Szbb#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1814296030Szbb#define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1815296039Szbb#define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1816296039Szbb#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */ 1817296030Szbb#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occurred */ 1818296030Szbb#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1819296030Szbb#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1820296030Szbb#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1821296030Szbb#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1822296030Szbb 1823296030Szbb/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1824296030Szbb#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1825296030Szbb#define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1826296030Szbb#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1827296030Szbb#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1828296030Szbb#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1829296030Szbb#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1830296030Szbb#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1831296030Szbb#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1832296030Szbb#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1833296030Szbb#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1834296030Szbb#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1835296030Szbb#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1836296030Szbb#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1837296030Szbb#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1838296030Szbb#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1839296030Szbb 1840296030Szbb#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1841296030Szbb#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1842296030Szbb GM_GPCR_AU_SPD_DIS) 1843296030Szbb 1844296030Szbb/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1845296030Szbb#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1846296030Szbb#define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1847296030Szbb#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1848296030Szbb#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1849296030Szbb#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1850296030Szbb /* (Yukon-2 only) */ 1851296030Szbb 1852296030Szbb#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1853296030Szbb#define TX_COL_DEF 0x04 1854296030Szbb 1855296030Szbb/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1856296030Szbb#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1857296039Szbb#define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1858296039Szbb#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1859296030Szbb#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1860296030Szbb 1861296039Szbb/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1862296039Szbb#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1863296039Szbb#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1864296039Szbb#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1865296039Szbb#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1866296039Szbb /* (Yukon-2 only) */ 1867296039Szbb 1868296039Szbb#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1869296039Szbb#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1870296039Szbb#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1871296039Szbb#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1872296039Szbb 1873296039Szbb#define TX_JAM_LEN_DEF 0x03 1874296039Szbb#define TX_JAM_IPG_DEF 0x0b 1875296039Szbb#define TX_IPG_JAM_DEF 0x1c 1876296039Szbb#define TX_BOF_LIM_DEF 0x04 1877296030Szbb 1878296039Szbb/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1879296030Szbb#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1880296030Szbb /* r/o on Yukon, r/w on Yukon-EC */ 1881289550Szbb#define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1882289550Szbb#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1883289551Szbb#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1884289551Szbb#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1885289550Szbb 1886289550Szbb#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1887289550Szbb#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1888289551Szbb 1889289550Szbb#define DATA_BLIND_DEF 0x04 1890289550Szbb#define IPG_DATA_DEF 0x1e 1891289550Szbb 1892289550Szbb/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1893289550Szbb#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1894289550Szbb#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1895289550Szbb#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1896289550Szbb#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1897289550Szbb#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1898289550Szbb 1899289550Szbb#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1900289550Szbb#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1901289550Szbb 1902289551Szbb/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1903297450Szbb#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1904297450Szbb#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1905289550Szbb 1906289551Szbb/* Receive Frame Status Encoding */ 1907296039Szbb#define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1908289551Szbb#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 1909289551Szbb#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 1910289551Szbb#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 1911296039Szbb#define GMR_FS_MC BIT_10 /* Multicast Packet */ 1912289551Szbb#define GMR_FS_BC BIT_9 /* Broadcast Packet */ 1913289550Szbb#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 1914289551Szbb#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 1915289551Szbb#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 1916289551Szbb#define GMR_FS_MII_ERR BIT_5 /* MII Error */ 1917289551Szbb#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1918289551Szbb#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1919289551Szbb#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1920289551Szbb#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1921289551Szbb 1922297450Szbb#define GMR_FS_LEN_SHIFT 16 1923297450Szbb 1924289551Szbb#define GMR_FS_ANY_ERR ( \ 1925297450Szbb GMR_FS_RX_FF_OV | \ 1926297450Szbb GMR_FS_CRC_ERR | \ 1927289551Szbb GMR_FS_FRAGMENT | \ 1928289550Szbb GMR_FS_LONG_ERR | \ 1929289550Szbb GMR_FS_MII_ERR | \ 1930289551Szbb GMR_FS_BAD_FC | \ 1931296039Szbb GMR_FS_GOOD_FC | \ 1932297450Szbb GMR_FS_UN_SIZE | \ 1933296039Szbb GMR_FS_JABBER) 1934296039Szbb 1935296039Szbb/* Rx GMAC FIFO Flush Mask (default) */ 1936289550Szbb#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 1937289551Szbb 1938289551Szbb/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 1939289551Szbb 1940289551Szbb/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 1941289551Szbb/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 1942289550Szbb/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 1943289550Szbb/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 1944289550Szbb/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 1945289550Szbb/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1946297450Szbb/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1947297450Szbb/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 1948296030Szbb/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 1949297450Szbb/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 1950296030Szbb/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 1951297450Szbb/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1952297450Szbb/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1953297450Szbb/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1954297450Szbb 1955296030Szbb/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1956296030Szbb#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 1957289550Szbb#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1958289550Szbb#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1959289551Szbb#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1960289550Szbb#define GMF_RX_MACSEC_FLUSH_ON BIT_23 1961289551Szbb#define GMF_RX_MACSEC_FLUSH_OFF BIT_22 1962289551Szbb#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 1963289550Szbb#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 1964289550Szbb#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 1965289550Szbb#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 1966289551Szbb#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1967289550Szbb#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1968289551Szbb#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1969289551Szbb#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 1970289550Szbb#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1971289551Szbb#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1972289551Szbb#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1973289551Szbb#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1974289550Szbb#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1975289550Szbb#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1976289551Szbb#define GMF_OPER_ON BIT_3 /* Operational Mode On */ 1977289551Szbb#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1978289550Szbb#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1979289551Szbb#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1980289551Szbb 1981289550Szbb/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1982289551Szbb#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1983289550Szbb#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 1984289550Szbb#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1985289550Szbb#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1986289551Szbb#define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1987289551Szbb#define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 1988289551Szbb#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1989289550Szbb#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1990289550Szbb#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1991289550Szbb /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1992289551Szbb#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1993289551Szbb#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1994289551Szbb#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1995289551Szbb /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1996289550Szbb 1997289551Szbb#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1998289551Szbb#define GMF_TX_CTRL_DEF GMF_OPER_ON 1999289551Szbb 2000289550Szbb#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 2001289551Szbb#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 2002289551Szbb 2003289550Szbb/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 2004289550Szbb#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 2005289550Szbb#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 2006289551Szbb#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 2007289550Szbb 2008289551Szbb/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 2009289551Szbb#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 2010289551Szbb#define PC_POLL_RQ BIT_4 /* Poll Request Start */ 2011289551Szbb#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 2012289551Szbb#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 2013289550Szbb#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 2014289550Szbb#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 2015289551Szbb 2016289551Szbb/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 2017289551Szbb/* This register is used by the host driver software */ 2018289550Szbb#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 2019289550Szbb#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 2020289550Szbb#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 2021289550Szbb#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 2022289551Szbb#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 2023289551Szbb 2024289551Szbb#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 2025289551Szbb#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 2026289551Szbb 2027296030Szbb/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2028296030Szbb#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2029296030Szbb#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2030296030Szbb#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2031297389Szbb#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2032296030Szbb#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2033296030Szbb#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2034296030Szbb#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2035297389Szbb#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2036297389Szbb#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2037297389Szbb#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2038297389Szbb#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2039296030Szbb#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2040296030Szbb#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 2041297389Szbb#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 2042297389Szbb /* Microcontroller State */ 2043297389Szbb#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2044297389Szbb#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2045297389Szbb#define Y2_ASF_HCU_CCSR_ASF_RESET 0 2046297389Szbb#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2047297389Szbb#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2048296030Szbb 2049296030Szbb/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 2050289551Szbb/* This register is used by the ASF firmware */ 2051289551Szbb#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 2052289551Szbb#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 2053289550Szbb 2054289550Szbb/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2055289550Szbb#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 2056289551Szbb#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 2057289551Szbb#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 2058289550Szbb#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 2059289551Szbb#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 2060289550Szbb 2061289550Szbb/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2062289550Szbb#define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2063289550Szbb#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2064289550Szbb#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2065289551Szbb#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2066289550Szbb#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2067289550Szbb#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2068289551Szbb#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2069289550Szbb#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 2070289550Szbb#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 2071289551Szbb#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 2072289550Szbb#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 2073289550Szbb#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 2074289551Szbb#define GMC_PAUSE_ON BIT_3 /* Pause On */ 2075289550Szbb#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 2076289550Szbb#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 2077289551Szbb#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 2078289550Szbb 2079289550Szbb/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2080289551Szbb#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 2081289550Szbb#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 2082289550Szbb#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 2083289551Szbb#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 2084289550Szbb#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 2085289550Szbb#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 2086289551Szbb#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 2087289550Szbb#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 2088289550Szbb#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 2089289550Szbb#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 2090289550Szbb#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 2091289550Szbb#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 2092289550Szbb#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 2093289550Szbb#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 2094289550Szbb#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 2095289551Szbb#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 2096289551Szbb#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 2097289550Szbb#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 2098289551Szbb#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 2099289550Szbb#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 2100289550Szbb#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 2101289550Szbb#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 2102289551Szbb#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 2103289550Szbb 2104289550Szbb/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2105289551Szbb/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2106289550Szbb#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 2107289550Szbb#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 2108289551Szbb#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 2109289550Szbb#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 2110289550Szbb#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 2111289551Szbb#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 2112289550Szbb 2113289550Szbb#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 2114289551Szbb 2115289550Szbb/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2116289550Szbb#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 2117289551Szbb#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 2118289550Szbb 2119289550Szbb#define MSK_PORT_A 0 2120289551Szbb#define MSK_PORT_B 1 2121289550Szbb 2122289550Szbb/* Register access macros */ 2123289551Szbb#define CSR_WRITE_4(sc, reg, val) \ 2124289550Szbb bus_write_4((sc)->msk_res[0], (reg), (val)) 2125289550Szbb#define CSR_WRITE_2(sc, reg, val) \ 2126289550Szbb bus_write_2((sc)->msk_res[0], (reg), (val)) 2127289550Szbb#define CSR_WRITE_1(sc, reg, val) \ 2128289550Szbb bus_write_1((sc)->msk_res[0], (reg), (val)) 2129289550Szbb 2130289550Szbb#define CSR_READ_4(sc, reg) \ 2131289550Szbb bus_read_4((sc)->msk_res[0], (reg)) 2132289551Szbb#define CSR_READ_2(sc, reg) \ 2133289551Szbb bus_read_2((sc)->msk_res[0], (reg)) 2134289550Szbb#define CSR_READ_1(sc, reg) \ 2135289551Szbb bus_read_1((sc)->msk_res[0], (reg)) 2136289550Szbb 2137289550Szbb#define CSR_PCI_WRITE_4(sc, reg, val) \ 2138289550Szbb bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2139289551Szbb#define CSR_PCI_WRITE_2(sc, reg, val) \ 2140289550Szbb bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2141289550Szbb#define CSR_PCI_WRITE_1(sc, reg, val) \ 2142289551Szbb bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2143289550Szbb 2144289550Szbb#define CSR_PCI_READ_4(sc, reg) \ 2145289551Szbb bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2146289550Szbb#define CSR_PCI_READ_2(sc, reg) \ 2147289550Szbb bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2148289551Szbb#define CSR_PCI_READ_1(sc, reg) \ 2149289550Szbb bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2150289550Szbb 2151289551Szbb#define MSK_IF_READ_4(sc_if, reg) \ 2152289550Szbb CSR_READ_4((sc_if)->msk_softc, (reg)) 2153289550Szbb#define MSK_IF_READ_2(sc_if, reg) \ 2154289551Szbb CSR_READ_2((sc_if)->msk_softc, (reg)) 2155289550Szbb#define MSK_IF_READ_1(sc_if, reg) \ 2156289550Szbb CSR_READ_1((sc_if)->msk_softc, (reg)) 2157289551Szbb 2158289550Szbb#define MSK_IF_WRITE_4(sc_if, reg, val) \ 2159289550Szbb CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2160289551Szbb#define MSK_IF_WRITE_2(sc_if, reg, val) \ 2161289550Szbb CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2162289550Szbb#define MSK_IF_WRITE_1(sc_if, reg, val) \ 2163289550Szbb CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2164289550Szbb 2165289550Szbb#define GMAC_REG(port, reg) \ 2166289550Szbb ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2167289550Szbb#define GMAC_WRITE_2(sc, port, reg, val) \ 2168289550Szbb CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2169289551Szbb#define GMAC_READ_2(sc, port, reg) \ 2170289551Szbb CSR_READ_2((sc), GMAC_REG((port), (reg))) 2171289550Szbb 2172289551Szbb/* GPHY address (bits 15..11 of SMI control reg) */ 2173289551Szbb#define PHY_ADDR_MARV 0 2174289550Szbb 2175289550Szbb#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2176289550Szbb#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2177289550Szbb 2178289550Szbb#define MSK_RING_ALIGN 32768 2179289551Szbb#define MSK_STAT_ALIGN 32768 2180289550Szbb 2181289550Szbb/* Rx descriptor data structure */ 2182289551Szbbstruct msk_rx_desc { 2183289550Szbb uint32_t msk_addr; 2184289550Szbb uint32_t msk_control; 2185289551Szbb}; 2186289550Szbb 2187289550Szbb/* Tx descriptor data structure */ 2188289550Szbbstruct msk_tx_desc { 2189289550Szbb uint32_t msk_addr; 2190289550Szbb uint32_t msk_control; 2191289550Szbb}; 2192289550Szbb 2193289550Szbb/* Status descriptor data structure */ 2194289550Szbbstruct msk_stat_desc { 2195289550Szbb uint32_t msk_status; 2196289550Szbb uint32_t msk_control; 2197289550Szbb}; 2198289550Szbb 2199289550Szbb/* mask and shift value to get Tx async queue status for port 1 */ 2200289551Szbb#define STLE_TXA1_MSKL 0x00000fff 2201289550Szbb#define STLE_TXA1_SHIFTL 0 2202289550Szbb 2203289550Szbb/* mask and shift value to get Tx sync queue status for port 1 */ 2204289550Szbb#define STLE_TXS1_MSKL 0x00fff000 2205289550Szbb#define STLE_TXS1_SHIFTL 12 2206289550Szbb 2207289550Szbb/* mask and shift value to get Tx async queue status for port 2 */ 2208289551Szbb#define STLE_TXA2_MSKL 0xff000000 2209289551Szbb#define STLE_TXA2_SHIFTL 24 2210289550Szbb#define STLE_TXA2_MSKH 0x000f 2211289550Szbb/* this one shifts up */ 2212289550Szbb#define STLE_TXA2_SHIFTH 8 2213289550Szbb 2214289550Szbb/* mask and shift value to get Tx sync queue status for port 2 */ 2215289550Szbb#define STLE_TXS2_MSKL 0x00000000 2216289550Szbb#define STLE_TXS2_SHIFTL 0 2217289550Szbb#define STLE_TXS2_MSKH 0xfff0 2218289550Szbb#define STLE_TXS2_SHIFTH 4 2219289550Szbb 2220289550Szbb/* YUKON-2 bit values */ 2221289550Szbb#define HW_OWNER 0x80000000 2222289551Szbb#define SW_OWNER 0x00000000 2223289551Szbb 2224289550Szbb#define PU_PUTIDX_VALID 0x10000000 2225289550Szbb 2226289550Szbb/* YUKON-2 Control flags */ 2227289550Szbb#define UDPTCP 0x00010000 2228289550Szbb#define CALSUM 0x00020000 2229289550Szbb#define WR_SUM 0x00040000 2230289550Szbb#define INIT_SUM 0x00080000 2231289550Szbb#define LOCK_SUM 0x00100000 2232289550Szbb#define INS_VLAN 0x00200000 2233289550Szbb#define FRC_STAT 0x00400000 2234289550Szbb#define EOP 0x00800000 2235289550Szbb 2236289550Szbb#define TX_LOCK 0x01000000 2237289551Szbb#define BUF_SEND 0x02000000 2238289551Szbb#define PACKET_SEND 0x04000000 2239289551Szbb 2240289550Szbb#define NO_WARNING 0x40000000 2241289550Szbb#define NO_UPDATE 0x80000000 2242289550Szbb 2243289550Szbb/* YUKON-2 Rx/Tx opcodes defines */ 2244289550Szbb#define OP_TCPWRITE 0x11000000 2245289550Szbb#define OP_TCPSTART 0x12000000 2246289551Szbb#define OP_TCPINIT 0x14000000 2247289550Szbb#define OP_TCPLCK 0x18000000 2248289550Szbb#define OP_TCPCHKSUM OP_TCPSTART 2249289550Szbb#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2250289550Szbb#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2251289550Szbb#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2252289550Szbb#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2253289550Szbb#define OP_ADDR64 0x21000000 2254289550Szbb#define OP_VLAN 0x22000000 2255289550Szbb#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2256289550Szbb#define OP_LRGLEN 0x24000000 2257289550Szbb#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2258289550Szbb#define OP_MSS 0x28000000 2259289550Szbb#define OP_MSSVLAN (OP_MSS | OP_VLAN) 2260289550Szbb#define OP_BUFFER 0x40000000 2261289550Szbb#define OP_PACKET 0x41000000 2262289550Szbb#define OP_LARGESEND 0x43000000 2263289550Szbb 2264289550Szbb/* YUKON-2 STATUS opcodes defines */ 2265289550Szbb#define OP_RXSTAT 0x60000000 2266289550Szbb#define OP_RXTIMESTAMP 0x61000000 2267289550Szbb#define OP_RXVLAN 0x62000000 2268289550Szbb#define OP_RXCHKS 0x64000000 2269289550Szbb#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2270289550Szbb#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2271289550Szbb#define OP_RSS_HASH 0x65000000 2272289550Szbb#define OP_TXINDEXLE 0x68000000 2273289550Szbb 2274289550Szbb/* YUKON-2 SPECIAL opcodes defines */ 2275289550Szbb#define OP_PUTIDX 0x70000000 2276289550Szbb 2277289550Szbb#define STLE_OP_MASK 0xff000000 2278289550Szbb#define STLE_CSS_MASK 0x00ff0000 2279289550Szbb#define STLE_LEN_MASK 0x0000ffff 2280289550Szbb 2281289550Szbb/* CSS defined in status LE(valid for descriptor V2 format). */ 2282289550Szbb#define CSS_TCPUDP_CSUM_OK 0x00800000 2283289550Szbb#define CSS_UDP 0x00400000 2284289550Szbb#define CSS_TCP 0x00200000 2285289550Szbb#define CSS_IPFRAG 0x00100000 2286289550Szbb#define CSS_IPV6 0x00080000 2287289550Szbb#define CSS_IPV4_CSUM_OK 0x00040000 2288289550Szbb#define CSS_IPV4 0x00020000 2289289550Szbb#define CSS_PORT 0x00010000 2290289550Szbb 2291289550Szbb/* Descriptor Bit Definition */ 2292289550Szbb/* TxCtrl Transmit Buffer Control Field */ 2293289550Szbb/* RxCtrl Receive Buffer Control Field */ 2294289550Szbb#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2295289550Szbb#define BMU_STF BIT_30 /* Start of Frame */ 2296289550Szbb#define BMU_EOF BIT_29 /* End of Frame */ 2297289550Szbb#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2298289550Szbb#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 2299289550Szbb/* TxCtrl specific bits */ 2300289550Szbb#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2301289550Szbb#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 2302289550Szbb#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2303289550Szbb/* RxCtrl specific bits */ 2304289550Szbb#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2305289550Szbb#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2306289550Szbb#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2307289550Szbb /* Bit 23..16: BMU Check Opcodes */ 2308289550Szbb#define BMU_CHECK (0x55<<16) /* Default BMU check */ 2309289550Szbb#define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 2310289550Szbb#define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2311289550Szbb#define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2312289550Szbb 2313289550Szbb/* 2314289550Szbb * Controller requires an additional LE op code for 64bit DMA operation. 2315289550Szbb * Driver uses fixed number of RX buffers such that this limitation 2316289550Szbb * reduces number of available RX buffers with 64bit DMA so double 2317289550Szbb * number of RX buffers on platforms that support 64bit DMA. For TX 2318289550Szbb * side, controller requires an additional OP_ADDR64 op code if a TX 2319289550Szbb * buffer uses different high address value than previously used one. 2320289550Szbb * Driver monitors high DMA address change in TX and inserts an 2321289550Szbb * OP_ADDR64 op code if the high DMA address is changed. Driver 2322289550Szbb * allocates 50% more total TX buffers on platforms that support 64bit 2323289550Szbb * DMA. 2324289551Szbb */ 2325289550Szbb#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2326289550Szbb#define MSK_64BIT_DMA 2327289550Szbb#define MSK_TX_RING_CNT 384 2328289551Szbb#define MSK_RX_RING_CNT 512 2329289551Szbb#else 2330289551Szbb#undef MSK_64BIT_DMA 2331289550Szbb#define MSK_TX_RING_CNT 256 2332289550Szbb#define MSK_RX_RING_CNT 256 2333289550Szbb#endif 2334289550Szbb#define MSK_RX_BUF_ALIGN 8 2335289550Szbb#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2336289550Szbb#define MSK_MAXTXSEGS 35 2337289551Szbb#define MSK_TSO_MAXSGSIZE 4096 2338289550Szbb#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 2339289550Szbb 2340289550Szbb/* 2341289550Szbb * It seems that the hardware requires extra descriptors(LEs) to offload 2342289550Szbb * TCP/UDP checksum, VLAN hardware tag insertion and TSO. 2343289550Szbb * 2344289550Szbb * 1 descriptor for TCP/UDP checksum offload. 2345289550Szbb * 1 descriptor VLAN hardware tag insertion. 2346289550Szbb * 1 descriptor for TSO(TCP Segmentation Offload) 2347289550Szbb * 1 descriptor for each 64bits DMA transfers 2348289550Szbb */ 2349289550Szbb#ifdef MSK_64BIT_DMA 2350289550Szbb#define MSK_RESERVED_TX_DESC_CNT (MSK_MAXTXSEGS + 3) 2351289550Szbb#else 2352289550Szbb#define MSK_RESERVED_TX_DESC_CNT 3 2353289550Szbb#endif 2354289550Szbb 2355289550Szbb#define MSK_JUMBO_FRAMELEN 9022 2356289550Szbb#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2357289550Szbb#define MSK_MAX_FRAMELEN \ 2358289550Szbb (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2359289550Szbb#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2360289550Szbb 2361289550Szbbstruct msk_txdesc { 2362289550Szbb struct mbuf *tx_m; 2363289550Szbb bus_dmamap_t tx_dmamap; 2364289550Szbb struct msk_tx_desc *tx_le; 2365289550Szbb}; 2366289550Szbb 2367289550Szbbstruct msk_rxdesc { 2368289550Szbb struct mbuf *rx_m; 2369289550Szbb bus_dmamap_t rx_dmamap; 2370289550Szbb struct msk_rx_desc *rx_le; 2371289550Szbb}; 2372289550Szbb 2373289550Szbbstruct msk_chain_data { 2374289550Szbb bus_dma_tag_t msk_parent_tag; 2375289550Szbb bus_dma_tag_t msk_tx_tag; 2376289550Szbb struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2377289550Szbb bus_dma_tag_t msk_rx_tag; 2378289550Szbb struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2379289551Szbb bus_dma_tag_t msk_tx_ring_tag; 2380289550Szbb bus_dma_tag_t msk_rx_ring_tag; 2381 bus_dmamap_t msk_tx_ring_map; 2382 bus_dmamap_t msk_rx_ring_map; 2383 bus_dmamap_t msk_rx_sparemap; 2384 bus_dma_tag_t msk_jumbo_rx_tag; 2385 struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2386 bus_dma_tag_t msk_jumbo_rx_ring_tag; 2387 bus_dmamap_t msk_jumbo_rx_ring_map; 2388 bus_dmamap_t msk_jumbo_rx_sparemap; 2389 uint16_t msk_tso_mtu; 2390 uint32_t msk_last_csum; 2391 uint32_t msk_tx_high_addr; 2392 int msk_tx_prod; 2393 int msk_tx_cons; 2394 int msk_tx_cnt; 2395 int msk_tx_put; 2396 int msk_rx_cons; 2397 int msk_rx_prod; 2398 int msk_rx_putwm; 2399}; 2400 2401struct msk_ring_data { 2402 struct msk_tx_desc *msk_tx_ring; 2403 bus_addr_t msk_tx_ring_paddr; 2404 struct msk_rx_desc *msk_rx_ring; 2405 bus_addr_t msk_rx_ring_paddr; 2406 struct msk_rx_desc *msk_jumbo_rx_ring; 2407 bus_addr_t msk_jumbo_rx_ring_paddr; 2408}; 2409 2410#define MSK_TX_RING_ADDR(sc, i) \ 2411 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2412#define MSK_RX_RING_ADDR(sc, i) \ 2413 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2414#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2415 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2416 2417#define MSK_TX_RING_SZ \ 2418 (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2419#define MSK_RX_RING_SZ \ 2420 (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2421#define MSK_JUMBO_RX_RING_SZ \ 2422 (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2423 2424#define MSK_INC(x, y) (x) = (x + 1) % y 2425#ifdef MSK_64BIT_DMA 2426#define MSK_RX_INC(x, y) (x) = (x + 2) % y 2427#define MSK_RX_BUF_CNT (MSK_RX_RING_CNT / 2) 2428#define MSK_JUMBO_RX_BUF_CNT (MSK_JUMBO_RX_RING_CNT / 2) 2429#else 2430#define MSK_RX_INC(x, y) (x) = (x + 1) % y 2431#define MSK_RX_BUF_CNT MSK_RX_RING_CNT 2432#define MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT 2433#endif 2434 2435#define MSK_PCI_BUS 0 2436#define MSK_PCIX_BUS 1 2437#define MSK_PEX_BUS 2 2438 2439#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2440#define MSK_PROC_MIN 30 2441#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2442 2443#define MSK_INT_HOLDOFF_DEFAULT 100 2444 2445#define MSK_TX_TIMEOUT 5 2446#define MSK_PUT_WM 10 2447 2448struct msk_mii_data { 2449 int port; 2450 uint32_t pmd; 2451 int mii_flags; 2452}; 2453 2454/* Forward decl. */ 2455struct msk_if_softc; 2456 2457struct msk_hw_stats { 2458 /* Rx stats. */ 2459 uint32_t rx_ucast_frames; 2460 uint32_t rx_bcast_frames; 2461 uint32_t rx_pause_frames; 2462 uint32_t rx_mcast_frames; 2463 uint32_t rx_crc_errs; 2464 uint32_t rx_spare1; 2465 uint64_t rx_good_octets; 2466 uint64_t rx_bad_octets; 2467 uint32_t rx_runts; 2468 uint32_t rx_runt_errs; 2469 uint32_t rx_pkts_64; 2470 uint32_t rx_pkts_65_127; 2471 uint32_t rx_pkts_128_255; 2472 uint32_t rx_pkts_256_511; 2473 uint32_t rx_pkts_512_1023; 2474 uint32_t rx_pkts_1024_1518; 2475 uint32_t rx_pkts_1519_max; 2476 uint32_t rx_pkts_too_long; 2477 uint32_t rx_pkts_jabbers; 2478 uint32_t rx_spare2; 2479 uint32_t rx_fifo_oflows; 2480 uint32_t rx_spare3; 2481 /* Tx stats. */ 2482 uint32_t tx_ucast_frames; 2483 uint32_t tx_bcast_frames; 2484 uint32_t tx_pause_frames; 2485 uint32_t tx_mcast_frames; 2486 uint64_t tx_octets; 2487 uint32_t tx_pkts_64; 2488 uint32_t tx_pkts_65_127; 2489 uint32_t tx_pkts_128_255; 2490 uint32_t tx_pkts_256_511; 2491 uint32_t tx_pkts_512_1023; 2492 uint32_t tx_pkts_1024_1518; 2493 uint32_t tx_pkts_1519_max; 2494 uint32_t tx_spare1; 2495 uint32_t tx_colls; 2496 uint32_t tx_late_colls; 2497 uint32_t tx_excess_colls; 2498 uint32_t tx_multi_colls; 2499 uint32_t tx_single_colls; 2500 uint32_t tx_underflows; 2501}; 2502 2503/* Softc for the Marvell Yukon II controller. */ 2504struct msk_softc { 2505 struct resource *msk_res[1]; /* I/O resource */ 2506 struct resource_spec *msk_res_spec; 2507 struct resource *msk_irq[1]; /* IRQ resources */ 2508 struct resource_spec *msk_irq_spec; 2509 void *msk_intrhand; /* irq handler handle */ 2510 device_t msk_dev; 2511 uint8_t msk_hw_id; 2512 uint8_t msk_hw_rev; 2513 uint8_t msk_bustype; 2514 uint8_t msk_num_port; 2515 int msk_expcap; 2516 int msk_pcixcap; 2517 int msk_ramsize; /* amount of SRAM on NIC */ 2518 uint32_t msk_pmd; /* physical media type */ 2519 uint32_t msk_intrmask; 2520 uint32_t msk_intrhwemask; 2521 uint32_t msk_pflags; 2522 int msk_clock; 2523 struct msk_if_softc *msk_if[2]; 2524 device_t msk_devs[2]; 2525 int msk_txqsize; 2526 int msk_rxqsize; 2527 int msk_txqstart[2]; 2528 int msk_txqend[2]; 2529 int msk_rxqstart[2]; 2530 int msk_rxqend[2]; 2531 bus_dma_tag_t msk_stat_tag; 2532 bus_dmamap_t msk_stat_map; 2533 struct msk_stat_desc *msk_stat_ring; 2534 bus_addr_t msk_stat_ring_paddr; 2535 int msk_int_holdoff; 2536 int msk_process_limit; 2537 int msk_stat_cons; 2538 int msk_stat_count; 2539 struct mtx msk_mtx; 2540}; 2541 2542#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 2543#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2544#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2545#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2546#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2547#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2548 2549#define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 2550 2551/* Softc for each logical interface. */ 2552struct msk_if_softc { 2553 struct ifnet *msk_ifp; /* interface info */ 2554 device_t msk_miibus; 2555 device_t msk_if_dev; 2556 int32_t msk_port; /* port # on controller */ 2557 int msk_framesize; 2558 int msk_phytype; 2559 int msk_phyaddr; 2560 uint32_t msk_flags; 2561#define MSK_FLAG_MSI 0x0001 2562#define MSK_FLAG_FASTETHER 0x0004 2563#define MSK_FLAG_JUMBO 0x0008 2564#define MSK_FLAG_JUMBO_NOCSUM 0x0010 2565#define MSK_FLAG_RAMBUF 0x0020 2566#define MSK_FLAG_DESCV2 0x0040 2567#define MSK_FLAG_AUTOTX_CSUM 0x0080 2568#define MSK_FLAG_NOHWVLAN 0x0100 2569#define MSK_FLAG_NORXCHK 0x0200 2570#define MSK_FLAG_NORX_CSUM 0x0400 2571#define MSK_FLAG_SUSPEND 0x2000 2572#define MSK_FLAG_DETACH 0x4000 2573#define MSK_FLAG_LINK 0x8000 2574 struct callout msk_tick_ch; 2575 int msk_watchdog_timer; 2576 uint32_t msk_txq; /* Tx. Async Queue offset */ 2577 uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2578 uint32_t msk_rxq; /* Rx. Qeueue offset */ 2579 struct msk_chain_data msk_cdata; 2580 struct msk_ring_data msk_rdata; 2581 struct msk_softc *msk_softc; /* parent controller */ 2582 struct msk_hw_stats msk_stats; 2583 int msk_if_flags; 2584 uint16_t msk_vtag; /* VLAN tag id. */ 2585 uint32_t msk_csum; 2586}; 2587 2588#define MSK_TIMEOUT 1000 2589#define MSK_PHY_POWERUP 1 2590#define MSK_PHY_POWERDOWN 0 2591