if_mskreg.h revision 165138
1/****************************************************************************** 2 * 3 * Name: skgehw.h 4 * Project: Gigabit Ethernet Adapters, Common Modules 5 * Version: $Revision: 2.49 $ 6 * Date: $Date: 2005/01/20 13:01:35 $ 7 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 8 * 9 ******************************************************************************/ 10 11/****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 ******************************************************************************/ 47 48/*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 80/*- 81 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 82 * 83 * Permission to use, copy, modify, and distribute this software for any 84 * purpose with or without fee is hereby granted, provided that the above 85 * copyright notice and this permission notice appear in all copies. 86 * 87 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 88 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 89 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 90 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 91 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 92 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 93 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 94 */ 95 96/*$FreeBSD: head/sys/dev/msk/if_mskreg.h 165138 2006-12-13 02:30:11Z yongari $*/ 97 98/* 99 * SysKonnect PCI vendor ID 100 */ 101#define VENDORID_SK 0x1148 102 103/* 104 * Marvell PCI vendor ID 105 */ 106#define VENDORID_MARVELL 0x11AB 107 108/* 109 * D-Link PCI vendor ID 110 */ 111#define VENDORID_DLINK 0x1186 112 113/* 114 * SysKonnect ethernet device IDs 115 */ 116#define DEVICEID_SK_YUKON2 0x9000 117#define DEVICEID_SK_YUKON2_EXPR 0x9e00 118 119/* 120 * Marvell gigabit ethernet device IDs 121 */ 122#define DEVICEID_MRVL_8021CU 0x4340 123#define DEVICEID_MRVL_8022CU 0x4341 124#define DEVICEID_MRVL_8061CU 0x4342 125#define DEVICEID_MRVL_8062CU 0x4343 126#define DEVICEID_MRVL_8021X 0x4344 127#define DEVICEID_MRVL_8022X 0x4345 128#define DEVICEID_MRVL_8061X 0x4346 129#define DEVICEID_MRVL_8062X 0x4347 130#define DEVICEID_MRVL_8035 0x4350 131#define DEVICEID_MRVL_8036 0x4351 132#define DEVICEID_MRVL_8038 0x4352 133#define DEVICEID_MRVL_4360 0x4360 134#define DEVICEID_MRVL_4361 0x4361 135#define DEVICEID_MRVL_4362 0x4362 136#define DEVICEID_MRVL_4363 0x4363 137#define DEVICEID_MRVL_4364 0x4364 138 139/* 140 * D-Link gigabit ethernet device ID 141 */ 142#define DEVICEID_DLINK_DGE550SX 0x4001 143#define DEVICEID_DLINK_DGE560T 0x4b00 144 145#define BIT_31 (1 << 31) 146#define BIT_30 (1 << 30) 147#define BIT_29 (1 << 29) 148#define BIT_28 (1 << 28) 149#define BIT_27 (1 << 27) 150#define BIT_26 (1 << 26) 151#define BIT_25 (1 << 25) 152#define BIT_24 (1 << 24) 153#define BIT_23 (1 << 23) 154#define BIT_22 (1 << 22) 155#define BIT_21 (1 << 21) 156#define BIT_20 (1 << 20) 157#define BIT_19 (1 << 19) 158#define BIT_18 (1 << 18) 159#define BIT_17 (1 << 17) 160#define BIT_16 (1 << 16) 161#define BIT_15 (1 << 15) 162#define BIT_14 (1 << 14) 163#define BIT_13 (1 << 13) 164#define BIT_12 (1 << 12) 165#define BIT_11 (1 << 11) 166#define BIT_10 (1 << 10) 167#define BIT_9 (1 << 9) 168#define BIT_8 (1 << 8) 169#define BIT_7 (1 << 7) 170#define BIT_6 (1 << 6) 171#define BIT_5 (1 << 5) 172#define BIT_4 (1 << 4) 173#define BIT_3 (1 << 3) 174#define BIT_2 (1 << 2) 175#define BIT_1 (1 << 1) 176#define BIT_0 (1 << 0) 177 178#define SHIFT31(x) ((x) << 31) 179#define SHIFT30(x) ((x) << 30) 180#define SHIFT29(x) ((x) << 29) 181#define SHIFT28(x) ((x) << 28) 182#define SHIFT27(x) ((x) << 27) 183#define SHIFT26(x) ((x) << 26) 184#define SHIFT25(x) ((x) << 25) 185#define SHIFT24(x) ((x) << 24) 186#define SHIFT23(x) ((x) << 23) 187#define SHIFT22(x) ((x) << 22) 188#define SHIFT21(x) ((x) << 21) 189#define SHIFT20(x) ((x) << 20) 190#define SHIFT19(x) ((x) << 19) 191#define SHIFT18(x) ((x) << 18) 192#define SHIFT17(x) ((x) << 17) 193#define SHIFT16(x) ((x) << 16) 194#define SHIFT15(x) ((x) << 15) 195#define SHIFT14(x) ((x) << 14) 196#define SHIFT13(x) ((x) << 13) 197#define SHIFT12(x) ((x) << 12) 198#define SHIFT11(x) ((x) << 11) 199#define SHIFT10(x) ((x) << 10) 200#define SHIFT9(x) ((x) << 9) 201#define SHIFT8(x) ((x) << 8) 202#define SHIFT7(x) ((x) << 7) 203#define SHIFT6(x) ((x) << 6) 204#define SHIFT5(x) ((x) << 5) 205#define SHIFT4(x) ((x) << 4) 206#define SHIFT3(x) ((x) << 3) 207#define SHIFT2(x) ((x) << 2) 208#define SHIFT1(x) ((x) << 1) 209#define SHIFT0(x) ((x) << 0) 210 211/* 212 * PCI Configuration Space header 213 */ 214#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 215#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 216#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 217#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 218#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 219#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 220#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 221#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 222 223/* PCI Express Capability */ 224#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 225#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 226#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 227#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 228#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 229#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 230#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 231#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 232#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 233 234/* PCI Express Extended Capabilities */ 235#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 236#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 237#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 238#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 239#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 240#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 241#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 242#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 243 244/* PCI_OUR_REG_1 32 bit Our Register 1 */ 245#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 246#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 247#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 248#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 249#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 250#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 251#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 252#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 253#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 254 /* 1 = Map Flash to memory */ 255 /* 0 = Disable addr. dec */ 256#define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 257#define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 258#define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 259#define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 260#define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 261#define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 262#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 263#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 264#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 265#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 266#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 267#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 268#define PCI_BURST_DIS BIT_9 /* Burst Disable */ 269#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 270#define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 271#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 272#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 273 274/* PCI_OUR_REG_2 32 bit Our Register 2 */ 275#define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 276#define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 277#define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 278 /* Bit 13..12: reserved */ 279#define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 280#define PCI_PATCH_DIR_3 BIT_11 281#define PCI_PATCH_DIR_2 BIT_10 282#define PCI_PATCH_DIR_1 BIT_9 283#define PCI_PATCH_DIR_0 BIT_8 284#define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 285#define PCI_EXT_PATCH_3 BIT_7 286#define PCI_EXT_PATCH_2 BIT_6 287#define PCI_EXT_PATCH_1 BIT_5 288#define PCI_EXT_PATCH_0 BIT_4 289#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 290#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 291#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 292 293/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 294#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 295#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 296#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 297#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 298#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 299#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 300#define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 301#define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 302 303#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 304/* possible values for the speed field of the register */ 305#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 306#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 307#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 308#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 309 310/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 311#define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 312#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 313#define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 314#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 315#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 316#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 317#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 318#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 319#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 320#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 321 322/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 323#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 324#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 325#define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 326#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 327#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 328#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 329#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 330#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 331#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 332#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 333#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 334 335#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 336 337/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 338#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 339#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 340#define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 341#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 342#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 343 344/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 345#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 346#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 347#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 348#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 349#define PEX_COMP_TO BIT_14 /* Completion Timeout */ 350#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 351#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 352#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 353 354#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 355 356/* Control Register File (Address Map) */ 357 358/* 359 * Bank 0 360 */ 361#define B0_RAP 0x0000 /* 8 bit Register Address Port */ 362#define B0_CTST 0x0004 /* 16 bit Control/Status register */ 363#define B0_LED 0x0006 /* 8 Bit LED register */ 364#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 365#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 366#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 367#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 368#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 369#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 370 371/* Special ISR registers (Yukon-2 only) */ 372#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 373#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 374#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 375#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 376#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 377 378/* 379 * Bank 1 380 * - completely empty (this is the RAP Block window) 381 * Note: if RAP = 1 this page is reserved 382 */ 383 384/* 385 * Bank 2 386 */ 387/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 388#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 389#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 390#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 391#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 392#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 393#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 394#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 395#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 396#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 397#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 398#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 399#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 400#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 401#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 402#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 403#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 404#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 405#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 406#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 407#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 408#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 409#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 410#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 411#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 412#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 413#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 414#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 415#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 416#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 417 418#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 419#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 420 421/* 422 * Bank 3 423 */ 424/* RAM Random Registers */ 425#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 426#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 427#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 428 429#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 430 431/* RAM Interface Registers */ 432/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 433/* 434 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 435 * not usable in SW. Please notice these are NOT real timeouts, these are 436 * the number of qWords transferred continuously. 437 */ 438#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 439#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 440#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 441#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 442#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 443#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 444#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 445#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 446#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 447#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 448#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 449#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 450#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 451#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 452#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 453 454/* 455 * Bank 4 - 5 456 */ 457/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 458#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 459#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 460#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 461#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 462#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 463#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 464#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 465 466#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 467 468/* RSS key registers for Yukon-2 Family */ 469#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 470/* RSS key register offsets */ 471#define KEY_IDX_0 0 /* offset for location of KEY 0 */ 472#define KEY_IDX_1 4 /* offset for location of KEY 1 */ 473#define KEY_IDX_2 8 /* offset for location of KEY 2 */ 474#define KEY_IDX_3 12 /* offset for location of KEY 3 */ 475 /* 0x0280 - 0x0292: MAC 2 */ 476#define RSS_KEY_ADDR(Port, KeyIndex) \ 477 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 478 479/* 480 * Bank 8 - 15 481 */ 482/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 483#define B8_Q_REGS 0x0400 484 485/* Queue Register Offsets, use Q_ADDR() to access */ 486#define Q_D 0x00 /* 8*32 bit Current Descriptor */ 487#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 488#define Q_DONE 0x24 /* 16 bit Done Index */ 489#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 490#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 491#define Q_BC 0x30 /* 32 bit Current Byte Counter */ 492#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 493#define Q_F 0x38 /* 32 bit Flag Register */ 494#define Q_T1 0x3c /* 32 bit Test Register 1 */ 495#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 496#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 497#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 498#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 499#define Q_WM 0x40 /* 16 bit FIFO Watermark */ 500#define Q_AL 0x42 /* 8 bit FIFO Alignment */ 501#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 502#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 503#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 504#define Q_RL 0x4a /* 8 bit FIFO Read Level */ 505#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 506#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 507#define Q_WL 0x4e /* 8 bit FIFO Write Level */ 508#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 509 510#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 511 512/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 513#define Y2_B8_PREF_REGS 0x0450 514 515#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 516#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 517#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 518#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 519#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 520#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 521#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 522#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 523#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 524#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 525 526#define PREF_UNIT_MASK_IDX 0x0fff 527 528#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 529 530/* 531 * Bank 16 - 23 532 */ 533/* RAM Buffer Registers */ 534#define B16_RAM_REGS 0x0800 535 536/* RAM Buffer Register Offsets, use RB_ADDR() to access */ 537#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 538#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 539#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 540#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 541#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 542#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 543#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 544#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 545#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 546#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 547#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 548#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 549#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 550 551/* 552 * Bank 24 553 */ 554/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 555#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 556#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 557#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 558#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 559#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 560#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 561#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 562#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 563#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 564#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 565#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 566#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 567#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 568 569/* 570 * Bank 25 571 */ 572 /* 0x0c80 - 0x0cbf: MAC 2 */ 573 /* 0x0cc0 - 0x0cff: reserved */ 574 575/* 576 * Bank 26 577 */ 578/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 579#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 580#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 581#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 582#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 583#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 584#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 585#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 586#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 587#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 588#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 589 590/* 591 * Bank 27 592 */ 593 /* 0x0d80 - 0x0dbf: MAC 2 */ 594 /* 0x0daa - 0x0dff: reserved */ 595 596/* 597 * Bank 28 598 */ 599/* Descriptor Poll Timer Registers */ 600#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 601#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 602#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 603#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 604/* Time Stamp Timer Registers (YUKON only) */ 605#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 606#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 607#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 608/* Polling Unit Registers (Yukon-2 only) */ 609#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 610#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 611#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 612#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 613/* ASF Subsystem Registers (Yukon-2 only) */ 614#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 615#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 616#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 617#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 618#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 619#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 620#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 621#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 622#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 623 624/* 625 * Bank 29 626 */ 627 628/* Status BMU Registers (Yukon-2 only)*/ 629#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 630#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 631#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 632#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 633#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 634#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 635#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 636#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 637#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 638#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 639/* FIFO Control/Status Registers (Yukon-2 only)*/ 640#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 641#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 642#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 643#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 644#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 645#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 646#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 647/* Level and ISR Timer Registers (Yukon-2 only)*/ 648#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 649#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 650#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 651#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 652#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 653#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 654#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 655#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 656#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 657#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 658#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 659#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 660 661#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 662#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 663#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 664#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 665 666/* 667 * Bank 30 668 */ 669/* GMAC and GPHY Control Registers (YUKON only) */ 670#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 671#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 672#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 673#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 674#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 675 676/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 677 678#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 679 680#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 681#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 682#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 683#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 684#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 685#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 686#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 687#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 688 689/* WOL Pattern Length Registers (YUKON only) */ 690 691#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 692#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 693 694/* WOL Pattern Counter Registers (YUKON only) */ 695 696#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 697#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 698 699/* 700 * Bank 32 - 33 701 */ 702#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 703#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 704 705/* offset to configuration space on Yukon-2 */ 706#define Y2_CFG_SPC 0x1c00 707#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 708#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 709 710/* 711 * Control Register Bit Definitions: 712 */ 713/* B0_CTST 24 bit Control/Status register */ 714#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 715#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 716#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 717#define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 718#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 719#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 720#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 721#define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 722#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 723#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 724#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 725#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 726#define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 727#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 728#define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 729#define CS_MRST_SET BIT_2 /* Set Master Reset */ 730#define CS_RST_CLR BIT_1 /* Clear Software Reset */ 731#define CS_RST_SET BIT_0 /* Set Software Reset */ 732 733#define LED_STAT_ON BIT_1 /* Status LED On */ 734#define LED_STAT_OFF BIT_0 /* Status LED Off */ 735 736/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 737#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 738#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 739#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 740#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 741#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 742#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 743#define PC_VCC_ON BIT_1 /* Switch VCC On */ 744#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 745 746/* B0_ISRC 32 bit Interrupt Source Register */ 747/* B0_IMSK 32 bit Interrupt Mask Register */ 748/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 749/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 750/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 751/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 752/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 753/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 754#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 755#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 756#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 757#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 758#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 759#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 760#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 761#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 762#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 763#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 764#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 765#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 766#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 767#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 768#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 769#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 770#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 771#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 772 773#define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 774 775#define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 776 777#define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 778 779#define Y2_IS_PORT_A \ 780 (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 781#define Y2_IS_PORT_B \ 782 (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 783 784/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 785/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 786/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 787#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 788#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 789#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 790#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 791#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 792#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 793#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 794#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 795#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 796#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 797#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 798#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 799#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 800#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 801#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 802#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 803#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 804#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 805 806#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 807 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 808#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 809 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 810 811#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 812 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 813 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 814 815/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 816#define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 817#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 818#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 819 820/* B2_CHIP_ID 8 bit Chip Identification Number */ 821#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 822#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 823#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 824#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 825#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 826#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 827#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 828#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 829 830#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 831#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 832#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 833#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 834 835#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 836#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 837#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 838 839#define CHIP_REV_YU_EC_U_A0 0 840#define CHIP_REV_YU_EC_U_A1 1 841 842/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 843#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 844#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 845#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 846#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 847#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 848#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 849#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 850#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 851 852/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 853#define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 854#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 855#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 856 857#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 858#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 859 860/* B2_E_3 8 bit lower 4 bits used for HW self test result */ 861#define B2_E3_RES_MASK 0x0f 862 863/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 864/* Yukon-EC/FE */ 865#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 866#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 867/* Yukon-2 */ 868#define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 869#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 870#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 871#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 872#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 873#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 874 875/* B2_TI_CTRL 8 bit Timer control */ 876/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 877#define TIM_START BIT_2 /* Start Timer */ 878#define TIM_STOP BIT_1 /* Stop Timer */ 879#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 880 881/* B2_TI_TEST 8 Bit Timer Test */ 882/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 883/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 884#define TIM_T_ON BIT_2 /* Test mode on */ 885#define TIM_T_OFF BIT_1 /* Test mode off */ 886#define TIM_T_STEP BIT_0 /* Test step */ 887 888/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 889/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 890#define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 891 892/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 893#define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 894#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 895 896/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 897#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 898#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 899#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 900#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 901#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 902#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 903#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 904#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 905 906/* B2_I2C_CTRL 32 bit I2C HW Control Register */ 907#define I2C_FLAG BIT_31 /* Start read/write if WR */ 908#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 909#define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 910#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 911#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 912#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 913#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 914#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 915#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 916#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 917#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 918#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 919#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 920#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 921 922/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 923#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 924 925/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 926#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 927#define I2C_DATA BIT_1 /* I2C Data Port */ 928#define I2C_CLK BIT_0 /* I2C Clock Port */ 929 930/* I2C Address */ 931#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 932 933 934/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 935#define BSC_START BIT_1 /* Start Blink Source Counter */ 936#define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 937 938/* B2_BSC_STAT 8 bit Blink Source Counter Status */ 939#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 940 941/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 942#define BSC_T_ON BIT_2 /* Test mode on */ 943#define BSC_T_OFF BIT_1 /* Test mode off */ 944#define BSC_T_STEP BIT_0 /* Test step */ 945 946/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 947#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 948#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 949 950/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 951#define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 952 953/* RAM Interface Registers */ 954/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 955#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 956#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 957#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 958#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 959 960#define MSK_RI_TO_53 36 /* RAM interface timeout */ 961 962/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 963/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 964/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 965/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 966/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 967#define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 968 969/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 970#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 971#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 972#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 973#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 974#define TXA_START_RC BIT_3 /* Start sync Rate Control */ 975#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 976#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 977#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 978 979/* TXA_TEST 8 bit Tx Arbiter Test Register */ 980#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 981#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 982#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 983#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 984#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 985#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 986 987/* TXA_STAT 8 bit Tx Arbiter Status Register */ 988#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 989 990/* Q_BC 32 bit Current Byte Counter */ 991#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 992 993/* Rx BMU Control / Status Registers (Yukon-2) */ 994#define BMU_IDLE BIT_31 /* BMU Idle State */ 995#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 996#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 997#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 998#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 999#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1000#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1001#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1002#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 1003#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 1004#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 1005#define BMU_START BIT_8 /* Start Rx/Tx Queue */ 1006#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1007#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 1008#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 1009#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 1010#define BMU_OP_ON BIT_3 /* BMU Operational On */ 1011#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 1012#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 1013#define BMU_RST_SET BIT_0 /* Set BMU Reset */ 1014 1015#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 1016#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 1017 BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1018 1019/* Tx BMU Control / Status Registers (Yukon-2) */ 1020 /* Bit 31: same as for Rx */ 1021#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 1022#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 1023#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 1024 /* Bit 10..0: same as for Rx */ 1025 1026/* Q_F 32 bit Flag Register */ 1027#define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */ 1028#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 1029#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1030#define F_WM_REACHED BIT_25 /* Watermark reached */ 1031#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1032#define F_FIFO_LEVEL (0x1f<<16) /* Bit 23..16: # of Qwords in FIFO */ 1033#define F_WATER_MARK 0x0007ff /* Bit 10.. 0: Watermark */ 1034 1035/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1036/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1037#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1038#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1039#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1040#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1041 1042/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1043/* RB_START 32 bit RAM Buffer Start Address */ 1044/* RB_END 32 bit RAM Buffer End Address */ 1045/* RB_WP 32 bit RAM Buffer Write Pointer */ 1046/* RB_RP 32 bit RAM Buffer Read Pointer */ 1047/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 1048/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1049/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1050/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1051/* RB_PC 32 bit RAM Buffer Packet Counter */ 1052/* RB_LEV 32 bit RAM Buffer Level Register */ 1053#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1054 1055/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 1056#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1057#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 1058#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1059#define RB_PC_INC BIT_0 /* Packet Counter Increment */ 1060 1061/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1062#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1063#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1064#define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1065#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1066#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1067#define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1068 1069/* RB_CTRL 8 bit RAM Buffer Control Register */ 1070#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1071#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1072#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 1073#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1074#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1075#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1076 1077/* RAM Buffer High Pause Threshold values */ 1078#define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 1079#define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1080#define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1081 1082/* Threshold values for Yukon-EC Ultra */ 1083#define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1084#define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1085#define MSK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */ 1086#define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1087 1088#define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1089#define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1090/* performance sensitive drivers should set this define to 0x80 */ 1091#define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 1092 1093/* Receive and Transmit Queues */ 1094#define Q_R1 0x0000 /* Receive Queue 1 */ 1095#define Q_R2 0x0080 /* Receive Queue 2 */ 1096#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1097#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1098#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1099#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 1100 1101#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1102#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 1103#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1104#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 1105 1106#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1107 1108/* Minimum RAM Buffer Rx Queue Size */ 1109#define MSK_MIN_RXQ_SIZE 10 1110/* Minimum RAM Buffer Tx Queue Size */ 1111#define MSK_MIN_TXQ_SIZE 10 1112/* Percentage of queue size from whole memory. 80 % for receive */ 1113#define MSK_RAM_QUOTA_RX 80 1114 1115/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1116#define WOL_CTL_LINK_CHG_OCC BIT_15 1117#define WOL_CTL_MAGIC_PKT_OCC BIT_14 1118#define WOL_CTL_PATTERN_OCC BIT_13 1119#define WOL_CTL_CLEAR_RESULT BIT_12 1120#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1121#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 1122#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 1123#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 1124#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 1125#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 1126#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 1127#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 1128#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1129#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1130#define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1131#define WOL_CTL_DIS_PATTERN_UNIT BIT_0 1132 1133#define WOL_CTL_DEFAULT \ 1134 (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1135 WOL_CTL_DIS_PME_ON_PATTERN | \ 1136 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1137 WOL_CTL_DIS_LINK_CHG_UNIT | \ 1138 WOL_CTL_DIS_PATTERN_UNIT | \ 1139 WOL_CTL_DIS_MAGIC_PKT_UNIT) 1140 1141/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1142#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 1143 1144/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 1145#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 1146#define WOL_PATT_MATCH_PME_ALL 0x7f 1147 1148 1149/* 1150 * Marvel-PHY Registers, indirect addressed over GMAC 1151 */ 1152#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 1153#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 1154#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1155#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1156#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 1157#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 1158#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 1159#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 1160#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 1161 /* Marvel-specific registers */ 1162#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1163#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1164 /* 0x0b - 0x0e: reserved */ 1165#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1166#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1167#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1168#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1169#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1170#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1171#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1172#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1173#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1174#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1175#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 1176#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1177#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1178#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 1179#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 1180#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 1181 1182/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1183#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 1184#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 1185#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 1186#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 1187#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 1188 1189#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 1190#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 1191#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 1192#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 1193#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1194#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 1195#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 1196#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 1197#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1198#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 1199 1200#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 1201#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 1202#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 1203 1204#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1205#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 1206#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1207#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ 1208#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 1209#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 1210#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 1211#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1212 1213#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1214#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1215#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1216 1217/* different Marvell PHY Ids */ 1218#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1219 1220#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1221#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1222#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 1223#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 1224#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1225#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 1226 1227/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1228#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1229#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1230#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1231#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 1232#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1233#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1234#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1235 1236/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1237/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1238#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1239#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1240#define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1241#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1242#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1243#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 1244#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1245#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1246#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1247#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1248#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1249 1250/* special defines for FIBER (88E1011S only) */ 1251#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1252#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1253#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1254#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1255 1256/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1257#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1258#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1259#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1260#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1261 1262/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1263#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1264#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1265#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1266#define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1267#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1268#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1269 1270/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1271#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1272#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1273#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 1274#define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 1275#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1276#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 1277#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1278#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 1279#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1280#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 1281#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 1282#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 1283 1284#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1285#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1286 1287#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 1288 1289#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1290#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1291#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1292 1293/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1294#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 1295#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 1296#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 1297 /* !!! Errata in spec. (1 = disable) */ 1298 1299#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 1300 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1301 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1302 1303/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1304#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1305#define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 1306#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 1307#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 1308#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 1309#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1310#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 1311#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 1312#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 1313 1314/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1315#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1316#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 1317#define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 1318#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1319#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 1320#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 1321#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 1322#define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 1323#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 1324#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 1325#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 1326#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 1327#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 1328#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 1329#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 1330#define PHY_M_PS_JABBER BIT_0 /* Jabber */ 1331 1332#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1333 1334/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1335#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 1336#define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1337 1338/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1339/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1340#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 1341#define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 1342#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 1343#define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 1344#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1345#define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 1346#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 1347#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 1348#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 1349#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 1350#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 1351#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 1352#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 1353#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 1354#define PHY_M_IS_JABBER BIT_0 /* Jabber */ 1355 1356#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1357 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1358 1359/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1360#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1361#define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 1362#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 1363#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 1364 /* (88E1011 only) */ 1365#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 1366 /* (88E1011 only) */ 1367#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 1368 /* (88E1111 only) */ 1369#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 1370 /* !!! Errata in spec. (1 = disable) */ 1371#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 1372#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1373#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 1374#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 1375#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 1376#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 1377 1378#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1379 /* 00=1x; 01=2x; 10=3x; 11=4x */ 1380#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 1381 /* 00=dis; 01=1x; 10=2x; 11=3x */ 1382#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1383 /* 01X=0; 110=2.5; 111=25 (MHz) */ 1384 1385#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 1386 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1387 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1388#define MAC_TX_CLK_0_MHZ 2 1389#define MAC_TX_CLK_2_5_MHZ 6 1390#define MAC_TX_CLK_25_MHZ 7 1391 1392/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1393#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 1394#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1395#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1396#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1397#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 1398#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 1399#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 1400 /* (88E1111 only) */ 1401#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1402 /* (88E1011 only) */ 1403#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1404#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 1405#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 1406#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 1407#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 1408 1409#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 1410 1411#define PULS_NO_STR 0 /* no pulse stretching */ 1412#define PULS_21MS 1 /* 21 ms to 42 ms */ 1413#define PULS_42MS 2 /* 42 ms to 84 ms */ 1414#define PULS_84MS 3 /* 84 ms to 170 ms */ 1415#define PULS_170MS 4 /* 170 ms to 340 ms */ 1416#define PULS_340MS 5 /* 340 ms to 670 ms */ 1417#define PULS_670MS 6 /* 670 ms to 1.3 s */ 1418#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1419 1420#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 1421 1422#define BLINK_42MS 0 /* 42 ms */ 1423#define BLINK_84MS 1 /* 84 ms */ 1424#define BLINK_170MS 2 /* 170 ms */ 1425#define BLINK_340MS 3 /* 340 ms */ 1426#define BLINK_670MS 4 /* 670 ms */ 1427 1428/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1429#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 1430#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1431#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1432#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1433#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1434#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1435#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1436 1437#define MO_LED_NORM 0 1438#define MO_LED_BLINK 1 1439#define MO_LED_OFF 2 1440#define MO_LED_ON 3 1441 1442/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1443#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 1444#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1445#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 1446#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 1447#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1448 1449/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1450#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 1451#define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1452#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 1453#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1454#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 1455#define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 1456#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 1457 /* (88E1111 only) */ 1458#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 1459#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 1460#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1461 1462/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1463#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 1464#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 1465 /* (88E1111 only) */ 1466#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1467#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 1468 /* (88E1111 only) */ 1469#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 1470 1471/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1472#define CABD_STAT_NORMAL 0 1473#define CABD_STAT_SHORT 1 1474#define CABD_STAT_OPEN 2 1475#define CABD_STAT_FAIL 3 1476 1477/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1478/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1479#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 1480#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 1481#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 1482 1483#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1484#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 1485#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 1486 1487#define LED_PAR_CTRL_COLX 0x00 1488#define LED_PAR_CTRL_ERROR 0x01 1489#define LED_PAR_CTRL_DUPLEX 0x02 1490#define LED_PAR_CTRL_DP_COL 0x03 1491#define LED_PAR_CTRL_SPEED 0x04 1492#define LED_PAR_CTRL_LINK 0x05 1493#define LED_PAR_CTRL_TX 0x06 1494#define LED_PAR_CTRL_RX 0x07 1495#define LED_PAR_CTRL_ACT 0x08 1496#define LED_PAR_CTRL_LNK_RX 0x09 1497#define LED_PAR_CTRL_LNK_AC 0x0a 1498#define LED_PAR_CTRL_ACT_BL 0x0b 1499#define LED_PAR_CTRL_TX_BL 0x0c 1500#define LED_PAR_CTRL_RX_BL 0x0d 1501#define LED_PAR_CTRL_COL_BL 0x0e 1502#define LED_PAR_CTRL_INACT 0x0f 1503 1504/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1505#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1506#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1507#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1508 1509/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1510/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1511#define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1512#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1513#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1514 1515/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1516#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1517#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1518#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1519#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1520#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1521 1522/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1523#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 1524#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1525#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1526#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1527 1528#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1529#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 1530#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 1531#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 1532 1533/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1534#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1535#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1536#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1537#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1538#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1539#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1540 1541#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1542#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1543#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1544#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1545#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1546#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1547 1548/* 1549 * GMAC registers 1550 * 1551 * The GMAC registers are 16 or 32 bits wide. 1552 * The GMACs host processor interface is 16 bits wide, 1553 * therefore ALL registers will be addressed with 16 bit accesses. 1554 * 1555 * Note: NA reg = Network Address e.g DA, SA etc. 1556 */ 1557 1558/* Port Registers */ 1559#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1560#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1561#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1562#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1563#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1564#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1565#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1566 1567/* Source Address Registers */ 1568#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1569#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1570#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1571#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1572#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1573#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1574 1575/* Multicast Address Hash Registers */ 1576#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1577#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1578#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1579#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1580 1581/* Interrupt Source Registers */ 1582#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1583#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1584#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1585 1586/* Interrupt Mask Registers */ 1587#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1588#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1589#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1590 1591/* Serial Management Interface (SMI) Registers */ 1592#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1593#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1594#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1595 1596/* MIB Counters */ 1597#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1598#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1599 1600/* 1601 * MIB Counters base address definitions (low word) - 1602 * use offset 4 for access to high word (32 bit r/o) 1603 */ 1604#define GM_RXF_UC_OK \ 1605 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1606#define GM_RXF_BC_OK \ 1607 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1608#define GM_RXF_MPAUSE \ 1609 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1610#define GM_RXF_MC_OK \ 1611 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1612#define GM_RXF_FCS_ERR \ 1613 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1614#define GM_RXO_OK_LO \ 1615 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1616#define GM_RXO_OK_HI \ 1617 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1618#define GM_RXO_ERR_LO \ 1619 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1620#define GM_RXO_ERR_HI \ 1621 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1622#define GM_RXF_SHT \ 1623 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1624#define GM_RXE_FRAG \ 1625 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1626#define GM_RXF_64B \ 1627 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1628#define GM_RXF_127B \ 1629 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1630#define GM_RXF_255B \ 1631 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1632#define GM_RXF_511B \ 1633 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1634#define GM_RXF_1023B \ 1635 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1636#define GM_RXF_1518B \ 1637 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1638#define GM_RXF_MAX_SZ \ 1639 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1640#define GM_RXF_LNG_ERR \ 1641 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1642#define GM_RXF_JAB_PKT \ 1643 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1644#define GM_RXE_FIFO_OV \ 1645 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1646#define GM_TXF_UC_OK \ 1647 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1648#define GM_TXF_BC_OK \ 1649 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1650#define GM_TXF_MPAUSE \ 1651 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1652#define GM_TXF_MC_OK \ 1653 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1654#define GM_TXO_OK_LO \ 1655 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1656#define GM_TXO_OK_HI \ 1657 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1658#define GM_TXF_64B \ 1659 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1660#define GM_TXF_127B \ 1661 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1662#define GM_TXF_255B \ 1663 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1664#define GM_TXF_511B \ 1665 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1666#define GM_TXF_1023B \ 1667 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1668#define GM_TXF_1518B \ 1669 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1670#define GM_TXF_MAX_SZ \ 1671 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1672#define GM_TXF_COL \ 1673 (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1674#define GM_TXF_LAT_COL \ 1675 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1676#define GM_TXF_ABO_COL \ 1677 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1678#define GM_TXF_MUL_COL \ 1679 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1680#define GM_TXF_SNG_COL \ 1681 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1682#define GM_TXE_FIFO_UR \ 1683 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1684 1685/*----------------------------------------------------------------------------*/ 1686/* 1687 * GMAC Bit Definitions 1688 * 1689 * If the bit access behaviour differs from the register access behaviour 1690 * (r/w, r/o) this is documented after the bit number. 1691 * The following bit access behaviours are used: 1692 * (sc) self clearing 1693 * (r/o) read only 1694 */ 1695 1696/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1697#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1698#define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1699#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1700#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1701#define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1702#define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1703#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occured */ 1704#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */ 1705#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1706#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1707#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1708#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1709 1710/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1711#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1712#define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1713#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1714#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1715#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1716#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1717#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1718#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1719#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1720#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1721#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1722#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1723#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1724#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1725#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1726 1727#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1728#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1729 GM_GPCR_AU_SPD_DIS) 1730 1731/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1732#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1733#define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1734#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1735#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1736#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1737 /* (Yukon-2 only) */ 1738 1739#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1740#define TX_COL_DEF 0x04 1741 1742/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1743#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1744#define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1745#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1746#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1747 1748/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1749#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1750#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1751#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1752#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1753 /* (Yukon-2 only) */ 1754 1755#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1756#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1757#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1758#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1759 1760#define TX_JAM_LEN_DEF 0x03 1761#define TX_JAM_IPG_DEF 0x0b 1762#define TX_IPG_JAM_DEF 0x1c 1763#define TX_BOF_LIM_DEF 0x04 1764 1765/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1766#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1767 /* r/o on Yukon, r/w on Yukon-EC */ 1768#define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1769#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1770#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1771#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1772 1773#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1774#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1775 1776#define DATA_BLIND_DEF 0x04 1777#define IPG_DATA_DEF 0x1e 1778 1779/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1780#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1781#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1782#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1783#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1784#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1785 1786#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1787#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1788 1789/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1790#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1791#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1792 1793/* Receive Frame Status Encoding */ 1794#define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1795#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 1796#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 1797#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 1798#define GMR_FS_MC BIT_10 /* Multicast Packet */ 1799#define GMR_FS_BC BIT_9 /* Broadcast Packet */ 1800#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 1801#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 1802#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 1803#define GMR_FS_MII_ERR BIT_5 /* MII Error */ 1804#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1805#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1806#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1807#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1808 1809#define GMR_FS_LEN_SHIFT 16 1810 1811#define GMR_FS_ANY_ERR ( \ 1812 GMR_FS_RX_FF_OV | \ 1813 GMR_FS_CRC_ERR | \ 1814 GMR_FS_FRAGMENT | \ 1815 GMR_FS_LONG_ERR | \ 1816 GMR_FS_MII_ERR | \ 1817 GMR_FS_BAD_FC | \ 1818 GMR_FS_GOOD_FC | \ 1819 GMR_FS_UN_SIZE | \ 1820 GMR_FS_JABBER) 1821 1822/* Rx GMAC FIFO Flush Mask (default) */ 1823#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 1824 1825/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 1826 1827/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 1828/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 1829/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 1830/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 1831/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 1832/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1833/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1834/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 1835/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 1836/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 1837/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 1838/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1839/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1840/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1841 1842/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1843#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 1844#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1845#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1846#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1847#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1848#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1849#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1850#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 1851#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1852#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1853#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1854#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1855#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1856#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1857#define GMF_OPER_ON BIT_3 /* Operational Mode On */ 1858#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1859#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1860#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1861 1862/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1863#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1864#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 1865#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1866#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1867#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1868#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1869#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1870 /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1871#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1872#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1873#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1874 /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1875 1876#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1877#define GMF_TX_CTRL_DEF GMF_OPER_ON 1878 1879#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 1880#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 1881 1882/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1883#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 1884#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 1885#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 1886 1887/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 1888#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 1889#define PC_POLL_RQ BIT_4 /* Poll Request Start */ 1890#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 1891#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 1892#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 1893#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 1894 1895/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1896/* This register is used by the host driver software */ 1897#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 1898#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 1899#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 1900#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 1901#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 1902 1903#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 1904#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 1905 1906/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 1907/* This register is used by the ASF firmware */ 1908#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 1909#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 1910 1911/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 1912#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 1913#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 1914#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 1915#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 1916#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 1917 1918/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 1919#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 1920#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 1921#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 1922#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 1923#define GMC_PAUSE_ON BIT_3 /* Pause On */ 1924#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 1925#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 1926#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 1927 1928/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 1929#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 1930#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 1931#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 1932#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 1933#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 1934#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 1935#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 1936#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 1937#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 1938#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 1939#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 1940#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 1941#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 1942#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 1943#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 1944#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 1945#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 1946#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 1947#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 1948#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 1949#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 1950#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 1951#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 1952 1953/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 1954/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 1955#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 1956#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 1957#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 1958#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 1959#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 1960#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 1961 1962#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 1963 1964/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 1965#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 1966#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 1967 1968#define MSK_PORT_A 0 1969#define MSK_PORT_B 1 1970 1971/* Register access macros */ 1972#define CSR_WRITE_4(sc, reg, val) \ 1973 bus_write_4((sc)->msk_res[0], (reg), (val)) 1974#define CSR_WRITE_2(sc, reg, val) \ 1975 bus_write_2((sc)->msk_res[0], (reg), (val)) 1976#define CSR_WRITE_1(sc, reg, val) \ 1977 bus_write_1((sc)->msk_res[0], (reg), (val)) 1978 1979#define CSR_READ_4(sc, reg) \ 1980 bus_read_4((sc)->msk_res[0], (reg)) 1981#define CSR_READ_2(sc, reg) \ 1982 bus_read_2((sc)->msk_res[0], (reg)) 1983#define CSR_READ_1(sc, reg) \ 1984 bus_read_1((sc)->msk_res[0], (reg)) 1985 1986#define CSR_PCI_WRITE_4(sc, reg, val) \ 1987 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 1988#define CSR_PCI_WRITE_2(sc, reg, val) \ 1989 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 1990#define CSR_PCI_WRITE_1(sc, reg, val) \ 1991 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 1992 1993#define CSR_PCI_READ_4(sc, reg) \ 1994 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 1995#define CSR_PCI_READ_2(sc, reg) \ 1996 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 1997#define CSR_PCI_READ_1(sc, reg) \ 1998 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 1999 2000#define MSK_IF_READ_4(sc_if, reg) \ 2001 CSR_READ_4((sc_if)->msk_softc, (reg)) 2002#define MSK_IF_READ_2(sc_if, reg) \ 2003 CSR_READ_2((sc_if)->msk_softc, (reg)) 2004#define MSK_IF_READ_1(sc_if, reg) \ 2005 CSR_READ_1((sc_if)->msk_softc, (reg)) 2006 2007#define MSK_IF_WRITE_4(sc_if, reg, val) \ 2008 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2009#define MSK_IF_WRITE_2(sc_if, reg, val) \ 2010 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2011#define MSK_IF_WRITE_1(sc_if, reg, val) \ 2012 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2013 2014#define GMAC_REG(port, reg) \ 2015 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2016#define GMAC_WRITE_2(sc, port, reg, val) \ 2017 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2018#define GMAC_READ_2(sc, port, reg) \ 2019 CSR_READ_2((sc), GMAC_REG((port), (reg))) 2020 2021/* GPHY address (bits 15..11 of SMI control reg) */ 2022#define PHY_ADDR_MARV 0 2023 2024/*-RMV- DWORD 1: Deviations */ 2025#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/ 2026#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/ 2027#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/ 2028#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/ 2029#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */ 2030#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */ 2031#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */ 2032#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */ 2033#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */ 2034#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */ 2035#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */ 2036#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */ 2037#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */ 2038#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */ 2039#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */ 2040/*-RMV- compl&Stat BMU deadl) */ 2041#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */ 2042#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */ 2043#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */ 2044#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */ 2045/*-RMV- with odd offset) */ 2046#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/ 2047#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/ 2048 2049#define HW_FEATURE(sc, f) \ 2050 (((((sc)->msk_hw_feature & 0x30000000) >> 28) & ((f) & 0x0fffffff)) != 0) 2051 2052 2053#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2054#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2055 2056/* 2057 * At first I guessed 8 bytes, the size of a single descriptor, would be 2058 * required alignment constraints. But, it seems that Yukon II have 4096 2059 * bytes boundary alignment constraints. 2060 */ 2061#define MSK_RING_ALIGN 4096 2062#define MSK_STAT_ALIGN 4096 2063 2064/* Rx descriptor data structure */ 2065struct msk_rx_desc { 2066 uint32_t msk_addr; 2067 uint32_t msk_control; 2068}; 2069 2070/* Tx descriptor data structure */ 2071struct msk_tx_desc { 2072 uint32_t msk_addr; 2073 uint32_t msk_control; 2074}; 2075 2076/* Status descriptor data structure */ 2077struct msk_stat_desc { 2078 uint32_t msk_status; 2079 uint32_t msk_control; 2080}; 2081 2082/* mask and shift value to get Tx async queue status for port 1 */ 2083#define STLE_TXA1_MSKL 0x00000fff 2084#define STLE_TXA1_SHIFTL 0 2085 2086/* mask and shift value to get Tx sync queue status for port 1 */ 2087#define STLE_TXS1_MSKL 0x00fff000 2088#define STLE_TXS1_SHIFTL 12 2089 2090/* mask and shift value to get Tx async queue status for port 2 */ 2091#define STLE_TXA2_MSKL 0xff000000 2092#define STLE_TXA2_SHIFTL 24 2093#define STLE_TXA2_MSKH 0x000f 2094/* this one shifts up */ 2095#define STLE_TXA2_SHIFTH 8 2096 2097/* mask and shift value to get Tx sync queue status for port 2 */ 2098#define STLE_TXS2_MSKL 0x00000000 2099#define STLE_TXS2_SHIFTL 0 2100#define STLE_TXS2_MSKH 0xfff0 2101#define STLE_TXS2_SHIFTH 4 2102 2103/* YUKON-2 bit values */ 2104#define HW_OWNER 0x80000000 2105#define SW_OWNER 0x00000000 2106 2107#define PU_PUTIDX_VALID 0x10000000 2108 2109/* YUKON-2 Control flags */ 2110#define UDPTCP 0x00010000 2111#define CALSUM 0x00020000 2112#define WR_SUM 0x00040000 2113#define INIT_SUM 0x00080000 2114#define LOCK_SUM 0x00100000 2115#define INS_VLAN 0x00200000 2116#define FRC_STAT 0x00400000 2117#define EOP 0x00800000 2118 2119#define TX_LOCK 0x01000000 2120#define BUF_SEND 0x02000000 2121#define PACKET_SEND 0x04000000 2122 2123#define NO_WARNING 0x40000000 2124#define NO_UPDATE 0x80000000 2125 2126/* YUKON-2 Rx/Tx opcodes defines */ 2127#define OP_TCPWRITE 0x11000000 2128#define OP_TCPSTART 0x12000000 2129#define OP_TCPINIT 0x14000000 2130#define OP_TCPLCK 0x18000000 2131#define OP_TCPCHKSUM OP_TCPSTART 2132#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2133#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2134#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2135#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2136#define OP_ADDR64 0x21000000 2137#define OP_VLAN 0x22000000 2138#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2139#define OP_LRGLEN 0x24000000 2140#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2141#define OP_BUFFER 0x40000000 2142#define OP_PACKET 0x41000000 2143#define OP_LARGESEND 0x43000000 2144 2145/* YUKON-2 STATUS opcodes defines */ 2146#define OP_RXSTAT 0x60000000 2147#define OP_RXTIMESTAMP 0x61000000 2148#define OP_RXVLAN 0x62000000 2149#define OP_RXCHKS 0x64000000 2150#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2151#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2152#define OP_RSS_HASH 0x65000000 2153#define OP_TXINDEXLE 0x68000000 2154 2155/* YUKON-2 SPECIAL opcodes defines */ 2156#define OP_PUTIDX 0x70000000 2157 2158#define STLE_OP_MASK 0xff000000 2159#define STLE_LEN_MASK 0x0000ffff 2160 2161/* Descriptor Bit Definition */ 2162/* TxCtrl Transmit Buffer Control Field */ 2163/* RxCtrl Receive Buffer Control Field */ 2164#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2165#define BMU_STF BIT_30 /* Start of Frame */ 2166#define BMU_EOF BIT_29 /* End of Frame */ 2167#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2168#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 2169/* TxCtrl specific bits */ 2170#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2171#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 2172#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2173/* RxCtrl specific bits */ 2174#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2175#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2176#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2177 /* Bit 23..16: BMU Check Opcodes */ 2178#define BMU_CHECK (0x55<<16) /* Default BMU check */ 2179#define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 2180#define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2181#define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2182 2183#define MSK_TX_RING_CNT 256 2184#define MSK_RX_RING_CNT 256 2185#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2186#define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT)) 2187#define MSK_MAXTXSEGS 32 2188#define MSK_MAXRXSEGS 32 2189 2190/* 2191 * It seems that the hardware requires extra decriptors(LEs) to offload 2192 * TCP/UDP checksum, VLAN hardware tag inserstion and TSO. 2193 * 2194 * 1 descriptor for TCP/UDP checksum offload. 2195 * 1 descriptor VLAN hardware tag insertion. 2196 * 1 descriptor for TSO(TCP Segmentation Offload) 2197 * 1 descriptor for 64bits DMA : Not applicatable due to the use of 2198 * BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation. 2199 */ 2200#define MSK_RESERVED_TX_DESC_CNT 3 2201 2202/* 2203 * Jumbo buffer stuff. Note that we must allocate more jumbo 2204 * buffers than there are descriptors in the receive ring. This 2205 * is because we don't know how long it will take for a packet 2206 * to be released after we hand it off to the upper protocol 2207 * layers. To be safe, we allocate 1.5 times the number of 2208 * receive descriptors. 2209 */ 2210#define MSK_JUMBO_FRAMELEN 9022 2211#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2212#define MSK_MAX_FRAMELEN \ 2213 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2214#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2215#define MSK_JSLOTS ((MSK_RX_RING_CNT * 3) / 2) 2216 2217#define MSK_JRAWLEN (MSK_JUMBO_FRAMELEN + ETHER_ALIGN) 2218#define MSK_JLEN (MSK_JRAWLEN + (sizeof(uint64_t) - \ 2219 (MSK_JRAWLEN % sizeof(uint64_t)))) 2220#define MSK_JPAGESZ PAGE_SIZE 2221#define MSK_RESID \ 2222 (MSK_JPAGESZ - (MSK_JLEN * MSK_JSLOTS) % MSK_JPAGESZ) 2223#define MSK_JMEM ((MSK_JLEN * MSK_JSLOTS) + MSK_RESID) 2224 2225struct msk_jpool_entry { 2226 int slot; 2227 SLIST_ENTRY(msk_jpool_entry) jpool_entries; 2228}; 2229 2230struct msk_txdesc { 2231 struct mbuf *tx_m; 2232 bus_dmamap_t tx_dmamap; 2233 struct msk_tx_desc *tx_le; 2234}; 2235 2236struct msk_rxdesc { 2237 struct mbuf *rx_m; 2238 bus_dmamap_t rx_dmamap; 2239 struct msk_rx_desc *rx_le; 2240}; 2241 2242struct msk_chain_data { 2243 bus_dma_tag_t msk_parent_tag; 2244 bus_dma_tag_t msk_tx_tag; 2245 struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2246 bus_dma_tag_t msk_rx_tag; 2247 struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2248 bus_dma_tag_t msk_tx_ring_tag; 2249 bus_dma_tag_t msk_rx_ring_tag; 2250 bus_dmamap_t msk_tx_ring_map; 2251 bus_dmamap_t msk_rx_ring_map; 2252 bus_dmamap_t msk_rx_sparemap; 2253 bus_dma_tag_t msk_jumbo_rx_tag; 2254 bus_dma_tag_t msk_jumbo_tag; 2255 bus_dmamap_t msk_jumbo_map; 2256 bus_dma_tag_t msk_jumbo_mtag; 2257 caddr_t msk_jslots[MSK_JSLOTS]; 2258 struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2259 bus_dma_tag_t msk_jumbo_rx_ring_tag; 2260 bus_dmamap_t msk_jumbo_rx_ring_map; 2261 bus_dmamap_t msk_jumbo_rx_sparemap; 2262 uint16_t msk_tso_mtu; 2263 int msk_tx_prod; 2264 int msk_tx_cons; 2265 int msk_tx_cnt; 2266 int msk_tx_put; 2267 int msk_rx_cons; 2268 int msk_rx_prod; 2269 int msk_rx_putwm; 2270}; 2271 2272struct msk_ring_data { 2273 struct msk_tx_desc *msk_tx_ring; 2274 bus_addr_t msk_tx_ring_paddr; 2275 struct msk_rx_desc *msk_rx_ring; 2276 bus_addr_t msk_rx_ring_paddr; 2277 struct msk_rx_desc *msk_jumbo_rx_ring; 2278 bus_addr_t msk_jumbo_rx_ring_paddr; 2279 void *msk_jumbo_buf; 2280 bus_addr_t msk_jumbo_buf_paddr; 2281}; 2282 2283#define MSK_TX_RING_ADDR(sc, i) \ 2284 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2285#define MSK_RX_RING_ADDR(sc, i) \ 2286 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2287#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2288 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2289 2290#define MSK_TX_RING_SZ \ 2291 (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2292#define MSK_RX_RING_SZ \ 2293 (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2294#define MSK_JUMBO_RX_RING_SZ \ 2295 (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2296#define MSK_STAT_RING_SZ \ 2297 (sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT) 2298 2299#define MSK_INC(x, y) (x) = (x + 1) % y 2300 2301#define MSK_PCI_BUS 0 2302#define MSK_PCIX_BUS 1 2303#define MSK_PEX_BUS 2 2304 2305#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2306#define MSK_PROC_MIN 30 2307#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2308 2309#define MSK_TX_TIMEOUT 5 2310#define MSK_PUT_WM 10 2311 2312/* Forward decl. */ 2313struct msk_if_softc; 2314 2315/* Softc for the Marvell Yukon II controller. */ 2316struct msk_softc { 2317 struct resource *msk_res[2]; /* I/O and IRQ resources */ 2318 struct resource_spec *msk_res_spec; 2319 void *msk_intrhand; /* irq handler handle */ 2320 device_t msk_dev; 2321 uint8_t msk_hw_id; 2322 uint8_t msk_hw_rev; 2323 uint8_t msk_bustype; 2324 uint8_t msk_num_port; 2325 int msk_ramsize; /* amount of SRAM on NIC */ 2326 uint32_t msk_pmd; /* physical media type */ 2327 uint32_t msk_coppertype; 2328 uint32_t msk_intrmask; 2329 uint32_t msk_intrhwemask; 2330 int msk_suspended; 2331 int msk_hw_feature; 2332 int msk_clock; 2333 int msk_marvell_phy; 2334 int msk_msi; 2335 struct msk_if_softc *msk_if[2]; 2336 device_t msk_devs[2]; 2337 int msk_txqsize; 2338 int msk_rxqsize; 2339 int msk_txqstart[2]; 2340 int msk_txqend[2]; 2341 int msk_rxqstart[2]; 2342 int msk_rxqend[2]; 2343 bus_dma_tag_t msk_stat_tag; 2344 bus_dmamap_t msk_stat_map; 2345 struct msk_stat_desc *msk_stat_ring; 2346 bus_addr_t msk_stat_ring_paddr; 2347 int msk_process_limit; 2348 int msk_stat_cons; 2349 struct taskqueue *msk_tq; 2350 struct task msk_int_task; 2351 struct mtx msk_mtx; 2352}; 2353 2354#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 2355#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2356#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2357#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2358#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2359#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2360 2361#define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 2362 2363/* Softc for each logical interface. */ 2364struct msk_if_softc { 2365 struct ifnet *msk_ifp; /* interface info */ 2366 device_t msk_miibus; 2367 device_t msk_if_dev; 2368 int32_t msk_port; /* port # on controller */ 2369 int msk_framesize; 2370 int msk_phytype; 2371 int msk_phyaddr; 2372 int msk_link; 2373 struct callout msk_tick_ch; 2374 struct callout msk_watchdog_ch; 2375 uint32_t msk_txq; /* Tx. Async Queue offset */ 2376 uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2377 uint32_t msk_rxq; /* Rx. Qeueue offset */ 2378 struct msk_chain_data msk_cdata; 2379 struct msk_ring_data msk_rdata; 2380 struct msk_softc *msk_softc; /* parent controller */ 2381 struct task msk_link_task; 2382 struct task msk_tx_task; 2383 int msk_if_flags; 2384 int msk_detach; 2385 uint16_t msk_vtag; /* VLAN tag id. */ 2386 SLIST_HEAD(__msk_jfreehead, msk_jpool_entry) msk_jfree_listhead; 2387 SLIST_HEAD(__msk_jinusehead, msk_jpool_entry) msk_jinuse_listhead; 2388 struct mtx msk_jlist_mtx; 2389}; 2390 2391#define MSK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->msk_jlist_mtx) 2392#define MSK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_jlist_mtx) 2393 2394#define MSK_TIMEOUT 1000 2395#define MSK_PHY_POWERUP 1 2396#define MSK_PHY_POWERDOWN 0 2397