1265555Sambrisko/* 2282531Skadesai * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3272744Skadesai * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4282531Skadesai * Support: freebsdraid@avagotech.com 5265555Sambrisko * 6265555Sambrisko * Redistribution and use in source and binary forms, with or without 7272744Skadesai * modification, are permitted provided that the following conditions are 8272744Skadesai * met: 9265555Sambrisko * 10272744Skadesai * 1. Redistributions of source code must retain the above copyright notice, 11272744Skadesai * this list of conditions and the following disclaimer. 2. Redistributions 12272744Skadesai * in binary form must reproduce the above copyright notice, this list of 13272744Skadesai * conditions and the following disclaimer in the documentation and/or other 14272744Skadesai * materials provided with the distribution. 3. Neither the name of the 15272744Skadesai * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16272744Skadesai * promote products derived from this software without specific prior written 17272744Skadesai * permission. 18265555Sambrisko * 19272744Skadesai * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20272744Skadesai * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21272744Skadesai * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22272744Skadesai * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23272744Skadesai * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24272744Skadesai * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25272744Skadesai * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26272744Skadesai * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27272744Skadesai * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28272744Skadesai * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29265555Sambrisko * POSSIBILITY OF SUCH DAMAGE. 30265555Sambrisko * 31272744Skadesai * The views and conclusions contained in the software and documentation are 32272744Skadesai * those of the authors and should not be interpreted as representing 33265555Sambrisko * official policies,either expressed or implied, of the FreeBSD Project. 34265555Sambrisko * 35282531Skadesai * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36272744Skadesai * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37265555Sambrisko * 38265555Sambrisko */ 39265555Sambrisko 40265555Sambrisko#include <sys/cdefs.h> 41265555Sambrisko__FBSDID("$FreeBSD: stable/11/sys/dev/mrsas/mrsas.h 346944 2019-04-30 07:12:30Z kadesai $"); 42265555Sambrisko 43265555Sambrisko#ifndef MRSAS_H 44272744Skadesai#define MRSAS_H 45265555Sambrisko 46272744Skadesai#include <sys/param.h> /* defines used in kernel.h */ 47265555Sambrisko#include <sys/module.h> 48265555Sambrisko#include <sys/systm.h> 49265555Sambrisko#include <sys/proc.h> 50265555Sambrisko#include <sys/errno.h> 51272744Skadesai#include <sys/kernel.h> /* types used in module initialization */ 52272744Skadesai#include <sys/conf.h> /* cdevsw struct */ 53272744Skadesai#include <sys/uio.h> /* uio struct */ 54265555Sambrisko#include <sys/malloc.h> 55272744Skadesai#include <sys/bus.h> /* structs, prototypes for pci bus 56272744Skadesai * stuff */ 57265555Sambrisko#include <sys/rman.h> 58265555Sambrisko#include <sys/types.h> 59272741Skadesai#include <sys/lock.h> 60272741Skadesai#include <sys/sema.h> 61265555Sambrisko#include <sys/sysctl.h> 62265555Sambrisko#include <sys/stat.h> 63265555Sambrisko#include <sys/taskqueue.h> 64265555Sambrisko#include <sys/poll.h> 65265555Sambrisko#include <sys/selinfo.h> 66265555Sambrisko 67272744Skadesai#include <machine/bus.h> 68272744Skadesai#include <machine/resource.h> 69272744Skadesai#include <machine/atomic.h> 70272741Skadesai 71272744Skadesai#include <dev/pci/pcivar.h> /* For pci_get macros! */ 72272744Skadesai#include <dev/pci/pcireg.h> 73272744Skadesai 74272744Skadesai 75272744Skadesai#define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76272744Skadesai 77265555Sambrisko/* 78265555Sambrisko * Device IDs and PCI 79265555Sambrisko */ 80272744Skadesai#define MRSAS_TBOLT 0x005b 81272744Skadesai#define MRSAS_INVADER 0x005d 82272744Skadesai#define MRSAS_FURY 0x005f 83299670Skadesai#define MRSAS_INTRUDER 0x00ce 84299670Skadesai#define MRSAS_INTRUDER_24 0x00cf 85301203Skadesai#define MRSAS_CUTLASS_52 0x0052 86301203Skadesai#define MRSAS_CUTLASS_53 0x0053 87342716Skadesai/* Gen3.5 Conroller */ 88342716Skadesai#define MRSAS_VENTURA 0x0014 89342716Skadesai#define MRSAS_CRUSADER 0x0015 90342716Skadesai#define MRSAS_HARPOON 0x0016 91342716Skadesai#define MRSAS_TOMCAT 0x0017 92342716Skadesai#define MRSAS_VENTURA_4PORT 0x001B 93342716Skadesai#define MRSAS_CRUSADER_4PORT 0x001C 94342720Skadesai#define MRSAS_AERO_10E0 0x10E0 95342720Skadesai#define MRSAS_AERO_10E1 0x10E1 96342720Skadesai#define MRSAS_AERO_10E2 0x10E2 97342720Skadesai#define MRSAS_AERO_10E3 0x10E3 98342720Skadesai#define MRSAS_AERO_10E4 0x10E4 99342720Skadesai#define MRSAS_AERO_10E5 0x10E5 100342720Skadesai#define MRSAS_AERO_10E6 0x10E6 101342720Skadesai#define MRSAS_AERO_10E7 0x10E7 102265555Sambrisko 103342720Skadesai 104265555Sambrisko/* 105272744Skadesai * Firmware State Defines 106265555Sambrisko */ 107272744Skadesai#define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 108272744Skadesai#define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 109272744Skadesai#define MRSAS_FW_STATE_CHNG_INTERRUPT 1 110265555Sambrisko 111265555Sambrisko/* 112265555Sambrisko * Message Frame Defines 113265555Sambrisko */ 114272744Skadesai#define MRSAS_SENSE_LEN 96 115272744Skadesai#define MRSAS_FUSION_MAX_RESET_TRIES 3 116265555Sambrisko 117265555Sambrisko/* 118272744Skadesai * Miscellaneous Defines 119265555Sambrisko */ 120272744Skadesai#define BYTE_ALIGNMENT 1 121272744Skadesai#define MRSAS_MAX_NAME_LENGTH 32 122346944Skadesai#define MRSAS_VERSION "07.709.04.00-fbsd" 123272744Skadesai#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 124272744Skadesai#define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 125272744Skadesai#define DONE 0 126272744Skadesai#define MRSAS_PAGE_SIZE 4096 127272744Skadesai#define MRSAS_RESET_NOTICE_INTERVAL 5 128272744Skadesai#define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 129272744Skadesai#define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 130272744Skadesai#define THRESHOLD_REPLY_COUNT 50 131272744Skadesai#define MAX_MSIX_COUNT 128 132265555Sambrisko 133342716Skadesai#define MAX_STREAMS_TRACKED 8 134342716Skadesai#define MR_STREAM_BITMAP 0x76543210 135342716Skadesai#define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */ 136342716Skadesai#define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 137342716Skadesai#define ZERO_LAST_STREAM 0x0fffffff 138342716Skadesai 139272744Skadesai/* 140272744Skadesai * Boolean types 141272744Skadesai */ 142265555Sambrisko#if (__FreeBSD_version < 901000) 143272744Skadesaitypedef enum _boolean { 144272744Skadesai false, true 145272744Skadesai} boolean; 146272744Skadesai 147265555Sambrisko#endif 148272744Skadesaienum err { 149272744Skadesai SUCCESS, FAIL 150272744Skadesai}; 151265555Sambrisko 152265555SambriskoMALLOC_DECLARE(M_MRSAS); 153265555SambriskoSYSCTL_DECL(_hw_mrsas); 154265555Sambrisko 155272744Skadesai#define MRSAS_INFO (1 << 0) 156272744Skadesai#define MRSAS_TRACE (1 << 1) 157272744Skadesai#define MRSAS_FAULT (1 << 2) 158272744Skadesai#define MRSAS_OCR (1 << 3) 159272744Skadesai#define MRSAS_TOUT MRSAS_OCR 160272744Skadesai#define MRSAS_AEN (1 << 4) 161272744Skadesai#define MRSAS_PRL11 (1 << 5) 162265555Sambrisko 163272744Skadesai#define mrsas_dprint(sc, level, msg, args...) \ 164265555Sambriskodo { \ 165265555Sambrisko if (sc->mrsas_debug & level) \ 166265555Sambrisko device_printf(sc->mrsas_dev, msg, ##args); \ 167265555Sambrisko} while (0) 168265555Sambrisko 169265555Sambrisko 170265555Sambrisko/**************************************************************************** 171265555Sambrisko * Raid Context structure which describes MegaRAID specific IO Paramenters 172265555Sambrisko * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 173265555Sambrisko ****************************************************************************/ 174265555Sambrisko 175265555Sambriskotypedef struct _RAID_CONTEXT { 176272744Skadesai u_int8_t Type:4; 177272744Skadesai u_int8_t nseg:4; 178272744Skadesai u_int8_t resvd0; 179272744Skadesai u_int16_t timeoutValue; 180272744Skadesai u_int8_t regLockFlags; 181272744Skadesai u_int8_t resvd1; 182272744Skadesai u_int16_t VirtualDiskTgtId; 183272744Skadesai u_int64_t regLockRowLBA; 184272744Skadesai u_int32_t regLockLength; 185272744Skadesai u_int16_t nextLMId; 186272744Skadesai u_int8_t exStatus; 187272744Skadesai u_int8_t status; 188272744Skadesai u_int8_t RAIDFlags; 189272744Skadesai u_int8_t numSGE; 190272744Skadesai u_int16_t configSeqNum; 191272744Skadesai u_int8_t spanArm; 192299668Skadesai u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 193299668Skadesai u_int8_t numSGEExt; /* 0x1E 1M IO support */ 194299668Skadesai u_int8_t resvd2; /* 0x1F */ 195272744Skadesai} RAID_CONTEXT; 196265555Sambrisko 197342716Skadesai/* 198342716Skadesai * Raid Context structure which describes ventura MegaRAID specific IO Paramenters 199342716Skadesai * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 200342716Skadesai */ 201342716Skadesaitypedef struct _RAID_CONTEXT_G35 { 202342716Skadesai u_int16_t Type:4; 203342716Skadesai u_int16_t nseg:4; 204342716Skadesai u_int16_t resvd0:8; 205342716Skadesai u_int16_t timeoutValue; 206342716Skadesai union { 207342716Skadesai struct { 208342716Skadesai u_int16_t reserved:1; 209342716Skadesai u_int16_t sld:1; 210342716Skadesai u_int16_t c2f:1; 211342716Skadesai u_int16_t fwn:1; 212342716Skadesai u_int16_t sqn:1; 213342716Skadesai u_int16_t sbs:1; 214342716Skadesai u_int16_t rw:1; 215342716Skadesai u_int16_t log:1; 216342716Skadesai u_int16_t cpuSel:4; 217342716Skadesai u_int16_t setDivert:4; 218342716Skadesai } bits; 219342716Skadesai u_int16_t s; 220342716Skadesai } routingFlags; 221342716Skadesai u_int16_t VirtualDiskTgtId; 222342716Skadesai u_int64_t regLockRowLBA; 223342716Skadesai u_int32_t regLockLength; 224342716Skadesai union { 225342716Skadesai u_int16_t nextLMId; 226342716Skadesai u_int16_t peerSMID; 227342716Skadesai } smid; 228342716Skadesai u_int8_t exStatus; 229342716Skadesai u_int8_t status; 230342716Skadesai u_int8_t RAIDFlags; 231342716Skadesai u_int8_t spanArm; 232342716Skadesai u_int16_t configSeqNum; 233342716Skadesai u_int16_t numSGE:12; 234342716Skadesai u_int16_t reserved:3; 235342716Skadesai u_int16_t streamDetected:1; 236342716Skadesai u_int8_t resvd2[2]; 237342716Skadesai} RAID_CONTEXT_G35; 238265555Sambrisko 239342716Skadesaitypedef union _RAID_CONTEXT_UNION { 240342716Skadesai RAID_CONTEXT raid_context; 241342716Skadesai RAID_CONTEXT_G35 raid_context_g35; 242342716Skadesai} RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; 243342716Skadesai 244342716Skadesai 245265555Sambrisko/************************************************************************* 246265555Sambrisko * MPI2 Defines 247265555Sambrisko ************************************************************************/ 248265555Sambrisko 249272744Skadesai#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 250272744Skadesai#define MPI2_WHOINIT_HOST_DRIVER (0x04) 251272744Skadesai#define MPI2_VERSION_MAJOR (0x02) 252272744Skadesai#define MPI2_VERSION_MINOR (0x00) 253272744Skadesai#define MPI2_VERSION_MAJOR_MASK (0xFF00) 254272744Skadesai#define MPI2_VERSION_MAJOR_SHIFT (8) 255272744Skadesai#define MPI2_VERSION_MINOR_MASK (0x00FF) 256272744Skadesai#define MPI2_VERSION_MINOR_SHIFT (0) 257272744Skadesai#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 258265555Sambrisko MPI2_VERSION_MINOR) 259272744Skadesai#define MPI2_HEADER_VERSION_UNIT (0x10) 260272744Skadesai#define MPI2_HEADER_VERSION_DEV (0x00) 261272744Skadesai#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 262272744Skadesai#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 263272744Skadesai#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 264272744Skadesai#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 265272744Skadesai#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 266272744Skadesai#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 267272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 268272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 269272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 270272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 271272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 272272744Skadesai#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 273272744Skadesai#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 274323819Sjkim#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 275323819Sjkim#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 276323819Sjkim#define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 277272744Skadesai#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 278272744Skadesai#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 279272744Skadesai#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 280272744Skadesai#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 281272744Skadesai#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 282272744Skadesai#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 283272744Skadesai#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 284272744Skadesai#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 285272744Skadesai#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 286272744Skadesai#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 287272744Skadesai#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 288272744Skadesai#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 289272744Skadesai#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 290272744Skadesai#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 291272744Skadesai#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 292272744Skadesai#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 293265555Sambrisko 294265555Sambrisko#ifndef MPI2_POINTER 295272744Skadesai#define MPI2_POINTER * 296265555Sambrisko#endif 297265555Sambrisko 298265555Sambrisko 299265555Sambrisko/*************************************** 300265555Sambrisko * MPI2 Structures 301265555Sambrisko ***************************************/ 302265555Sambrisko 303272744Skadesaitypedef struct _MPI25_IEEE_SGE_CHAIN64 { 304272744Skadesai u_int64_t Address; 305272744Skadesai u_int32_t Length; 306272744Skadesai u_int16_t Reserved1; 307272744Skadesai u_int8_t NextChainOffset; 308272744Skadesai u_int8_t Flags; 309272744Skadesai} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 310272744SkadesaiMpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 311265555Sambrisko 312272744Skadesaitypedef struct _MPI2_SGE_SIMPLE_UNION { 313272744Skadesai u_int32_t FlagsLength; 314272744Skadesai union { 315272744Skadesai u_int32_t Address32; 316272744Skadesai u_int64_t Address64; 317272744Skadesai } u; 318272744Skadesai} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 319272744SkadesaiMpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 320265555Sambrisko 321272744Skadesaitypedef struct { 322272744Skadesai u_int8_t CDB[20]; /* 0x00 */ 323272744Skadesai u_int32_t PrimaryReferenceTag; /* 0x14 */ 324272744Skadesai u_int16_t PrimaryApplicationTag;/* 0x18 */ 325272744Skadesai u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 326272744Skadesai u_int32_t TransferLength; /* 0x1C */ 327272744Skadesai} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 328272744SkadesaiMpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 329265555Sambrisko 330272744Skadesaitypedef struct _MPI2_SGE_CHAIN_UNION { 331272744Skadesai u_int16_t Length; 332272744Skadesai u_int8_t NextChainOffset; 333272744Skadesai u_int8_t Flags; 334272744Skadesai union { 335272744Skadesai u_int32_t Address32; 336272744Skadesai u_int64_t Address64; 337272744Skadesai } u; 338272744Skadesai} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 339272744SkadesaiMpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 340265555Sambrisko 341272744Skadesaitypedef struct _MPI2_IEEE_SGE_SIMPLE32 { 342272744Skadesai u_int32_t Address; 343272744Skadesai u_int32_t FlagsLength; 344272744Skadesai} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 345272744SkadesaiMpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 346272744Skadesaitypedef struct _MPI2_IEEE_SGE_SIMPLE64 { 347272744Skadesai u_int64_t Address; 348272744Skadesai u_int32_t Length; 349272744Skadesai u_int16_t Reserved1; 350272744Skadesai u_int8_t Reserved2; 351272744Skadesai u_int8_t Flags; 352272744Skadesai} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 353272744SkadesaiMpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 354265555Sambrisko 355272744Skadesaitypedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 356272744Skadesai MPI2_IEEE_SGE_SIMPLE32 Simple32; 357272744Skadesai MPI2_IEEE_SGE_SIMPLE64 Simple64; 358272744Skadesai} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 359272744SkadesaiMpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 360265555Sambrisko 361272744Skadesaitypedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 362272744Skadesaitypedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 363265555Sambrisko 364272744Skadesaitypedef union _MPI2_IEEE_SGE_CHAIN_UNION { 365272744Skadesai MPI2_IEEE_SGE_CHAIN32 Chain32; 366272744Skadesai MPI2_IEEE_SGE_CHAIN64 Chain64; 367272744Skadesai} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 368272744SkadesaiMpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 369265555Sambrisko 370272744Skadesaitypedef union _MPI2_SGE_IO_UNION { 371272744Skadesai MPI2_SGE_SIMPLE_UNION MpiSimple; 372272744Skadesai MPI2_SGE_CHAIN_UNION MpiChain; 373272744Skadesai MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 374272744Skadesai MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 375272744Skadesai} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 376272744SkadesaiMpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 377265555Sambrisko 378272744Skadesaitypedef union { 379272744Skadesai u_int8_t CDB32[32]; 380272744Skadesai MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 381272744Skadesai MPI2_SGE_SIMPLE_UNION SGE; 382272744Skadesai} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 383272744SkadesaiMpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 384265555Sambrisko 385323819Sjkim/**************************************************************************** 386323819Sjkim * * SCSI Task Management messages 387323819Sjkim * ****************************************************************************/ 388323819Sjkim 389323819Sjkim/*SCSI Task Management Request Message */ 390323819Sjkimtypedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST { 391323819Sjkim u_int16_t DevHandle; /*0x00 */ 392323819Sjkim u_int8_t ChainOffset; /*0x02 */ 393323819Sjkim u_int8_t Function; /*0x03 */ 394323819Sjkim u_int8_t Reserved1; /*0x04 */ 395323819Sjkim u_int8_t TaskType; /*0x05 */ 396323819Sjkim u_int8_t Reserved2; /*0x06 */ 397323819Sjkim u_int8_t MsgFlags; /*0x07 */ 398323819Sjkim u_int8_t VP_ID; /*0x08 */ 399323819Sjkim u_int8_t VF_ID; /*0x09 */ 400323819Sjkim u_int16_t Reserved3; /*0x0A */ 401323819Sjkim u_int8_t LUN[8]; /*0x0C */ 402323819Sjkim u_int32_t Reserved4[7]; /*0x14 */ 403323819Sjkim u_int16_t TaskMID; /*0x30 */ 404323819Sjkim u_int16_t Reserved5; /*0x32 */ 405323819Sjkim} MPI2_SCSI_TASK_MANAGE_REQUEST; 406323819Sjkim 407323819Sjkim/*SCSI Task Management Reply Message */ 408323819Sjkimtypedef struct _MPI2_SCSI_TASK_MANAGE_REPLY { 409323819Sjkim u_int16_t DevHandle; /*0x00 */ 410323819Sjkim u_int8_t MsgLength; /*0x02 */ 411323819Sjkim u_int8_t Function; /*0x03 */ 412323819Sjkim u_int8_t ResponseCode; /*0x04 */ 413323819Sjkim u_int8_t TaskType; /*0x05 */ 414323819Sjkim u_int8_t Reserved1; /*0x06 */ 415323819Sjkim u_int8_t MsgFlags; /*0x07 */ 416323819Sjkim u_int8_t VP_ID; /*0x08 */ 417323819Sjkim u_int8_t VF_ID; /*0x09 */ 418323819Sjkim u_int16_t Reserved2; /*0x0A */ 419323819Sjkim u_int16_t Reserved3; /*0x0C */ 420323819Sjkim u_int16_t IOCStatus; /*0x0E */ 421323819Sjkim u_int32_t IOCLogInfo; /*0x10 */ 422323819Sjkim u_int32_t TerminationCount; /*0x14 */ 423323819Sjkim u_int32_t ResponseInfo; /*0x18 */ 424323819Sjkim} MPI2_SCSI_TASK_MANAGE_REPLY; 425323819Sjkim 426323819Sjkimtypedef struct _MR_TM_REQUEST { 427323819Sjkim char request[128]; 428323819Sjkim} MR_TM_REQUEST; 429323819Sjkim 430323819Sjkimtypedef struct _MR_TM_REPLY { 431323819Sjkim char reply[128]; 432323819Sjkim} MR_TM_REPLY; 433323819Sjkim 434323819Sjkim/* SCSI Task Management Request Message */ 435323819Sjkimtypedef struct _MR_TASK_MANAGE_REQUEST { 436323819Sjkim /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 437323819Sjkim MR_TM_REQUEST TmRequest; 438323819Sjkim union { 439323819Sjkim struct { 440323819Sjkim u_int32_t isTMForLD:1; 441323819Sjkim u_int32_t isTMForPD:1; 442323819Sjkim u_int32_t reserved1:30; 443323819Sjkim u_int32_t reserved2; 444323819Sjkim } tmReqFlags; 445323819Sjkim MR_TM_REPLY TMReply; 446323819Sjkim } uTmReqReply; 447323819Sjkim} MR_TASK_MANAGE_REQUEST; 448323819Sjkim 449323819Sjkim/* TaskType values */ 450323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 451323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 452323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 453323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 454323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 455323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 456323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 457323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 458323819Sjkim#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 459323819Sjkim 460323819Sjkim/* ResponseCode values */ 461323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 462323819Sjkim#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 463323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 464323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 465323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 466323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 467323819Sjkim#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 468323819Sjkim#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 469323819Sjkim 470265555Sambrisko/* 471272744Skadesai * RAID SCSI IO Request Message Total SGE count will be one less than 472272744Skadesai * _MPI2_SCSI_IO_REQUEST 473265555Sambrisko */ 474272744Skadesaitypedef struct _MPI2_RAID_SCSI_IO_REQUEST { 475272744Skadesai u_int16_t DevHandle; /* 0x00 */ 476272744Skadesai u_int8_t ChainOffset; /* 0x02 */ 477272744Skadesai u_int8_t Function; /* 0x03 */ 478272744Skadesai u_int16_t Reserved1; /* 0x04 */ 479272744Skadesai u_int8_t Reserved2; /* 0x06 */ 480272744Skadesai u_int8_t MsgFlags; /* 0x07 */ 481272744Skadesai u_int8_t VP_ID; /* 0x08 */ 482272744Skadesai u_int8_t VF_ID; /* 0x09 */ 483272744Skadesai u_int16_t Reserved3; /* 0x0A */ 484272744Skadesai u_int32_t SenseBufferLowAddress;/* 0x0C */ 485272744Skadesai u_int16_t SGLFlags; /* 0x10 */ 486272744Skadesai u_int8_t SenseBufferLength; /* 0x12 */ 487272744Skadesai u_int8_t Reserved4; /* 0x13 */ 488272744Skadesai u_int8_t SGLOffset0; /* 0x14 */ 489272744Skadesai u_int8_t SGLOffset1; /* 0x15 */ 490272744Skadesai u_int8_t SGLOffset2; /* 0x16 */ 491272744Skadesai u_int8_t SGLOffset3; /* 0x17 */ 492272744Skadesai u_int32_t SkipCount; /* 0x18 */ 493272744Skadesai u_int32_t DataLength; /* 0x1C */ 494272744Skadesai u_int32_t BidirectionalDataLength; /* 0x20 */ 495272744Skadesai u_int16_t IoFlags; /* 0x24 */ 496272744Skadesai u_int16_t EEDPFlags; /* 0x26 */ 497272744Skadesai u_int32_t EEDPBlockSize; /* 0x28 */ 498272744Skadesai u_int32_t SecondaryReferenceTag;/* 0x2C */ 499272744Skadesai u_int16_t SecondaryApplicationTag; /* 0x30 */ 500272744Skadesai u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 501272744Skadesai u_int8_t LUN[8]; /* 0x34 */ 502272744Skadesai u_int32_t Control; /* 0x3C */ 503272744Skadesai MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 504342716Skadesai RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 505272744Skadesai MPI2_SGE_IO_UNION SGL; /* 0x80 */ 506272744Skadesai} MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 507272744SkadesaiMRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 508265555Sambrisko 509265555Sambrisko/* 510265555Sambrisko * MPT RAID MFA IO Descriptor. 511265555Sambrisko */ 512265555Sambriskotypedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 513272744Skadesai u_int32_t RequestFlags:8; 514272744Skadesai u_int32_t MessageAddress1:24; /* bits 31:8 */ 515272744Skadesai u_int32_t MessageAddress2; /* bits 61:32 */ 516272744Skadesai} MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 517265555Sambrisko 518265555Sambrisko/* Default Request Descriptor */ 519272744Skadesaitypedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 520272744Skadesai u_int8_t RequestFlags; /* 0x00 */ 521272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 522272744Skadesai u_int16_t SMID; /* 0x02 */ 523272744Skadesai u_int16_t LMID; /* 0x04 */ 524272744Skadesai u_int16_t DescriptorTypeDependent; /* 0x06 */ 525272744Skadesai} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 526272744Skadesai 527272744Skadesai MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 528272744SkadesaiMpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 529272744Skadesai 530265555Sambrisko/* High Priority Request Descriptor */ 531272744Skadesaitypedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 532272744Skadesai u_int8_t RequestFlags; /* 0x00 */ 533272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 534272744Skadesai u_int16_t SMID; /* 0x02 */ 535272744Skadesai u_int16_t LMID; /* 0x04 */ 536272744Skadesai u_int16_t Reserved1; /* 0x06 */ 537272744Skadesai} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 538272744Skadesai 539272744Skadesai MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 540272744SkadesaiMpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 541272744Skadesai 542265555Sambrisko/* SCSI IO Request Descriptor */ 543272744Skadesaitypedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 544272744Skadesai u_int8_t RequestFlags; /* 0x00 */ 545272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 546272744Skadesai u_int16_t SMID; /* 0x02 */ 547272744Skadesai u_int16_t LMID; /* 0x04 */ 548272744Skadesai u_int16_t DevHandle; /* 0x06 */ 549272744Skadesai} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 550265555Sambrisko 551272744Skadesai MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 552272744SkadesaiMpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 553272744Skadesai 554265555Sambrisko/* SCSI Target Request Descriptor */ 555272744Skadesaitypedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 556272744Skadesai u_int8_t RequestFlags; /* 0x00 */ 557272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 558272744Skadesai u_int16_t SMID; /* 0x02 */ 559272744Skadesai u_int16_t LMID; /* 0x04 */ 560272744Skadesai u_int16_t IoIndex; /* 0x06 */ 561272744Skadesai} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 562265555Sambrisko 563272744Skadesai MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 564272744SkadesaiMpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 565272744Skadesai 566265555Sambrisko/* RAID Accelerator Request Descriptor */ 567272744Skadesaitypedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 568272744Skadesai u_int8_t RequestFlags; /* 0x00 */ 569272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 570272744Skadesai u_int16_t SMID; /* 0x02 */ 571272744Skadesai u_int16_t LMID; /* 0x04 */ 572272744Skadesai u_int16_t Reserved; /* 0x06 */ 573272744Skadesai} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 574265555Sambrisko 575272744Skadesai MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 576272744SkadesaiMpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 577272744Skadesai 578265555Sambrisko/* union of Request Descriptors */ 579272744Skadesaitypedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 580272744Skadesai MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 581272744Skadesai MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 582272744Skadesai MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 583272744Skadesai MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 584272744Skadesai MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 585272744Skadesai MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 586272744Skadesai union { 587272744Skadesai struct { 588272744Skadesai u_int32_t low; 589272744Skadesai u_int32_t high; 590272744Skadesai } u; 591272744Skadesai u_int64_t Words; 592272744Skadesai } addr; 593272744Skadesai} MRSAS_REQUEST_DESCRIPTOR_UNION; 594265555Sambrisko 595265555Sambrisko/* Default Reply Descriptor */ 596272744Skadesaitypedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 597272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 598272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 599272744Skadesai u_int16_t DescriptorTypeDependent1; /* 0x02 */ 600272744Skadesai u_int32_t DescriptorTypeDependent2; /* 0x04 */ 601272744Skadesai} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 602272744SkadesaiMpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 603265555Sambrisko 604265555Sambrisko/* Address Reply Descriptor */ 605272744Skadesaitypedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 606272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 607272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 608272744Skadesai u_int16_t SMID; /* 0x02 */ 609272744Skadesai u_int32_t ReplyFrameAddress; /* 0x04 */ 610272744Skadesai} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 611272744SkadesaiMpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 612265555Sambrisko 613265555Sambrisko/* SCSI IO Success Reply Descriptor */ 614272744Skadesaitypedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 615272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 616272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 617272744Skadesai u_int16_t SMID; /* 0x02 */ 618272744Skadesai u_int16_t TaskTag; /* 0x04 */ 619272744Skadesai u_int16_t Reserved1; /* 0x06 */ 620272744Skadesai} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 621265555Sambrisko 622272744Skadesai MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 623272744SkadesaiMpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 624272744Skadesai 625265555Sambrisko/* TargetAssist Success Reply Descriptor */ 626272744Skadesaitypedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 627272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 628272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 629272744Skadesai u_int16_t SMID; /* 0x02 */ 630272744Skadesai u_int8_t SequenceNumber; /* 0x04 */ 631272744Skadesai u_int8_t Reserved1; /* 0x05 */ 632272744Skadesai u_int16_t IoIndex; /* 0x06 */ 633272744Skadesai} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 634265555Sambrisko 635272744Skadesai MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 636272744SkadesaiMpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 637272744Skadesai 638265555Sambrisko/* Target Command Buffer Reply Descriptor */ 639272744Skadesaitypedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 640272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 641272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 642272744Skadesai u_int8_t VP_ID; /* 0x02 */ 643272744Skadesai u_int8_t Flags; /* 0x03 */ 644272744Skadesai u_int16_t InitiatorDevHandle; /* 0x04 */ 645272744Skadesai u_int16_t IoIndex; /* 0x06 */ 646272744Skadesai} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 647265555Sambrisko 648272744Skadesai MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 649272744SkadesaiMpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 650272744Skadesai 651265555Sambrisko/* RAID Accelerator Success Reply Descriptor */ 652272744Skadesaitypedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 653272744Skadesai u_int8_t ReplyFlags; /* 0x00 */ 654272744Skadesai u_int8_t MSIxIndex; /* 0x01 */ 655272744Skadesai u_int16_t SMID; /* 0x02 */ 656272744Skadesai u_int32_t Reserved; /* 0x04 */ 657272744Skadesai} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 658265555Sambrisko 659272744Skadesai MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 660272744SkadesaiMpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 661272744Skadesai 662265555Sambrisko/* union of Reply Descriptors */ 663272744Skadesaitypedef union _MPI2_REPLY_DESCRIPTORS_UNION { 664272744Skadesai MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 665272744Skadesai MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 666272744Skadesai MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 667272744Skadesai MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 668272744Skadesai MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 669272744Skadesai MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 670272744Skadesai u_int64_t Words; 671272744Skadesai} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 672272744SkadesaiMpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 673265555Sambrisko 674273377Shselaskytypedef union { 675272744Skadesai volatile unsigned int val; 676273377Shselasky unsigned int val_rdonly; 677273040Skadesai} mrsas_atomic_t; 678265555Sambrisko 679273040Skadesai#define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 680273040Skadesai#define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 681273040Skadesai#define mrsas_atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 682273040Skadesai#define mrsas_atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 683265555Sambrisko 684342716Skadesaistatic inline int 685342716Skadesaimrsas_atomic_inc_return(mrsas_atomic_t *v) 686342716Skadesai{ 687342716Skadesai return 1 + atomic_fetchadd_int(&(v)->val, 1); 688342716Skadesai} 689342716Skadesai 690265555Sambrisko/* IOCInit Request message */ 691272744Skadesaitypedef struct _MPI2_IOC_INIT_REQUEST { 692272744Skadesai u_int8_t WhoInit; /* 0x00 */ 693272744Skadesai u_int8_t Reserved1; /* 0x01 */ 694272744Skadesai u_int8_t ChainOffset; /* 0x02 */ 695272744Skadesai u_int8_t Function; /* 0x03 */ 696272744Skadesai u_int16_t Reserved2; /* 0x04 */ 697272744Skadesai u_int8_t Reserved3; /* 0x06 */ 698272744Skadesai u_int8_t MsgFlags; /* 0x07 */ 699272744Skadesai u_int8_t VP_ID; /* 0x08 */ 700272744Skadesai u_int8_t VF_ID; /* 0x09 */ 701272744Skadesai u_int16_t Reserved4; /* 0x0A */ 702272744Skadesai u_int16_t MsgVersion; /* 0x0C */ 703272744Skadesai u_int16_t HeaderVersion; /* 0x0E */ 704272744Skadesai u_int32_t Reserved5; /* 0x10 */ 705272744Skadesai u_int16_t Reserved6; /* 0x14 */ 706342716Skadesai u_int8_t HostPageSize; /* 0x16 */ 707272744Skadesai u_int8_t HostMSIxVectors; /* 0x17 */ 708272744Skadesai u_int16_t Reserved8; /* 0x18 */ 709272744Skadesai u_int16_t SystemRequestFrameSize; /* 0x1A */ 710272744Skadesai u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 711272744Skadesai u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 712272744Skadesai u_int32_t SenseBufferAddressHigh; /* 0x20 */ 713272744Skadesai u_int32_t SystemReplyAddressHigh; /* 0x24 */ 714272744Skadesai u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 715272744Skadesai u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 716272744Skadesai u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 717272744Skadesai u_int64_t TimeStamp; /* 0x40 */ 718272744Skadesai} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 719272744SkadesaiMpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 720265555Sambrisko 721265555Sambrisko/* 722265555Sambrisko * MR private defines 723265555Sambrisko */ 724272744Skadesai#define MR_PD_INVALID 0xFFFF 725342716Skadesai#define MR_DEVHANDLE_INVALID 0xFFFF 726272744Skadesai#define MAX_SPAN_DEPTH 8 727272744Skadesai#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 728272744Skadesai#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 729272744Skadesai#define MAX_ROW_SIZE 32 730272744Skadesai#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 731272744Skadesai#define MAX_LOGICAL_DRIVES 64 732272744Skadesai#define MAX_LOGICAL_DRIVES_EXT 256 733342716Skadesai#define MAX_LOGICAL_DRIVES_DYN 512 734265555Sambrisko 735272744Skadesai#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 736272744Skadesai#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 737265555Sambrisko 738272744Skadesai#define MAX_ARRAYS 128 739272744Skadesai#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 740272735Skadesai 741272744Skadesai#define MAX_ARRAYS_EXT 256 742272744Skadesai#define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 743342716Skadesai#define MAX_API_ARRAYS_DYN 512 744272735Skadesai 745272744Skadesai#define MAX_PHYSICAL_DEVICES 256 746272744Skadesai#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 747342716Skadesai#define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 748272744Skadesai#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 749299667Skadesai#define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 750323819Sjkim#define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100 751272735Skadesai 752342716Skadesai#define MR_DCMD_PD_GET_INFO 0x02020000 753272744Skadesai#define MRSAS_MAX_PD_CHANNELS 1 754272744Skadesai#define MRSAS_MAX_LD_CHANNELS 1 755272744Skadesai#define MRSAS_MAX_DEV_PER_CHANNEL 256 756272744Skadesai#define MRSAS_DEFAULT_INIT_ID -1 757272744Skadesai#define MRSAS_MAX_LUN 8 758272744Skadesai#define MRSAS_DEFAULT_CMD_PER_LUN 256 759272744Skadesai#define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 760272744Skadesai MRSAS_MAX_DEV_PER_CHANNEL) 761272744Skadesai#define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 762272744Skadesai MRSAS_MAX_DEV_PER_CHANNEL) 763272735Skadesai 764272735Skadesai 765272744Skadesai#define VD_EXT_DEBUG 0 766323819Sjkim#define TM_DEBUG 1 767272735Skadesai 768272744Skadesai/******************************************************************* 769272744Skadesai * RAID map related structures 770265555Sambrisko ********************************************************************/ 771272735Skadesai#pragma pack(1) 772265555Sambriskotypedef struct _MR_DEV_HANDLE_INFO { 773272744Skadesai u_int16_t curDevHdl; 774272744Skadesai u_int8_t validHandles; 775342716Skadesai u_int8_t interfaceType; 776272744Skadesai u_int16_t devHandle[2]; 777272744Skadesai} MR_DEV_HANDLE_INFO; 778272744Skadesai 779272735Skadesai#pragma pack() 780272744Skadesai 781265555Sambriskotypedef struct _MR_ARRAY_INFO { 782272744Skadesai u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 783272744Skadesai} MR_ARRAY_INFO; 784272744Skadesai 785265555Sambriskotypedef struct _MR_QUAD_ELEMENT { 786272744Skadesai u_int64_t logStart; 787272744Skadesai u_int64_t logEnd; 788272744Skadesai u_int64_t offsetInSpan; 789272744Skadesai u_int32_t diff; 790272744Skadesai u_int32_t reserved1; 791272744Skadesai} MR_QUAD_ELEMENT; 792272744Skadesai 793265555Sambriskotypedef struct _MR_SPAN_INFO { 794272744Skadesai u_int32_t noElements; 795272744Skadesai u_int32_t reserved1; 796272744Skadesai MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 797272744Skadesai} MR_SPAN_INFO; 798265555Sambrisko 799272744Skadesaitypedef struct _MR_LD_SPAN_ { 800272744Skadesai u_int64_t startBlk; 801272744Skadesai u_int64_t numBlks; 802272744Skadesai u_int16_t arrayRef; 803272744Skadesai u_int8_t spanRowSize; 804272744Skadesai u_int8_t spanRowDataSize; 805272744Skadesai u_int8_t reserved[4]; 806272744Skadesai} MR_LD_SPAN; 807272744Skadesai 808265555Sambriskotypedef struct _MR_SPAN_BLOCK_INFO { 809272744Skadesai u_int64_t num_rows; 810272744Skadesai MR_LD_SPAN span; 811272744Skadesai MR_SPAN_INFO block_span_info; 812272744Skadesai} MR_SPAN_BLOCK_INFO; 813265555Sambrisko 814265555Sambriskotypedef struct _MR_LD_RAID { 815272744Skadesai struct { 816272744Skadesai u_int32_t fpCapable:1; 817342716Skadesai u_int32_t raCapable:1; 818342716Skadesai u_int32_t reserved5:2; 819272744Skadesai u_int32_t ldPiMode:4; 820272744Skadesai u_int32_t pdPiMode:4; 821272744Skadesai u_int32_t encryptionType:8; 822272744Skadesai u_int32_t fpWriteCapable:1; 823272744Skadesai u_int32_t fpReadCapable:1; 824272744Skadesai u_int32_t fpWriteAcrossStripe:1; 825272744Skadesai u_int32_t fpReadAcrossStripe:1; 826272744Skadesai u_int32_t fpNonRWCapable:1; 827323819Sjkim u_int32_t tmCapable:1; 828342716Skadesai u_int32_t fpCacheBypassCapable:1; 829342716Skadesai u_int32_t reserved4:5; 830272744Skadesai } capability; 831272744Skadesai u_int32_t reserved6; 832272744Skadesai u_int64_t size; 833265555Sambrisko 834272744Skadesai u_int8_t spanDepth; 835272744Skadesai u_int8_t level; 836272744Skadesai u_int8_t stripeShift; 837272744Skadesai u_int8_t rowSize; 838265555Sambrisko 839272744Skadesai u_int8_t rowDataSize; 840272744Skadesai u_int8_t writeMode; 841272744Skadesai u_int8_t PRL; 842272744Skadesai u_int8_t SRL; 843265555Sambrisko 844272744Skadesai u_int16_t targetId; 845272744Skadesai u_int8_t ldState; 846272744Skadesai u_int8_t regTypeReqOnWrite; 847272744Skadesai u_int8_t modFactor; 848272744Skadesai u_int8_t regTypeReqOnRead; 849272744Skadesai u_int16_t seqNum; 850265555Sambrisko 851272744Skadesai struct { 852272744Skadesai u_int32_t ldSyncRequired:1; 853272744Skadesai u_int32_t regTypeReqOnReadLsValid:1; 854272744Skadesai u_int32_t reserved:30; 855272744Skadesai } flags; 856265555Sambrisko 857272744Skadesai u_int8_t LUN[8]; 858272744Skadesai u_int8_t fpIoTimeoutForLd; 859272744Skadesai u_int8_t reserved2[3]; 860272744Skadesai u_int32_t logicalBlockLength; 861272744Skadesai struct { 862272744Skadesai u_int32_t LdPiExp:4; 863272744Skadesai u_int32_t LdLogicalBlockExp:4; 864272744Skadesai u_int32_t reserved1:24; 865272744Skadesai } exponent; 866272744Skadesai u_int8_t reserved3[0x80 - 0x38]; 867272744Skadesai} MR_LD_RAID; 868265555Sambrisko 869265555Sambriskotypedef struct _MR_LD_SPAN_MAP { 870272744Skadesai MR_LD_RAID ldRaid; 871272744Skadesai u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 872272744Skadesai MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 873272744Skadesai} MR_LD_SPAN_MAP; 874265555Sambrisko 875265555Sambriskotypedef struct _MR_FW_RAID_MAP { 876272744Skadesai u_int32_t totalSize; 877272744Skadesai union { 878272744Skadesai struct { 879272744Skadesai u_int32_t maxLd; 880272744Skadesai u_int32_t maxSpanDepth; 881272744Skadesai u_int32_t maxRowSize; 882272744Skadesai u_int32_t maxPdCount; 883272744Skadesai u_int32_t maxArrays; 884272744Skadesai } validationInfo; 885272744Skadesai u_int32_t version[5]; 886272744Skadesai u_int32_t reserved1[5]; 887272744Skadesai } raid_desc; 888272744Skadesai u_int32_t ldCount; 889272744Skadesai u_int32_t Reserved1; 890265555Sambrisko 891272744Skadesai /* 892272744Skadesai * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 893272744Skadesai * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 894272744Skadesai * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 895272744Skadesai * 0x0,.....]. This is to help reduce the entire strcture size if 896272744Skadesai * there are few LDs or driver is looking info for 1 LD only. 897272744Skadesai */ 898272744Skadesai u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 899272744Skadesai u_int8_t fpPdIoTimeoutSec; 900272744Skadesai u_int8_t reserved2[7]; 901272744Skadesai MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 902272744Skadesai MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 903272744Skadesai MR_LD_SPAN_MAP ldSpanMap[1]; 904272744Skadesai} MR_FW_RAID_MAP; 905272735Skadesai 906272744Skadesai 907272735Skadesaitypedef struct _MR_FW_RAID_MAP_EXT { 908272735Skadesai /* Not used in new map */ 909272744Skadesai u_int32_t reserved; 910272735Skadesai 911272735Skadesai union { 912272744Skadesai struct { 913272744Skadesai u_int32_t maxLd; 914272744Skadesai u_int32_t maxSpanDepth; 915272744Skadesai u_int32_t maxRowSize; 916272744Skadesai u_int32_t maxPdCount; 917272744Skadesai u_int32_t maxArrays; 918272744Skadesai } validationInfo; 919272744Skadesai u_int32_t version[5]; 920272744Skadesai u_int32_t reserved1[5]; 921272744Skadesai } fw_raid_desc; 922272735Skadesai 923272744Skadesai u_int8_t fpPdIoTimeoutSec; 924272744Skadesai u_int8_t reserved2[7]; 925272735Skadesai 926272744Skadesai u_int16_t ldCount; 927272744Skadesai u_int16_t arCount; 928272744Skadesai u_int16_t spanCount; 929272744Skadesai u_int16_t reserve3; 930272735Skadesai 931272744Skadesai MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 932272744Skadesai u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 933272744Skadesai MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 934272744Skadesai MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 935272744Skadesai} MR_FW_RAID_MAP_EXT; 936272735Skadesai 937272735Skadesai 938272735Skadesaitypedef struct _MR_DRV_RAID_MAP { 939272744Skadesai /* 940272744Skadesai * Total size of this structure, including this field. This feild 941272744Skadesai * will be manupulated by driver for ext raid map, else pick the 942272744Skadesai * value from firmware raid map. 943272735Skadesai */ 944272744Skadesai u_int32_t totalSize; 945272735Skadesai 946272735Skadesai union { 947272744Skadesai struct { 948272744Skadesai u_int32_t maxLd; 949272744Skadesai u_int32_t maxSpanDepth; 950272744Skadesai u_int32_t maxRowSize; 951272744Skadesai u_int32_t maxPdCount; 952272744Skadesai u_int32_t maxArrays; 953272744Skadesai } validationInfo; 954272744Skadesai u_int32_t version[5]; 955272744Skadesai u_int32_t reserved1[5]; 956272744Skadesai } drv_raid_desc; 957272735Skadesai 958272744Skadesai /* timeout value used by driver in FP IOs */ 959272744Skadesai u_int8_t fpPdIoTimeoutSec; 960272744Skadesai u_int8_t reserved2[7]; 961272735Skadesai 962272744Skadesai u_int16_t ldCount; 963272744Skadesai u_int16_t arCount; 964272744Skadesai u_int16_t spanCount; 965272744Skadesai u_int16_t reserve3; 966272735Skadesai 967342716Skadesai MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 968342716Skadesai u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 969342716Skadesai MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 970272744Skadesai MR_LD_SPAN_MAP ldSpanMap[1]; 971272735Skadesai 972272744Skadesai} MR_DRV_RAID_MAP; 973272735Skadesai 974272744Skadesai/* 975272744Skadesai * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 976272744Skadesai * created to sync with old raid. And it is mainly for code re-use purpose. 977272735Skadesai */ 978272735Skadesai 979272735Skadesai#pragma pack(1) 980272735Skadesaitypedef struct _MR_DRV_RAID_MAP_ALL { 981272735Skadesai 982272744Skadesai MR_DRV_RAID_MAP raidMap; 983342716Skadesai MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 984272744Skadesai} MR_DRV_RAID_MAP_ALL; 985272744Skadesai 986272735Skadesai#pragma pack() 987272735Skadesai 988272744Skadesaitypedef struct _LD_LOAD_BALANCE_INFO { 989272744Skadesai u_int8_t loadBalanceFlag; 990272744Skadesai u_int8_t reserved1; 991282527Skadesai mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 992282527Skadesai u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 993272744Skadesai} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 994265555Sambrisko 995265555Sambrisko/* SPAN_SET is info caclulated from span info from Raid map per ld */ 996265555Sambriskotypedef struct _LD_SPAN_SET { 997272744Skadesai u_int64_t log_start_lba; 998272744Skadesai u_int64_t log_end_lba; 999272744Skadesai u_int64_t span_row_start; 1000272744Skadesai u_int64_t span_row_end; 1001272744Skadesai u_int64_t data_strip_start; 1002272744Skadesai u_int64_t data_strip_end; 1003272744Skadesai u_int64_t data_row_start; 1004272744Skadesai u_int64_t data_row_end; 1005272744Skadesai u_int8_t strip_offset[MAX_SPAN_DEPTH]; 1006272744Skadesai u_int32_t span_row_data_width; 1007272744Skadesai u_int32_t diff; 1008272744Skadesai u_int32_t reserved[2]; 1009272744Skadesai} LD_SPAN_SET, *PLD_SPAN_SET; 1010265555Sambrisko 1011265555Sambriskotypedef struct LOG_BLOCK_SPAN_INFO { 1012272744Skadesai LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1013272744Skadesai} LD_SPAN_INFO, *PLD_SPAN_INFO; 1014265555Sambrisko 1015265555Sambrisko#pragma pack(1) 1016265555Sambriskotypedef struct _MR_FW_RAID_MAP_ALL { 1017272744Skadesai MR_FW_RAID_MAP raidMap; 1018272744Skadesai MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1019272744Skadesai} MR_FW_RAID_MAP_ALL; 1020272744Skadesai 1021265555Sambrisko#pragma pack() 1022265555Sambrisko 1023265555Sambriskostruct IO_REQUEST_INFO { 1024272744Skadesai u_int64_t ldStartBlock; 1025272744Skadesai u_int32_t numBlocks; 1026272744Skadesai u_int16_t ldTgtId; 1027272744Skadesai u_int8_t isRead; 1028272744Skadesai u_int16_t devHandle; 1029342716Skadesai u_int8_t pdInterface; 1030272744Skadesai u_int64_t pdBlock; 1031272744Skadesai u_int8_t fpOkForIo; 1032265555Sambrisko u_int8_t IoforUnevenSpan; 1033272744Skadesai u_int8_t start_span; 1034272744Skadesai u_int8_t reserved; 1035272744Skadesai u_int64_t start_row; 1036282527Skadesai /* span[7:5], arm[4:0] */ 1037282527Skadesai u_int8_t span_arm; 1038282527Skadesai u_int8_t pd_after_lb; 1039342716Skadesai boolean_t raCapable; 1040342716Skadesai u_int16_t r1_alt_dev_handle; 1041265555Sambrisko}; 1042265555Sambrisko 1043299667Skadesai/* 1044299667Skadesai * define MR_PD_CFG_SEQ structure for system PDs 1045299667Skadesai */ 1046299667Skadesaistruct MR_PD_CFG_SEQ { 1047299667Skadesai u_int16_t seqNum; 1048299667Skadesai u_int16_t devHandle; 1049323819Sjkim struct { 1050323819Sjkim u_int8_t tmCapable:1; 1051323819Sjkim u_int8_t reserved:7; 1052323819Sjkim } capability; 1053342716Skadesai u_int8_t reserved; 1054342716Skadesai u_int16_t pdTargetId; 1055299667Skadesai} __packed; 1056299667Skadesai 1057299667Skadesaistruct MR_PD_CFG_SEQ_NUM_SYNC { 1058299667Skadesai u_int32_t size; 1059299667Skadesai u_int32_t count; 1060299667Skadesai struct MR_PD_CFG_SEQ seq[1]; 1061299667Skadesai} __packed; 1062299667Skadesai 1063342716Skadesaitypedef struct _STREAM_DETECT { 1064342716Skadesai u_int64_t nextSeqLBA; 1065342716Skadesai struct megasas_cmd_fusion *first_cmd_fusion; 1066342716Skadesai struct megasas_cmd_fusion *last_cmd_fusion; 1067342716Skadesai u_int32_t countCmdsInStream; 1068342716Skadesai u_int16_t numSGEsInGroup; 1069342716Skadesai u_int8_t isRead; 1070342716Skadesai u_int8_t groupDepth; 1071342716Skadesai boolean_t groupFlush; 1072342716Skadesai u_int8_t reserved[7]; 1073342716Skadesai} STREAM_DETECT, *PTR_STREAM_DETECT; 1074299667Skadesai 1075342716Skadesaitypedef struct _LD_STREAM_DETECT { 1076342716Skadesai boolean_t writeBack; 1077342716Skadesai boolean_t FPWriteEnabled; 1078342716Skadesai boolean_t membersSSDs; 1079342716Skadesai boolean_t fpCacheBypassCapable; 1080342716Skadesai u_int32_t mruBitMap; 1081342716Skadesai volatile long iosToFware; 1082342716Skadesai volatile long writeBytesOutstanding; 1083342716Skadesai STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED]; 1084342716Skadesai} LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT; 1085342716Skadesai 1086342716Skadesai 1087265555Sambriskotypedef struct _MR_LD_TARGET_SYNC { 1088272744Skadesai u_int8_t targetId; 1089272744Skadesai u_int8_t reserved; 1090272744Skadesai u_int16_t seqNum; 1091272744Skadesai} MR_LD_TARGET_SYNC; 1092265555Sambrisko 1093342716Skadesai 1094342716Skadesai/* 1095342716Skadesai * RAID Map descriptor Types. 1096342716Skadesai * Each element should uniquely idetify one data structure in the RAID map 1097342716Skadesai */ 1098342716Skadesaitypedef enum _MR_RAID_MAP_DESC_TYPE { 1099342716Skadesai RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */ 1100342716Skadesai RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */ 1101342716Skadesai RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */ 1102342716Skadesai RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */ 1103342716Skadesai RAID_MAP_DESC_TYPE_COUNT, 1104342716Skadesai} MR_RAID_MAP_DESC_TYPE; 1105342716Skadesai 1106342716Skadesai/* 1107342716Skadesai * This table defines the offset, size and num elements of each descriptor 1108342716Skadesai * type in the RAID Map buffer 1109342716Skadesai */ 1110342716Skadesaitypedef struct _MR_RAID_MAP_DESC_TABLE { 1111342716Skadesai /* Raid map descriptor type */ 1112342716Skadesai u_int32_t raidMapDescType; 1113342716Skadesai /* Offset into the RAID map buffer where descriptor data is saved */ 1114342716Skadesai u_int32_t raidMapDescOffset; 1115342716Skadesai /* total size of the descriptor buffer */ 1116342716Skadesai u_int32_t raidMapDescBufferSize; 1117342716Skadesai /* Number of elements contained in the descriptor buffer */ 1118342716Skadesai u_int32_t raidMapDescElements; 1119342716Skadesai} MR_RAID_MAP_DESC_TABLE; 1120342716Skadesai 1121342716Skadesai/* 1122342716Skadesai * Dynamic Raid Map Structure. 1123342716Skadesai */ 1124342716Skadesaitypedef struct _MR_FW_RAID_MAP_DYNAMIC { 1125342716Skadesai u_int32_t raidMapSize; 1126342716Skadesai u_int32_t descTableOffset; 1127342716Skadesai u_int32_t descTableSize; 1128342716Skadesai u_int32_t descTableNumElements; 1129342716Skadesai u_int64_t PCIThresholdBandwidth; 1130342716Skadesai u_int32_t reserved2[3]; 1131342716Skadesai 1132342716Skadesai u_int8_t fpPdIoTimeoutSec; 1133342716Skadesai u_int8_t reserved3[3]; 1134342716Skadesai u_int32_t rmwFPSeqNum; 1135342716Skadesai u_int16_t ldCount; 1136342716Skadesai u_int16_t arCount; 1137342716Skadesai u_int16_t spanCount; 1138342716Skadesai u_int16_t reserved4[3]; 1139342716Skadesai 1140342716Skadesai /* 1141342716Skadesai * The below structure of pointers is only to be used by the driver. 1142342716Skadesai * This is added in the API to reduce the amount of code changes needed in 1143342716Skadesai * the driver to support dynamic RAID map. 1144342716Skadesai * Firmware should not update these pointers while preparing the raid map 1145342716Skadesai */ 1146342716Skadesai union { 1147342716Skadesai struct { 1148342716Skadesai MR_DEV_HANDLE_INFO *devHndlInfo; 1149342716Skadesai u_int16_t *ldTgtIdToLd; 1150342716Skadesai MR_ARRAY_INFO *arMapInfo; 1151342716Skadesai MR_LD_SPAN_MAP *ldSpanMap; 1152342716Skadesai } ptrStruct; 1153342716Skadesai u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT]; 1154342716Skadesai } RaidMapDescPtrs; 1155342716Skadesai 1156342716Skadesai /* 1157342716Skadesai * RAID Map descriptor table defines the layout of data in the RAID Map. 1158342716Skadesai * The size of the descriptor table itself could change. 1159342716Skadesai */ 1160342716Skadesai 1161342716Skadesai /* Variable Size descriptor Table. */ 1162342716Skadesai MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT]; 1163342716Skadesai /* Variable Size buffer containing all data */ 1164342716Skadesai u_int32_t raidMapDescData[1]; 1165342716Skadesai 1166342716Skadesai} MR_FW_RAID_MAP_DYNAMIC; 1167342716Skadesai 1168342716Skadesai 1169272744Skadesai#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1170272744Skadesai#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1171272744Skadesai#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1172272744Skadesai#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1173272744Skadesai#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1174272744Skadesai#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1175272744Skadesai#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1176265555Sambrisko 1177342716Skadesai/* Few NVME flags defines*/ 1178342716Skadesai#define MPI2_SGE_FLAGS_SHIFT (0x02) 1179342716Skadesai#define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1180342716Skadesai#define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1181342716Skadesai#define IEEE_SGE_FLAGS_FORMAT_PQI (0x01) 1182342716Skadesai#define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1183342716Skadesai#define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03) 1184342716Skadesai 1185342716Skadesai 1186342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1187342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1188342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04) 1189342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1190342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C) 1191342716Skadesai#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1192342716Skadesai 1193265555Sambriskounion desc_value { 1194272744Skadesai u_int64_t word; 1195272744Skadesai struct { 1196272744Skadesai u_int32_t low; 1197272744Skadesai u_int32_t high; 1198272744Skadesai } u; 1199265555Sambrisko}; 1200265555Sambrisko 1201272744Skadesai/******************************************************************* 1202272744Skadesai * Temporary command 1203265555Sambrisko ********************************************************************/ 1204265555Sambriskostruct mrsas_tmp_dcmd { 1205272744Skadesai bus_dma_tag_t tmp_dcmd_tag; 1206272744Skadesai bus_dmamap_t tmp_dcmd_dmamap; 1207272744Skadesai void *tmp_dcmd_mem; 1208272744Skadesai bus_addr_t tmp_dcmd_phys_addr; 1209265555Sambrisko}; 1210265555Sambrisko 1211342716Skadesai#define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1212342716Skadesai#define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1213342716Skadesai#define MR_MIN_MAP_SIZE 0x10000 1214342716Skadesai 1215342716Skadesai 1216272744Skadesai/******************************************************************* 1217272744Skadesai * Register set, included legacy controllers 1068 and 1078, 1218265555Sambrisko * structure extended for 1078 registers 1219272744Skadesai *******************************************************************/ 1220265555Sambrisko#pragma pack(1) 1221265555Sambriskotypedef struct _mrsas_register_set { 1222272744Skadesai u_int32_t doorbell; /* 0000h */ 1223272744Skadesai u_int32_t fusion_seq_offset; /* 0004h */ 1224272744Skadesai u_int32_t fusion_host_diag; /* 0008h */ 1225272744Skadesai u_int32_t reserved_01; /* 000Ch */ 1226265555Sambrisko 1227272744Skadesai u_int32_t inbound_msg_0; /* 0010h */ 1228272744Skadesai u_int32_t inbound_msg_1; /* 0014h */ 1229272744Skadesai u_int32_t outbound_msg_0; /* 0018h */ 1230272744Skadesai u_int32_t outbound_msg_1; /* 001Ch */ 1231265555Sambrisko 1232272744Skadesai u_int32_t inbound_doorbell; /* 0020h */ 1233272744Skadesai u_int32_t inbound_intr_status; /* 0024h */ 1234272744Skadesai u_int32_t inbound_intr_mask; /* 0028h */ 1235265555Sambrisko 1236272744Skadesai u_int32_t outbound_doorbell; /* 002Ch */ 1237272744Skadesai u_int32_t outbound_intr_status; /* 0030h */ 1238272744Skadesai u_int32_t outbound_intr_mask; /* 0034h */ 1239265555Sambrisko 1240272744Skadesai u_int32_t reserved_1[2]; /* 0038h */ 1241265555Sambrisko 1242272744Skadesai u_int32_t inbound_queue_port; /* 0040h */ 1243272744Skadesai u_int32_t outbound_queue_port; /* 0044h */ 1244265555Sambrisko 1245272744Skadesai u_int32_t reserved_2[9]; /* 0048h */ 1246272744Skadesai u_int32_t reply_post_host_index;/* 006Ch */ 1247272744Skadesai u_int32_t reserved_2_2[12]; /* 0070h */ 1248265555Sambrisko 1249272744Skadesai u_int32_t outbound_doorbell_clear; /* 00A0h */ 1250265555Sambrisko 1251272744Skadesai u_int32_t reserved_3[3]; /* 00A4h */ 1252265555Sambrisko 1253272744Skadesai u_int32_t outbound_scratch_pad; /* 00B0h */ 1254272744Skadesai u_int32_t outbound_scratch_pad_2; /* 00B4h */ 1255342716Skadesai u_int32_t outbound_scratch_pad_3; /* 00B8h */ 1256342716Skadesai u_int32_t outbound_scratch_pad_4; /* 00BCh */ 1257265555Sambrisko 1258272744Skadesai u_int32_t inbound_low_queue_port; /* 00C0h */ 1259265555Sambrisko 1260272744Skadesai u_int32_t inbound_high_queue_port; /* 00C4h */ 1261265555Sambrisko 1262342720Skadesai u_int32_t inbound_single_queue_port; /* 00C8h */ 1263272744Skadesai u_int32_t res_6[11]; /* CCh */ 1264272744Skadesai u_int32_t host_diag; 1265272744Skadesai u_int32_t seq_offset; 1266272744Skadesai u_int32_t index_registers[807]; /* 00CCh */ 1267272744Skadesai} mrsas_reg_set; 1268265555Sambrisko 1269265555Sambrisko#pragma pack() 1270265555Sambrisko 1271265555Sambrisko/******************************************************************* 1272265555Sambrisko * Firmware Interface Defines 1273265555Sambrisko ******************************************************************* 1274265555Sambrisko * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 1275265555Sambrisko * for protocol between the software and firmware. Commands are 1276265555Sambrisko * issued using "message frames". 1277265555Sambrisko ******************************************************************/ 1278265555Sambrisko/* 1279265555Sambrisko * FW posts its state in upper 4 bits of outbound_msg_0 register 1280265555Sambrisko */ 1281272744Skadesai#define MFI_STATE_MASK 0xF0000000 1282272744Skadesai#define MFI_STATE_UNDEFINED 0x00000000 1283272744Skadesai#define MFI_STATE_BB_INIT 0x10000000 1284272744Skadesai#define MFI_STATE_FW_INIT 0x40000000 1285272744Skadesai#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 1286272744Skadesai#define MFI_STATE_FW_INIT_2 0x70000000 1287272744Skadesai#define MFI_STATE_DEVICE_SCAN 0x80000000 1288272744Skadesai#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 1289272744Skadesai#define MFI_STATE_FLUSH_CACHE 0xA0000000 1290272744Skadesai#define MFI_STATE_READY 0xB0000000 1291272744Skadesai#define MFI_STATE_OPERATIONAL 0xC0000000 1292272744Skadesai#define MFI_STATE_FAULT 0xF0000000 1293272744Skadesai#define MFI_RESET_REQUIRED 0x00000001 1294272744Skadesai#define MFI_RESET_ADAPTER 0x00000002 1295272744Skadesai#define MEGAMFI_FRAME_SIZE 64 1296272744Skadesai#define MRSAS_MFI_FRAME_SIZE 1024 1297272744Skadesai#define MRSAS_MFI_SENSE_SIZE 128 1298265555Sambrisko 1299265555Sambrisko/* 1300265555Sambrisko * During FW init, clear pending cmds & reset state using inbound_msg_0 1301265555Sambrisko * 1302272744Skadesai * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1303272744Skadesai * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1304272744Skadesai * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1305272744Skadesai * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1306272744Skadesai * signal to FW to stop processing 1307265555Sambrisko */ 1308265555Sambrisko 1309272744Skadesai#define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1310272744Skadesai#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1311272744Skadesai#define DIAG_WRITE_ENABLE (0x00000080) 1312272744Skadesai#define DIAG_RESET_ADAPTER (0x00000004) 1313265555Sambrisko 1314272744Skadesai#define MFI_ADP_RESET 0x00000040 1315272744Skadesai#define MFI_INIT_ABORT 0x00000001 1316272744Skadesai#define MFI_INIT_READY 0x00000002 1317272744Skadesai#define MFI_INIT_MFIMODE 0x00000004 1318272744Skadesai#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1319272744Skadesai#define MFI_INIT_HOTPLUG 0x00000010 1320272744Skadesai#define MFI_STOP_ADP 0x00000020 1321272744Skadesai#define MFI_RESET_FLAGS MFI_INIT_READY| \ 1322272744Skadesai MFI_INIT_MFIMODE| \ 1323272744Skadesai MFI_INIT_ABORT 1324265555Sambrisko 1325265555Sambrisko/* 1326272744Skadesai * MFI frame flags 1327265555Sambrisko */ 1328272744Skadesai#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1329272744Skadesai#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1330272744Skadesai#define MFI_FRAME_SGL32 0x0000 1331272744Skadesai#define MFI_FRAME_SGL64 0x0002 1332272744Skadesai#define MFI_FRAME_SENSE32 0x0000 1333272744Skadesai#define MFI_FRAME_SENSE64 0x0004 1334272744Skadesai#define MFI_FRAME_DIR_NONE 0x0000 1335272744Skadesai#define MFI_FRAME_DIR_WRITE 0x0008 1336272744Skadesai#define MFI_FRAME_DIR_READ 0x0010 1337272744Skadesai#define MFI_FRAME_DIR_BOTH 0x0018 1338272744Skadesai#define MFI_FRAME_IEEE 0x0020 1339265555Sambrisko 1340265555Sambrisko/* 1341265555Sambrisko * Definition for cmd_status 1342265555Sambrisko */ 1343272744Skadesai#define MFI_CMD_STATUS_POLL_MODE 0xFF 1344265555Sambrisko 1345265555Sambrisko/* 1346265555Sambrisko * MFI command opcodes 1347265555Sambrisko */ 1348272744Skadesai#define MFI_CMD_INIT 0x00 1349272744Skadesai#define MFI_CMD_LD_READ 0x01 1350272744Skadesai#define MFI_CMD_LD_WRITE 0x02 1351272744Skadesai#define MFI_CMD_LD_SCSI_IO 0x03 1352272744Skadesai#define MFI_CMD_PD_SCSI_IO 0x04 1353272744Skadesai#define MFI_CMD_DCMD 0x05 1354272744Skadesai#define MFI_CMD_ABORT 0x06 1355272744Skadesai#define MFI_CMD_SMP 0x07 1356272744Skadesai#define MFI_CMD_STP 0x08 1357272744Skadesai#define MFI_CMD_INVALID 0xff 1358265555Sambrisko 1359272744Skadesai#define MR_DCMD_CTRL_GET_INFO 0x01010000 1360272744Skadesai#define MR_DCMD_LD_GET_LIST 0x03010000 1361272744Skadesai#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1362272744Skadesai#define MR_FLUSH_CTRL_CACHE 0x01 1363272744Skadesai#define MR_FLUSH_DISK_CACHE 0x02 1364265555Sambrisko 1365272744Skadesai#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1366272744Skadesai#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1367272744Skadesai#define MR_ENABLE_DRIVE_SPINDOWN 0x01 1368265555Sambrisko 1369272744Skadesai#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1370272744Skadesai#define MR_DCMD_CTRL_EVENT_GET 0x01040300 1371272744Skadesai#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1372272744Skadesai#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1373265555Sambrisko 1374272744Skadesai#define MR_DCMD_CLUSTER 0x08000000 1375272744Skadesai#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1376272744Skadesai#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1377272744Skadesai#define MR_DCMD_PD_LIST_QUERY 0x02010100 1378265555Sambrisko 1379272744Skadesai#define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1380272744Skadesai#define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1381272744Skadesai#define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1382272744Skadesai#define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1383272744Skadesai#define MAX_MR_ROW_SIZE 32 1384272744Skadesai#define MR_CPX_DIR_WRITE 1 1385272744Skadesai#define MR_CPX_DIR_READ 0 1386272744Skadesai#define MR_CPX_VERSION 1 1387265555Sambrisko 1388272744Skadesai#define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1389265555Sambrisko 1390272744Skadesai#define MR_EVT_CFG_CLEARED 0x0004 1391265555Sambrisko 1392272744Skadesai#define MR_EVT_LD_STATE_CHANGE 0x0051 1393272744Skadesai#define MR_EVT_PD_INSERTED 0x005b 1394272744Skadesai#define MR_EVT_PD_REMOVED 0x0070 1395272744Skadesai#define MR_EVT_LD_CREATED 0x008a 1396272744Skadesai#define MR_EVT_LD_DELETED 0x008b 1397272744Skadesai#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1398272744Skadesai#define MR_EVT_LD_OFFLINE 0x00fc 1399272744Skadesai#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1400272744Skadesai#define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1401265555Sambrisko 1402265555Sambrisko/* 1403265555Sambrisko * MFI command completion codes 1404265555Sambrisko */ 1405265555Sambriskoenum MFI_STAT { 1406272744Skadesai MFI_STAT_OK = 0x00, 1407272744Skadesai MFI_STAT_INVALID_CMD = 0x01, 1408272744Skadesai MFI_STAT_INVALID_DCMD = 0x02, 1409272744Skadesai MFI_STAT_INVALID_PARAMETER = 0x03, 1410272744Skadesai MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1411272744Skadesai MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1412272744Skadesai MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1413272744Skadesai MFI_STAT_APP_IN_USE = 0x07, 1414272744Skadesai MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1415272744Skadesai MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1416272744Skadesai MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1417272744Skadesai MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1418272744Skadesai MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1419272744Skadesai MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1420272744Skadesai MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1421272744Skadesai MFI_STAT_FLASH_BUSY = 0x0f, 1422272744Skadesai MFI_STAT_FLASH_ERROR = 0x10, 1423272744Skadesai MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1424272744Skadesai MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1425272744Skadesai MFI_STAT_FLASH_NOT_OPEN = 0x13, 1426272744Skadesai MFI_STAT_FLASH_NOT_STARTED = 0x14, 1427272744Skadesai MFI_STAT_FLUSH_FAILED = 0x15, 1428272744Skadesai MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1429272744Skadesai MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1430272744Skadesai MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1431272744Skadesai MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1432272744Skadesai MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1433272744Skadesai MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1434272744Skadesai MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1435272744Skadesai MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1436272744Skadesai MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1437272744Skadesai MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1438272744Skadesai MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1439272744Skadesai MFI_STAT_MFC_HW_ERROR = 0x21, 1440272744Skadesai MFI_STAT_NO_HW_PRESENT = 0x22, 1441272744Skadesai MFI_STAT_NOT_FOUND = 0x23, 1442272744Skadesai MFI_STAT_NOT_IN_ENCL = 0x24, 1443272744Skadesai MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1444272744Skadesai MFI_STAT_PD_TYPE_WRONG = 0x26, 1445272744Skadesai MFI_STAT_PR_DISABLED = 0x27, 1446272744Skadesai MFI_STAT_ROW_INDEX_INVALID = 0x28, 1447272744Skadesai MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1448272744Skadesai MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1449272744Skadesai MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1450272744Skadesai MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1451272744Skadesai MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1452272744Skadesai MFI_STAT_SCSI_IO_FAILED = 0x2e, 1453272744Skadesai MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1454272744Skadesai MFI_STAT_SHUTDOWN_FAILED = 0x30, 1455272744Skadesai MFI_STAT_TIME_NOT_SET = 0x31, 1456272744Skadesai MFI_STAT_WRONG_STATE = 0x32, 1457272744Skadesai MFI_STAT_LD_OFFLINE = 0x33, 1458272744Skadesai MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1459272744Skadesai MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1460272744Skadesai MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1461272744Skadesai MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1462272744Skadesai MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1463272744Skadesai MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1464265555Sambrisko 1465272744Skadesai MFI_STAT_INVALID_STATUS = 0xFF 1466265555Sambrisko}; 1467265555Sambrisko 1468265555Sambrisko/* 1469265555Sambrisko * Number of mailbox bytes in DCMD message frame 1470265555Sambrisko */ 1471272744Skadesai#define MFI_MBOX_SIZE 12 1472265555Sambrisko 1473265555Sambriskoenum MR_EVT_CLASS { 1474265555Sambrisko 1475272744Skadesai MR_EVT_CLASS_DEBUG = -2, 1476272744Skadesai MR_EVT_CLASS_PROGRESS = -1, 1477272744Skadesai MR_EVT_CLASS_INFO = 0, 1478272744Skadesai MR_EVT_CLASS_WARNING = 1, 1479272744Skadesai MR_EVT_CLASS_CRITICAL = 2, 1480272744Skadesai MR_EVT_CLASS_FATAL = 3, 1481272744Skadesai MR_EVT_CLASS_DEAD = 4, 1482265555Sambrisko 1483265555Sambrisko}; 1484265555Sambrisko 1485265555Sambriskoenum MR_EVT_LOCALE { 1486265555Sambrisko 1487272744Skadesai MR_EVT_LOCALE_LD = 0x0001, 1488272744Skadesai MR_EVT_LOCALE_PD = 0x0002, 1489272744Skadesai MR_EVT_LOCALE_ENCL = 0x0004, 1490272744Skadesai MR_EVT_LOCALE_BBU = 0x0008, 1491272744Skadesai MR_EVT_LOCALE_SAS = 0x0010, 1492272744Skadesai MR_EVT_LOCALE_CTRL = 0x0020, 1493272744Skadesai MR_EVT_LOCALE_CONFIG = 0x0040, 1494272744Skadesai MR_EVT_LOCALE_CLUSTER = 0x0080, 1495272744Skadesai MR_EVT_LOCALE_ALL = 0xffff, 1496265555Sambrisko 1497265555Sambrisko}; 1498265555Sambrisko 1499265555Sambriskoenum MR_EVT_ARGS { 1500265555Sambrisko 1501272744Skadesai MR_EVT_ARGS_NONE, 1502272744Skadesai MR_EVT_ARGS_CDB_SENSE, 1503272744Skadesai MR_EVT_ARGS_LD, 1504272744Skadesai MR_EVT_ARGS_LD_COUNT, 1505272744Skadesai MR_EVT_ARGS_LD_LBA, 1506272744Skadesai MR_EVT_ARGS_LD_OWNER, 1507272744Skadesai MR_EVT_ARGS_LD_LBA_PD_LBA, 1508272744Skadesai MR_EVT_ARGS_LD_PROG, 1509272744Skadesai MR_EVT_ARGS_LD_STATE, 1510272744Skadesai MR_EVT_ARGS_LD_STRIP, 1511272744Skadesai MR_EVT_ARGS_PD, 1512272744Skadesai MR_EVT_ARGS_PD_ERR, 1513272744Skadesai MR_EVT_ARGS_PD_LBA, 1514272744Skadesai MR_EVT_ARGS_PD_LBA_LD, 1515272744Skadesai MR_EVT_ARGS_PD_PROG, 1516272744Skadesai MR_EVT_ARGS_PD_STATE, 1517272744Skadesai MR_EVT_ARGS_PCI, 1518272744Skadesai MR_EVT_ARGS_RATE, 1519272744Skadesai MR_EVT_ARGS_STR, 1520272744Skadesai MR_EVT_ARGS_TIME, 1521272744Skadesai MR_EVT_ARGS_ECC, 1522272744Skadesai MR_EVT_ARGS_LD_PROP, 1523272744Skadesai MR_EVT_ARGS_PD_SPARE, 1524272744Skadesai MR_EVT_ARGS_PD_INDEX, 1525272744Skadesai MR_EVT_ARGS_DIAG_PASS, 1526272744Skadesai MR_EVT_ARGS_DIAG_FAIL, 1527272744Skadesai MR_EVT_ARGS_PD_LBA_LBA, 1528272744Skadesai MR_EVT_ARGS_PORT_PHY, 1529272744Skadesai MR_EVT_ARGS_PD_MISSING, 1530272744Skadesai MR_EVT_ARGS_PD_ADDRESS, 1531272744Skadesai MR_EVT_ARGS_BITMAP, 1532272744Skadesai MR_EVT_ARGS_CONNECTOR, 1533272744Skadesai MR_EVT_ARGS_PD_PD, 1534272744Skadesai MR_EVT_ARGS_PD_FRU, 1535272744Skadesai MR_EVT_ARGS_PD_PATHINFO, 1536272744Skadesai MR_EVT_ARGS_PD_POWER_STATE, 1537272744Skadesai MR_EVT_ARGS_GENERIC, 1538265555Sambrisko}; 1539265555Sambrisko 1540265555Sambrisko/* 1541272744Skadesai * Thunderbolt (and later) Defines 1542265555Sambrisko */ 1543299668Skadesai#define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1544272744Skadesai#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1545272744Skadesai#define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1546272744Skadesai#define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1547272744Skadesai#define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1548272744Skadesai#define MRSAS_LOAD_BALANCE_FLAG 0x1 1549272744Skadesai#define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1550272744Skadesai#define HOST_DIAG_WRITE_ENABLE 0x80 1551272744Skadesai#define HOST_DIAG_RESET_ADAPTER 0x4 1552272744Skadesai#define MRSAS_TBOLT_MAX_RESET_TRIES 3 1553323819Sjkim#define MRSAS_MAX_MFI_CMDS 16 1554323819Sjkim#define MRSAS_MAX_IOCTL_CMDS 3 1555265555Sambrisko 1556265555Sambrisko/* 1557272744Skadesai * Invader Defines 1558265555Sambrisko */ 1559272744Skadesai#define MPI2_TYPE_CUDA 0x2 1560272744Skadesai#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1561272744Skadesai#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1562272744Skadesai#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1563272744Skadesai#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1564272744Skadesai#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1565342716Skadesai#define MR_RL_WRITE_THROUGH_MODE 0x00 1566342716Skadesai#define MR_RL_WRITE_BACK_MODE 0x01 1567265555Sambrisko 1568272744Skadesai/* 1569272744Skadesai * T10 PI defines 1570265555Sambrisko */ 1571272744Skadesai#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1572272744Skadesai#define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1573272744Skadesai#define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1574272744Skadesai#define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1575272744Skadesai#define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1576272744Skadesai#define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1577272744Skadesai#define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1578272744Skadesai#define MRSAS_SCSIBLOCKSIZE 512 1579265555Sambrisko 1580265555Sambrisko/* 1581265555Sambrisko * Raid context flags 1582265555Sambrisko */ 1583272744Skadesai#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1584272744Skadesai#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1585265555Sambriskotypedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1586272744Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1587272744Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1588342716Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 1589342716Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 1590342716Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 1591342716Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 1592342716Skadesai MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 1593342716Skadesai} MR_RAID_FLAGS_IO_SUB_TYPE; 1594265555Sambrisko/* 1595265555Sambrisko * Request descriptor types 1596265555Sambrisko */ 1597272744Skadesai#define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1598272744Skadesai#define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1599272744Skadesai#define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1600272744Skadesai#define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1601272744Skadesai#define MRSAS_FP_CMD_LEN 16 1602272744Skadesai#define MRSAS_FUSION_IN_RESET 0 1603265555Sambrisko 1604272744Skadesai#define RAID_CTX_SPANARM_ARM_SHIFT (0) 1605272744Skadesai#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1606272744Skadesai#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1607272744Skadesai#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1608265555Sambrisko 1609272744Skadesai/* 1610265555Sambrisko * Define region lock types 1611265555Sambrisko */ 1612272744Skadesaitypedef enum _REGION_TYPE { 1613272744Skadesai REGION_TYPE_UNUSED = 0, 1614272744Skadesai REGION_TYPE_SHARED_READ = 1, 1615272744Skadesai REGION_TYPE_SHARED_WRITE = 2, 1616272744Skadesai REGION_TYPE_EXCLUSIVE = 3, 1617272744Skadesai} REGION_TYPE; 1618265555Sambrisko 1619265555Sambrisko 1620265555Sambrisko/* 1621272744Skadesai * SCSI-CAM Related Defines 1622265555Sambrisko */ 1623272744Skadesai#define MRSAS_SCSI_MAX_LUNS 0 1624272744Skadesai#define MRSAS_SCSI_INITIATOR_ID 255 1625272744Skadesai#define MRSAS_SCSI_MAX_CMDS 8 1626272744Skadesai#define MRSAS_SCSI_MAX_CDB_LEN 16 1627272744Skadesai#define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1628272744Skadesai#define MRSAS_INTERNAL_CMDS 32 1629342716Skadesai#define MRSAS_FUSION_INT_CMDS 8 1630265555Sambrisko 1631299668Skadesai#define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1632299668Skadesai#define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1633299668Skadesai#define MEGASAS_256K_IO 128 1634299668Skadesai#define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1635299668Skadesai 1636265555Sambrisko/* Request types */ 1637272744Skadesai#define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1638272744Skadesai#define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1639272744Skadesai#define MRSAS_REQ_TYPE_PASSTHRU 0x2 1640272744Skadesai#define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1641272744Skadesai#define MRSAS_REQ_TYPE_SCSI_IO 0x4 1642265555Sambrisko 1643265555Sambrisko/* Request states */ 1644272744Skadesai#define MRSAS_REQ_STATE_FREE 0 1645272744Skadesai#define MRSAS_REQ_STATE_BUSY 1 1646272744Skadesai#define MRSAS_REQ_STATE_TRAN 2 1647272744Skadesai#define MRSAS_REQ_STATE_COMPLETE 3 1648265555Sambrisko 1649282526Skadesaitypedef enum _MR_SCSI_CMD_TYPE { 1650282526Skadesai READ_WRITE_LDIO = 0, 1651282526Skadesai NON_READ_WRITE_LDIO = 1, 1652282526Skadesai READ_WRITE_SYSPDIO = 2, 1653282526Skadesai NON_READ_WRITE_SYSPDIO = 3, 1654282533Skadesai} MR_SCSI_CMD_TYPE; 1655282526Skadesai 1656265555Sambriskoenum mrsas_req_flags { 1657272744Skadesai MRSAS_DIR_UNKNOWN = 0x1, 1658272744Skadesai MRSAS_DIR_IN = 0x2, 1659272744Skadesai MRSAS_DIR_OUT = 0x4, 1660272744Skadesai MRSAS_DIR_NONE = 0x8, 1661265555Sambrisko}; 1662265555Sambrisko 1663272744Skadesai/* 1664272744Skadesai * Adapter Reset States 1665265555Sambrisko */ 1666265555Sambriskoenum { 1667272744Skadesai MRSAS_HBA_OPERATIONAL = 0, 1668272744Skadesai MRSAS_ADPRESET_SM_INFAULT = 1, 1669272744Skadesai MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1670272744Skadesai MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1671272744Skadesai MRSAS_HW_CRITICAL_ERROR = 4, 1672272744Skadesai MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1673265555Sambrisko}; 1674265555Sambrisko 1675272744Skadesai/* 1676272744Skadesai * MPT Command Structure 1677265555Sambrisko */ 1678265555Sambriskostruct mrsas_mpt_cmd { 1679272744Skadesai MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1680272744Skadesai bus_addr_t io_request_phys_addr; 1681272744Skadesai MPI2_SGE_IO_UNION *chain_frame; 1682272744Skadesai bus_addr_t chain_frame_phys_addr; 1683272744Skadesai u_int32_t sge_count; 1684272744Skadesai u_int8_t *sense; 1685272744Skadesai bus_addr_t sense_phys_addr; 1686272744Skadesai u_int8_t retry_for_fw_reset; 1687272744Skadesai MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1688272744Skadesai u_int32_t sync_cmd_idx; 1689272744Skadesai u_int32_t index; 1690272744Skadesai u_int8_t flags; 1691282527Skadesai u_int8_t pd_r1_lb; 1692272744Skadesai u_int8_t load_balance; 1693272744Skadesai bus_size_t length; 1694272744Skadesai u_int32_t error_code; 1695272744Skadesai bus_dmamap_t data_dmamap; 1696272744Skadesai void *data; 1697272744Skadesai union ccb *ccb_ptr; 1698272744Skadesai struct callout cm_callout; 1699272744Skadesai struct mrsas_softc *sc; 1700323819Sjkim boolean_t tmCapable; 1701342716Skadesai u_int16_t r1_alt_dev_handle; 1702342716Skadesai boolean_t cmd_completed; 1703342716Skadesai struct mrsas_mpt_cmd *peer_cmd; 1704342716Skadesai bool callout_owner; 1705272744Skadesai TAILQ_ENTRY(mrsas_mpt_cmd) next; 1706342716Skadesai u_int8_t pdInterface; 1707265555Sambrisko}; 1708265555Sambrisko 1709272744Skadesai/* 1710272744Skadesai * MFI Command Structure 1711265555Sambrisko */ 1712265555Sambriskostruct mrsas_mfi_cmd { 1713272744Skadesai union mrsas_frame *frame; 1714272744Skadesai bus_dmamap_t frame_dmamap; 1715272744Skadesai void *frame_mem; 1716272744Skadesai bus_addr_t frame_phys_addr; 1717272744Skadesai u_int8_t *sense; 1718272744Skadesai bus_dmamap_t sense_dmamap; 1719272744Skadesai void *sense_mem; 1720272744Skadesai bus_addr_t sense_phys_addr; 1721272744Skadesai u_int32_t index; 1722272744Skadesai u_int8_t sync_cmd; 1723272744Skadesai u_int8_t cmd_status; 1724272744Skadesai u_int8_t abort_aen; 1725272744Skadesai u_int8_t retry_for_fw_reset; 1726272744Skadesai struct mrsas_softc *sc; 1727272744Skadesai union ccb *ccb_ptr; 1728272744Skadesai union { 1729272744Skadesai struct { 1730272744Skadesai u_int16_t smid; 1731272744Skadesai u_int16_t resvd; 1732272744Skadesai } context; 1733272744Skadesai u_int32_t frame_count; 1734272744Skadesai } cmd_id; 1735272744Skadesai TAILQ_ENTRY(mrsas_mfi_cmd) next; 1736265555Sambrisko}; 1737265555Sambrisko 1738265555Sambrisko 1739265555Sambrisko/* 1740265555Sambrisko * define constants for device list query options 1741265555Sambrisko */ 1742265555Sambriskoenum MR_PD_QUERY_TYPE { 1743272744Skadesai MR_PD_QUERY_TYPE_ALL = 0, 1744272744Skadesai MR_PD_QUERY_TYPE_STATE = 1, 1745272744Skadesai MR_PD_QUERY_TYPE_POWER_STATE = 2, 1746272744Skadesai MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1747272744Skadesai MR_PD_QUERY_TYPE_SPEED = 4, 1748272744Skadesai MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1749265555Sambrisko}; 1750265555Sambrisko 1751272744Skadesai#define MR_EVT_CFG_CLEARED 0x0004 1752272744Skadesai#define MR_EVT_LD_STATE_CHANGE 0x0051 1753272744Skadesai#define MR_EVT_PD_INSERTED 0x005b 1754272744Skadesai#define MR_EVT_PD_REMOVED 0x0070 1755272744Skadesai#define MR_EVT_LD_CREATED 0x008a 1756272744Skadesai#define MR_EVT_LD_DELETED 0x008b 1757272744Skadesai#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1758272744Skadesai#define MR_EVT_LD_OFFLINE 0x00fc 1759323819Sjkim#define MR_EVT_CTRL_PROP_CHANGED 0x012f 1760272744Skadesai#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1761265555Sambrisko 1762265555Sambriskoenum MR_PD_STATE { 1763272744Skadesai MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1764272744Skadesai MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1765272744Skadesai MR_PD_STATE_HOT_SPARE = 0x02, 1766272744Skadesai MR_PD_STATE_OFFLINE = 0x10, 1767272744Skadesai MR_PD_STATE_FAILED = 0x11, 1768272744Skadesai MR_PD_STATE_REBUILD = 0x14, 1769272744Skadesai MR_PD_STATE_ONLINE = 0x18, 1770272744Skadesai MR_PD_STATE_COPYBACK = 0x20, 1771272744Skadesai MR_PD_STATE_SYSTEM = 0x40, 1772272744Skadesai}; 1773265555Sambrisko 1774272744Skadesai/* 1775265555Sambrisko * defines the physical drive address structure 1776265555Sambrisko */ 1777265555Sambrisko#pragma pack(1) 1778265555Sambriskostruct MR_PD_ADDRESS { 1779272744Skadesai u_int16_t deviceId; 1780272744Skadesai u_int16_t enclDeviceId; 1781265555Sambrisko 1782272744Skadesai union { 1783272744Skadesai struct { 1784272744Skadesai u_int8_t enclIndex; 1785272744Skadesai u_int8_t slotNumber; 1786272744Skadesai } mrPdAddress; 1787272744Skadesai struct { 1788272744Skadesai u_int8_t enclPosition; 1789272744Skadesai u_int8_t enclConnectorIndex; 1790272744Skadesai } mrEnclAddress; 1791272744Skadesai } u1; 1792272744Skadesai u_int8_t scsiDevType; 1793272744Skadesai union { 1794272744Skadesai u_int8_t connectedPortBitmap; 1795272744Skadesai u_int8_t connectedPortNumbers; 1796272744Skadesai } u2; 1797272744Skadesai u_int64_t sasAddr[2]; 1798265555Sambrisko}; 1799272744Skadesai 1800265555Sambrisko#pragma pack() 1801265555Sambrisko 1802265555Sambrisko/* 1803265555Sambrisko * defines the physical drive list structure 1804265555Sambrisko */ 1805265555Sambrisko#pragma pack(1) 1806265555Sambriskostruct MR_PD_LIST { 1807272744Skadesai u_int32_t size; 1808272744Skadesai u_int32_t count; 1809272744Skadesai struct MR_PD_ADDRESS addr[1]; 1810265555Sambrisko}; 1811272744Skadesai 1812265555Sambrisko#pragma pack() 1813265555Sambrisko 1814265555Sambrisko#pragma pack(1) 1815265555Sambriskostruct mrsas_pd_list { 1816272744Skadesai u_int16_t tid; 1817272744Skadesai u_int8_t driveType; 1818272744Skadesai u_int8_t driveState; 1819265555Sambrisko}; 1820272744Skadesai 1821265555Sambrisko#pragma pack() 1822265555Sambrisko 1823272744Skadesai/* 1824265555Sambrisko * defines the logical drive reference structure 1825265555Sambrisko */ 1826272744Skadesaitypedef union _MR_LD_REF { 1827272744Skadesai struct { 1828272744Skadesai u_int8_t targetId; 1829272744Skadesai u_int8_t reserved; 1830272744Skadesai u_int16_t seqNum; 1831272744Skadesai } ld_context; 1832272744Skadesai u_int32_t ref; 1833272744Skadesai} MR_LD_REF; 1834265555Sambrisko 1835265555Sambrisko 1836265555Sambrisko/* 1837265555Sambrisko * defines the logical drive list structure 1838265555Sambrisko */ 1839265555Sambrisko#pragma pack(1) 1840265555Sambriskostruct MR_LD_LIST { 1841272744Skadesai u_int32_t ldCount; 1842272744Skadesai u_int32_t reserved; 1843272744Skadesai struct { 1844272744Skadesai MR_LD_REF ref; 1845272744Skadesai u_int8_t state; 1846272744Skadesai u_int8_t reserved[3]; 1847272744Skadesai u_int64_t size; 1848272744Skadesai } ldList[MAX_LOGICAL_DRIVES_EXT]; 1849272744Skadesai}; 1850272744Skadesai 1851265555Sambrisko#pragma pack() 1852265555Sambrisko 1853265555Sambrisko/* 1854265555Sambrisko * SAS controller properties 1855265555Sambrisko */ 1856265555Sambrisko#pragma pack(1) 1857265555Sambriskostruct mrsas_ctrl_prop { 1858272744Skadesai u_int16_t seq_num; 1859272744Skadesai u_int16_t pred_fail_poll_interval; 1860272744Skadesai u_int16_t intr_throttle_count; 1861272744Skadesai u_int16_t intr_throttle_timeouts; 1862272744Skadesai u_int8_t rebuild_rate; 1863272744Skadesai u_int8_t patrol_read_rate; 1864272744Skadesai u_int8_t bgi_rate; 1865272744Skadesai u_int8_t cc_rate; 1866272744Skadesai u_int8_t recon_rate; 1867272744Skadesai u_int8_t cache_flush_interval; 1868272744Skadesai u_int8_t spinup_drv_count; 1869272744Skadesai u_int8_t spinup_delay; 1870272744Skadesai u_int8_t cluster_enable; 1871272744Skadesai u_int8_t coercion_mode; 1872272744Skadesai u_int8_t alarm_enable; 1873272744Skadesai u_int8_t disable_auto_rebuild; 1874272744Skadesai u_int8_t disable_battery_warn; 1875272744Skadesai u_int8_t ecc_bucket_size; 1876272744Skadesai u_int16_t ecc_bucket_leak_rate; 1877272744Skadesai u_int8_t restore_hotspare_on_insertion; 1878272744Skadesai u_int8_t expose_encl_devices; 1879272744Skadesai u_int8_t maintainPdFailHistory; 1880272744Skadesai u_int8_t disallowHostRequestReordering; 1881272744Skadesai u_int8_t abortCCOnError; 1882272744Skadesai u_int8_t loadBalanceMode; 1883272744Skadesai u_int8_t disableAutoDetectBackplane; 1884272744Skadesai u_int8_t snapVDSpace; 1885272744Skadesai /* 1886272744Skadesai * Add properties that can be controlled by a bit in the following 1887272744Skadesai * structure. 1888272744Skadesai */ 1889272744Skadesai struct { 1890272744Skadesai u_int32_t copyBackDisabled:1; 1891272744Skadesai u_int32_t SMARTerEnabled:1; 1892272744Skadesai u_int32_t prCorrectUnconfiguredAreas:1; 1893272744Skadesai u_int32_t useFdeOnly:1; 1894272744Skadesai u_int32_t disableNCQ:1; 1895272744Skadesai u_int32_t SSDSMARTerEnabled:1; 1896272744Skadesai u_int32_t SSDPatrolReadEnabled:1; 1897272744Skadesai u_int32_t enableSpinDownUnconfigured:1; 1898272744Skadesai u_int32_t autoEnhancedImport:1; 1899272744Skadesai u_int32_t enableSecretKeyControl:1; 1900272744Skadesai u_int32_t disableOnlineCtrlReset:1; 1901272744Skadesai u_int32_t allowBootWithPinnedCache:1; 1902272744Skadesai u_int32_t disableSpinDownHS:1; 1903272744Skadesai u_int32_t enableJBOD:1; 1904272744Skadesai u_int32_t disableCacheBypass:1; 1905272744Skadesai u_int32_t useDiskActivityForLocate:1; 1906272744Skadesai u_int32_t enablePI:1; 1907272744Skadesai u_int32_t preventPIImport:1; 1908272744Skadesai u_int32_t useGlobalSparesForEmergency:1; 1909272744Skadesai u_int32_t useUnconfGoodForEmergency:1; 1910272744Skadesai u_int32_t useEmergencySparesforSMARTer:1; 1911272744Skadesai u_int32_t forceSGPIOForQuadOnly:1; 1912272744Skadesai u_int32_t enableConfigAutoBalance:1; 1913272744Skadesai u_int32_t enableVirtualCache:1; 1914272744Skadesai u_int32_t enableAutoLockRecovery:1; 1915272744Skadesai u_int32_t disableImmediateIO:1; 1916272744Skadesai u_int32_t disableT10RebuildAssist:1; 1917272744Skadesai u_int32_t ignore64ldRestriction:1; 1918272744Skadesai u_int32_t enableSwZone:1; 1919272744Skadesai u_int32_t limitMaxRateSATA3G:1; 1920272744Skadesai u_int32_t reserved:2; 1921272744Skadesai } OnOffProperties; 1922272744Skadesai u_int8_t autoSnapVDSpace; 1923272744Skadesai u_int8_t viewSpace; 1924272744Skadesai u_int16_t spinDownTime; 1925272744Skadesai u_int8_t reserved[24]; 1926265555Sambrisko 1927272744Skadesai}; 1928272744Skadesai 1929265555Sambrisko#pragma pack() 1930265555Sambrisko 1931265555Sambrisko 1932265555Sambrisko/* 1933265555Sambrisko * SAS controller information 1934265555Sambrisko */ 1935265555Sambriskostruct mrsas_ctrl_info { 1936272744Skadesai /* 1937272744Skadesai * PCI device information 1938272744Skadesai */ 1939272744Skadesai struct { 1940272744Skadesai u_int16_t vendor_id; 1941272744Skadesai u_int16_t device_id; 1942272744Skadesai u_int16_t sub_vendor_id; 1943272744Skadesai u_int16_t sub_device_id; 1944272744Skadesai u_int8_t reserved[24]; 1945272744Skadesai } __packed pci; 1946272744Skadesai /* 1947272744Skadesai * Host interface information 1948272744Skadesai */ 1949272744Skadesai struct { 1950272744Skadesai u_int8_t PCIX:1; 1951272744Skadesai u_int8_t PCIE:1; 1952272744Skadesai u_int8_t iSCSI:1; 1953272744Skadesai u_int8_t SAS_3G:1; 1954272744Skadesai u_int8_t reserved_0:4; 1955272744Skadesai u_int8_t reserved_1[6]; 1956272744Skadesai u_int8_t port_count; 1957272744Skadesai u_int64_t port_addr[8]; 1958272744Skadesai } __packed host_interface; 1959272744Skadesai /* 1960272744Skadesai * Device (backend) interface information 1961272744Skadesai */ 1962272744Skadesai struct { 1963272744Skadesai u_int8_t SPI:1; 1964272744Skadesai u_int8_t SAS_3G:1; 1965272744Skadesai u_int8_t SATA_1_5G:1; 1966272744Skadesai u_int8_t SATA_3G:1; 1967272744Skadesai u_int8_t reserved_0:4; 1968272744Skadesai u_int8_t reserved_1[6]; 1969272744Skadesai u_int8_t port_count; 1970272744Skadesai u_int64_t port_addr[8]; 1971272744Skadesai } __packed device_interface; 1972265555Sambrisko 1973272744Skadesai u_int32_t image_check_word; 1974272744Skadesai u_int32_t image_component_count; 1975265555Sambrisko 1976272744Skadesai struct { 1977272744Skadesai char name[8]; 1978272744Skadesai char version[32]; 1979272744Skadesai char build_date[16]; 1980272744Skadesai char built_time[16]; 1981272744Skadesai } __packed image_component[8]; 1982265555Sambrisko 1983272744Skadesai u_int32_t pending_image_component_count; 1984265555Sambrisko 1985272744Skadesai struct { 1986272744Skadesai char name[8]; 1987272744Skadesai char version[32]; 1988272744Skadesai char build_date[16]; 1989272744Skadesai char build_time[16]; 1990272744Skadesai } __packed pending_image_component[8]; 1991265555Sambrisko 1992272744Skadesai u_int8_t max_arms; 1993272744Skadesai u_int8_t max_spans; 1994272744Skadesai u_int8_t max_arrays; 1995272744Skadesai u_int8_t max_lds; 1996272744Skadesai char product_name[80]; 1997272744Skadesai char serial_no[32]; 1998265555Sambrisko 1999272744Skadesai /* 2000272744Skadesai * Other physical/controller/operation information. Indicates the 2001272744Skadesai * presence of the hardware 2002272744Skadesai */ 2003272744Skadesai struct { 2004272744Skadesai u_int32_t bbu:1; 2005272744Skadesai u_int32_t alarm:1; 2006272744Skadesai u_int32_t nvram:1; 2007272744Skadesai u_int32_t uart:1; 2008272744Skadesai u_int32_t reserved:28; 2009272744Skadesai } __packed hw_present; 2010265555Sambrisko 2011272744Skadesai u_int32_t current_fw_time; 2012265555Sambrisko 2013272744Skadesai /* 2014272744Skadesai * Maximum data transfer sizes 2015272744Skadesai */ 2016272744Skadesai u_int16_t max_concurrent_cmds; 2017272744Skadesai u_int16_t max_sge_count; 2018272744Skadesai u_int32_t max_request_size; 2019265555Sambrisko 2020272744Skadesai /* 2021272744Skadesai * Logical and physical device counts 2022272744Skadesai */ 2023272744Skadesai u_int16_t ld_present_count; 2024272744Skadesai u_int16_t ld_degraded_count; 2025272744Skadesai u_int16_t ld_offline_count; 2026265555Sambrisko 2027272744Skadesai u_int16_t pd_present_count; 2028272744Skadesai u_int16_t pd_disk_present_count; 2029272744Skadesai u_int16_t pd_disk_pred_failure_count; 2030272744Skadesai u_int16_t pd_disk_failed_count; 2031265555Sambrisko 2032272744Skadesai /* 2033272744Skadesai * Memory size information 2034272744Skadesai */ 2035272744Skadesai u_int16_t nvram_size; 2036272744Skadesai u_int16_t memory_size; 2037272744Skadesai u_int16_t flash_size; 2038265555Sambrisko 2039272744Skadesai /* 2040272744Skadesai * Error counters 2041272744Skadesai */ 2042272744Skadesai u_int16_t mem_correctable_error_count; 2043272744Skadesai u_int16_t mem_uncorrectable_error_count; 2044265555Sambrisko 2045272744Skadesai /* 2046272744Skadesai * Cluster information 2047272744Skadesai */ 2048272744Skadesai u_int8_t cluster_permitted; 2049272744Skadesai u_int8_t cluster_active; 2050265555Sambrisko 2051272744Skadesai /* 2052272744Skadesai * Additional max data transfer sizes 2053272744Skadesai */ 2054272744Skadesai u_int16_t max_strips_per_io; 2055265555Sambrisko 2056272744Skadesai /* 2057272744Skadesai * Controller capabilities structures 2058272744Skadesai */ 2059272744Skadesai struct { 2060272744Skadesai u_int32_t raid_level_0:1; 2061272744Skadesai u_int32_t raid_level_1:1; 2062272744Skadesai u_int32_t raid_level_5:1; 2063272744Skadesai u_int32_t raid_level_1E:1; 2064272744Skadesai u_int32_t raid_level_6:1; 2065272744Skadesai u_int32_t reserved:27; 2066272744Skadesai } __packed raid_levels; 2067265555Sambrisko 2068272744Skadesai struct { 2069272744Skadesai u_int32_t rbld_rate:1; 2070272744Skadesai u_int32_t cc_rate:1; 2071272744Skadesai u_int32_t bgi_rate:1; 2072272744Skadesai u_int32_t recon_rate:1; 2073272744Skadesai u_int32_t patrol_rate:1; 2074272744Skadesai u_int32_t alarm_control:1; 2075272744Skadesai u_int32_t cluster_supported:1; 2076272744Skadesai u_int32_t bbu:1; 2077272744Skadesai u_int32_t spanning_allowed:1; 2078272744Skadesai u_int32_t dedicated_hotspares:1; 2079272744Skadesai u_int32_t revertible_hotspares:1; 2080272744Skadesai u_int32_t foreign_config_import:1; 2081272744Skadesai u_int32_t self_diagnostic:1; 2082272744Skadesai u_int32_t mixed_redundancy_arr:1; 2083272744Skadesai u_int32_t global_hot_spares:1; 2084272744Skadesai u_int32_t reserved:17; 2085272744Skadesai } __packed adapter_operations; 2086265555Sambrisko 2087272744Skadesai struct { 2088272744Skadesai u_int32_t read_policy:1; 2089272744Skadesai u_int32_t write_policy:1; 2090272744Skadesai u_int32_t io_policy:1; 2091272744Skadesai u_int32_t access_policy:1; 2092272744Skadesai u_int32_t disk_cache_policy:1; 2093272744Skadesai u_int32_t reserved:27; 2094272744Skadesai } __packed ld_operations; 2095265555Sambrisko 2096272744Skadesai struct { 2097272744Skadesai u_int8_t min; 2098272744Skadesai u_int8_t max; 2099272744Skadesai u_int8_t reserved[2]; 2100272744Skadesai } __packed stripe_sz_ops; 2101265555Sambrisko 2102272744Skadesai struct { 2103272744Skadesai u_int32_t force_online:1; 2104272744Skadesai u_int32_t force_offline:1; 2105272744Skadesai u_int32_t force_rebuild:1; 2106272744Skadesai u_int32_t reserved:29; 2107272744Skadesai } __packed pd_operations; 2108265555Sambrisko 2109272744Skadesai struct { 2110272744Skadesai u_int32_t ctrl_supports_sas:1; 2111272744Skadesai u_int32_t ctrl_supports_sata:1; 2112272744Skadesai u_int32_t allow_mix_in_encl:1; 2113272744Skadesai u_int32_t allow_mix_in_ld:1; 2114272744Skadesai u_int32_t allow_sata_in_cluster:1; 2115272744Skadesai u_int32_t reserved:27; 2116272744Skadesai } __packed pd_mix_support; 2117265555Sambrisko 2118272744Skadesai /* 2119272744Skadesai * Define ECC single-bit-error bucket information 2120272744Skadesai */ 2121272744Skadesai u_int8_t ecc_bucket_count; 2122272744Skadesai u_int8_t reserved_2[11]; 2123265555Sambrisko 2124272744Skadesai /* 2125272744Skadesai * Include the controller properties (changeable items) 2126272744Skadesai */ 2127272744Skadesai struct mrsas_ctrl_prop properties; 2128265555Sambrisko 2129265555Sambrisko /* 2130272744Skadesai * Define FW pkg version (set in envt v'bles on OEM basis) 2131272744Skadesai */ 2132272744Skadesai char package_version[0x60]; 2133265555Sambrisko 2134272744Skadesai u_int64_t deviceInterfacePortAddr2[8]; 2135272744Skadesai u_int8_t reserved3[128]; 2136265555Sambrisko 2137272744Skadesai struct { 2138272744Skadesai u_int16_t minPdRaidLevel_0:4; 2139272744Skadesai u_int16_t maxPdRaidLevel_0:12; 2140265555Sambrisko 2141272744Skadesai u_int16_t minPdRaidLevel_1:4; 2142272744Skadesai u_int16_t maxPdRaidLevel_1:12; 2143265555Sambrisko 2144272744Skadesai u_int16_t minPdRaidLevel_5:4; 2145272744Skadesai u_int16_t maxPdRaidLevel_5:12; 2146265555Sambrisko 2147272744Skadesai u_int16_t minPdRaidLevel_1E:4; 2148272744Skadesai u_int16_t maxPdRaidLevel_1E:12; 2149265555Sambrisko 2150272744Skadesai u_int16_t minPdRaidLevel_6:4; 2151272744Skadesai u_int16_t maxPdRaidLevel_6:12; 2152265555Sambrisko 2153272744Skadesai u_int16_t minPdRaidLevel_10:4; 2154272744Skadesai u_int16_t maxPdRaidLevel_10:12; 2155265555Sambrisko 2156272744Skadesai u_int16_t minPdRaidLevel_50:4; 2157272744Skadesai u_int16_t maxPdRaidLevel_50:12; 2158265555Sambrisko 2159272744Skadesai u_int16_t minPdRaidLevel_60:4; 2160272744Skadesai u_int16_t maxPdRaidLevel_60:12; 2161265555Sambrisko 2162272744Skadesai u_int16_t minPdRaidLevel_1E_RLQ0:4; 2163272744Skadesai u_int16_t maxPdRaidLevel_1E_RLQ0:12; 2164265555Sambrisko 2165272744Skadesai u_int16_t minPdRaidLevel_1E0_RLQ0:4; 2166272744Skadesai u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 2167265555Sambrisko 2168272744Skadesai u_int16_t reserved[6]; 2169272744Skadesai } pdsForRaidLevels; 2170265555Sambrisko 2171272744Skadesai u_int16_t maxPds; /* 0x780 */ 2172272744Skadesai u_int16_t maxDedHSPs; /* 0x782 */ 2173272744Skadesai u_int16_t maxGlobalHSPs; /* 0x784 */ 2174272744Skadesai u_int16_t ddfSize; /* 0x786 */ 2175272744Skadesai u_int8_t maxLdsPerArray; /* 0x788 */ 2176272744Skadesai u_int8_t partitionsInDDF; /* 0x789 */ 2177272744Skadesai u_int8_t lockKeyBinding; /* 0x78a */ 2178272744Skadesai u_int8_t maxPITsPerLd; /* 0x78b */ 2179272744Skadesai u_int8_t maxViewsPerLd; /* 0x78c */ 2180272744Skadesai u_int8_t maxTargetId; /* 0x78d */ 2181272744Skadesai u_int16_t maxBvlVdSize; /* 0x78e */ 2182265555Sambrisko 2183272744Skadesai u_int16_t maxConfigurableSSCSize; /* 0x790 */ 2184272744Skadesai u_int16_t currentSSCsize; /* 0x792 */ 2185265555Sambrisko 2186272744Skadesai char expanderFwVersion[12]; /* 0x794 */ 2187265555Sambrisko 2188272744Skadesai u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 2189265555Sambrisko 2190272744Skadesai u_int16_t cacheMemorySize; /* 0x7A2 */ 2191265555Sambrisko 2192272744Skadesai struct { /* 0x7A4 */ 2193272744Skadesai u_int32_t supportPIcontroller:1; 2194272744Skadesai u_int32_t supportLdPIType1:1; 2195272744Skadesai u_int32_t supportLdPIType2:1; 2196272744Skadesai u_int32_t supportLdPIType3:1; 2197272744Skadesai u_int32_t supportLdBBMInfo:1; 2198272744Skadesai u_int32_t supportShieldState:1; 2199272744Skadesai u_int32_t blockSSDWriteCacheChange:1; 2200272744Skadesai u_int32_t supportSuspendResumeBGops:1; 2201272744Skadesai u_int32_t supportEmergencySpares:1; 2202272744Skadesai u_int32_t supportSetLinkSpeed:1; 2203272744Skadesai u_int32_t supportBootTimePFKChange:1; 2204272744Skadesai u_int32_t supportJBOD:1; 2205272744Skadesai u_int32_t disableOnlinePFKChange:1; 2206272744Skadesai u_int32_t supportPerfTuning:1; 2207272744Skadesai u_int32_t supportSSDPatrolRead:1; 2208272744Skadesai u_int32_t realTimeScheduler:1; 2209265555Sambrisko 2210272744Skadesai u_int32_t supportResetNow:1; 2211272744Skadesai u_int32_t supportEmulatedDrives:1; 2212272744Skadesai u_int32_t headlessMode:1; 2213272744Skadesai u_int32_t dedicatedHotSparesLimited:1; 2214272744Skadesai 2215272744Skadesai 2216272744Skadesai u_int32_t supportUnevenSpans:1; 2217272744Skadesai u_int32_t reserved:11; 2218272744Skadesai } adapterOperations2; 2219272744Skadesai 2220272744Skadesai u_int8_t driverVersion[32]; /* 0x7A8 */ 2221272744Skadesai u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 2222272744Skadesai u_int8_t temperatureROC; /* 0x7C9 */ 2223272744Skadesai u_int8_t temperatureCtrl; /* 0x7CA */ 2224272744Skadesai u_int8_t reserved4; /* 0x7CB */ 2225272744Skadesai u_int16_t maxConfigurablePds; /* 0x7CC */ 2226272744Skadesai 2227272744Skadesai 2228272744Skadesai u_int8_t reserved5[2]; /* 0x7CD reserved */ 2229272744Skadesai 2230265555Sambrisko struct { 2231272744Skadesai u_int32_t peerIsPresent:1; 2232272744Skadesai u_int32_t peerIsIncompatible:1; 2233265555Sambrisko 2234272744Skadesai u_int32_t hwIncompatible:1; 2235272744Skadesai u_int32_t fwVersionMismatch:1; 2236272744Skadesai u_int32_t ctrlPropIncompatible:1; 2237272744Skadesai u_int32_t premiumFeatureMismatch:1; 2238272744Skadesai u_int32_t reserved:26; 2239272744Skadesai } cluster; 2240265555Sambrisko 2241272744Skadesai char clusterId[16]; /* 0x7D4 */ 2242265555Sambrisko 2243272744Skadesai char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 2244265555Sambrisko 2245272744Skadesai struct { /* 0x7E8 */ 2246282533Skadesai u_int32_t supportPersonalityChange:2; 2247282533Skadesai u_int32_t supportThermalPollInterval:1; 2248282533Skadesai u_int32_t supportDisableImmediateIO:1; 2249282533Skadesai u_int32_t supportT10RebuildAssist:1; 2250282533Skadesai u_int32_t supportMaxExtLDs:1; 2251282533Skadesai u_int32_t supportCrashDump:1; 2252282533Skadesai u_int32_t supportSwZone:1; 2253282533Skadesai u_int32_t supportDebugQueue:1; 2254282533Skadesai u_int32_t supportNVCacheErase:1; 2255282533Skadesai u_int32_t supportForceTo512e:1; 2256282533Skadesai u_int32_t supportHOQRebuild:1; 2257282533Skadesai u_int32_t supportAllowedOpsforDrvRemoval:1; 2258282533Skadesai u_int32_t supportDrvActivityLEDSetting:1; 2259282533Skadesai u_int32_t supportNVDRAM:1; 2260282533Skadesai u_int32_t supportForceFlash:1; 2261282533Skadesai u_int32_t supportDisableSESMonitoring:1; 2262282533Skadesai u_int32_t supportCacheBypassModes:1; 2263282533Skadesai u_int32_t supportSecurityonJBOD:1; 2264282533Skadesai u_int32_t discardCacheDuringLDDelete:1; 2265299667Skadesai u_int32_t supportTTYLogCompression:1; 2266299667Skadesai u_int32_t supportCPLDUpdate:1; 2267299667Skadesai u_int32_t supportDiskCacheSettingForSysPDs:1; 2268299667Skadesai u_int32_t supportExtendedSSCSize:1; 2269299667Skadesai u_int32_t useSeqNumJbodFP:1; 2270299667Skadesai u_int32_t reserved:7; 2271282533Skadesai } adapterOperations3; 2272272744Skadesai 2273342716Skadesai u_int8_t pad_cpld[16]; 2274342716Skadesai 2275342716Skadesai struct { 2276342716Skadesai u_int16_t ctrlInfoExtSupported:1; 2277342716Skadesai u_int16_t supportIbuttonLess:1; 2278342716Skadesai u_int16_t supportedEncAlgo:1; 2279342716Skadesai u_int16_t supportEncryptedMfc:1; 2280342716Skadesai u_int16_t imageUploadSupported:1; 2281342716Skadesai u_int16_t supportSESCtrlInMultipathCfg:1; 2282342716Skadesai u_int16_t supportPdMapTargetId:1; 2283342716Skadesai u_int16_t FWSwapsBBUVPDInfo:1; 2284342716Skadesai u_int16_t reserved:8; 2285342716Skadesai } adapterOperations4; 2286342716Skadesai 2287342716Skadesai u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ 2288272735Skadesai} __packed; 2289272735Skadesai 2290265555Sambrisko/* 2291265555Sambrisko * When SCSI mid-layer calls driver's reset routine, driver waits for 2292265555Sambrisko * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 2293265555Sambrisko * that the driver cannot _actually_ abort or reset pending commands. While 2294265555Sambrisko * it is waiting for the commands to complete, it prints a diagnostic message 2295265555Sambrisko * every MRSAS_RESET_NOTICE_INTERVAL seconds 2296265555Sambrisko */ 2297272744Skadesai#define MRSAS_RESET_WAIT_TIME 180 2298272744Skadesai#define MRSAS_INTERNAL_CMD_WAIT_TIME 180 2299272744Skadesai#define MRSAS_RESET_NOTICE_INTERVAL 5 2300272744Skadesai#define MRSAS_IOCTL_CMD 0 2301272744Skadesai#define MRSAS_DEFAULT_CMD_TIMEOUT 90 2302272744Skadesai#define MRSAS_THROTTLE_QUEUE_DEPTH 16 2303265555Sambrisko 2304272739Skadesai/* 2305272739Skadesai * MSI-x regsiters offset defines 2306272739Skadesai */ 2307272744Skadesai#define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 2308272744Skadesai#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 2309272744Skadesai#define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 2310272744Skadesai#define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 2311272744Skadesai#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 2312272744Skadesai#define MR_MAX_MSIX_REG_ARRAY 16 2313272739Skadesai 2314272744Skadesai/* 2315323819Sjkim * SYNC CACHE offset define 2316323819Sjkim */ 2317323819Sjkim#define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 2318323819Sjkim 2319342720Skadesai#define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24) 2320342720Skadesai 2321323819Sjkim/* 2322265555Sambrisko * FW reports the maximum of number of commands that it can accept (maximum 2323265555Sambrisko * commands that can be outstanding) at any time. The driver must report a 2324265555Sambrisko * lower number to the mid layer because it can issue a few internal commands 2325265555Sambrisko * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 2326265555Sambrisko * is shown below 2327265555Sambrisko */ 2328272744Skadesai#define MRSAS_INT_CMDS 32 2329272744Skadesai#define MRSAS_SKINNY_INT_CMDS 5 2330272744Skadesai#define MRSAS_MAX_MSIX_QUEUES 128 2331265555Sambrisko 2332265555Sambrisko/* 2333272744Skadesai * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2334272744Skadesai * based on the size of bus_addr_t 2335265555Sambrisko */ 2336272744Skadesai#define IS_DMA64 (sizeof(bus_addr_t) == 8) 2337265555Sambrisko 2338272744Skadesai#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2339272744Skadesai#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2340272744Skadesai#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2341272744Skadesai#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2342265555Sambrisko 2343272744Skadesai#define MFI_OB_INTR_STATUS_MASK 0x00000002 2344272744Skadesai#define MFI_POLL_TIMEOUT_SECS 60 2345265555Sambrisko 2346272744Skadesai#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2347272744Skadesai#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2348272744Skadesai#define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2349272744Skadesai#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2350272744Skadesai#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2351272744Skadesai#define MFI_1068_PCSR_OFFSET 0x84 2352272744Skadesai#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2353272744Skadesai#define MFI_1068_FW_READY 0xDDDD0000 2354265555Sambrisko 2355272739Skadesaitypedef union _MFI_CAPABILITIES { 2356272744Skadesai struct { 2357272744Skadesai u_int32_t support_fp_remote_lun:1; 2358272744Skadesai u_int32_t support_additional_msix:1; 2359272744Skadesai u_int32_t support_fastpath_wb:1; 2360272744Skadesai u_int32_t support_max_255lds:1; 2361282526Skadesai u_int32_t support_ndrive_r1_lb:1; 2362282526Skadesai u_int32_t support_core_affinity:1; 2363282526Skadesai u_int32_t security_protocol_cmds_fw:1; 2364299668Skadesai u_int32_t support_ext_queue_depth:1; 2365299668Skadesai u_int32_t support_ext_io_size:1; 2366299668Skadesai u_int32_t reserved:23; 2367282533Skadesai } mfi_capabilities; 2368272744Skadesai u_int32_t reg; 2369272744Skadesai} MFI_CAPABILITIES; 2370272739Skadesai 2371265555Sambrisko#pragma pack(1) 2372265555Sambriskostruct mrsas_sge32 { 2373272744Skadesai u_int32_t phys_addr; 2374272744Skadesai u_int32_t length; 2375265555Sambrisko}; 2376272744Skadesai 2377265555Sambrisko#pragma pack() 2378265555Sambrisko 2379265555Sambrisko#pragma pack(1) 2380265555Sambriskostruct mrsas_sge64 { 2381272744Skadesai u_int64_t phys_addr; 2382272744Skadesai u_int32_t length; 2383265555Sambrisko}; 2384272744Skadesai 2385265555Sambrisko#pragma pack() 2386265555Sambrisko 2387265555Sambrisko#pragma pack() 2388265555Sambriskounion mrsas_sgl { 2389272744Skadesai struct mrsas_sge32 sge32[1]; 2390272744Skadesai struct mrsas_sge64 sge64[1]; 2391265555Sambrisko}; 2392272744Skadesai 2393265555Sambrisko#pragma pack() 2394265555Sambrisko 2395265555Sambrisko#pragma pack(1) 2396265555Sambriskostruct mrsas_header { 2397272744Skadesai u_int8_t cmd; /* 00e */ 2398272744Skadesai u_int8_t sense_len; /* 01h */ 2399272744Skadesai u_int8_t cmd_status; /* 02h */ 2400272744Skadesai u_int8_t scsi_status; /* 03h */ 2401265555Sambrisko 2402272744Skadesai u_int8_t target_id; /* 04h */ 2403272744Skadesai u_int8_t lun; /* 05h */ 2404272744Skadesai u_int8_t cdb_len; /* 06h */ 2405272744Skadesai u_int8_t sge_count; /* 07h */ 2406265555Sambrisko 2407272744Skadesai u_int32_t context; /* 08h */ 2408272744Skadesai u_int32_t pad_0; /* 0Ch */ 2409265555Sambrisko 2410272744Skadesai u_int16_t flags; /* 10h */ 2411272744Skadesai u_int16_t timeout; /* 12h */ 2412272744Skadesai u_int32_t data_xferlen; /* 14h */ 2413265555Sambrisko}; 2414272744Skadesai 2415265555Sambrisko#pragma pack() 2416265555Sambrisko 2417265555Sambrisko#pragma pack(1) 2418265555Sambriskostruct mrsas_init_frame { 2419272744Skadesai u_int8_t cmd; /* 00h */ 2420272744Skadesai u_int8_t reserved_0; /* 01h */ 2421272744Skadesai u_int8_t cmd_status; /* 02h */ 2422265555Sambrisko 2423272744Skadesai u_int8_t reserved_1; /* 03h */ 2424272744Skadesai MFI_CAPABILITIES driver_operations; /* 04h */ 2425272744Skadesai u_int32_t context; /* 08h */ 2426272744Skadesai u_int32_t pad_0; /* 0Ch */ 2427265555Sambrisko 2428272744Skadesai u_int16_t flags; /* 10h */ 2429272744Skadesai u_int16_t reserved_3; /* 12h */ 2430272744Skadesai u_int32_t data_xfer_len; /* 14h */ 2431265555Sambrisko 2432272744Skadesai u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2433272744Skadesai u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2434272744Skadesai u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2435272744Skadesai u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2436272744Skadesai u_int32_t driver_ver_lo; /* 28h */ 2437272744Skadesai u_int32_t driver_ver_hi; /* 2Ch */ 2438272744Skadesai u_int32_t reserved_4[4]; /* 30h */ 2439265555Sambrisko}; 2440272744Skadesai 2441265555Sambrisko#pragma pack() 2442265555Sambrisko 2443265555Sambrisko#pragma pack(1) 2444265555Sambriskostruct mrsas_io_frame { 2445272744Skadesai u_int8_t cmd; /* 00h */ 2446272744Skadesai u_int8_t sense_len; /* 01h */ 2447272744Skadesai u_int8_t cmd_status; /* 02h */ 2448272744Skadesai u_int8_t scsi_status; /* 03h */ 2449265555Sambrisko 2450272744Skadesai u_int8_t target_id; /* 04h */ 2451272744Skadesai u_int8_t access_byte; /* 05h */ 2452272744Skadesai u_int8_t reserved_0; /* 06h */ 2453272744Skadesai u_int8_t sge_count; /* 07h */ 2454265555Sambrisko 2455272744Skadesai u_int32_t context; /* 08h */ 2456272744Skadesai u_int32_t pad_0; /* 0Ch */ 2457265555Sambrisko 2458272744Skadesai u_int16_t flags; /* 10h */ 2459272744Skadesai u_int16_t timeout; /* 12h */ 2460272744Skadesai u_int32_t lba_count; /* 14h */ 2461265555Sambrisko 2462272744Skadesai u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2463272744Skadesai u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2464265555Sambrisko 2465272744Skadesai u_int32_t start_lba_lo; /* 20h */ 2466272744Skadesai u_int32_t start_lba_hi; /* 24h */ 2467265555Sambrisko 2468272744Skadesai union mrsas_sgl sgl; /* 28h */ 2469265555Sambrisko}; 2470272744Skadesai 2471265555Sambrisko#pragma pack() 2472265555Sambrisko 2473265555Sambrisko#pragma pack(1) 2474265555Sambriskostruct mrsas_pthru_frame { 2475272744Skadesai u_int8_t cmd; /* 00h */ 2476272744Skadesai u_int8_t sense_len; /* 01h */ 2477272744Skadesai u_int8_t cmd_status; /* 02h */ 2478272744Skadesai u_int8_t scsi_status; /* 03h */ 2479265555Sambrisko 2480272744Skadesai u_int8_t target_id; /* 04h */ 2481272744Skadesai u_int8_t lun; /* 05h */ 2482272744Skadesai u_int8_t cdb_len; /* 06h */ 2483272744Skadesai u_int8_t sge_count; /* 07h */ 2484265555Sambrisko 2485272744Skadesai u_int32_t context; /* 08h */ 2486272744Skadesai u_int32_t pad_0; /* 0Ch */ 2487265555Sambrisko 2488272744Skadesai u_int16_t flags; /* 10h */ 2489272744Skadesai u_int16_t timeout; /* 12h */ 2490272744Skadesai u_int32_t data_xfer_len; /* 14h */ 2491265555Sambrisko 2492272744Skadesai u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2493272744Skadesai u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2494265555Sambrisko 2495272744Skadesai u_int8_t cdb[16]; /* 20h */ 2496272744Skadesai union mrsas_sgl sgl; /* 30h */ 2497265555Sambrisko}; 2498272744Skadesai 2499265555Sambrisko#pragma pack() 2500265555Sambrisko 2501265555Sambrisko#pragma pack(1) 2502265555Sambriskostruct mrsas_dcmd_frame { 2503272744Skadesai u_int8_t cmd; /* 00h */ 2504272744Skadesai u_int8_t reserved_0; /* 01h */ 2505272744Skadesai u_int8_t cmd_status; /* 02h */ 2506272744Skadesai u_int8_t reserved_1[4]; /* 03h */ 2507272744Skadesai u_int8_t sge_count; /* 07h */ 2508265555Sambrisko 2509272744Skadesai u_int32_t context; /* 08h */ 2510272744Skadesai u_int32_t pad_0; /* 0Ch */ 2511265555Sambrisko 2512272744Skadesai u_int16_t flags; /* 10h */ 2513272744Skadesai u_int16_t timeout; /* 12h */ 2514265555Sambrisko 2515272744Skadesai u_int32_t data_xfer_len; /* 14h */ 2516272744Skadesai u_int32_t opcode; /* 18h */ 2517265555Sambrisko 2518272744Skadesai union { /* 1Ch */ 2519272744Skadesai u_int8_t b[12]; 2520272744Skadesai u_int16_t s[6]; 2521272744Skadesai u_int32_t w[3]; 2522272744Skadesai } mbox; 2523265555Sambrisko 2524272744Skadesai union mrsas_sgl sgl; /* 28h */ 2525265555Sambrisko}; 2526272744Skadesai 2527265555Sambrisko#pragma pack() 2528265555Sambrisko 2529265555Sambrisko#pragma pack(1) 2530265555Sambriskostruct mrsas_abort_frame { 2531272744Skadesai u_int8_t cmd; /* 00h */ 2532272744Skadesai u_int8_t reserved_0; /* 01h */ 2533272744Skadesai u_int8_t cmd_status; /* 02h */ 2534265555Sambrisko 2535272744Skadesai u_int8_t reserved_1; /* 03h */ 2536272744Skadesai MFI_CAPABILITIES driver_operations; /* 04h */ 2537272744Skadesai u_int32_t context; /* 08h */ 2538272744Skadesai u_int32_t pad_0; /* 0Ch */ 2539265555Sambrisko 2540272744Skadesai u_int16_t flags; /* 10h */ 2541272744Skadesai u_int16_t reserved_3; /* 12h */ 2542272744Skadesai u_int32_t reserved_4; /* 14h */ 2543265555Sambrisko 2544272744Skadesai u_int32_t abort_context; /* 18h */ 2545272744Skadesai u_int32_t pad_1; /* 1Ch */ 2546265555Sambrisko 2547272744Skadesai u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2548272744Skadesai u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2549265555Sambrisko 2550272744Skadesai u_int32_t reserved_5[6]; /* 28h */ 2551265555Sambrisko}; 2552272744Skadesai 2553265555Sambrisko#pragma pack() 2554265555Sambrisko 2555265555Sambrisko#pragma pack(1) 2556265555Sambriskostruct mrsas_smp_frame { 2557272744Skadesai u_int8_t cmd; /* 00h */ 2558272744Skadesai u_int8_t reserved_1; /* 01h */ 2559272744Skadesai u_int8_t cmd_status; /* 02h */ 2560272744Skadesai u_int8_t connection_status; /* 03h */ 2561265555Sambrisko 2562272744Skadesai u_int8_t reserved_2[3]; /* 04h */ 2563272744Skadesai u_int8_t sge_count; /* 07h */ 2564265555Sambrisko 2565272744Skadesai u_int32_t context; /* 08h */ 2566272744Skadesai u_int32_t pad_0; /* 0Ch */ 2567265555Sambrisko 2568272744Skadesai u_int16_t flags; /* 10h */ 2569272744Skadesai u_int16_t timeout; /* 12h */ 2570265555Sambrisko 2571272744Skadesai u_int32_t data_xfer_len; /* 14h */ 2572272744Skadesai u_int64_t sas_addr; /* 18h */ 2573265555Sambrisko 2574272744Skadesai union { 2575272744Skadesai struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2576272744Skadesai struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2577272744Skadesai } sgl; 2578265555Sambrisko}; 2579272744Skadesai 2580265555Sambrisko#pragma pack() 2581265555Sambrisko 2582265555Sambrisko 2583265555Sambrisko#pragma pack(1) 2584265555Sambriskostruct mrsas_stp_frame { 2585272744Skadesai u_int8_t cmd; /* 00h */ 2586272744Skadesai u_int8_t reserved_1; /* 01h */ 2587272744Skadesai u_int8_t cmd_status; /* 02h */ 2588272744Skadesai u_int8_t reserved_2; /* 03h */ 2589265555Sambrisko 2590272744Skadesai u_int8_t target_id; /* 04h */ 2591272744Skadesai u_int8_t reserved_3[2]; /* 05h */ 2592272744Skadesai u_int8_t sge_count; /* 07h */ 2593265555Sambrisko 2594272744Skadesai u_int32_t context; /* 08h */ 2595272744Skadesai u_int32_t pad_0; /* 0Ch */ 2596265555Sambrisko 2597272744Skadesai u_int16_t flags; /* 10h */ 2598272744Skadesai u_int16_t timeout; /* 12h */ 2599265555Sambrisko 2600272744Skadesai u_int32_t data_xfer_len; /* 14h */ 2601265555Sambrisko 2602272744Skadesai u_int16_t fis[10]; /* 18h */ 2603272744Skadesai u_int32_t stp_flags; 2604265555Sambrisko 2605272744Skadesai union { 2606272744Skadesai struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2607272744Skadesai struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2608272744Skadesai } sgl; 2609265555Sambrisko}; 2610272744Skadesai 2611265555Sambrisko#pragma pack() 2612265555Sambrisko 2613265555Sambriskounion mrsas_frame { 2614272744Skadesai struct mrsas_header hdr; 2615272744Skadesai struct mrsas_init_frame init; 2616272744Skadesai struct mrsas_io_frame io; 2617272744Skadesai struct mrsas_pthru_frame pthru; 2618272744Skadesai struct mrsas_dcmd_frame dcmd; 2619272744Skadesai struct mrsas_abort_frame abort; 2620272744Skadesai struct mrsas_smp_frame smp; 2621272744Skadesai struct mrsas_stp_frame stp; 2622272744Skadesai u_int8_t raw_bytes[64]; 2623265555Sambrisko}; 2624265555Sambrisko 2625265555Sambrisko#pragma pack(1) 2626265555Sambriskounion mrsas_evt_class_locale { 2627265555Sambrisko 2628272744Skadesai struct { 2629272744Skadesai u_int16_t locale; 2630272744Skadesai u_int8_t reserved; 2631272744Skadesai int8_t class; 2632272744Skadesai } __packed members; 2633272744Skadesai 2634272744Skadesai u_int32_t word; 2635272744Skadesai 2636265555Sambrisko} __packed; 2637265555Sambrisko 2638265555Sambrisko#pragma pack() 2639265555Sambrisko 2640265555Sambrisko 2641265555Sambrisko#pragma pack(1) 2642265555Sambriskostruct mrsas_evt_log_info { 2643272744Skadesai u_int32_t newest_seq_num; 2644272744Skadesai u_int32_t oldest_seq_num; 2645272744Skadesai u_int32_t clear_seq_num; 2646272744Skadesai u_int32_t shutdown_seq_num; 2647272744Skadesai u_int32_t boot_seq_num; 2648272744Skadesai 2649265555Sambrisko} __packed; 2650265555Sambrisko 2651265555Sambrisko#pragma pack() 2652265555Sambrisko 2653265555Sambriskostruct mrsas_progress { 2654265555Sambrisko 2655265555Sambrisko u_int16_t progress; 2656265555Sambrisko u_int16_t elapsed_seconds; 2657265555Sambrisko 2658265555Sambrisko} __packed; 2659265555Sambrisko 2660265555Sambriskostruct mrsas_evtarg_ld { 2661265555Sambrisko 2662265555Sambrisko u_int16_t target_id; 2663265555Sambrisko u_int8_t ld_index; 2664265555Sambrisko u_int8_t reserved; 2665265555Sambrisko 2666265555Sambrisko} __packed; 2667265555Sambrisko 2668265555Sambriskostruct mrsas_evtarg_pd { 2669265555Sambrisko u_int16_t device_id; 2670265555Sambrisko u_int8_t encl_index; 2671265555Sambrisko u_int8_t slot_number; 2672265555Sambrisko 2673265555Sambrisko} __packed; 2674265555Sambrisko 2675265555Sambriskostruct mrsas_evt_detail { 2676265555Sambrisko 2677265555Sambrisko u_int32_t seq_num; 2678265555Sambrisko u_int32_t time_stamp; 2679265555Sambrisko u_int32_t code; 2680265555Sambrisko union mrsas_evt_class_locale cl; 2681265555Sambrisko u_int8_t arg_type; 2682265555Sambrisko u_int8_t reserved1[15]; 2683265555Sambrisko 2684265555Sambrisko union { 2685265555Sambrisko struct { 2686265555Sambrisko struct mrsas_evtarg_pd pd; 2687265555Sambrisko u_int8_t cdb_length; 2688265555Sambrisko u_int8_t sense_length; 2689265555Sambrisko u_int8_t reserved[2]; 2690265555Sambrisko u_int8_t cdb[16]; 2691265555Sambrisko u_int8_t sense[64]; 2692265555Sambrisko } __packed cdbSense; 2693265555Sambrisko 2694265555Sambrisko struct mrsas_evtarg_ld ld; 2695265555Sambrisko 2696265555Sambrisko struct { 2697265555Sambrisko struct mrsas_evtarg_ld ld; 2698265555Sambrisko u_int64_t count; 2699265555Sambrisko } __packed ld_count; 2700265555Sambrisko 2701265555Sambrisko struct { 2702265555Sambrisko u_int64_t lba; 2703265555Sambrisko struct mrsas_evtarg_ld ld; 2704265555Sambrisko } __packed ld_lba; 2705265555Sambrisko 2706265555Sambrisko struct { 2707265555Sambrisko struct mrsas_evtarg_ld ld; 2708265555Sambrisko u_int32_t prevOwner; 2709265555Sambrisko u_int32_t newOwner; 2710265555Sambrisko } __packed ld_owner; 2711265555Sambrisko 2712265555Sambrisko struct { 2713265555Sambrisko u_int64_t ld_lba; 2714265555Sambrisko u_int64_t pd_lba; 2715265555Sambrisko struct mrsas_evtarg_ld ld; 2716265555Sambrisko struct mrsas_evtarg_pd pd; 2717265555Sambrisko } __packed ld_lba_pd_lba; 2718265555Sambrisko 2719265555Sambrisko struct { 2720265555Sambrisko struct mrsas_evtarg_ld ld; 2721265555Sambrisko struct mrsas_progress prog; 2722265555Sambrisko } __packed ld_prog; 2723265555Sambrisko 2724265555Sambrisko struct { 2725265555Sambrisko struct mrsas_evtarg_ld ld; 2726265555Sambrisko u_int32_t prev_state; 2727265555Sambrisko u_int32_t new_state; 2728265555Sambrisko } __packed ld_state; 2729265555Sambrisko 2730265555Sambrisko struct { 2731265555Sambrisko u_int64_t strip; 2732265555Sambrisko struct mrsas_evtarg_ld ld; 2733265555Sambrisko } __packed ld_strip; 2734265555Sambrisko 2735265555Sambrisko struct mrsas_evtarg_pd pd; 2736265555Sambrisko 2737265555Sambrisko struct { 2738265555Sambrisko struct mrsas_evtarg_pd pd; 2739265555Sambrisko u_int32_t err; 2740265555Sambrisko } __packed pd_err; 2741265555Sambrisko 2742265555Sambrisko struct { 2743265555Sambrisko u_int64_t lba; 2744265555Sambrisko struct mrsas_evtarg_pd pd; 2745265555Sambrisko } __packed pd_lba; 2746265555Sambrisko 2747265555Sambrisko struct { 2748265555Sambrisko u_int64_t lba; 2749265555Sambrisko struct mrsas_evtarg_pd pd; 2750265555Sambrisko struct mrsas_evtarg_ld ld; 2751265555Sambrisko } __packed pd_lba_ld; 2752265555Sambrisko 2753265555Sambrisko struct { 2754265555Sambrisko struct mrsas_evtarg_pd pd; 2755265555Sambrisko struct mrsas_progress prog; 2756265555Sambrisko } __packed pd_prog; 2757265555Sambrisko 2758265555Sambrisko struct { 2759265555Sambrisko struct mrsas_evtarg_pd pd; 2760265555Sambrisko u_int32_t prevState; 2761265555Sambrisko u_int32_t newState; 2762265555Sambrisko } __packed pd_state; 2763265555Sambrisko 2764265555Sambrisko struct { 2765265555Sambrisko u_int16_t vendorId; 2766265555Sambrisko u_int16_t deviceId; 2767265555Sambrisko u_int16_t subVendorId; 2768265555Sambrisko u_int16_t subDeviceId; 2769265555Sambrisko } __packed pci; 2770265555Sambrisko 2771265555Sambrisko u_int32_t rate; 2772272744Skadesai char str[96]; 2773265555Sambrisko 2774265555Sambrisko struct { 2775265555Sambrisko u_int32_t rtc; 2776265555Sambrisko u_int32_t elapsedSeconds; 2777265555Sambrisko } __packed time; 2778265555Sambrisko 2779265555Sambrisko struct { 2780265555Sambrisko u_int32_t ecar; 2781265555Sambrisko u_int32_t elog; 2782272744Skadesai char str[64]; 2783265555Sambrisko } __packed ecc; 2784265555Sambrisko 2785265555Sambrisko u_int8_t b[96]; 2786265555Sambrisko u_int16_t s[48]; 2787265555Sambrisko u_int32_t w[24]; 2788265555Sambrisko u_int64_t d[12]; 2789272744Skadesai } args; 2790265555Sambrisko 2791272744Skadesai char description[128]; 2792265555Sambrisko 2793265555Sambrisko} __packed; 2794265555Sambrisko 2795272739Skadesaistruct mrsas_irq_context { 2796272744Skadesai struct mrsas_softc *sc; 2797272744Skadesai uint32_t MSIxIndex; 2798272739Skadesai}; 2799272739Skadesai 2800299666Skadesaienum MEGASAS_OCR_REASON { 2801299666Skadesai FW_FAULT_OCR = 0, 2802323819Sjkim MFI_DCMD_TIMEOUT_OCR = 1, 2803299666Skadesai}; 2804299666Skadesai 2805272737Skadesai/* Controller management info added to support Linux Emulator */ 2806272744Skadesai#define MAX_MGMT_ADAPTERS 1024 2807265555Sambrisko 2808272737Skadesaistruct mrsas_mgmt_info { 2809272737Skadesai u_int16_t count; 2810272737Skadesai struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2811272744Skadesai int max_index; 2812272737Skadesai}; 2813272737Skadesai 2814282533Skadesai#define PCI_TYPE0_ADDRESSES 6 2815282533Skadesai#define PCI_TYPE1_ADDRESSES 2 2816282533Skadesai#define PCI_TYPE2_ADDRESSES 5 2817282525Skadesai 2818282533Skadesaitypedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2819282533Skadesai u_int16_t vendorID; 2820282533Skadesai //(ro) 2821282533Skadesai u_int16_t deviceID; 2822282533Skadesai //(ro) 2823282533Skadesai u_int16_t command; 2824282533Skadesai //Device control 2825282525Skadesai u_int16_t status; 2826282533Skadesai u_int8_t revisionID; 2827282533Skadesai //(ro) 2828282533Skadesai u_int8_t progIf; 2829282533Skadesai //(ro) 2830282533Skadesai u_int8_t subClass; 2831282533Skadesai //(ro) 2832282533Skadesai u_int8_t baseClass; 2833282533Skadesai //(ro) 2834282533Skadesai u_int8_t cacheLineSize; 2835282533Skadesai //(ro +) 2836282533Skadesai u_int8_t latencyTimer; 2837282533Skadesai //(ro +) 2838282533Skadesai u_int8_t headerType; 2839282533Skadesai //(ro) 2840282533Skadesai u_int8_t bist; 2841282533Skadesai //Built in self test 2842282525Skadesai 2843282533Skadesai union { 2844282533Skadesai struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 2845282525Skadesai u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 2846282525Skadesai u_int32_t cis; 2847282525Skadesai u_int16_t subVendorID; 2848282525Skadesai u_int16_t subSystemID; 2849282525Skadesai u_int32_t romBaseAddress; 2850282525Skadesai u_int8_t capabilitiesPtr; 2851282525Skadesai u_int8_t reserved1[3]; 2852282525Skadesai u_int32_t reserved2; 2853282525Skadesai u_int8_t interruptLine; 2854282533Skadesai u_int8_t interruptPin; 2855282533Skadesai //(ro) 2856282533Skadesai u_int8_t minimumGrant; 2857282533Skadesai //(ro) 2858282533Skadesai u_int8_t maximumLatency; 2859282533Skadesai //(ro) 2860282533Skadesai } type0; 2861282525Skadesai 2862282533Skadesai /* 2863282533Skadesai * PCI to PCI Bridge 2864282533Skadesai */ 2865282525Skadesai 2866282533Skadesai struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 2867282533Skadesai u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 2868282533Skadesai u_int8_t primaryBus; 2869282533Skadesai u_int8_t secondaryBus; 2870282533Skadesai u_int8_t subordinateBus; 2871282533Skadesai u_int8_t secondaryLatency; 2872282533Skadesai u_int8_t ioBase; 2873282533Skadesai u_int8_t ioLimit; 2874282533Skadesai u_int16_t secondaryStatus; 2875282533Skadesai u_int16_t memoryBase; 2876282533Skadesai u_int16_t memoryLimit; 2877282533Skadesai u_int16_t prefetchBase; 2878282533Skadesai u_int16_t prefetchLimit; 2879282533Skadesai u_int32_t prefetchBaseUpper32; 2880282533Skadesai u_int32_t prefetchLimitUpper32; 2881282533Skadesai u_int16_t ioBaseUpper16; 2882282533Skadesai u_int16_t ioLimitUpper16; 2883282533Skadesai u_int8_t capabilitiesPtr; 2884282533Skadesai u_int8_t reserved1[3]; 2885282533Skadesai u_int32_t romBaseAddress; 2886282533Skadesai u_int8_t interruptLine; 2887282533Skadesai u_int8_t interruptPin; 2888282533Skadesai u_int16_t bridgeControl; 2889282533Skadesai } type1; 2890282525Skadesai 2891282533Skadesai /* 2892282533Skadesai * PCI to CARDBUS Bridge 2893282533Skadesai */ 2894282525Skadesai 2895282533Skadesai struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 2896282533Skadesai u_int32_t socketRegistersBaseAddress; 2897282533Skadesai u_int8_t capabilitiesPtr; 2898282533Skadesai u_int8_t reserved; 2899282533Skadesai u_int16_t secondaryStatus; 2900282533Skadesai u_int8_t primaryBus; 2901282533Skadesai u_int8_t secondaryBus; 2902282533Skadesai u_int8_t subordinateBus; 2903282533Skadesai u_int8_t secondaryLatency; 2904282533Skadesai struct { 2905282533Skadesai u_int32_t base; 2906282533Skadesai u_int32_t limit; 2907282533Skadesai } range [PCI_TYPE2_ADDRESSES - 1]; 2908282533Skadesai u_int8_t interruptLine; 2909282533Skadesai u_int8_t interruptPin; 2910282533Skadesai u_int16_t bridgeControl; 2911282533Skadesai } type2; 2912282533Skadesai } u; 2913282525Skadesai 2914282533Skadesai} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 2915282525Skadesai 2916282533Skadesai#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 2917282525Skadesai 2918282533Skadesaitypedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 2919282533Skadesai union { 2920282533Skadesai struct { 2921282533Skadesai u_int32_t linkSpeed:4; 2922282533Skadesai u_int32_t linkWidth:6; 2923282533Skadesai u_int32_t aspmSupport:2; 2924282533Skadesai u_int32_t losExitLatency:3; 2925282533Skadesai u_int32_t l1ExitLatency:3; 2926282533Skadesai u_int32_t rsvdp:6; 2927282533Skadesai u_int32_t portNumber:8; 2928282533Skadesai } bits; 2929282525Skadesai 2930282525Skadesai u_int32_t asUlong; 2931282533Skadesai } u; 2932282533Skadesai} MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 2933282525Skadesai 2934282533Skadesai#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 2935282525Skadesai 2936282533Skadesaitypedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 2937282533Skadesai union { 2938282533Skadesai struct { 2939282533Skadesai u_int16_t linkSpeed:4; 2940282533Skadesai u_int16_t negotiatedLinkWidth:6; 2941282533Skadesai u_int16_t linkTrainingError:1; 2942282533Skadesai u_int16_t linkTraning:1; 2943282533Skadesai u_int16_t slotClockConfig:1; 2944282533Skadesai u_int16_t rsvdZ:3; 2945282533Skadesai } bits; 2946282525Skadesai 2947282525Skadesai u_int16_t asUshort; 2948282533Skadesai } u; 2949282525Skadesai u_int16_t reserved; 2950282533Skadesai} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 2951282525Skadesai 2952282533Skadesai#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 2953282525Skadesai 2954282525Skadesai 2955282533Skadesaitypedef struct _MRSAS_DRV_PCI_CAPABILITIES { 2956282533Skadesai MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 2957282533Skadesai MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 2958282533Skadesai} MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 2959282525Skadesai 2960282533Skadesai#define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 2961282525Skadesai 2962282525Skadesai/* PCI information */ 2963282533Skadesaitypedef struct _MRSAS_DRV_PCI_INFORMATION { 2964282533Skadesai u_int32_t busNumber; 2965282533Skadesai u_int8_t deviceNumber; 2966282533Skadesai u_int8_t functionNumber; 2967282533Skadesai u_int8_t interruptVector; 2968282533Skadesai u_int8_t reserved1; 2969282533Skadesai MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 2970282533Skadesai MRSAS_DRV_PCI_CAPABILITIES capability; 2971282533Skadesai u_int32_t domainID; 2972282533Skadesai u_int8_t reserved2[28]; 2973282533Skadesai} MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 2974282525Skadesai 2975342716Skadesaitypedef enum _MR_PD_TYPE { 2976342716Skadesai UNKNOWN_DRIVE = 0, 2977342716Skadesai PARALLEL_SCSI = 1, 2978342716Skadesai SAS_PD = 2, 2979342716Skadesai SATA_PD = 3, 2980342716Skadesai FC_PD = 4, 2981342716Skadesai NVME_PD = 5, 2982342716Skadesai} MR_PD_TYPE; 2983342716Skadesai 2984342716Skadesaitypedef union _MR_PD_REF { 2985342716Skadesai struct { 2986342716Skadesai u_int16_t deviceId; 2987342716Skadesai u_int16_t seqNum; 2988342716Skadesai } mrPdRef; 2989342716Skadesai u_int32_t ref; 2990342716Skadesai} MR_PD_REF; 2991342716Skadesai 2992342716Skadesai/* 2993342716Skadesai * define the DDF Type bit structure 2994342716Skadesai */ 2995342716Skadesaiunion MR_PD_DDF_TYPE { 2996342716Skadesai struct { 2997342716Skadesai union { 2998342716Skadesai struct { 2999342716Skadesai u_int16_t forcedPDGUID:1; 3000342716Skadesai u_int16_t inVD:1; 3001342716Skadesai u_int16_t isGlobalSpare:1; 3002342716Skadesai u_int16_t isSpare:1; 3003342716Skadesai u_int16_t isForeign:1; 3004342716Skadesai u_int16_t reserved:7; 3005342716Skadesai u_int16_t intf:4; 3006342716Skadesai } pdType; 3007342716Skadesai u_int16_t type; 3008342716Skadesai }; 3009342716Skadesai u_int16_t reserved; 3010342716Skadesai } ddf; 3011342716Skadesai struct { 3012342716Skadesai u_int32_t reserved; 3013342716Skadesai } nonDisk; 3014342716Skadesai u_int32_t type; 3015342716Skadesai} __packed; 3016342716Skadesai 3017342716Skadesai/* 3018342716Skadesai * defines the progress structure 3019342716Skadesai */ 3020342716Skadesaiunion MR_PROGRESS { 3021342716Skadesai struct { 3022342716Skadesai u_int16_t progress; 3023342716Skadesai union { 3024342716Skadesai u_int16_t elapsedSecs; 3025342716Skadesai u_int16_t elapsedSecsForLastPercent; 3026342716Skadesai }; 3027342716Skadesai } mrProgress; 3028342716Skadesai u_int32_t w; 3029342716Skadesai} __packed; 3030342716Skadesai 3031342716Skadesai/* 3032342716Skadesai * defines the physical drive progress structure 3033342716Skadesai */ 3034342716Skadesaistruct MR_PD_PROGRESS { 3035342716Skadesai struct { 3036342716Skadesai u_int32_t rbld:1; 3037342716Skadesai u_int32_t patrol:1; 3038342716Skadesai u_int32_t clear:1; 3039342716Skadesai u_int32_t copyBack:1; 3040342716Skadesai u_int32_t erase:1; 3041342716Skadesai u_int32_t locate:1; 3042342716Skadesai u_int32_t reserved:26; 3043342716Skadesai } active; 3044342716Skadesai union MR_PROGRESS rbld; 3045342716Skadesai union MR_PROGRESS patrol; 3046342716Skadesai union { 3047342716Skadesai union MR_PROGRESS clear; 3048342716Skadesai union MR_PROGRESS erase; 3049342716Skadesai }; 3050342716Skadesai 3051342716Skadesai struct { 3052342716Skadesai u_int32_t rbld:1; 3053342716Skadesai u_int32_t patrol:1; 3054342716Skadesai u_int32_t clear:1; 3055342716Skadesai u_int32_t copyBack:1; 3056342716Skadesai u_int32_t erase:1; 3057342716Skadesai u_int32_t reserved:27; 3058342716Skadesai } pause; 3059342716Skadesai 3060342716Skadesai union MR_PROGRESS reserved[3]; 3061342716Skadesai} __packed; 3062342716Skadesai 3063342716Skadesai 3064342716Skadesaistruct mrsas_pd_info { 3065342716Skadesai MR_PD_REF ref; 3066342716Skadesai u_int8_t inquiryData[96]; 3067342716Skadesai u_int8_t vpdPage83[64]; 3068342716Skadesai 3069342716Skadesai u_int8_t notSupported; 3070342716Skadesai u_int8_t scsiDevType; 3071342716Skadesai 3072342716Skadesai union { 3073342716Skadesai u_int8_t connectedPortBitmap; 3074342716Skadesai u_int8_t connectedPortNumbers; 3075342716Skadesai }; 3076342716Skadesai 3077342716Skadesai u_int8_t deviceSpeed; 3078342716Skadesai u_int32_t mediaErrCount; 3079342716Skadesai u_int32_t otherErrCount; 3080342716Skadesai u_int32_t predFailCount; 3081342716Skadesai u_int32_t lastPredFailEventSeqNum; 3082342716Skadesai 3083342716Skadesai u_int16_t fwState; 3084342716Skadesai u_int8_t disabledForRemoval; 3085342716Skadesai u_int8_t linkSpeed; 3086342716Skadesai union MR_PD_DDF_TYPE state; 3087342716Skadesai 3088342716Skadesai struct { 3089342716Skadesai u_int8_t count; 3090342716Skadesai u_int8_t isPathBroken:4; 3091342716Skadesai u_int8_t reserved3:3; 3092342716Skadesai u_int8_t widePortCapable:1; 3093342716Skadesai 3094342716Skadesai u_int8_t connectorIndex[2]; 3095342716Skadesai u_int8_t reserved[4]; 3096342716Skadesai u_int64_t sasAddr[2]; 3097342716Skadesai u_int8_t reserved2[16]; 3098342716Skadesai } pathInfo; 3099342716Skadesai 3100342716Skadesai u_int64_t rawSize; 3101342716Skadesai u_int64_t nonCoercedSize; 3102342716Skadesai u_int64_t coercedSize; 3103342716Skadesai u_int16_t enclDeviceId; 3104342716Skadesai u_int8_t enclIndex; 3105342716Skadesai 3106342716Skadesai union { 3107342716Skadesai u_int8_t slotNumber; 3108342716Skadesai u_int8_t enclConnectorIndex; 3109342716Skadesai }; 3110342716Skadesai 3111342716Skadesai struct MR_PD_PROGRESS progInfo; 3112342716Skadesai u_int8_t badBlockTableFull; 3113342716Skadesai u_int8_t unusableInCurrentConfig; 3114342716Skadesai u_int8_t vpdPage83Ext[64]; 3115342716Skadesai u_int8_t powerState; 3116342716Skadesai u_int8_t enclPosition; 3117342716Skadesai u_int32_t allowedOps; 3118342716Skadesai u_int16_t copyBackPartnerId; 3119342716Skadesai u_int16_t enclPartnerDeviceId; 3120342716Skadesai struct { 3121342716Skadesai u_int16_t fdeCapable:1; 3122342716Skadesai u_int16_t fdeEnabled:1; 3123342716Skadesai u_int16_t secured:1; 3124342716Skadesai u_int16_t locked:1; 3125342716Skadesai u_int16_t foreign:1; 3126342716Skadesai u_int16_t needsEKM:1; 3127342716Skadesai u_int16_t reserved:10; 3128342716Skadesai } security; 3129342716Skadesai u_int8_t mediaType; 3130342716Skadesai u_int8_t notCertified; 3131342716Skadesai u_int8_t bridgeVendor[8]; 3132342716Skadesai u_int8_t bridgeProductIdentification[16]; 3133342716Skadesai u_int8_t bridgeProductRevisionLevel[4]; 3134342716Skadesai u_int8_t satBridgeExists; 3135342716Skadesai 3136342716Skadesai u_int8_t interfaceType; 3137342716Skadesai u_int8_t temperature; 3138342716Skadesai u_int8_t emulatedBlockSize; 3139342716Skadesai u_int16_t userDataBlockSize; 3140342716Skadesai u_int16_t reserved2; 3141342716Skadesai 3142342716Skadesai struct { 3143342716Skadesai u_int32_t piType:3; 3144342716Skadesai u_int32_t piFormatted:1; 3145342716Skadesai u_int32_t piEligible:1; 3146342716Skadesai u_int32_t NCQ:1; 3147342716Skadesai u_int32_t WCE:1; 3148342716Skadesai u_int32_t commissionedSpare:1; 3149342716Skadesai u_int32_t emergencySpare:1; 3150342716Skadesai u_int32_t ineligibleForSSCD:1; 3151342716Skadesai u_int32_t ineligibleForLd:1; 3152342716Skadesai u_int32_t useSSEraseType:1; 3153342716Skadesai u_int32_t wceUnchanged:1; 3154342716Skadesai u_int32_t supportScsiUnmap:1; 3155342716Skadesai u_int32_t reserved:18; 3156342716Skadesai } properties; 3157342716Skadesai 3158342716Skadesai u_int64_t shieldDiagCompletionTime; 3159342716Skadesai u_int8_t shieldCounter; 3160342716Skadesai 3161342716Skadesai u_int8_t linkSpeedOther; 3162342716Skadesai u_int8_t reserved4[2]; 3163342716Skadesai 3164342716Skadesai struct { 3165342716Skadesai u_int32_t bbmErrCountSupported:1; 3166342716Skadesai u_int32_t bbmErrCount:31; 3167342716Skadesai } bbmErr; 3168342716Skadesai 3169342716Skadesai u_int8_t reserved1[512-428]; 3170342716Skadesai} __packed; 3171342716Skadesai 3172342716Skadesaistruct mrsas_target { 3173342716Skadesai u_int16_t target_id; 3174342716Skadesai u_int32_t queue_depth; 3175342716Skadesai u_int8_t interface_type; 3176342716Skadesai u_int32_t max_io_size_kb; 3177342716Skadesai} __packed; 3178342716Skadesai 3179342716Skadesai#define MR_NVME_PAGE_SIZE_MASK 0x000000FF 3180342716Skadesai#define MR_DEFAULT_NVME_PAGE_SIZE 4096 3181342716Skadesai#define MR_DEFAULT_NVME_PAGE_SHIFT 12 3182342716Skadesai 3183265555Sambrisko/******************************************************************* 3184265555Sambrisko * per-instance data 3185265555Sambrisko ********************************************************************/ 3186265555Sambriskostruct mrsas_softc { 3187272744Skadesai device_t mrsas_dev; 3188272744Skadesai struct cdev *mrsas_cdev; 3189299669Skadesai struct intr_config_hook mrsas_ich; 3190299669Skadesai struct cdev *mrsas_linux_emulator_cdev; 3191272744Skadesai uint16_t device_id; 3192272744Skadesai struct resource *reg_res; 3193272744Skadesai int reg_res_id; 3194272744Skadesai bus_space_tag_t bus_tag; 3195272744Skadesai bus_space_handle_t bus_handle; 3196272744Skadesai bus_dma_tag_t mrsas_parent_tag; 3197272744Skadesai bus_dma_tag_t verbuf_tag; 3198272744Skadesai bus_dmamap_t verbuf_dmamap; 3199272744Skadesai void *verbuf_mem; 3200272744Skadesai bus_addr_t verbuf_phys_addr; 3201272744Skadesai bus_dma_tag_t sense_tag; 3202272744Skadesai bus_dmamap_t sense_dmamap; 3203272744Skadesai void *sense_mem; 3204272744Skadesai bus_addr_t sense_phys_addr; 3205272744Skadesai bus_dma_tag_t io_request_tag; 3206272744Skadesai bus_dmamap_t io_request_dmamap; 3207272744Skadesai void *io_request_mem; 3208272744Skadesai bus_addr_t io_request_phys_addr; 3209272744Skadesai bus_dma_tag_t chain_frame_tag; 3210272744Skadesai bus_dmamap_t chain_frame_dmamap; 3211272744Skadesai void *chain_frame_mem; 3212272744Skadesai bus_addr_t chain_frame_phys_addr; 3213272744Skadesai bus_dma_tag_t reply_desc_tag; 3214272744Skadesai bus_dmamap_t reply_desc_dmamap; 3215272744Skadesai void *reply_desc_mem; 3216272744Skadesai bus_addr_t reply_desc_phys_addr; 3217272744Skadesai bus_dma_tag_t ioc_init_tag; 3218272744Skadesai bus_dmamap_t ioc_init_dmamap; 3219272744Skadesai void *ioc_init_mem; 3220272744Skadesai bus_addr_t ioc_init_phys_mem; 3221272744Skadesai bus_dma_tag_t data_tag; 3222272744Skadesai struct cam_sim *sim_0; 3223272744Skadesai struct cam_sim *sim_1; 3224272744Skadesai struct cam_path *path_0; 3225272744Skadesai struct cam_path *path_1; 3226272744Skadesai struct mtx sim_lock; 3227272744Skadesai struct mtx pci_lock; 3228272744Skadesai struct mtx io_lock; 3229272744Skadesai struct mtx ioctl_lock; 3230272744Skadesai struct mtx mpt_cmd_pool_lock; 3231272744Skadesai struct mtx mfi_cmd_pool_lock; 3232272744Skadesai struct mtx raidmap_lock; 3233272744Skadesai struct mtx aen_lock; 3234342716Skadesai struct mtx stream_lock; 3235272744Skadesai struct selinfo mrsas_select; 3236272744Skadesai uint32_t mrsas_aen_triggered; 3237272744Skadesai uint32_t mrsas_poll_waiting; 3238272741Skadesai 3239272744Skadesai struct sema ioctl_count_sema; 3240272744Skadesai uint32_t max_fw_cmds; 3241342716Skadesai uint16_t max_scsi_cmds; 3242272744Skadesai uint32_t max_num_sge; 3243272744Skadesai struct resource *mrsas_irq[MAX_MSIX_COUNT]; 3244272744Skadesai void *intr_handle[MAX_MSIX_COUNT]; 3245272744Skadesai int irq_id[MAX_MSIX_COUNT]; 3246272744Skadesai struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 3247272744Skadesai int msix_vectors; 3248272744Skadesai int msix_enable; 3249272744Skadesai uint32_t msix_reg_offset[16]; 3250282533Skadesai uint8_t mask_interrupts; 3251299668Skadesai uint16_t max_chain_frame_sz; 3252272744Skadesai struct mrsas_mpt_cmd **mpt_cmd_list; 3253272744Skadesai struct mrsas_mfi_cmd **mfi_cmd_list; 3254272744Skadesai TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 3255272744Skadesai TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 3256272744Skadesai bus_addr_t req_frames_desc_phys; 3257272744Skadesai u_int8_t *req_frames_desc; 3258272744Skadesai u_int8_t *req_desc; 3259272744Skadesai bus_addr_t io_request_frames_phys; 3260272744Skadesai u_int8_t *io_request_frames; 3261272744Skadesai bus_addr_t reply_frames_desc_phys; 3262272744Skadesai u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 3263272744Skadesai u_int32_t reply_q_depth; 3264272744Skadesai u_int32_t request_alloc_sz; 3265272744Skadesai u_int32_t reply_alloc_sz; 3266272744Skadesai u_int32_t io_frames_alloc_sz; 3267272744Skadesai u_int32_t chain_frames_alloc_sz; 3268272744Skadesai u_int16_t max_sge_in_main_msg; 3269272744Skadesai u_int16_t max_sge_in_chain; 3270272744Skadesai u_int8_t chain_offset_io_request; 3271272744Skadesai u_int8_t chain_offset_mfi_pthru; 3272272744Skadesai u_int32_t map_sz; 3273272744Skadesai u_int64_t map_id; 3274299667Skadesai u_int64_t pd_seq_map_id; 3275272744Skadesai struct mrsas_mfi_cmd *map_update_cmd; 3276299667Skadesai struct mrsas_mfi_cmd *jbod_seq_cmd; 3277272744Skadesai struct mrsas_mfi_cmd *aen_cmd; 3278272744Skadesai u_int8_t fast_path_io; 3279272744Skadesai void *chan; 3280272744Skadesai void *ocr_chan; 3281272744Skadesai u_int8_t adprecovery; 3282272744Skadesai u_int8_t remove_in_progress; 3283272744Skadesai u_int8_t ocr_thread_active; 3284272744Skadesai u_int8_t do_timedout_reset; 3285272744Skadesai u_int32_t reset_in_progress; 3286272744Skadesai u_int32_t reset_count; 3287323819Sjkim u_int32_t block_sync_cache; 3288342716Skadesai u_int32_t drv_stream_detection; 3289323819Sjkim u_int8_t fw_sync_cache_support; 3290323819Sjkim mrsas_atomic_t target_reset_outstanding; 3291323819Sjkim#define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) 3292323819Sjkim struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; 3293299667Skadesai 3294299667Skadesai bus_dma_tag_t jbodmap_tag[2]; 3295299667Skadesai bus_dmamap_t jbodmap_dmamap[2]; 3296299667Skadesai void *jbodmap_mem[2]; 3297299667Skadesai bus_addr_t jbodmap_phys_addr[2]; 3298299667Skadesai 3299272744Skadesai bus_dma_tag_t raidmap_tag[2]; 3300272744Skadesai bus_dmamap_t raidmap_dmamap[2]; 3301272744Skadesai void *raidmap_mem[2]; 3302272744Skadesai bus_addr_t raidmap_phys_addr[2]; 3303272744Skadesai bus_dma_tag_t mficmd_frame_tag; 3304272744Skadesai bus_dma_tag_t mficmd_sense_tag; 3305342716Skadesai bus_addr_t evt_detail_phys_addr; 3306272744Skadesai bus_dma_tag_t evt_detail_tag; 3307272744Skadesai bus_dmamap_t evt_detail_dmamap; 3308272744Skadesai struct mrsas_evt_detail *evt_detail_mem; 3309342716Skadesai bus_addr_t pd_info_phys_addr; 3310342716Skadesai bus_dma_tag_t pd_info_tag; 3311342716Skadesai bus_dmamap_t pd_info_dmamap; 3312342716Skadesai struct mrsas_pd_info *pd_info_mem; 3313282528Skadesai struct mrsas_ctrl_info *ctrl_info; 3314272744Skadesai bus_dma_tag_t ctlr_info_tag; 3315272744Skadesai bus_dmamap_t ctlr_info_dmamap; 3316272744Skadesai void *ctlr_info_mem; 3317272744Skadesai bus_addr_t ctlr_info_phys_addr; 3318272744Skadesai u_int32_t max_sectors_per_req; 3319273377Shselasky u_int32_t disableOnlineCtrlReset; 3320273040Skadesai mrsas_atomic_t fw_outstanding; 3321342716Skadesai mrsas_atomic_t prp_count; 3322342716Skadesai mrsas_atomic_t sge_holes; 3323342716Skadesai 3324272744Skadesai u_int32_t mrsas_debug; 3325272744Skadesai u_int32_t mrsas_io_timeout; 3326272744Skadesai u_int32_t mrsas_fw_fault_check_delay; 3327272744Skadesai u_int32_t io_cmds_highwater; 3328272744Skadesai u_int8_t UnevenSpanSupport; 3329272744Skadesai struct sysctl_ctx_list sysctl_ctx; 3330272744Skadesai struct sysctl_oid *sysctl_tree; 3331272744Skadesai struct proc *ocr_thread; 3332272744Skadesai u_int32_t last_seq_num; 3333272744Skadesai bus_dma_tag_t el_info_tag; 3334272744Skadesai bus_dmamap_t el_info_dmamap; 3335272744Skadesai void *el_info_mem; 3336272744Skadesai bus_addr_t el_info_phys_addr; 3337272744Skadesai struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 3338272744Skadesai struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 3339342716Skadesai struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS]; 3340272744Skadesai u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 3341272744Skadesai struct taskqueue *ev_tq; 3342272744Skadesai struct task ev_task; 3343272744Skadesai u_int32_t CurLdCount; 3344272744Skadesai u_int64_t reset_flags; 3345282533Skadesai int lb_pending_cmds; 3346272744Skadesai LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 3347272744Skadesai LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 3348272735Skadesai 3349323819Sjkim u_int8_t mrsas_gen3_ctrl; 3350282526Skadesai u_int8_t secure_jbod_support; 3351299667Skadesai u_int8_t use_seqnum_jbod_fp; 3352342716Skadesai /* FW suport for more than 256 PD/JBOD */ 3353342716Skadesai u_int32_t support_morethan256jbod; 3354272744Skadesai u_int8_t max256vdSupport; 3355272744Skadesai u_int16_t fw_supported_vd_count; 3356272744Skadesai u_int16_t fw_supported_pd_count; 3357272735Skadesai 3358272744Skadesai u_int16_t drv_supported_vd_count; 3359272744Skadesai u_int16_t drv_supported_pd_count; 3360272735Skadesai 3361272744Skadesai u_int32_t max_map_sz; 3362272744Skadesai u_int32_t current_map_sz; 3363272744Skadesai u_int32_t old_map_sz; 3364272744Skadesai u_int32_t new_map_sz; 3365272744Skadesai u_int32_t drv_map_sz; 3366272735Skadesai 3367342716Skadesai u_int32_t nvme_page_size; 3368342716Skadesai boolean_t is_ventura; 3369342720Skadesai boolean_t is_aero; 3370342716Skadesai boolean_t msix_combined; 3371342720Skadesai boolean_t atomic_desc_support; 3372342716Skadesai u_int16_t maxRaidMapSize; 3373342716Skadesai 3374272744Skadesai /* Non dma-able memory. Driver local copy. */ 3375272744Skadesai MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 3376342716Skadesai PTR_LD_STREAM_DETECT *streamDetectByLD; 3377265555Sambrisko}; 3378265555Sambrisko 3379265555Sambrisko/* Compatibility shims for different OS versions */ 3380265555Sambrisko#if __FreeBSD_version >= 800001 3381272744Skadesai#define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3382265555Sambrisko kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3383272744Skadesai#define mrsas_kproc_exit(arg) kproc_exit(arg) 3384265555Sambrisko#else 3385272744Skadesai#define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3386265555Sambrisko kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3387272744Skadesai#define mrsas_kproc_exit(arg) kthread_exit(arg) 3388265555Sambrisko#endif 3389265555Sambrisko 3390265555Sambriskostatic __inline void 3391273040Skadesaimrsas_clear_bit(int b, volatile void *p) 3392265555Sambrisko{ 3393272744Skadesai atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3394265555Sambrisko} 3395265555Sambrisko 3396265555Sambriskostatic __inline void 3397273040Skadesaimrsas_set_bit(int b, volatile void *p) 3398265555Sambrisko{ 3399272744Skadesai atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3400265555Sambrisko} 3401265555Sambrisko 3402265555Sambriskostatic __inline int 3403273040Skadesaimrsas_test_bit(int b, volatile void *p) 3404265555Sambrisko{ 3405272744Skadesai return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 3406265555Sambrisko} 3407265555Sambrisko 3408272744Skadesai#endif /* MRSAS_H */ 3409